K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 1 -
K7N641845M
Rev. 1.3 September 2008
72Mb NtRAM
TM
Specification
100TQFP/165FBGA with Pb/Pb-Free
(RoHS compliant)
* Samsung Electronics reserves the right to change products or specification without notice.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 2 -
K7N641845M
Rev. 1.3 September 2008
Document Title
2Mx36 & 4Mx18-Bit Pipelined NtRAMTM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
1.0
1.1
1.2
1.3
Remark
Advance
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Final
Final
Final
Final
Final
History
1. Initial document.
1. Delete the speed bins (FT : 7.5ns, 8.5ns / PP : 200MHz)
1. Change to the New JTAG scan order.
1. Add the comment about Vdd/Vddq wide by note on page 13.
1. Delete the 119 BGA package type.
1. Delete the 1.8V and 3.3V Vdd voltage level
( Change the part number to K7N6436(18)45M from K7N6436(18)31M )
1. Add the overshoot timing
1. Change ordering information
1. Add the current in the DC Elecrical Characteristics
1. change standby current value
1. Correct typo
Draft Date
Sep. 30. 2002
Oct. 8. 2002
Feb. 25, 2003
Mar. 10, 2003
Aug. 18, 2004
Oct. 20, 2004
Feb. 16, 2006
Apr. 03, 2006
Feb. 27, 2007
Mar. 25, 2008
Sep. 03, 2008
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 3 -
K7N641845M
Rev. 1.3 September 2008
72Mb NtRAM (Pipelined) Ordering Information
Note 1. P(Q,E,F) [Package type] : 100TQFP ; P-Pb Free, Q-Pb, 165FBGA ; E-Pb Free, F-Pb
2. C(I) [Operating Temperature] : C-Commercial, I-Industrial
Org. VDD (V) Speed (ns) Access Time (ns) Part Number RoHS Avail.
4Mx18 2.5 4.0 2.6 K7N641845M-P(Q,E,F)1C(I)225 √
2.5 6.0 3.5 K7N641845M-P(Q,E,F)1C(I)216 √
2Mx36 2.5 4.0 2.6 K7N643645M-P(Q,E,F)1C(I)225 √
2.5 6.0 3.5 K7N643645M-P(Q,E,F)1C(I)216 √
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 4 -
K7N641845M
Rev. 1.3 September 2008
2Mx36 & 4Mx18-Bit Pipelined NtRAMTM
The K7N643645M and K7N641845M are 75,497,472-bits Syn-
chronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N643645M and K7N641845M are implemented with
SAMSUNG′s high performance CMOS technology and is avail-
able in 100pin TQFP and 165FBGA packages. Multiple power
and ground pins minimize ground bounce.
GENERAL DESCRIPTIONFEATURES
• 2.5V ±5% Power Supply.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A.
• 165FBGA(11x15 ball aray) with body size of 15mmx17mm.
FAST ACCESS TIMES
PARAMETER Symbol -25 -16 Unit
Cycle Time tCYC 4.0 6.0 ns
Clock Access Time tCD 2.6 3.5 ns
Output Enable Access Time tOE 2.6 3.5 ns
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung.
LOGIC BLOCK DIAGRAM
WE
BW
x
CLK
CKE
CS
1
CS
2
CS
2
ADV
OE
ZZ
DQa
0
~ DQd
7
or
DQa
0
~ DQb
8
ADDRESS
ADDRESS
REGISTER
CONTROL
LOGIC
A
′
0
~A
′
1
36 or 18
DQPa ~ DQPd
OUTPUT
BUFFER
REGISTER
DATA-IN
REGISTER
DATA-IN
REGISTER
K
K
K
REGISTER
BURST
ADDRESS
COUNTER
WRITE
ADDRESS
REGISTER
WRITE
CONTROL
LOGIC
CONTROL
REGISTER
K
A [0:20]or
A [0:21]
LBO
A
2
~A
20
or
A
2
~A
21
A
0
~A
1
(x=a,b,c,d or a,b)
2Mx36, 4Mx18
MEMORY
ARRAY
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 5 -
K7N641845M
Rev. 1.3 September 2008
PIN CONFIGURATION(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
VDD
VDD
VDD
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
VDD
VDD
ZZ
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A6
A7
CS1
CS2
BWd
BWc
BWb
BWa
CS2
VDD
VSS
CLK
WE
CKE
OE
ADV
A18
A17
A8
81 A9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A16
A15
A14
A13
A12
A11
A10
A19
A20
VDD
VSS
N.C.
N.C.
A0
A1
A2
A3
A4
A5
31
LBO
PIN NAME
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.
A0 - A20
ADV
WE
CLK
CKE
CS1
CS2
CS2
BWx(x=a,b,c,d)
OE
ZZ
LBO
Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
32,33,34,35,36,37,42,
43,44,45,46,47,48,49,
50,81,82,83,84,99,
100
85
88
89
87
98
97
92
93,94,95,96
86
64
31
VDD
VSS
N.C.
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
VDDQ
VSSQ
Power Supply(2.5V)
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
(2.5V)
Output Ground
14,15,16,41,65,66,91
17,40,67,90
38,39
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
K7N643645M(2Mx36)
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 6 -
K7N641845M
Rev. 1.3 September 2008
PIN CONFIGURATION(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb8
DQb7
VSSQ
VDDQ
DQb6
DQb5
VDD
VDD
VDD
VSS
DQb4
DQb3
VDDQ
VSSQ
DQb2
DQb1
DQb0
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQa0
DQa1
DQa2
VSSQ
VDDQ
DQa3
DQa4
VSS
VDD
VDD
ZZ
DQa5
DQa6
VDDQ
VSSQ
DQa7
DQa8
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A6
A7
CS1
CS2
BWb
BWa
CS2
VDD
VSS
CLK
WE
CKE
OE
ADV
A19
A18
A8
81 A9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A17
A16
A15
A14
A13
A12
A11
A20
A21
VDD
VSS
N.C.
N.C.
A0
A1
A2
A3
A4
A5
31
LBO
K7N641845M(4Mx18)
N.C.
N.C.
PIN NAME
NOTE : A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.
A0 - A21
ADV
WE
CLK
CKE
CS1
CS2
CS2
BWx(x=a,b)
OE
ZZ
LBO
Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
32,33,34,35,36,37,42,
43,44,45,46,47,48,49,
50,80,81,82,83,84,99,
100
85
88
89
87
98
97
92
93,94
86
64
31
VDD
VSS
N.C.
DQa0~a8
DQb0~b8
VDDQ
VSSQ
Power Supply(2.5V)
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
(2.5V)
Output Ground
14,15,16,41,65,66,91
17,40,67,90
1,2,3,6,7,25,28,29,30,
38,39,51,52,53,56,57,
75,78,79,95,96
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 7 -
K7N641845M
Rev. 1.3 September 2008
165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)
PIN NAME
SYMBOL PIN NAME SYMBOL PIN NAME
A
A0,A1
ADV
WE
CLK
CKE
CS1
CS2
CS2
BWx
(x=a,b,c,d)
OE
ZZ
LBO
TCK
TMS
TDI
TDO
Address Inputs
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
VDD
VSS
N.C.
DQa
DQb
DQc
DQd
DQPa~Pd
VDDQ
Power Supply
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
K7N643645M(2Mx36)
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
** Checked NoConnect(NC) pins are resered for higher density address, i.e. 11B for 128Mb and 1A for 256Mb.
1 2 3 4 5 6 7 8 9 10 11
ANC** A CS1BWcBWbCS2CKE ADV A A NC
BNC A CS2 BWdBWaCLK WE OE A A NC**
CDQPc NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPb
DDQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
EDQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
FDQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
GDQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
HNC VDD NC VDD VSS VSS VSS VDD NC NC ZZ
JDQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
KDQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
LDQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
MDQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
NDQPd NC VDDQ VSS NC NC NC VSS VDDQ NC DQPa
PNCAAATDIA1*TDO A A A NC
RLBO AAATMSA0*TCKAAAA
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 8 -
K7N641845M
Rev. 1.3 September 2008
PIN NAME
SYMBOL PIN NAME SYMBOL PIN NAME
A
A0,A1
ADV
WE
CLK
CKE
CS1
CS2
CS2
BWx
(x=a,b)
OE
ZZ
LBO
TCK
TMS
TDI
TDO
Address Inputs
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
VDD
VSS
N.C.
DQa
DQb
DQPa, Pb
VDDQ
Power Supply
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)
K7N641845M(4Mx18)
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
** Checked NoConnect(NC) pins are resered for higher density address, i.e. 11B for 128Mb and 1A for 256Mb.
1 2 3 4 5 6 7 8 9 10 11
ANC** A CS1BWbNC CS2CKE ADV A A A
BNC A CS2 NC BWaCLK WE OE A A NC**
CNC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPa
DNC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa
ENC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa
FNC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa
GNC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa
HNC VDD NC VDD VSS VSS VSS VDD NC NC ZZ
JDQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC
KDQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC
LDQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC
MDQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC
NDQPb NC VDDQ VSS NC NC NC VSS VDDQ NC NC
PNCAAATDIA1*TDO A A A NC
RLBO AAATMSA0*TCKAAAA
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 9 -
K7N641845M
Rev. 1.3 September 2008
FUNCTION DESCRIPTION
BURST SEQUENCE TABLE (Interleaved Burst, LBO=High)
LBO PIN HIGH Case 1 Case 2 Case 3 Case 4
A1A0A1A0A1A0A1A0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
BQ TABLE (Linear Burst, LBO=Low)
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
LBO PIN LOW Case 1 Case 2 Case 3 Case 4
A1A0A1A0A1A0A1A0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
The K7N643645M and K7N641845M are NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-
lined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 10 -
K7N641845M
Rev. 1.3 September 2008
STATE DIAGRAM FOR NtRAMTM
BEGIN
WRITE
BURST
WRITE
BEGIN
READ
WRITE
DS
READ
BURST
READ
DS
WRITE
DS
READ
DS
READ
DS
WRITE
BURST
DESELECT
BURST
READ
BURST
WRITE
READ WRITE
BURST BURST
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does
not change the state of the device.
2. States change on the rising edge of the clock(CLK)
COMMAND ACTION
DS DESELECT
READ BEGIN READ
WRITE BEGIN WRITE
BURST
BEGIN READ
BEGIN WRITE
CONTINUE DESELECT
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 11 -
K7N641845M
Rev. 1.3 September 2008
SYNCHRONOUS TRUTH TABLE
Notes : 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by (↑).
3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins(ZZ and OE).
CS1CS2CS2ADV WE BWxOE CKE CLK ADDRESS ACCESSED OPERATION
HXXLXXX L ↑N/A Not Selected
XLXLXXX L ↑N/A Not Selected
XXHLXXX L ↑N/A Not Selected
XXXHXXX L ↑N/A Not Selected Continue
LHLLHXL L ↑External Address Begin Burst Read Cycle
XXXHXXL L ↑Next Address Continue Burst Read Cycle
LHLLHXH L ↑External Address NOP/Dummy Read
XXXHXXH L ↑Next Address Dummy Read
LHLLLLX L ↑External Address Begin Burst Write Cycle
XXXHXLX L ↑Next Address Continue Burst Write Cycle
LHLLLHX L ↑N/A NOP/Write Abort
XXXHXHX L ↑Next Address Write Abort
XXXXXXX H ↑Current Address Ignore Clock
WRITE TRUTH TABLE(x36)
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
WE BWaBWbBWcBWdOPERATION
HXXXX READ
L L H H H WRITE BYTE a
L H L H H WRITE BYTE b
L H H L H WRITE BYTE c
L H H H L WRITE BYTE d
LLLLL WRITE ALL BYTEs
L H H H H WRITE ABORT/NOP
TRUTH TABLES
WRITE TRUTH TABLE(x18)
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
WE BWaBWbOPERATION
H X X READ
L L H WRITE BYTE a
L H L WRITE BYTE b
L L L WRITE ALL BYTEs
L H H WRITE ABORT/NOP
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 12 -
K7N641845M
Rev. 1.3 September 2008
ASYNCHRONOUS TRUTH TABLE
OPERATION ZZ OE I/O STATUS
Sleep Mode H X High-Z
Read LL DQ
L H High-Z
Write L X Din, High-Z
Deselected L X High-Z
Notes
1. X means "Don′t Care".
2. Sleep Mode means power Sleep Mode of which stand-by current does
not depend on cycle time.
3. Deselected means power Sleep Mode of which stand-by current
depends on cycle time.
ABSOLUTE MAXIMUM RATINGS*
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER SYMBOL RATING UNIT
Voltage on VDD Supply Relative to VSS VDD -0.3 to 3.6 V
Voltage on Any Other Pin Relative to VSS VIN -0.3 to VDD+0.3 V
Power Dissipation PD1.6 W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature TOPR 0 to 70 °C
Storage Temperature Range Under Bias TBIAS -10 to 85 °C
OPERATING CONDITIONS(0°C ≤ TA ≤ 70°C)
*Note : VDD and VDDQ must be supplied with identical vlotage levels.
PARAMETER SYMBOL MIN Typ. MAX UNIT
Supply Voltage VDD 2.375 2.5 2.625 V
VDDQ 2.375 2.5 2.625 V
Ground VSS 000V
CAPACITANCE*(TA=25°C, f=1MHz)
*Note : Sampled not 100% tested.
PARAMETER SYMBOL TEST CONDITION TYP MAX UNIT
Input Capacitance CIN VIN=0V - TBD pF
Output Capacitance COUT VOUT=0V - TBD pF
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 13 -
K7N641845M
Rev. 1.3 September 2008
DC ELECTRICAL CHARACTERISTICS(VDD=2.5V ±5%, TA=0°C to +70°C)
Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.
2. Data states are all zero.
3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT NOTES
Input Leakage Current(except ZZ) IIL VDD=Max ; VIN=VSS to VDD -2 +2 µA
Output Leakage Current IOL Output Disabled, -2 +2 µA
Operating Current ICC VDD=Max IOUT=0mA
Cycle Time ≥ tCYC Min
-25 - 470 mA 1,2
-16 - 350
Standby Current
ISB
Device deselected, IOUT=0mA,
ZZ≤VIL, f=Max,
All Inputs≤0.2V or ≥ VDD-0.2V
-25 - 200
mA
-16 - 200
ISB1 Device deselected, IOUT=0mA, ZZ≤0.2V, f=0,
All Inputs=fixed (VDD-0.2V or 0.2V) - 170 mA
ISB2
Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,
f=Max, All Inputs≤VIL or ≥VIH - 170 mA
Output Low Voltage VOL IOL=1.0mA - 0.4 V
Output High Voltage VOH IOH=-1.0mA 2.0 - V
Input Low Voltage VIL -0.3* 0.7 V
Input High Voltage VIH 1.7 VDD+0.3** V 3
(TA=0 to 70°C, VDD=2.5V ±5%, unless otherwise specified)
TEST CONDITIONS
PARAMETER VALUE
Input Pulse Level 0 to 2.5V
Input Rise and Fall Time(Measured at 20% to 80%) 1.0V/ns
Input and Output Timing Reference Levels VDDQ/2
Output Load See Fig. 1
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
5pF*
+2.5V
1667Ω
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Zo=50Ω
RL=50Ω
VL=VDDQ/2
30pF*
1538Ω
VDDQ
VIL
VDDQ+1.0V
20% tCYC(MIN)
VSS
VIH
VSS-1.0V
20% tCYC(MIN)
Undershoot TimingOvershoot Timing
VDDQ+0.5V
VSS-0.5V
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 14 -
K7N641845M
Rev. 1.3 September 2008
AC TIMING CHARACTERISTICS
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges
when ADV is sampled low and CS is sampled low.
All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
4. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC.
The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,2.625V) than tHZC, which is a Max. parameter(worst case at 70°C,2.375V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
PARAMETER SYMBOL -25 -16 UNIT
MIN MAX MIN MAX
Cycle Time tCYC 4.0 - 6.0 - ns
Clock Access Time tCD - 2.6 - 3.5 ns
Output Enable to Data Valid tOE - 2.6 - 3.5 ns
Clock High to Output Low-Z tLZC 1.5 - 1.5 - ns
Output Hold from Clock High tOH 1.5 - 1.5 - ns
Output Enable Low to Output Low-Z tLZOE 0-0-ns
Output Enable High to Output High-Z tHZOE - 2.6 - 3.0 ns
Clock High to Output High-Z tHZC - 2.6 - 3.0 ns
Clock High Pulse Width tCH 1.7 - 2.2 - ns
Clock Low Pulse Width tCL 1.7 - 2.2 - ns
Address Setup to Clock High tAS 1.2 -1.5 -ns
CKE Setup to Clock High tCES 1.2 -1.5 -ns
Data Setup to Clock High tDS 1.2 -1.5 -ns
Write Setup to Clock High (WE, BWX)tWS 1.2 -1.5 -ns
Address Advance Setup to Clock High tADVS 1.2 -1.5 -ns
Chip Select Setup to Clock High tCSS 1.2 -1.5 -ns
Address Hold from Clock High tAH 0.3 - 0.5 - ns
CKE Hold from Clock High tCEH 0.3 - 0.5 - ns
Data Hold from Clock High tDH 0.3 - 0.5 - ns
Write Hold from Clock High (WE, BWX)tWH 0.3 - 0.5 - ns
Address Advance Hold from Clock High tADVH 0.3 - 0.5 - ns
Chip Select Hold from Clock High tCSH 0.3 - 0.5 - ns
ZZ High to Power Down tPDS 2-2-cycle
ZZ Low to Power Up tPUS 2-2-cycle
(VDD=2.5V ±5%, TA=0 to 70°C)
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 15 -
K7N641845M
Rev. 1.3 September 2008
SLEEP MODE
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP
MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-
ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given
while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS
Current during SLEEP MODE ZZ ≥ VIH ISB2 170 mA
ZZ active to input ignored tPDS 2 cycle
ZZ inactive to input sampled tPUS 2 cycle
ZZ active to SLEEP current tZZI 2 cycle
ZZ inactive to exit SLEEP current tRZZI 0
K
tPDS
ZZ setup cycle
tRZZI
ZZ
Isupply
All inputs
(except ZZ)
Outputs
(Q)
tZZI
tPUS
ZZ recovery cycle
Deselect or Read Only
High-Z
DON′T CARE
ISB2
SLEEP MODE WAVEFORM
Normal
operation
cycle
Deselect or Read Only
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 16 -
K7N641845M
Rev. 1.3 September 2008
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
TAP Controller State Diagram
JTAG Block Diagram
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg.
Control Signals
TAP Controller
TDO
TDI
TMS
TCK
Test Logic Reset
Run Test Idle
011
1
1
0
0
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
1
1
1
1
JTAG Instruction Coding
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
IR2 IR1 IR0 Instruction TDO Output Notes
0 0 0 EXTEST Boundary Scan Register 1
0 0 1 IDCODE Identification Register 3
0 1 0 SAMPLE-Z Boundary Scan Register 2
0 1 1 BYPASS Bypass Register 4
1 0 0 SAMPLE Boundary Scan Register 5
1 0 1 RESERVED Do Not Use 6
1 1 0 BYPASS Bypass Register 4
1 1 1 BYPASS Bypass Register 4
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 17 -
K7N641845M
Rev. 1.3 September 2008
Note: 1. NC and Vss pins included in the scan exit order are read as "X" ( i.e. don′t care).
BIT PIN ID BIT PIN ID
79 1R
80 2R
81 3P
82 3R
83 2P
84 4R
85 4P
86 5N
87 6P
88 6R
89 Internal
BIT PIN ID BIT PIN ID
16N408A
27N418B
3 10N 42 7A
4 11P 43 7B
58P446B
68R456A
79R465B
89P475A
9 10P 48 4A
10 10R 49 4B
11 11R 50 3B
12 11H 51 3A
13 11N 52 2A
14 11M 53 2B
15 11L 54 2C
16 11K 55 1B
17 11J 56 1A
18 10M 57 1C
19 10L 58 1D
20 10K 59 1E
21 10J 60 1F
22 9H 61 1G
23 10H 62 2D
24 11G 63 2E
25 11F 64 2F
26 11E 65 2G
27 11D 66 1H
28 10G 67 3H
29 10F 68 1J
30 10E 69 1K
31 10D 70 1L
32 11C 71 1M
33 11A 72 2J
34 11B 73 2K
35 10A 74 2L
36 10B 75 2M
37 9A 76 1N
38 9B 77 2N
39 10C 78 1P
BOUNDARY SCAN EXIT ORDER
ID REGISTER DEFINITION
Part Revision Number
(31:28)
Part Configuration
(27:18)
Vendor Definition
(17:12)
Samsung JEDEC Code
(11: 1) Start Bit(0)
2Mx36 0000 01001 00100 XXXXXX 00001001110 1
4Mx18 0000 01010 00011 XXXXXX 00001001110 1
SCAN REGISTER DEFINITION
Part Instruction Register Bypass Register ID Register Boundary Scan
2Mx36 3 bits 1 bits 32 bits 89 bits
4Mx18 3 bits 1 bits 32 bits 89 bits
SCAN INFORMATION (165 FBGA )
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 18 -
K7N641845M
Rev. 1.3 September 2008
JTAG DC OPERATING CONDITIONS
NOTE : The input level of SRAM pin is to follow the SRAM DC specification.
Parameter Symbol Min Typ Max Unit Note
Power Supply Voltage VDD 2.375 2.5 2.625 V
Input High Level VIH 1.7 - VDD+0.3 V
Input Low Level VIL -0.3 - 0.7 V
Output High Voltage VOH 2.0 - - V
Output Low Voltage VOL --0.4V
JTAG TIMING DIAGRAM
JTAG AC Characteristics
Parameter Symbol Min Max Unit Note
TCK Cycle Time tCHCH 50 - ns
TCK High Pulse Width tCHCL 20 - ns
TCK Low Pulse Width tCLCH 20 - ns
TMS Input Setup Time tMVCH 5-ns
TMS Input Hold Time tCHMX 5-ns
TDI Input Setup Time tDVCH 5-ns
TDI Input Hold Time tCHDX 5-ns
SRAM Input Setup Time tSVCH 5-ns
SRAM Input Hold Time tCHSX 5-ns
Clock Low to Output Valid tCLQV 010ns
JTAG AC TEST CONDITIONS
Parameter Symbol Min Unit Note
Input High/Low Level VIH/VIL 2.5/0 V
Input Rise/Fall Time TR/TF 1.0/1.0 ns
Input and Output Timing Reference Level VDDQ/2 V
TCK
TMS
TDI
PI
tCHCH
tMVCH tCHMX
tCHCL tCLCH
tDVCH tCHDX
tCLQV
TDO
(SRAM)
tSVCH tCHSX
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 19 -
K7N641845M
Rev. 1.3 September 2008
Clock
CKE
Address
WRITE
CS
ADV
OE
Data Out
TIMING WAVEFORM OF READ CYCLE
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tCH tCL
tCES tCEH
tAS tAH
A1 A2 A3
tWS tWH
tCSS tCSH
tOE tHZOE
tLZOE
tCD
tOH tHZC
Q3-4Q3-3Q3-2Q3-1Q2-4Q2-3Q2-2Q2-1
Q1-1
Don′t Care
Undefined
tCYC
tADVS tADVH
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 20 -
K7N641845M
Rev. 1.3 September 2008
TIMING WAVEFORM OF WRTE CYCLE
Clock
Address
WRITE
CS
ADV
Data In
tCH tCL
A2 A3
D2-1D1-1 D2-2 D2-3 D2-4 D3-1 D3-2 D3-3
OE
Data Out
tDS tDH
Don′t Care
Undefined
tCYC
CKE
A1
D3-4
tCES tCEH
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
Q0-4
tHZOE
Q0-3
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 21 -
K7N641845M
Rev. 1.3 September 2008
TIMING WAVEFORM OF SINGLE READ/WRITE
Clock
Address
WRITE
CS
ADV
OE
Data In
tCH tCL
tDS tDH
Data Out
A2 A4 A5
D2
tOE
tLZOE
Q1
Don′t Care
Undefined
tCYC
CKE
tCES tCEH
A1 A3 A7A6
Q3 Q4 Q7Q6
D5
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
A9
A8
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 22 -
K7N641845M
Rev. 1.3 September 2008
TIMING WAVEFORM OF CKE OPERATION
Clock
Address
WRITE
CS
ADV
OE
Data In
tCH tCL
Data Out
A1 A2 A3 A4 A5
tCES tCEH
Don′t Care
Undefined
tCYC
CKE
tDS tDH
D2
Q4Q1
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tCD
tLZC
tHZC
Q3
A6
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 23 -
K7N641845M
Rev. 1.3 September 2008
TIMING WAVEFORM OF CS OPERATION
Clock
Address
WRITE
CS
ADV
OE
Data In
tCH tCL
Data Out
A1 A2 A3 A4 A5
Don′t Care
Undefined
tCYC
CKE
D5
Q4
tCES tCEH
Q1 Q2
tOE
tLZOE
D3
tCD
tLZC
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tHZC
tDH
tDS
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 24 -
K7N641845M
Rev. 1.3 September 2008
PACKAGE DIMENSIONS
0.10 MAX
0~8
°
22.00
±
0.30
20.00
±
0.20
16.00
±
0.30
14.00
±
0.20
1.40
±
0.10
1.60 MAX
0.05 MIN
(0.58)
0.50
±
0.10
#1
(0.83)
0.50
±
0.10
100-TQFP-1420A
0.65 0.30
±
0.10
0.10 MAX
+ 0.10
- 0.05
0.127
Units ; millimeters/Inches
K7N643645M
2Mx36 & 4Mx18 Pipelined NtRAMTM
- 25 -
K7N641845M
Rev. 1.3 September 2008
165 FBGA PACKAGE DIMENSIONS
CSide View
15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array
F
A
∅ H
GBBottom View
Top View
A
B
D
E
E
Symbol Value Units Note Symbol Value Units Note
A17 ± 0.1 mm E1.0 mm
B15 ± 0.1 mm F14.0 mm
C1.3 ± 0.1 mm G10.0 mm
D0.35 ± 0.05 mm H0.50 ± 0.05 mm
