Agilent 0.6 Amp Output Current IGBT
Gate Drive Optocoupler
Data Sheet
Features
• 0.6 A maximum peak output
current
• 0.5 A minimum peak output
current
• 15 kV/µs minimum Common Mode
Rejection (CMR) at VCM = 1500 V
• 1.0 V maximum low level output
voltage (VOL) eliminates need for
negative gate drive
•I
CC = 5 mA maximum supply
current
• Under Voltage Lock-Out protection
(UVLO) with hysteresis
• Wide operating VCC range:
15 to 30 Volts
• 0.5 µs maximum propagation delay
•±0.35 µs maximum delay between
devices/channels
• Industrial temperature range:
-40°C to 100°C
• HCPL-315J: Channel One to
Channel Two output isolation =
1500 Vrms/1 min.
• Safety and Regulatory Approval:
UL Recognized (UL1577)
3750 Vrms/1 min.
IEC/EN/DIN EN 60747-5-2
Approved
VIORM = 630 Vpeak
(HCPL-3150 Option 060 only)
VIORM = 891 Vpeak (HCPL-315J)
CSA Certified
Applications
• Isolated IGBT/MOSFET gate drive
• AC and brushless DC motor drives
• Industrial inverters
• Switch Mode Power Supplies
(SMPS)
• Uninterruptable Power Supplies
(UPS)
HCPL-3150 (Single Channel)
HCPL-315J (Dual Channel)
A 0.1
µ
F bypass capacitor must be connected between the VCC and
VEE pins for each channel.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.
Functional Diagram
TRUTH TABLE
VCC - VEE VCC - VEE
“Positive Going” “Negative-Going”
LED (i.e., Turn-On) (i.e., Turn-Off) VO
OFF 0 - 30 V 0 - 30 V LOW
ON 0 - 11 V 0 - 9.5 V LOW
ON 11 - 13.5 V 9.5 - 12 V TRANSITION
ON 13.5 - 30 V 12 - 30 V HIGH
1
3
SHIELD
2
4
8
6
7
5
N/C
CATHODE
ANODE
N/C
VCC
VO
VO
VEE
HCPL-3150
1
3SHIELD
2
8
16
14
15
9
N/C
CATHODE
ANODE
N/C
VCC
VEE
VO
VEE
7
6
10
11
CATHODE
ANODE
VO
VCC
SHIELD
HCPL-315J
Description
The HCPL-315X consists of a LED
optically coupled to an integrated
circuit with a power output stage.
This optocoupler is ideally suited
for driving power IGBTs and
MOSFETs used in motor control
inverter applications. The high
operating voltage range of the
output stage provides the drive
voltages required by gate
controlled devices. The voltage
and current supplied by this
optocoupler makes it ideally
suited for directly driving IGBTs
with ratings up to 1200 V/50 A.
For IGBTs with higher ratings, the
HCPL-3150/315J can be used to
drive a discrete power stage
which drives the IGBT gate.
2
Package Outline Drawings
Standard DIP Package 9.40 (0.370)
9.90 (0.390)
PIN ONE
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A 3150 Z
YYWW
DATE CODE
0.76 (0.030)
1.40 (0.055) 2.28 (0.090)
2.80 (0.110)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
6.10 (0.240)
6.60 (0.260)
0.20 (0.008)
0.33 (0.013)
5° TYP.
7.36 (0.290)
7.88 (0.310)
1
2
3
4
8
7
6
5
5678
4321
GND1
VDD1
VIN+
VIN–
GND2
VDD2
VOUT+
VOUT–
PIN DIAGRAM
PIN ONE DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060.
OPTION NUMBERS 300 AND 500 NOT MARKED.
OPTION CODE*
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
3.56 ± 0.13
(0.140 ± 0.005)
Ordering Information
Specify Part Number followed by Option Number (if desired)
Example
HCPL-315Y#XXXX
No Option = Standard DIP package, 50 per tube.
060 = IEC/EN/DIN EN 60747-5-2 VIORM = 630 Vpeak Option, 50 per tube.
(HCPL-3150 only)
300 = Gull Wing Surface Mount Option, 50 per tube. (HCPL-3150 only)
500 = Tape and Reel Packaging Option. HCPL-3150; 1000 per reel.
HCPL-315J; 850 per reel.
XXXE = Lead Free Option
f = Single Channel, 8-pin PDIP.
J = Dual Channel, SO16.
Option data sheets available. Contact Agilent sales representative or authorized distributor.
Remarks: The notation “#” is used for existing products, while (new) products launched since 15th July 2001 and lead free option
will use “–”.
Selection Guide: Invertor Gate Drive Optoisolators
Widebody
Package Type 8-Pin DIP (300 mil) (400 mil) Small Outline SO-16
Part Number HCPL-3150 HCPL-3120 HCPL-J312 HCPL-J314 HCNW-3120 HCPL-315J HCPL-316J HCPL-314J
Number of Channels 1 1 1 1 1 2 1 2
IEC/EN/DIN EN VIORM VIORM VIORM VIORM
60747-5-2 630 Vpeak 891Vpeak 1414 Vpeak 891 Vpeak
Approvals Option 060
UL Approval 3750 3750 5000 3750
Vrms/1 min. Vrms/1 min. Vrms/1min. Vrms/1 min.
Output Peak Current 0.6A 2.5A 2.5A 0.6A 2.5A 0.6A 2.5A 0.6A
CMR (minimum) 15 kV/µs 10 kV/µs 15 kV/µs 10 kV/µs
UVLO Yes No Yes No
Fault Status No Yes No
3
Package Outline Drawings Gull-Wing
Surface-Mount Option 300
16 - Lead Surface Mount
0.635 ± 0.25
(0.025 ± 0.010) 12° NOM.
0.20 (0.008)
0.33 (0.013)
9.65 ± 0.25
(0.380 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.65 ± 0.25
(0.380 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
MOLDED
1.080 ± 0.320
(0.043 ± 0.013)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.540
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED):
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
xx.xx = 0.01
xx.xxx = 0.005
A 3150 Z
YYWW
*MARKING CODE LETTER FOR OPTION
NUMBERS.
"V" = OPTION 060.
OPTION NUMBERS 300 AND 500 NOT MARKED.
OPTION
CODE* 1.016 (0.040)
1.27 (0.050)
10.9 (0.430)
2.0 (0.080)
LAND PATTERN RECOMMENDATION
3.56 ± 0.13
(0.140 ± 0.005)
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
HCPL-315J
10.36 ± 0.20
(0.408 ± 0.008) (0.295 ± 0.004)
7.49 ± 0.10
(0.406 ± 0.007)
10.31 ± 0.18
(0.138 ± 0.005)
3.51 ± 0.13
(0.018)
0.457 (0.050)
1.27
9°
16 15 14 11 10 9
123 678
VIEW
FROM
PIN 16
VIEW
FROM
PIN 1
(0.025 MIN.)
0.64
(0.408 ± 0.008)
10.36 ± 0.20
(0.0091 – 0.0125)
0.23 – 0.32
(0.345 ± 0.008)
8.76 ± 0.20
ALL LEADS TO BE COPLANAR ± (0.002 INCHES) 0.05 mm.
DIMENSIONS IN (INCHES) AND MILLIMETERS.
0 - 8°
VCC1
VO1
GND1
VCC2
VO2
GND2
NC
VIN1
V1
VIN2
V2
NC
(0.004 – 0.011)
0.10 – 0.30
STANDOFF
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
(0.458) 11.63
(0.085) 2.16
(0.025) 0.64
LAND PATTERN RECOMMENDATION
4
Solder Reflow Thermal Profile
0
TIME (SECONDS)
TEMPERATURE (°C)
200
100
50 150100 200 250
300
0
30
SEC.
50 SEC.
30
SEC.
160°C
140°C
150°C
PEAK
TEMP.
245°C
PEAK
TEMP.
240°CPEAK
TEMP.
230°C
SOLDERING
TIME
200°C
PREHEATING TIME
150°C, 90 + 30 SEC.
2.5°C ± 0.5°C/SEC.
3°C + 1°C/–0.5°C
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
Recommended Pb-Free IR Profile
217 °C
RAMP-DOWN
6 °C/SEC. MAX.
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
260 +0/-5 °C
t 25 °C to PEAK
60 to 150 SEC.
20-40 SEC.
TIME WITHIN 5 °C of ACTU AL
PEAK TEMPERA TURE
t
p
t
s
PREHEAT
60 to 180 SEC.
t
L
T
L
T
smax
T
smin
25
T
p
TIME
TEMPERATURE
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
T
smax
= 200 °C, T
smin
= 150 °C
Regulatory Information
The HCPL-3150 and HCPL-315J
have been approved by the
following organizations:
UL
Recognized under UL 1577,
Component Recognition
Program, File E55361.
CSA
Approved under CSA
Component Acceptance Notice
#5, File CA 88324.
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01.
(Option 060 and HCPL-315J
only)
5
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics
Description Symbol HCPL-3150#060 HCPL-315J** Unit
Installation classification per DIN VDE
0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms I-IV
for rated mains voltage ≤ 300 Vrms I-IV I-III
for rated mains voltage ≤ 600 Vrms I-III I-II
Climatic Classification 55/100/21 55/100/21
Pollution Degree (DIN VDE 0110/1.89) 2 2
Maximum Working Insulation Voltage VIORM 630 891 Vpeak
Input to Output Test V oltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with VPR 1181 1670 Vpeak
tm = 1 sec, Partial discharge < 5 pC
Input to Output Test V oltage, Method a*
VIORM x 1. 5 = VPR, Type and Sample Test, VPR 945 1336 Vpeak
tm = 60 sec, Partial discharge < 5 pC
Highest Allowable Overvoltage* VIOTM 6000 6000 Vpeak
(Transient Overvoltage tini = 10 sec)
Safety-Limiting Values – Maximum Values Allowed
in the Event of a Failure, also see Figure 37,
Thermal Derating Curve.
Case Temperature TS175 175 °C
Input Current IS, INPUT 230 400 mA
Output Power PS, OUTPUT 600 1200 mW
Insulation Resistance at TS, VIO = 500 V RS≥ 109≥ 109Ω
**Approval Pending.
*Refer to the front of the optocoupler section of the current Catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2, for a
detailed description of Method a and Method b partial discharge test profiles.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
6
Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Power Supply Voltage (VCC - VEE) 15 30 Volts
Input Current (ON) IF(ON) 716mA
Input Voltage (OFF) VF(OFF) -3.0 0.8 V
Operating Temperature TA-40 100 °C
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Note
Storage Temperature TS-55 125 °C
Operating Temperature TA-40 100 °C
Average Input Current IF(AVG) 25 mA 1, 16
Peak Transient Input Current IF(TRAN) 1.0 A
(<1 µs pulse width, 300 pps)
Reverse Input V oltage VR5 Volts
“High” Peak Output Current IOH(PEAK) 0.6 A 2, 16
“Low” Peak Output Current IOL(PEAK) 0.6 A 2, 16
Supply Voltage (VCC - VEE) 0 35 Volts
Output Voltage VO(PEAK) 0V
CC Volts
Output Power Dissipation PO250 mW 3, 16
Total Power Dissipation PT295 mW 4, 16
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile See Package Outline Drawings Section
Insulation and Safety Related Specifications
Parameter Symbol HCPL-3150 HCPL-315J Units Conditions
Minimum External Air Gap L(101) 7.1 8.3 mm Measured from input terminals to
(External Clearance) output terminals, shortest distance
through air.
Minimum External Tracking L(102) 7.4 8.3 mm Measured from input terminals to
(External Creepage) output erminals, shortest distance
path along body.
Minimum Internal Plastic 0.08 ≥0.5 mm Through insulation distance conductor
Gap (Internal Clearance) to conductor.
Tracking Resistance CTI ≥175 ≥175 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking
Index)
Isolation Group IIIa IIIa Material Group (DIN VDE 0110, 1/89,
Table 1)
Option 300 - surface mount classification is Class A in accordance wtih CECC 00802.
7
Electrical Specifications (DC)
Over recommended operating conditions (TA = -40 to 100°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V, VCC = 15 to 30 V,
VEE = Ground, each channel) unless otherwise specified.
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
High Level Output IOH 0.1 0.4 A VO = (VCC - 4 V) 2, 3, 5
Current 0.5 VO = (VCC - 15 V) 17 2
Low Level Output IOL 0.1 0.6 A VO = (VEE + 2.5 V) 5, 6, 5
Current 0.5 VO = (VEE + 15 V) 18 2
High Level Output VOH (VCC - 4) (VCC - 3) V IO = -100 mA 1, 3, 6, 7
Voltage 19
Low Level Output VOL 0.4 1.0 V IO = 100 mA 4, 6,
Voltage 20
High Level Supply ICCH 2.5 5.0 mA Output Open, 7, 8 16
Current IF = 7 to 16 mA
Low Level Supply ICCL 2.7 5.0 mA Output Open,
Current VF = -3.0 to +0.8 V
Threshold Input IFLH 2.2 5.0 mA HCPL-3150 IO = 0 mA, 9, 15,
Current Low to High 2.6 6.4 HCPL-315J VO > 5 V 21
Threshold Input VFHL 0.8 V
Voltage High to Low
Input Forward Voltage VF1.2 1.5 1.8 V HCPL-3150 IF = 10 mA 16
1.6 1.95 HCPL-315J
Temperature Coefficient ∆VF/∆TA-1.6 mV/°CI
F = 10 mA
of Forward Voltage
Input Reverse BVR5 V HCPL-3150 IR = 10 µA
Breakdown Voltage 3 HCPL-315J IR = 10 µA
Input Capacitance CIN 70 pF f = 1 MHz, VF = 0 V
UVLO Threshold VUVLO+ 11.0 12.3 13.5 V VO > 5 V, 22,
VUVLO- 9.5 10.7 12.0 IF = 10 mA 36
UVLO Hysteresis UVLOHYS 1.6 V
*All typical values at TA = 25°C and V CC - VEE = 30 V, unless otherwise noted.
8
Switching Specifications (AC)
Over recommended operating conditions (TA = -40 to 100°C, I F(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V, VCC = 15 to 30 V,
VEE = Ground) unless otherwise specified.
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Propagation Delay Time tPLH 0.10 0.30 0.50 µs Rg = 47 Ω, 10, 11, 14
to High Output Level Cg = 3 nF, 12, 13,
Propagation Delay Time tPHL 0.10 0.30 0.50 µsf = 10 kHz, 14, 23
to Low Output Level Duty Cycle = 50%
Pulse Width Distortion PWD 0.3 µs15
Propagation Delay PDD -0.35 0.35 µs 34, 36 10
Difference Between Any (tPHL - tPLH)
Two Parts or Channels
Rise Time tr0.1 µs23
Fall Time tf0.1 µs
UVLO Turn On Delay tUVLO ON 0.8 µsV
O > 5 V , IF = 10 m A 22
UVLO Turn Off Delay tUVLO OFF 0.6 VO < 5 V , IF = 10 m A
Output High Level |CMH| 15 30 kV/µsT
A = 25°C, 24 11, 12
Common Mode Transient IF = 10 to 16 mA,
Immunity VCM = 1500 V ,
VCC = 30 V
Output Low Level |CML| 15 30 kV/µsT
A = 25°C, 11, 13
Common Mode Transient VCM = 1500 V,
Immunity VF = 0 V, VCC = 30 V
9
Package Characteristics (each channel, unless otherwise specified)
Parameter Symbol Device Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary VISO HCPL-3150 3750 VRMS RH < 50%, t = 1 min., 8, 9
Withstand Voltage** HCPL-315J 3750 TA = 25°C
Output-Output Momentary VO-O HCPL-315J 1500 Vrms RH < 50%, t = 1 min., 17
Withstand Voltage** TA = 25°C
Resistance (Input-Output) RI-O 1012 ΩVI-O = 500 VDC 9
Capacitance (Input-Output) CI-O HCPL-3150 0.6 pF f = 1 MHz
HCPL-315J 1.3
LED-to-Case Thermal qLC HCPL-3150 391 °C/W Thermocouple 28 18
Resistance located at center
LED-to-Detector Thermal qLD HCPL-3150 439 °C/W underside of package
Resistance
Detector-to-Case Thermal qDC HCPL-3150 119 °C/W
Resistance
*All typical values at T A = 25 °C and VCC - VEE = 30 V, unless otherwise noted.
**The Input-Output/Output-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output/
output-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Agilent Application
Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
Notes:
1. Derate linearly above 70°C free-air
temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs,
maximum duty cycle = 0.2%. This
value is intended to allow for
component tolerances for designs
with IO peak minimum = 2.0 A. See
Applications section for additional
details on limiting IOH peak.
3. Derate linearly above 70°C free-air
temperature at a rate of 4.8 mW/°C.
4. Derate linearly above 70°C free-air
temperature at a rate of 5.4 mW/°C.
The maximum LED junction tem-
perature should not exceed 125°C.
5. Maximum pulse width = 50 µs,
maximum duty cycle = 0.5%.
6. In this test V
OH is measured with a dc
load current. When driving
capacitive loads VOH will approach
VCC as IOH approaches zero amps.
7. Maximum pulse width = 1 ms,
maximum duty cycle = 20%.
8. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥4500 Vrms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
9. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥4500 Vrms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
10. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥6000 Vrms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
11. Device considered a two-terminal
device: pins 1, 2, 3, and 4 shorted
together and pins 5, 6, 7, and 8
shorted together.
12. The difference between tPHL and tPLH
between any two HCPL-3120 parts
under the same test condition.
13. Pins 1 and 4 need to be connected to
LED common.
14. Common mode transient immunity
in the high state is the maximum
tolerable dVCM/dt of the common
mode pulse, VCM, to assure that the
output will remain in the high state
(i.e., VO> 15.0 V).
15. Common mode transient immunity
in a low state is the maximum
tolerable dVCM/dt of the common
mode pulse, VCM, to assure that the
output will remain in a low state (i.e.,
VO< 1.0 V).
16. This load condition approximates
the gate load of a 1200 V/75A IGBT.
17. Pulse Width Distortion (PWD) is
defined as |tPHL-tPLH| for any given
device.
10
Figure 4. VOL vs. Temperature. Figure 5. IOL vs. Temperature. Figure 6. VOL vs. IOL.
I
OL
– OUTPUT LOW CURRENT – A
-40
0
T
A
– TEMPERATURE – °C
100
0.8
0.4
-20
1.0
02040
0.2
60 80
V
F(OFF)
= -3.0 to 0.8 V
V
OUT
= 2.5 V
V
CC
= 15 to 30 V
V
EE
= 0 V
0.6
V
OL
– OUTPUT LOW VOLTAGE – V
-40
0
T
A
– TEMPERATURE – °C
100
0.8
0.6
-20
1.0
02040
0.2
60 80
V
F(OFF)
= -3.0 to 0.8 V
I
OUT
= 100 mA
V
CC
= 15 to 30 V
V
EE
= 0 V
0.4
V
OL
– OUTPUT LOW VOLTAGE – V
0
0
I
OL
– OUTPUT LOW CURRENT – A
1.0
4
0.2
5
0.4 0.6
1
0.8
V
F(OFF)
= -3.0 to 0.8 V
V
CC
= 15 to 30 V
V
EE
= 0 V
2
100 °C
25 °C
-40 °C
3
Figure 1. VOH vs. Temperature. Figure 2. IOH vs. Temperature. Figure 3. VOH vs. IOH.
(V
OH
- V
CC
) – HIGH OUTPUT VOLTAGE DROP – V
-40
-4
T
A
– TEMPERATURE – °C
100
-1
-2
-20
0
02040
-3
60 80
I
F
= 7 to 16 mA
I
OUT
= -100 mA
V
CC
= 15 to 30 V
V
EE
= 0 V
IOH – OUTPUT HIGH CURRENT – A
-40
0.25
TA – TEMPERATURE – °C
100
0.45
0.40
-20
0.50
02040
0.30
60 80
IF = 7 to 16 mA
VOUT = VCC - 4 V
VCC = 15 to 30 V
VEE = 0 V
0.35
(V
OH
- V
CC
) – OUTPUT HIGH VOLTAGE DROP – V
0
-6
I
OH
– OUTPUT HIGH CURRENT – A
1.0
-2
-3
0.2
-1
0.4 0.6
-5
0.8
I
F
= 7 to 16 mA
V
CC
= 15 to 30 V
V
EE
= 0 V
-4
100 °C
25 °C
-40 °C
ICC – SUPPLY CURRENT – mA
-40
1.5
TA – TEMPERATURE – °C
100
3.0
2.5
-20
3.5
02040
2.0
60 80
VCC = 30 V
VEE = 0 V
IF = 10 mA for ICCH
IF = 0 mA for ICCL
ICCH
ICCL
I
CC
– SUPPLY CURRENT – mA
15
1.5
V
CC
– SUPPLY VOLTAGE – V
30
3.0
2.5
3.5
20
2.0
25
I
F
= 10 mA for I
CCH
I
F
= 0 mA for I
CCL
T
A
= 25 °C
V
EE
= 0 V
I
CCH
I
CCL
I
FLH
– LOW TO HIGH CURRENT THRESHOLD – mA
-40
0
T
A
– TEMPERATURE – °C
100
3
2
-20
4
02040
1
60 80
5V
CC
= 15 TO 30 V
V
EE
= 0 V
OUTPUT = OPEN
Figure 7. ICC vs. Temperature. Figure 8. ICC vs. VCC. Figure 9. IFLH vs. Temperature.
11
Figure 16. Input Current vs. Forward Voltage.
I
F
– FORWARD CURRENT – mA
1.10
0.001
V
F
– FORWARD VOLTAGE – V
1.60
10
1.0
0.1
1.20
1000
1.30 1.40 1.50
T
A
= 25°C
I
F
V
F
+
–
0.01
100
VO – OUTPUT VOLTAGE – V
0
0
IF – FORWARD LED CURRENT – mA
5
25
15
1
30
2
5
34
20
10
Figure 15. Transfer Characteristics.Figure 14. Propagation Delay vs. Cg.Figure 13. Propagation Delay vs. Rg.
Figure 10. Propagation Delay vs. VCC. Figure 11. Propagation Delay vs. IF. Figure 12. Propagation Delay vs.
Temperature.
T
p
– PROPAGATION DELAY – ns
15
100
V
CC
– SUPPLY VOLTAGE – V
30
400
300
500
20
200
25
I
F
= 10 mA
T
A
= 25 °C
Rg = 47 Ω
Cg = 3 nF
DUTY CYCLE = 50%
f = 10 kHz
T
PLH
T
PHL
T
p
– PROPAGATION DELAY – ns
6
100
I
F
– FORWARD LED CURRENT – mA
16
400
300
500
10
200
12
V
CC
= 30 V, V
EE
= 0 V
Rg = 47 Ω, Cg = 3 nF
T
A
= 25 °C
DUTY CYCLE = 50%
f = 10 kHz
T
PLH
T
PHL
148
T
p
– PROPAGATION DELAY – ns
-40
100
T
A
– TEMPERATURE – °C
100
400
300
-20
500
02040
200
60 80
T
PLH
T
PHL
I
F(ON)
= 10 mA
I
F(OFF)
= 0 mA
V
CC
= 30 V, V
EE
= 0 V
Rg = 47 Ω, Cg = 3 nF
DUTY CYCLE = 50%
f = 10 kHz
T
p
– PROPAGATION DELAY – ns
0
100
Rg – SERIES LOAD RESISTANCE – Ω
200
400
300
50
500
100
200
150
T
PLH
T
PHL
V
CC
= 30 V, V
EE
= 0 V
T
A
= 25 °C
I
F
= 10 mA
Cg = 3 nF
DUTY CYCLE = 50%
f = 10 kHz
T
p
– PROPAGATION DELAY – ns
0
100
Cg – LOAD CAPACITANCE – nF
100
400
300
20
500
40
200
60 80
T
PLH
T
PHL
V
CC
= 30 V, V
EE
= 0 V
T
A
= 25 °C
I
F
= 10 mA
Rg = 47 Ω
DUTY CYCLE = 50%
f = 10 kHz
12
Figure 22. UVLO Test Circuit.
0.1 µF
VCC = 15
to 30 V
1
3
IF = 7 to
16 mA +
–
2
4
8
6
7
5
100 mA
VOH
0.1 µF
VCC = 15
to 30 V
1
3
IF+
–
2
4
8
6
7
5
VO > 5 V
Figure 17. IOH Test Circuit.
0.1 µF
VCC = 15
to 30 V
1
3
IF = 7 to
16 mA +
–
2
4
8
6
7
5
+
–4 V
IOH
Figure 18. IOL Test Circuit.
Figure 19. VOH Test Circuit.
0.1 µF
VCC = 15
to 30 V
1
3
+
–
2
4
8
6
7
5
2.5 V
IOL
+
–
0.1 µF
VCC = 15
to 30 V
1
3
+
–
2
4
8
6
7
5
100 mA
VOL
Figure 20. VOL Test Circuit.
Figure 21. IFLH Test Circuit.
0.1 µF
VCC
1
3
IF = 10 mA +
–
2
4
8
6
7
5
VO > 5 V
13
Figure 25a. Recommended LED Drive and Application Circuit.
Applications Information
Eliminating Negative IGBT Gate
Drive
To keep the IGBT firmly off, the
HCPL-3150/315J has a very low
maximum VOL specification of
1.0 V. The HCPL-3150/315J
realizes this very low VOL by
using a DMOS transistor with
4Ω (typical) on resistance in its
pull down circuit. When the
HCPL-3150/315J is in the low
state, the IGBT gate is shorted to
the emitter by Rg + 4 Ω.
Minimizing Rg and the lead
inductance from the HCPL-3150/
315J to the IGBT gate and
emitter (possibly by mounting
the HCPL-3150/315J on a small
PC board directly above the
IGBT) can eliminate the need for
negative IGBT gate drive in
many applications as shown in
Figure 25. Care should be taken
with such a PC board design to
avoid routing the IGBT collector
or emitter traces close to the
HCPL-3150/315J input as this
can result in unwanted coupling
of transient signals into the
HCPL-3150/315J and degrade
performance. (If the IGBT drain
must be routed near the HCPL-
3150/315J input, then the LED
should be reverse-biased when
in the off state, to prevent the
transient signals coupled from
the IGBT drain from turning on
the HCPL-3150/315J.)
Figure 24. CMR Test Circuit and Waveforms.
0.1 µF VCC = 15
to 30 V
47 Ω
1
3
IF = 7 to 16 mA
VO
+
–
+
–
2
4
8
6
7
5
10 KHz
50% DUTY
CYCLE
500 Ω
3 nF
IF
VOUT
tPHL
tPLH
tf
tr
10%
50%
90%
Figure 23. tPLH, tPHL, tr, and tf Test Circuit and Waveforms.
0.1 µF
VCC = 30 V
1
3
IF
VO+
–
+
–
2
4
8
6
7
5
A
+
–
B
VCM = 1500 V
5 V
VCM
∆t
0 V
VO
SWITCH AT B: IF = 0 mA
VO
SWITCH AT A: IF = 10 mA
VOL
VOH
∆t
VCM
δV
δt=
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF VCC = 18 V
1
3
+
–
2
4
8
6
7
5
270 Ω
HCPL-3150
+5 V
CONTROL
INPUT
Rg
Q1
Q2
74XXX
OPEN
COLLECTOR
14
Selecting the Gate Resistor (Rg) to
Minimize IGBT Switching Losses.
(Discussion applies to HCPL-3120,
HCPL-J312 and HCNW3120)
Step 1: Calculate Rg Minimum
from the IOL Peak
Specification. The IGBT and Rg
in Figure 26 can be analyzed as a
simple RC circuit with a voltage
supplied by the
HCPL-3150/315J.
(VCC – VEE - VOL)
Rg
≥
————————————
IOLPEAK
(VCC – VEE - 1.7 V)
= —————————————
IOLPEAK
(15 V + 5 V - 1.7 V)
= —————————————
2.5 A
= 30.5
Ω
The VOL value of 2 V in the pre-
vious equation is a conservative
value of VOL at the peak current
of 0.6A (see Figure 6). At lower
Rg values the voltage supplied
by the HCPL-3150/315J is not an
ideal voltage step. This results in
lower peak currents (more
margin) than predicted by this
analysis. When negative gate
drive is not used VEE in the
previous equation is equal to
zero volts.
Step 2: Check the HCPL-3150/
315J Power Dissipation and
Increase Rg if Necessary. The
HCPL-3150/315J total power
dissipation (PT) is equal to the
sum of the emitter power (PE)
and the output power (PO):
PT = PE + PO
PE = IF•V
F•Duty Cycle
PO = PO(BIAS) + PO (SWITCHING)
= ICC•(V
CC - VEE)
+ ESW(RG, QG)•f
For the circuit in Figure 26 with
IF (worst case) = 16 mA,
Rg = 30.5 Ω, Max Duty
Cycle = 80%, Qg = 500 nC,
f = 20 kHz and TA
max = 90°C:
PE = 16 mA•1.8 V•0.8 = 23 mW
PO = 4.25 mA•20 V
+ 4.0
µ
J•20 kHz
= 85 mW + 80 mW
= 165 mW
> 154 mW (PO(MAX) @ 90°C
= 250 mW-20C•4.8 mW/C)
Figure 25b. Recommended LED Drive and Application Circuit (HCPL-315J).
+ HVDC
3-PHASE
AC
0.1 µF
FLOATING
SUPPLY
V
CC
= 18 V
1
3
+
–
2
16
14
15
270 Ω
HCPL-315J
+5 V
CONTROL
INPUT
Rg
74XX
OPEN
COLLECTOR
GND 1
7
6
8
10
11
9
- HVDC
0.1 µF V
CC
= 18 V
+
–
Rg
270 Ω
+5 V
CONTROL
INPUT
74XX
OPEN
COLLECTOR
GND 1
15
Figure 26a. HCPL-3150 Typical Application Circuit with Negative IGBT Gate Drive.
PO Parameter Description
ICC Supply Current
VCC Positive Supply Voltage
VEE Negative Supply Voltage
ESW(Rg,Qg) Energy Dissipated in the HCPL-3150/315J for each IGBT
Switching Cycle (See Figure 27)
f Switching Frequency
PE Parameter Description
IFLED Current
VFLED On Voltage
Duty Cycle Maximum LED
Duty Cycle
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF VCC = 15 V
1
3
+
–
2
4
8
6
7
5
HCPL-3150
Rg
Q1
Q2
VEE = -5 V
–
+
270 Ω
+5 V
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
Figure 26b. HCPL-315J Typical Application Circuit with Negative IGBT Gate Drive.
+ HVDC
3-PHASE
AC
0.1 µF
FLOATING
SUPPLY
V
CC
= 15 V
1
3
–
2
16
14
15
270 Ω
HCPL-315J
+5 V
CONTROL
INPUT
Rg
74XX
OPEN
COLLECTOR
GND 1
7
6
8
10
11
9
- HVDC
0.1 µF V
CC
= 15 V
Rg
270 Ω
+5 V
CONTROL
INPUT
74XX
OPEN
COLLECTOR
GND 1
–
+
–
+
––
+
–
+
V
CC
= -5 V
V
EE
= -5 V
16
The value of 4.25 mA for ICC in
the previous equation was
obtained by derating the ICC max
of 5 mA (which occurs at -40°C)
to ICC max at 90°C (see
Figure 7).
Since PO for this case is greater
than PO(MAX), Rg must be
increased to reduce the HCPL-
3150 power dissipation.
PO(SWITCHING MAX)
= PO(MAX) - PO(BIAS)
= 154 mW - 85 mW
= 69 mW
PO(SWITCHINGMAX)
ESW(MAX) = ———————————
f
69 mW
= ————— = 3.45
µ
J
20 kHz
For Qg = 500 nC, from Figure 27,
a value of ESW = 3.45 µJ gives a
Rg = 41 Ω.
Thermal Model
(HCPL-3150)
The steady state thermal model
for the HCPL-3150 is shown in
Figure 28a. The thermal
resistance values given in this
model can be used to calculate
the temperatures at each node
for a given operating condition.
As shown by the model, all heat
generated flows through qCA
which raises the case
temperature TC accordingly. The
value of qCA depends on the
conditions of the board design
and is, therefore, determined by
the designer. The value of qCA =
83°C/W was obtained from
thermal measurements using a
2.5 x 2.5 inch PC board, with
small traces (no ground plane), a
single HCPL-3150 soldered into
the center of the board and still
air. The absolute maximum
power dissipation derating
specifications assume a qCAvalue
of 83°C/W.
From the thermal mode in
Figure 28a the LED and detector
IC junction temperatures can be
expressed as:
TJE = P
E • (qLC||(qLD + qDC) + qCA)
qLC • qDC
+ PD•(——————————— + qCA) + TA
qLC + qDC + qLD
qLC • qDC
TJD = PE (—————————— + qCA)
qLC + qDC + qLD
+ P
D•(qDC||( qLD + qLC) + qCA) + TA
Inserting the values for qLC and
qDC shown in Figure 28 gives:
TJE = LED junction temperature
TJD = detector IC junction temperature
TC= case temperature measured at the center of the package bottom
qLC = LED-to-case thermal resistance
qLD = LED-to-detector thermal resistance
qDC = detector-to-case thermal resistance
qCA = case-to-ambient thermal resistance
*qCA will depend on the board design and the placement of the part.
Figure 28a. Thermal Model.
θ
LD
= 439°C/W
T
JE
T
JD
θ
LC
= 391°C/W θ
DC
= 119°C/W
θ
CA
= 83°C/W*
T
C
T
A
TJE = P
E•(230°C/W + qCA)
+ P
D•(49°C/W + qCA) + T
A
TJD = P
E•(49°C/W + qCA)
+ P
D•(104°C/W + qCA) + TA
For example, given PE = 45 mW,
PO = 250 mW, TA = 70°C and qCA
= 83°C/W:
TJE = PE•313°C/W + PD•132°C/W + TA
= 45 mW•313°C/W + 250 mW
•132°C/W + 70°C = 117°C
TJD = PE•132°C/W + PD•187°C/W + TA
= 45 mW•132°C/W + 250 mW
•187°C/W + 70°C = 123°C
TJE and TJD should be limited to
125°C based on the board layout
and part placement (qCA) specific
to the application.
17
Thermal Model Dual-Channel
(SOIC-16) HCPL-315J Optoisolator
Definitions
q1, q2, q3, q4, q5, q6, q7, q8, q9,
q10: Thermal impedances
between nodes as shown in
Figure 28b. Ambient
Temperature: Measured
approximately 1.25 cm above the
optocoupler with no forced air.
Description
This thermal model assumes
that a 16-pin dual-channel
(SOIC-16) optocoupler is
soldered into an 8.5 cm x 8.1 cm
printed circuit board (PCB).
These optocouplers are hybrid
devices with four die: two LEDs
and two detectors. The
temperature at the LED and the
detector of the optocoupler can
be calculated by using the
equations below.
DTE1A = A11PE1 + A12PE2+A13PD1+A14PD2
DTE2A = A21PE1 + A22PE2+A23PD1+A24PD2
DTD1A = A31PE1 + A32PE2+A33PD1+A34PD2
DTD2A = A41PE1 + A42PE2+A43PD1+A44PD2
where:
DTE1A = Temperature difference between ambient and LED 1
DTE2A = Temperature difference between ambient and LED 2
DTD1A = Temperature difference between ambient and detector 1
DTD2A = Temperature difference between ambient and detector 2
PE1 = Power dissipation from LED 1;
PE2 = Power dissipation from LED 2;
PD1 = Power dissipation from detector 1;
PD2 = Power dissipation from detector 2
Axy thermal coefficient (units in °C/W) is a function of thermal
impedances q1 through q10.
Figure 28b. Thermal Impedance Model for HCPL-315J.
θ
6
θ
5
θ
9
θ
4
θ
8
θ
7
θ
10
θ
1
θ
3
θ
2
LED 1 LED 2
AMBIENT
DETECTOR 1 DETECTOR 2
P
E1
P
E2
P
D1
P
D2
Thermal Coefficient Data (units in °C/W)
Part Number A11, A22 A12, A21 A13, A31 A24, A42 A14, A41 A23, A32 A33, A44 A34, A43
HCPL-315J 198 64 62 64 83 90 137 69
Note: Maximum junction temperature for above part: 125°C.
18
below the threshold during a
transient. A minimum LED cur-
rent of 10 mA provides adequate
margin over the maximum IFLH
of 5 mA to achieve 15 kV/µs
CMR.
CMR with the LED Off (CMRL)
A high CMR LED drive circuit
must keep the LED off
(VF≤VF(OFF)) during common
mode transients. For example,
during a -dVCM/dt transient in
Figure 31, the current flowing
through CLEDP also flows
through the RSAT and VSAT of
the logic gate. As long as the low
state voltage developed across
the logic gate is less than
VF(OFF), the LED will remain off
and no common mode failure
will occur.
The open collector drive circuit,
shown in Figure 32, cannot keep
the LED off during a +dVCM/dt
transient, since all the current
flowing through CLEDN must be
supplied by the LED, and it is
Figure 27. Energy Dissipated in the HCPL-
3150 for Each IGBT Switching Cycle.
Esw – ENERGY PER SWITCHING CYCLE – µJ
0
0
Rg – GATE RESISTANCE – Ω
100
3
20
7
40
2
60 80
6Qg = 100 nC
Qg = 250 nC
Qg = 500 nC
5
4
1
V
CC
= 19 V
V
EE
= -9 V
LED Drive Circuit Considerations for
Ultra High CMR Performance
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side of
the optocoupler, through the
package, to the detector IC as
shown in Figure 29. The HCPL-
3150/315J improves CMR
performance by using a detector
IC with an optically transparent
Faraday shield, which diverts
the capacitively coupled current
away from the sensitive IC
circuitry. How ever, this shield
does not eliminate the capacitive
coupling between the LED and
optocoupler pins 5-8 as shown
in Figure 30. This capacitive
coupling causes perturbations in
the LED current during common
mode transients and becomes
the major source of CMR failures
for a shielded optocoupler. The
main design objective of a high
CMR LED drive circuit becomes
keeping the LED in the proper
state (on or off) during common
mode transients. For example,
the recommended application
circuit (Figure 25), can achieve
15 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in
the proper state are discussed in
the next two sections.
not recommended for applica-
tions requiring ultra high CMRL
performance. Figure 33 is an
alternative drive circuit which,
like the recommended
application circuit (Figure 25),
does achieve ultra high CMR
performance by shunting the
LED in the off state.
Under Voltage Lockout Feature
The HCPL-3150/315J contains
an under voltage lockout (UVLO)
feature that is designed to
protect the IGBT under fault
conditions which cause the
HCPL-3150/315J supply voltage
(equivalent to the fully-charged
IGBT gate voltage) to drop below
a level necessary to keep the
IGBT in a low resistance state.
When the HCPL-3150/315J
output is in the high state and
the supply voltage drops below
the HCPL-3150/315J VUVLO-
threshold (9.5 <VUVLO- <12.0),
the optocoupler output will go
into the low state with a typical
delay, UVLO Turn Off Delay, of
0.6 µs. When the HCPL-3150/
315J output is in the low state
and the supply voltage rises
above the HCPL-3150/315J
VUVLO+ threshold
(11.0 < VUVLO+ < 13.5), the
optocoupler will go into the high
state (assuming LED is “ON”)
with a typical delay, UVLO
TURN On Delay, of 0.8 µs.
IPM Dead Time and Propagation
Delay Specifications
The HCPL-3150/315J includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize “dead
time” in their power inverter
CMR with the LED On (CMRH)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
19
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
1
3
2
4
8
6
7
5
CLEDP
CLEDN
SHIELD
CLEDO1
CLEDO2
Figure 29. Optocoupler Input to Output Capacitance Model
for Unshielded Optocouplers.
Figure 30. Optocoupler Input to Output Capacitance Model
for Shielded Optocouplers.
Figure 31. Equivalent Circuit for Figure 25 During Common Mode Transient.
Rg
1
3
VSAT
2
4
8
6
7
5
+
VCM
I
LEDP
C
LEDP
C
LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dVCM/dt.
+5 V
+
–VCC = 18 V
• • •
• • •
0.1
µF
+
–
–
designs. Dead time is the time
period during which both the
high and low side power
transistors (Q1 and Q2 in Figure
25) are off. Any overlap in Q1
and Q2 conduction will result in
large currents flowing through
the power devices from the high-
to the low-voltage motor rails.
To minimize dead time in a
given design, the turn on of
LED2 should be delayed
(relative to the turn off of LED1)
so that under worst-case
conditions, transistor Q1 has
just turned off when transistor
Q2 turns on, as shown in Figure
34. The amount of delay
necessary to achieve this condi-
tions is equal to the maximum
value of the propagation delay
difference specification,
PDDMAX, which is specified to be
350 ns over the operating
temperature range of -40°C to
100°C.
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero, but
it does not tell a designer what
the maximum dead time will be.
The maximum dead time is
equivalent to the difference
between the maximum and
minimum propagation delay
difference specifications as
shown in Figure 35. The
maximum dead time for the
HCPL-3150/315J is 700 ns
(= 350 ns - (-350 ns)) over an
operating temperature range of
-40°C to 100°C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal tempera-
tures and test conditions since
the optocouplers under
consideration are typically
mounted in close proximity to
each other and are switching
identical IGBTs.
Figure 33. Recommended LED Drive Circuit for Ultra-
High CMR.
1
3
2
4
8
6
7
5
CLEDP
CLEDN
SHIELD
+5 V
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Q1 I
LEDN
Figure 32. Not Recommended Open Collector Drive
Circuit.
tPHL MAX
tPLH MIN
PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
VOUT1
ILED2
VOUT2
ILED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
Figure 34. Minimum LED Skew for Zero Dead Time.
Figure 35. Waveforms for Dead Time.
tPLH
MIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN)
= (tPHL MAX - tPLH MIN) – (tPHL MIN - tPLH MAX)
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
VOUT1
ILED2
VOUT2
ILED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
tPHL MIN
tPHL MAX
tPLH MAX
= PDD* MAX
(tPHL-tPLH) MAX
www.agilent.com/semiconductors
For product information and a complete list of
distributors, please go to our web site.
For technical assistance call:
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Data subject to change.
Copyright © 2005 Agilent Technologies, Inc.
Obsoletes 5989-2142EN
April 24, 2005
5989-2944EN
Figure 36. Under Voltage Lock Out.
V
O
– OUTPUT VOLTAGE – V
0
0
(V
CC
- V
EE
) – SUPPLY VOLTAGE – V
10
5
14
10 15
2
20
6
8
4
12
(12.3, 10.8)
(10.7, 9.2)
(10.7, 0.1) (12.3, 0.1)
Figure 37a. HCPL-3150: Thermal Derating Curve,
Dependence of Safety Limiting Value with Case
Temperature per IEC/EN/DIN EN 60747-5-2.
OUTPUT POWER – P
S
, INPUT CURRENT – I
S
0
0
T
S
– CASE TEMPERATURE – °C
200
600
400
25
800
50 75 100
200
150 175
P
S
(mW)
I
S
(mA)
125
100
300
500
700
Figure 37b. HCPL-315J: Thermal Derating Curve, Dependence of Safety
Limiting Value with Case Temperature per IEC/EN/DIN EN 60747-5-2.
PSI – POWER – mW
0
0
TS – CASE TEMPERATURE – °C
20050
800
12525 75 100 150
1200
400
200
600
1000
1400
175
PSI OUTPUT
PSI INPUT
