Agilent 0.6 Amp Output Current IGBT Gate Drive Optocoupler Data Sheet HCPL-3150 (Single Channel) HCPL-315J (Dual Channel) Description The HCPL-315X consists of a LED optically coupled to an integrated circuit with a power output stage. This optocoupler is ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving IGBTs with ratings up to 1200 V/50 A. For IGBTs with higher ratings, the HCPL-3150/315J can be used to drive a discrete power stage which drives the IGBT gate. Functional Diagram N/C 1 8 VCC ANODE 2 7 VO CATHODE 3 6 VO N/C 4 SHIELD 5 VEE N/C 1 16 VCC ANODE 2 15 VO CATHODE 3 ANODE 6 11 VCC CATHODE 7 10 VO N/C 8 HCPL-3150 14 VEE SHIELD 9 SHIELD VEE HCPL-315J TRUTH TABLE LED VCC - VEE "Positive Going" (i.e., Turn-On) VCC - VEE "Negative-Going" (i.e., Turn-Off) VO OFF ON ON ON 0 - 30 V 0 - 11 V 11 - 13.5 V 13.5 - 30 V 0 - 30 V 0 - 9.5 V 9.5 - 12 V 12 - 30 V LOW LOW TRANSITION HIGH A 0.1 F bypass capacitor must be connected between the VCC and VEE pins for each channel. Features * 0.6 A maximum peak output current * 0.5 A minimum peak output current * 15 kV/s minimum Common Mode Rejection (CMR) at VCM = 1500 V * 1.0 V maximum low level output voltage (VOL) eliminates need for negative gate drive * ICC = 5 mA maximum supply current * Under Voltage Lock-Out protection (UVLO) with hysteresis * Wide operating VCC range: 15 to 30 Volts * 0.5 s maximum propagation delay * 0.35 s maximum delay between devices/channels * Industrial temperature range: -40C to 100C * HCPL-315J: Channel One to Channel Two output isolation = 1500 Vrms/1 min. * Safety and Regulatory Approval: UL Recognized (UL1577) 3750 Vrms/1 min. IEC/EN/DIN EN 60747-5-2 Approved VIORM = 630 Vpeak (HCPL-3150 Option 060 only) VIORM = 891 Vpeak (HCPL-315J) CSA Certified Applications * Isolated IGBT/MOSFET gate drive * AC and brushless DC motor drives * Industrial inverters * Switch Mode Power Supplies (SMPS) * Uninterruptable Power Supplies (UPS) CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Selection Guide: Invertor Gate Drive Optoisolators Widebody Package Type 8-Pin DIP (300 mil) (400 mil) Small Outline SO-16 Part Number HCPL-3150 HCPL-3120 HCPL-J312 HCPL-J314 HCNW-3120 HCPL-315J HCPL-316J HCPL-314J Number of Channels 1 1 1 1 1 2 1 2 IEC/EN/DIN EN VIORM VIORM VIORM VIORM 60747-5-2 630 Vpeak 891Vpeak 1414 Vpeak 891 Vpeak Approvals Option 060 UL Approval 3750 3750 5000 3750 Vrms/1 min. Vrms/1 min. Vrms/1min. Vrms/1 min. Output Peak Current 0.6A 2.5A 2.5A 0.6A 2.5A 0.6A 2.5A 0.6A CMR (minimum) 15 kV/s 10 kV/s 15 kV/s 10 kV/s UVLO Yes No Yes No Fault Status No Yes No Ordering Information Specify Part Number followed by Option Number (if desired) Example HCPL-315Y#XXXX No Option = Standard DIP package, 50 per tube. 060 = IEC/EN/DIN EN 60747-5-2 VIORM = 630 Vpeak Option, 50 per tube. (HCPL-3150 only) 300 = Gull Wing Surface Mount Option, 50 per tube. (HCPL-3150 only) 500 = Tape and Reel Packaging Option. HCPL-3150; 1000 per reel. HCPL-315J; 850 per reel. XXXE = Lead Free Option f = Single Channel, 8-pin PDIP. J = Dual Channel, SO16. Option data sheets available. Contact Agilent sales representative or authorized distributor. Remarks: The notation "#" is used for existing products, while (new) products launched since 15th July 2001 and lead free option will use "-". Package Outline Drawings Standard DIP Package 9.40 (0.370) 9.90 (0.390) 8 7 6 5 OPTION CODE* YYWW PIN ONE 1.19 (0.047) MAX. 3.56 0.13 (0.140 0.005) 1 2 3 7.36 (0.290) 7.88 (0.310) 1.78 (0.070) MAX. 4.70 (0.185) MAX. DIMENSIONS PIN IN MILLIMETERS AND (INCHES). DIAGRAM 0.51 (0.020) MIN. 2.92 (0.115) MIN. 0.65 (0.025) MAX. 2.28 (0.090) 2.80 (0.110) 2 5 TYP. 4 PIN ONE 0.76 (0.030) 1.40 (0.055) 0.20 (0.008) 0.33 (0.013) 6.10 (0.240) 6.60 (0.260) DATE CODE A 3150 Z * MARKING1 CODE VDD1LETTER VDD2FOR 8 OPTION NUMBERS. "V" = OPTION 060. OPTION NUMBERS AND 500 VOUT+ 2 VIN+ 300 7 NOT MARKED. NOTE: FLOATING IS 0.25 mm (10 mils) MAX. V PROTRUSION 3 V LEAD 6 IN- 4 OUT- GND1 GND2 5 Package Outline Drawings Surface-Mount Option 300 Gull-Wing LAND PATTERN RECOMMENDATION 9.65 0.25 (0.380 0.010) 6 7 8 OPTION CODE* 5 A 3150 Z 6.350 0.25 (0.250 0.010) YYWW 1 MOLDED 3 2 1.016 (0.040) 10.9 (0.430) 4 2.0 (0.080) 1.27 (0.050) 9.65 0.25 (0.380 0.010) 1.780 (0.070) MAX. 1.19 (0.047) MAX. 7.62 0.25 (0.300 0.010) 0.20 (0.008) 0.33 (0.013) 3.56 0.13 (0.140 0.005) 1.080 0.320 (0.043 0.013) 0.635 0.25 (0.025 0.010) 0.635 0.130 (0.025 0.005) 2.540 (0.100) BSC 12 NOM. DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 xx.xxx = 0.005 LEAD COPLANARITY MAXIMUM: 0.102 (0.004) *MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION 060. OPTION NUMBERS 300 AND 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. 16 - Lead Surface Mount 9 VO2 11 10 GND2 VO1 10.36 0.20 (0.408 0.008) GND1 VCC1 16 15 14 VCC2 LAND PATTERN RECOMMENDATION (0.295 0.004) 7.49 0.10 NC VIN1 V1 VIN2 V2 NC HCPL-315J 1 2 3 6 7 8 (0.458) 11.63 (0.085) 2.16 (0.025) 0.64 (0.004 - 0.011) 0.10 - 0.30 STANDOFF (0.345 0.008) 8.76 0.20 VIEW FROM PIN 16 0 - 8 9 (0.025 MIN.) 0.64 VIEW FROM PIN 1 (0.138 0.005) 3.51 0.13 (0.0091 - 0.0125) 0.23 - 0.32 (0.408 0.008) 10.36 0.20 ALL LEADS TO BE COPLANAR (0.002 INCHES) 0.05 mm. (0.018) (0.050) 0.457 1.27 (0.406 0.007) 10.31 0.18 3 DIMENSIONS IN (INCHES) AND MILLIMETERS. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. Solder Reflow Thermal Profile Regulatory Information The HCPL-3150 and HCPL-315J have been approved by the following organizations: 300 TEMPERATURE (C) PREHEATING RATE 3C + 1C/-0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. PEAK TEMP. 245C PEAK TEMP. 240C 200 2.5C 0.5C/SEC. SOLDERING TIME 200C 30 SEC. 160C 150C 140C 30 SEC. 3C + 1C/-0.5C 100 PREHEATING TIME 150C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 200 TIME (SECONDS) Recommended Pb-Free IR Profile tp Tp TEMPERATURE TL Tsmax TIME WITHIN 5 C of ACTUAL PEAK TEMPERATURE 20-40 SEC. 260 +0/-5 C 217 C RAMP-UP 3 C/SEC. MAX. 150 - 200 C RAMP-DOWN 6 C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. tL 60 to 150 SEC. 25 t 25 C to PEAK TIME NOTES: THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 C, Tsmin = 150 C 4 UL Recognized under UL 1577, Component Recognition Program, File E55361. PEAK TEMP. 230C 250 CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. IEC/EN/DIN EN 60747-5-2 Approved under: IEC 60747-5-2:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01. (Option 060 and HCPL-315J only) IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 150 Vrms for rated mains voltage 300 Vrms for rated mains voltage 600 Vrms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, Partial discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage tini = 10 sec) Safety-Limiting Values - Maximum Values Allowed in the Event of a Failure, also see Figure 37, Thermal Derating Curve. Case Temperature Input Current Output Power Insulation Resistance at TS, VIO = 500 V Symbol HCPL-3150#060 HCPL-315J** Unit VIORM I-IV I-III 55/100/21 2 630 I-IV I-III I-II 55/100/21 2 891 Vpeak VPR 1181 1670 Vpeak VPR 945 1336 Vpeak VIOTM 6000 6000 Vpeak TS IS, INPUT PS, OUTPUT RS 175 230 600 109 175 400 1200 109 C mA mW **Approval Pending. *Refer to the front of the optocoupler section of the current Catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test profiles. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. 5 Insulation and Safety Related Specifications Parameter Minimum External Air Gap (External Clearance) Symbol L(101) HCPL-3150 7.1 HCPL-315J 8.3 Units mm Minimum External Tracking (External Creepage) L(102) 7.4 8.3 mm 0.08 0.5 mm 175 175 Volts IIIa IIIa Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output erminals, shortest distance path along body. Through insulation distance conductor to conductor. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) Option 300 - surface mount classification is Class A in accordance wtih CECC 00802. Absolute Maximum Ratings Parameter Storage Temperature Operating Temperature Average Input Current Peak Transient Input Current (<1 s pulse width, 300 pps) Reverse Input Voltage "High" Peak Output Current "Low" Peak Output Current Supply Voltage Output Voltage Output Power Dissipation Total Power Dissipation Lead Solder Temperature Solder Reflow Temperature Profile Symbol TS TA IF(AVG) IF(TRAN) Min. -55 -40 Max. 125 100 25 1.0 VR 5 Volts IOH(PEAK) 0.6 A IOL(PEAK) 0.6 A (VCC - VEE) 0 35 Volts VO(PEAK) 0 VCC Volts PO 250 mW PT 295 mW 260C for 10 sec., 1.6 mm below seating plane See Package Outline Drawings Section Recommended Operating Conditions Parameter Power Supply Voltage Input Current (ON) Input Voltage (OFF) Operating Temperature 6 Symbol (VCC - VEE) IF(ON) VF(OFF) TA Units C C mA A Min. 15 7 -3.0 -40 Max. 30 16 0.8 100 Units Volts mA V C Note 1, 16 2, 16 2, 16 3, 16 4, 16 Electrical Specifications (DC) Over recommended operating conditions (TA = -40 to 100C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V, VCC = 15 to 30 V, VEE = Ground, each channel) unless otherwise specified. Parameter High Level Output Current Low Level Output Current High Level Output Voltage Low Level Output Voltage High Level Supply Current Low Level Supply Current Threshold Input Current Low to High Symbol IOH Threshold Input Voltage High to Low Input Forward Voltage VFHL 0.8 VF 1.2 Temperature Coefficient of Forward Voltage Input Reverse Breakdown Voltage VF/TA Input Capacitance UVLO Threshold CIN VUVLO+ VUVLOUVLOHYS UVLO Hysteresis IOL VOH Min. 0.1 0.5 0.1 0.5 (VCC - 4) Typ.* 0.4 0.6 A (VCC - 3) V Test Conditions VO = (VCC - 4 V) VO = (VCC - 15 V) VO = (VEE + 2.5 V) VO = (VEE + 15 V) IO = -100 mA Units A VOL 0.4 1.0 V IO = 100 mA ICCH 2.5 5.0 mA ICCL 2.7 5.0 mA IFLH 2.2 2.6 5.0 6.4 mA Output Open, IF = 7 to 16 mA Output Open, VF = -3.0 to +0.8 V HCPL-3150 I O = 0 mA, HCPL-315J VO > 5 V BVR 1.5 1.6 -1.6 1.8 1.95 V mV/C 5 3 11.0 9.5 Fig. 2, 3, 17 5, 6, 18 1, 3, 19 4, 6, 20 7, 8 9, 15, 21 V V 70 12.3 10.7 1.6 *All typical values at TA = 25C and VCC - VEE = 30 V, unless otherwise noted. 7 Max. 13.5 12.0 pF V V HCPL-3150 I F = 10 mA HCPL-315J IF = 10 mA HCPL-3150 I R = 10 A HCPL-315J IR = 10 A f = 1 MHz, VF = 0 V VO > 5 V, IF = 10 mA 16 22, 36 Note 5 2 5 2 6, 7 16 Switching Specifications (AC) Over recommended operating conditions (TA = -40 to 100C, I F(ON) = 7 to 16 mA, V F(OFF) = -3.0 to 0.8 V, VCC = 15 to 30 V, VEE = Ground) unless otherwise specified. Parameter Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level Pulse Width Distortion Propagation Delay Difference Between Any Two Parts or Channels Rise Time Fall Time UVLO Turn On Delay UVLO Turn Off Delay Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity 8 Symbol tPLH Min. 0.10 Typ.* 0.30 Max. 0.50 Units s tPHL 0.10 0.30 0.50 s 0.3 0.35 s s PWD PDD (tPHL - tPLH) tr tf tUVLO ON tUVLO OFF |CMH| |CML| -0.35 s s s 15 0.1 0.1 0.8 0.6 30 15 30 kV/s kV/s Test Conditions Rg = 47 , Cg = 3 nF, f = 10 kHz, Duty Cycle = 50% Fig. Note 10, 11, 14 12, 13, 14, 23 34, 36 15 10 23 VO > 5 V, IF = 10 mA VO < 5 V, IF = 10 mA TA = 25C, IF = 10 to 16 mA, VCM = 1500 V, VCC = 30 V TA = 25C, VCM = 1500 V, VF = 0 V, V CC = 30 V 22 24 11, 12 11, 13 Package Characteristics (each channel, unless otherwise specified) Parameter Input-Output Momentary Withstand Voltage** Output-Output Momentary Withstand Voltage** Resistance (Input-Output) Capacitance (Input-Output) Symbol V ISO LED-to-Case Thermal Resistance LED-to-Detector Thermal Resistance Detector-to-Case Thermal Resistance V O-O Device HCPL-3150 HCPL-315J HCPL-315J Min. 3750 3750 1500 Typ. Max. Units V RMS Vrms pF qLC HCPL-3150 HCPL-315J HCPL-3150 1012 0.6 1.3 391 qLD HCPL-3150 439 C/W qDC HCPL-3150 119 C/W RI-O CI-O C/W Test Conditions RH < 50%, t = 1 min., TA = 25C RH < 50%, t = 1 min., TA = 25C V I-O = 500 V DC f = 1 MHz Fig. Note 8, 9 Thermocouple 28 located at center underside of package 17 9 18 *All typical values at T A = 25C and VCC - VEE = 30 V, unless otherwise noted. **The Input-Output/Output-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output/ output-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Agilent Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage." Notes: 1. Derate linearly above 70 C free-air temperature at a rate of 0.3 mA/ C. 2. Maximum pulse width = 10 s, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with I O peak minimum = 2.0 A. See Applications section for additional details on limiting IOH peak. 3. Derate linearly above 70 C free-air temperature at a rate of 4.8 mW/ C. 4. Derate linearly above 70 C free-air temperature at a rate of 5.4 mW/ C. The maximum LED junction temperature should not exceed 125 C. 5. Maximum pulse width = 50 s, maximum duty cycle = 0.5%. 6. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps. 9 7. Maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection current limit, II-O 5 A). 9. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection current limit, II-O 5 A). 10. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 6000 Vrms for 1 second (leakage detection current limit, II-O 5 A). 11. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 12. The difference between tPHL and t PLH between any two HCPL-3120 parts under the same test condition. 13. Pins 1 and 4 need to be connected to LED common. 14. Common mode transient immunity in the high state is the maximum tolerable dVCM /dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15.0 V). 15. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V). 16. This load condition approximates the gate load of a 1200 V/75A IGBT. 17. Pulse Width Distortion (PWD) is defined as |tPHL-tPLH| for any given device. -3 -4 -40 -20 0 20 40 60 80 100 0.40 0.35 0.30 0.25 -40 -20 TA - TEMPERATURE - C 100 0.2 0 -40 -20 0 20 40 60 80 100 0.8 0.6 0.4 VF(OFF) = -3.0 to 0.8 V VOUT = 2.5 V VCC = 15 to 30 V VEE = 0 V 0.2 0 -40 -20 0 20 40 60 80 100 ICC - SUPPLY CURRENT - mA 3.0 2.5 VCC = 30 V VEE = 0 V IF = 10 mA for ICCH IF = 0 mA for ICCL ICCH ICCL 3.0 2.5 40 60 80 TA - TEMPERATURE - C Figure 7. ICC vs. Temperature. 100 IF = 10 mA for ICCH IF = 0 mA for ICCL TA = 25 C VEE = 0 V 2.0 1.5 20 IF = 7 to 16 mA VCC = 15 to 30 V VEE = 0 V -5 -6 0 0.2 0.4 0.6 1.0 0.8 IOH - OUTPUT HIGH CURRENT - A VF(OFF) = -3.0 to 0.8 V VCC = 15 to 30 V 4 VEE = 0 V 3 2 1 0 15 20 25 VCC - SUPPLY VOLTAGE - V Figure 8. ICC vs. VCC. 100 C 25 C -40 C 0 0.2 0.4 0.8 0.6 1.0 Figure 6. VOL vs. I OL. 3.5 0 -4 IOL - OUTPUT LOW CURRENT - A Figure 5. IOL vs. Temperature. ICCH ICCL 1.5 -40 -20 -3 TA - TEMPERATURE - C 3.5 100 C 25 C -40 C -2 Figure 3. VOH vs. I OH. VOL - OUTPUT LOW VOLTAGE - V IOL - OUTPUT LOW CURRENT - A 0.4 Figure 4. VOL vs. Temperature. ICC - SUPPLY CURRENT - mA 80 -1 5 TA - TEMPERATURE - C 10 60 40 1.0 VF(OFF) = -3.0 to 0.8 V IOUT = 100 mA VCC = 15 to 30 V VEE = 0 V 0.6 2.0 20 Figure 2. IOH vs. Temperature. 1.0 0.8 0 TA - TEMPERATURE - C Figure 1. VOH vs. Temperature. VOL - OUTPUT LOW VOLTAGE - V 0.45 (VOH - VCC ) - OUTPUT HIGH VOLTAGE DROP - V -2 IF = 7 to 16 mA VOUT = VCC - 4 V VCC = 15 to 30 V VEE = 0 V 30 IFLH - LOW TO HIGH CURRENT THRESHOLD - mA -1 0.50 IF = 7 to 16 mA IOUT = -100 mA VCC = 15 to 30 V VEE = 0 V IOH - OUTPUT HIGH CURRENT - A (VOH - VCC ) - HIGH OUTPUT VOLTAGE DROP - V 0 5 VCC = 15 TO 30 V VEE = 0 V OUTPUT = OPEN 4 3 2 1 0 -40 -20 0 20 40 60 80 TA - TEMPERATURE - C Figure 9. IFLH vs. Temperature. 100 500 400 TPLH TPHL 300 200 15 25 20 400 300 200 TPLH TPHL 100 30 VCC - SUPPLY VOLTAGE - V 400 Tp - PROPAGATION DELAY - ns Tp - PROPAGATION DELAY - ns 12 14 300 200 TPLH TPHL 0 50 150 100 200 Figure 13. Propagation Delay vs. Rg. 1000 10 IF + VF - 1.0 0.1 0.01 0.001 1.10 1.20 1.30 1.40 1.50 300 200 TPLH TPHL 1.60 VF - FORWARD VOLTAGE - V Figure 16. Input Current vs. Forward Voltage. 20 40 60 80 100 30 VCC = 30 V, VEE = 0 V TA = 25 C IF = 10 mA Rg = 47 DUTY CYCLE = 50% f = 10 kHz 400 300 200 TPLH TPHL 100 0 TA - TEMPERATURE - C Figure 12. Propagation Delay vs. Temperature. 0 20 40 60 80 Cg - LOAD CAPACITANCE - nF Figure 14. Propagation Delay vs. Cg. TA = 25C 100 400 100 -40 -20 16 500 VCC = 30 V, VEE = 0 V TA = 25 C IF = 10 mA Cg = 3 nF DUTY CYCLE = 50% f = 10 kHz Rg - SERIES LOAD RESISTANCE - IF - FORWARD CURRENT - mA 10 Figure 11. Propagation Delay vs. I F. 500 11 8 IF(ON) = 10 mA IF(OFF) = 0 mA VCC = 30 V, VEE = 0 V Rg = 47 , Cg = 3 nF DUTY CYCLE = 50% f = 10 kHz IF - FORWARD LED CURRENT - mA Figure 10. Propagation Delay vs. VCC. 100 6 VO - OUTPUT VOLTAGE - V 100 500 VCC = 30 V, VEE = 0 V Rg = 47 , Cg = 3 nF TA = 25 C DUTY CYCLE = 50% f = 10 kHz Tp - PROPAGATION DELAY - ns IF = 10 mA TA = 25 C Rg = 47 Cg = 3 nF DUTY CYCLE = 50% f = 10 kHz Tp - PROPAGATION DELAY - ns Tp - PROPAGATION DELAY - ns 500 100 25 20 15 10 5 0 0 1 2 3 4 5 IF - FORWARD LED CURRENT - mA Figure 15. Transfer Characteristics. 8 1 1 8 2 7 3 6 4 5 0.1 F 2 0.1 F + - 7 4V IF = 7 to 16 mA IOL + VCC = 15 - to 30 V + VCC = 15 - to 30 V 6 3 IOH 4 5 Figure 17. IOH Test Circuit. 2.5 V + - Figure 18. IOL Test Circuit. 8 1 1 8 2 7 0.1 F 2 7 0.1 F VOH IF = 7 to 16 mA 100 mA + VCC = 15 - to 30 V + VCC = 15 - to 30 V 6 3 3 6 4 5 VOL 100 mA 4 5 Figure 19. VOH Test Circuit. 1 Figure 20. VOL Test Circuit. 8 1 8 2 7 0.1 F 7 3 6 3 6 4 5 4 5 IF VO > 5 V Figure 21. IFLH Test Circuit. 12 0.1 F 2 + VCC = 15 - to 30 V IF = 10 mA VO > 5 V Figure 22. UVLO Test Circuit. + - VCC 8 1 0.1 F IF = 7 to 16 mA + 10 KHz - 500 2 + - 7 IF VCC = 15 to 30 V tr tf VO 50% DUTY CYCLE 90% 47 6 3 50% VOUT 3 nF 4 10% 5 tPLH tPHL Figure 23. tPLH, t PHL, tr , and tf Test Circuit and Waveforms. VCM 5V t 0.1 F A B V 8 1 IF 2 7 VO 6 4 5 VCM t 0V + - 3 = t + - VCC = 30 V VOH VO SWITCH AT A: IF = 10 mA VO VOL - SWITCH AT B: IF = 0 mA + VCM = 1500 V Figure 24. CMR Test Circuit and Waveforms. Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the HCPL-3150/315J has a very low maximum VOL specification of 1.0 V. The HCPL-3150/315J realizes this very low VOL by using a DMOS transistor with 4 (typical) on resistance in its pull down circuit. When the HCPL-3150/315J is in the low state, the IGBT gate is shorted to the emitter by Rg + 4 . Minimizing Rg and the lead inductance from the HCPL-3150/ 315J to the IGBT gate and emitter (possibly by mounting the HCPL-3150/315J on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 25. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL-3150/315J input as this can result in unwanted coupling of transient signals into the HCPL-3150/315J and degrade performance. (If the IGBT drain must be routed near the HCPL3150/315J input, then the LED should be reverse-biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-3150/315J.) HCPL-3150 +5 V 1 270 8 0.1 F 2 + - VCC = 18 V + HVDC 7 Rg CONTROL INPUT 74XXX OPEN COLLECTOR 3 6 4 5 Figure 25a. Recommended LED Drive and Application Circuit. 13 Q1 3-PHASE AC Q2 - HVDC HCPL-315J +5 V 270 CONTROL INPUT 1 16 2 15 0.1 F + - FLOATING SUPPLY VCC = 18 V + HVDC Rg 74XX OPEN COLLECTOR 3 14 GND 1 +5 V 3-PHASE AC 6 270 CONTROL INPUT 11 0.1 F 7 VCC = 18 V + - 10 Rg 74XX OPEN COLLECTOR 8 9 GND 1 - HVDC Figure 25b. Recommended LED Drive and Application Circuit (HCPL-315J). Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses. (Discussion applies to HCPL-3120, HCPL-J312 and HCNW3120) Step 1: Calculate Rg Minimum from the IOL Peak Specification. The IGBT and Rg in Figure 26 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-3150/315J. (V CC - VEE - VOL) Rg ------------------------ IOLPEAK (V CC - VEE - 1.7 V) = -------------------------- IOLPEAK (15 V + 5 V - 1.7 V) = -------------------------- 2.5 A = 30.5 14 The VOL value of 2 V in the previous equation is a conservative value of VOL at the peak current of 0.6A (see Figure 6). At lower Rg values the voltage supplied by the HCPL-3150/315J is not an ideal voltage step. This results in lower peak currents (more margin) than predicted by this analysis. When negative gate drive is not used VEE in the previous equation is equal to zero volts. PT = PE + PO PE = I F * VF * Duty Cycle PO = PO(BIAS) + PO (SWITCHING) = ICC * (VCC - VEE) + ESW(RG, QG) * f For the circuit in Figure 26 with IF (worst case) = 16 mA, Rg = 30.5 , Max Duty Cycle = 80%, Qg = 500 nC, f = 20 kHz and TA max = 90C: PE = 16 mA * 1.8 V * 0.8 = 23 mW Step 2: Check the HCPL-3150/ 315J Power Dissipation and Increase Rg if Necessary. The HCPL-3150/315J total power dissipation (PT ) is equal to the sum of the emitter power (PE) and the output power (PO): PO = 4.25 mA * 20 V + 4.0 J* 20 kHz = 85 mW + 80 mW = 165 mW > 154 mW (PO(MAX) @ 90C = 250 mW-20C* 4.8 mW/C) HCPL-3150 +5 V 8 1 270 0.1 F 2 + - VCC = 15 V + HVDC 7 Rg Q1 CONTROL INPUT 6 3 - + 74XXX OPEN COLLECTOR 4 VEE = -5 V 3-PHASE AC 5 Q2 - HVDC Figure 26a. HCPL-3150 Typical Application Circuit with Negative IGBT Gate Drive. HCPL-315J +5 V CONTROL INPUT 1 16 2 15 270 0.1 F + - FLOATING SUPPLY VCC = 15 V + HVDC Rg 74XX OPEN COLLECTOR 3 14 - + VEE = -5 V GND 1 +5 V 6 11 270 0.1 F CONTROL INPUT 7 3-PHASE AC VCC = 15 V + - 10 Rg 74XX OPEN COLLECTOR 8 9 - + VCC = -5 V GND 1 - HVDC Figure 26b. HCPL-315J Typical Application Circuit with Negative IGBT Gate Drive. PE Parameter IF VF Duty Cycle Description LED Current LED On Voltage Maximum LED Duty Cycle P O Parameter I CC V CC V EE E SW(Rg,Qg) f 15 Description Supply Current Positive Supply Voltage Negative Supply Voltage Energy Dissipated in the HCPL-3150/315J for each IGBT Switching Cycle (See Figure 27) Switching Frequency The value of 4.25 mA for I CC in the previous equation was obtained by derating the ICC max of 5 mA (which occurs at -40C) to ICC max at 90C (see Figure 7). Since P O for this case is greater than P O(MAX), Rg must be increased to reduce the HCPL3150 power dissipation. PO(SWITCHING MAX) = PO(MAX) - PO(BIAS) = 154 mW - 85 mW = 69 mW PO(SWITCHINGMAX) ESW(MAX) = ---------------------- f 69 mW = 3.45 J = ---------- 20 kHz For Qg = 500 nC, from Figure 27, a value of ESW = 3.45 J gives a Rg = 41 . Thermal Model (HCPL-3150) The steady state thermal model for the HCPL-3150 is shown in Figure 28a. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. As shown by the model, all heat generated flows through qCA which raises the case temperature TC accordingly. The LD = 439C/W TJE TJD LC = 391C/W DC = 119C/W TC CA = 83C/W* TA Figure 28a. Thermal Model. 16 value of qCA depends on the conditions of the board design and is, therefore, determined by the designer. The value of qCA = 83C/W was obtained from thermal measurements using a 2.5 x 2.5 inch PC board, with small traces (no ground plane), a single HCPL-3150 soldered into the center of the board and still air. The absolute maximum power dissipation derating specifications assume a qCAvalue of 83C/W. From the thermal mode in Figure 28a the LED and detector IC junction temperatures can be expressed as: TJE = PE * (qLC||(qLD + qDC) + qCA) TJE = PE * (230C/W + qCA ) + PD * (49C/W + qCA) + TA TJD = PE * (49 C/W + qCA) + PD * (104 C/W + qCA) + TA For example, given PE = 45 mW, PO = 250 mW, TA = 70C and qCA = 83C/W: TJE = PE* 313C/W + PD* 132C/W + TA = 45 mW* 313C/W + 250 mW * 132C/W + 70 C = 117 C TJD = PE* 132C/W + PD* 187 C/W + TA = 45 mW* 132C/W + 250 mW * 187C/W + 70 C = 123 C TJE and TJD should be limited to 125C based on the board layout and part placement (qCA) specific to the application. qLC * qDC + PD * (---------------------- + qCA) + TA qLC + qDC + qLD qLC * qDC TJD = PE (-------------------- +q ) qLC + qDC + qLD CA + PD* (qDC||(qLD + qLC) + qCA) + TA Inserting the values for qLC and qDC shown in Figure 28 gives: TJE = TJD = TC = qLC = qLD = qDC = qCA = LED junction temperature detector IC junction temperature case temperature measured at the center of the package bottom LED-to-case thermal resistance LED-to-detector thermal resistance detector-to-case thermal resistance case-to-ambient thermal resistance *qCA will depend on the board design and the placement of the part. Thermal Model Dual-Channel (SOIC-16) HCPL-315J Optoisolator Definitions q1, q2, q3, q4, q5, q6, q7, q8, q9, q10: Thermal impedances between nodes as shown in Figure 28b. Ambient Temperature: Measured approximately 1.25 cm above the optocoupler with no forced air. Description This thermal model assumes that a 16-pin dual-channel (SOIC-16) optocoupler is soldered into an 8.5 cm x 8.1 cm printed circuit board (PCB). These optocouplers are hybrid devices with four die: two LEDs and two detectors. The temperature at the LED and the detector of the optocoupler can be calculated by using the equations below. 1 LED 1 LED 2 3 2 4 5 DETECTOR 1 7 DETECTOR 2 10 8 6 9 AMBIENT Figure 28b. Thermal Impedance Model for HCPL-315J. PE1 PD1 PE2 PD2 DT E1A = A 11P E1 + A12 PE2 +A13 PD1+A 14PD2 DT E2A = A 21P E1 + A22 PE2 +A23 PD1+A 24PD2 DT D1A = A 31P E1 + A32 PE2 +A33P D1+A34 PD2 DT D2A = A 41P E1 + A42 PE2 +A43P D1+A44 PD2 where: DT E1A = Temperature difference between ambient and LED 1 DT E2A = Temperature difference between ambient and LED 2 DT D1A = Temperature difference between ambient and detector 1 DT D2A = Temperature difference between ambient and detector 2 PE1 = Power dissipation from LED 1; PE2 = Power dissipation from LED 2; PD1 = Power dissipation from detector 1; PD2 = Power dissipation from detector 2 Axy thermal coefficient (units in C/W) is a function of thermal impedances q1 through q10 . Thermal Coefficient Data (units in C/W) Part Number HCPL-315J A11, A 22 198 A12, A 21 64 A13, A 31 62 Note: Maximum junction temperature for above part: 125C. 17 A24, A 42 64 A14, A 41 83 A23, A 32 90 A33, A 44 137 A34, A 43 69 Techniques to keep the LED in the proper state are discussed in the next two sections. CMR with the LED On (CMRH) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled 18 Esw - ENERGY PER SWITCHING CYCLE - J LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 29. The HCPL3150/315J improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. How ever, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins 5-8 as shown in Figure 30. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off) during common mode transients. For example, the recommended application circuit (Figure 25), can achieve 15 kV/s CMR while minimizing component complexity. not recommended for applications requiring ultra high CMRL performance. Figure 33 is an alternative drive circuit which, like the recommended application circuit (Figure 25), does achieve ultra high CMR performance by shunting the LED in the off state. 7 Qg = 100 nC 6 Qg = 250 nC Qg = 500 nC 5 VCC = 19 V 4 VEE = -9 V 3 2 1 0 0 20 40 60 80 100 Rg - GATE RESISTANCE - Figure 27. Energy Dissipated in the HCPL3150 for Each IGBT Switching Cycle. below the threshold during a transient. A minimum LED current of 10 mA provides adequate margin over the maximum IFLH of 5 mA to achieve 15 kV/s CMR. CMR with the LED Off (CMRL) A high CMR LED drive circuit must keep the LED off (VF VF(OFF)) during common mode transients. For example, during a -dVCM /dt transient in Figure 31, the current flowing through CLEDP also flows through the RSAT and VSAT of the logic gate. As long as the low state voltage developed across the logic gate is less than VF(OFF), the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure 32, cannot keep the LED off during a +dVCM/dt transient, since all the current flowing through CLEDN must be supplied by the LED, and it is Under Voltage Lockout Feature The HCPL-3150/315J contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL-3150/315J supply voltage (equivalent to the fully-charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL-3150/315J output is in the high state and the supply voltage drops below the HCPL-3150/315J VUVLOthreshold (9.5 <VUVLO- <12.0), the optocoupler output will go into the low state with a typical delay, UVLO Turn Off Delay, of 0.6 s. When the HCPL-3150/ 315J output is in the low state and the supply voltage rises above the HCPL-3150/315J VUVLO+ threshold (11.0 < VUVLO+ < 13.5), the optocoupler will go into the high state (assuming LED is "ON") with a typical delay, UVLO TURN On Delay, of 0.8 s. IPM Dead Time and Propagation Delay Specifications The HCPL-3150/315J includes a Propagation Delay Difference (PDD) specification intended to help designers minimize "dead time" in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 25) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices from the highto the low-voltage motor rails. 34. The amount of delay necessary to achieve this conditions is equal to the maximum value of the propagation delay difference specification, PDDMAX, which is specified to be 350 ns over the operating temperature range of -40C to 100C. To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and 8 1 2 7 2 3 6 3 5 4 1 CLEDP minimum propagation delay difference specifications as shown in Figure 35. The maximum dead time for the HCPL-3150/315J is 700 ns (= 350 ns - (-350 ns)) over an operating temperature range of -40 C to 100C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. CLEDO1 8 CLEDP 7 CLEDO2 CLEDN 4 Figure 29. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers. +5 V 8 0.1 F CLEDP 2 7 + - VCC = 18 V ILEDP 3 4 *** 6 CLEDN Rg SHIELD 5 * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING -dVCM/dt. + - VCM Figure 31. Equivalent Circuit for Figure 25 During Common Mode Transient. 19 5 SHIELD Figure 30. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers. 1 + VSAT - 6 CLEDN *** 1 8 +5 V 1 8 +5 V CLEDP 2 3 Q1 CLEDN CLEDP 7 2 6 3 5 4 7 6 CLEDN ILEDN 4 SHIELD Figure 32. Not Recommended Open Collector Drive Circuit. Figure 33. Recommended LED Drive Circuit for UltraHigh CMR. ILED1 ILED1 VOUT1 5 SHIELD VOUT1 Q1 ON Q1 ON Q1 OFF Q1 OFF Q2 ON Q2 ON VOUT2 ILED2 Q2 OFF VOUT2 Q2 OFF ILED2 tPHL MAX tPHL MIN tPLH MIN tPHL MAX tPLH PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 34. Minimum LED Skew for Zero Dead Time. MIN tPLH MAX (tPHL-tPLH) MAX = PDD* MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN) = (tPHL MAX - tPLH MIN) - (tPHL MIN - tPLH MAX) = PDD* MAX - PDD* MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 35. Waveforms for Dead Time. 12 (12.3, 10.8) 10 (10.7, 9.2) 8 6 4 2 0 (10.7, 0.1) 0 5 10 (12.3, 0.1) 15 20 OUTPUT POWER - PS, INPUT CURRENT - IS VO - OUTPUT VOLTAGE - V 14 800 600 500 400 300 200 100 0 (VCC - VEE ) - SUPPLY VOLTAGE - V Figure 36. Under Voltage Lock Out. PSI - POWER - mW PSI INPUT 1000 800 600 400 200 0 25 50 75 100 125 150 175 200 TS - CASE TEMPERATURE - C Figure 37b. HCPL-315J: Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per IEC/EN/DIN EN 60747-5-2. www.agilent.com/semiconductors For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (916) 788-6763 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6756 2394 India, Australia, New Zealand: (+65) 6755 1939 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject to change. Copyright (c) 2005 Agilent Technologies, Inc. Obsoletes 5989-2142EN April 24, 2005 5989-2944EN 25 50 75 100 125 150 175 200 Figure 37a. HCPL-3150: Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per IEC/EN/DIN EN 60747-5-2. PSI OUTPUT 0 0 TS - CASE TEMPERATURE - C 1400 1200 PS (mW) IS (mA) 700