MR0A16A
64K x 16 MRAM Memory
MR0A16A Rev. 5, 12/20111
RoHS
CONTENTS
1. DEVICE PIN ASSIGNMENT......................................................................... 3
2. ELECTRICAL SPECIFICATIONS................................................................. 4
3. TIMING SPECIFICATIONS.......................................................................... 7
4. ORDERING INFORMATION....................................................................... 12
5. MECHANICAL DRAWING.......................................................................... 13
6. REVISION HISTORY...................................................................................... 15
How to Reach Us.......................................................................................... 15
Everspin Technologies © 2011
FEATURES
• + 3.3 Volt power supply
• Fast 35ns read/write cycle
• SRAM compatible timing
• Unlimited read & write endurance
• Commercial, Industrial, Extended Temperatures
• Data always non-volatile for >20-years at temperature
• RoHS-compliant TSOP2 and BGA packages available
BENEFITS
• One memory replaces FLASH, SRAM, EEPROM and BBSRAM in system
for simpler, more ecient designs
• Improves reliability by replacing battery-backed SRAM
• Automatic data protection on power loss
INTRODUCTION
The MR0A16A is a 1,048,576-bit magnetoresistive random access
memory (MRAM) device organized as 65,536 words of 16 bits. The
MR0A16A oers SRAM compatible 35 ns read/write timing with unlim-
ited endurance. Data is always non-volatile for greater than 20-years. Data is automatically protected on
power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specication. The
MR0A16A is the ideal memory solution for applications that must permanently store and retrieve critical
data and programs quickly.
The MR0A16A is available in small footprint 400-mil, 44-lead plastic small-outline TSOP type-2 package or
8 mm x 8 mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers. These packages are compat-
ible with similar low-power SRAM products and other non-volatile RAM products.
The MR0A16A provides highly reliable data storage over a wide range of temperatures. The product is
oered with commercial temperature (0 to +70 °C), industrial temperature (-40 to +85 °C), and extended
temperature (-40 to +105 °C) range options.
MR0A16A Rev. 5, 12/20112
CHIP
ENABLE
BUFFER
OUTPUT
ENABLE
BUFFER
ADDRESS
BUFFER
WRITE
ENABLE
BUFFER
G
E
21
OUTPUT ENABLE
2M x 8 BIT
MEMORY
ARRAY
ROW
DECODER
COLUMN
DECODER
SENSE
AMPS
OUTPUT
BUFFER
WRITE
DRIVER
FINAL
WRITE
DRIVERS
WRITE ENABLE
W
A[20:0]
11
10
88
8
8
8
8
DQ[7:0]
1. DEVICE PIN ASSIGNMENT
Figure 1.1 Block Diagram
Table 1.1 Pin Functions
Signal Name Function
A Address Input
E Chip Enable
W Write Enable
G Output Enable
DQ (U or L) Data I/O
VDD Power Supply
VSS Ground
DC Do Not Connect
NC No Connection
MR0A16A
Everspin Technologies © 2011
MR0A16A Rev. 5, 12/20113
Figure 1.2 Pin Diagrams for Available Packages (Top View)
44-Pin TSOP Type 2 48-Pin BGA
Table 1.2 Operating Modes
DEVICE PIN ASSIGNMENT MR0A16A
Everspin Technologies © 2011
E1G1W1LB1UB1Mode VDD Current DQL[7:0]2DQU[15:8]2
H X X X X Not selected ISB1, ISB2 Hi-Z Hi-Z
L H H X X Output disabled IDDR Hi-Z Hi-Z
L X X H H Output disabled IDDR Hi-Z Hi-Z
L L H L H Lower Byte Read IDDR DOut Hi-Z
L L H H L Upper Byte Read IDDR Hi-Z DOut
L L H L L Word Read IDDR DOut DOut
L X L L H Lower Byte Write IDDW Din Hi-Z
L X L H L Upper Byte Write IDDW Hi-Z Din
L X L L L Word Write IDDW Din Din
1 H = high, L = low, X = don’t care
2 Hi-Z = high impedance
A
A
A
VDD
E
VSS
W
A
A
A22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44 A
G
VSS
VDD
DC
A
A
A
A
A
A
A
A
A
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
VDD
VSS
DQU8
DQU9
DQU10
DQU11
DQU12
DQU13
UB
LB
DQU14
DQU15
123456
LB G A0 A1 A2 NC A
DQU8 UB A3 A4 E DQL0 B
DQU9 DQU10 A5 A6 DQL1 DQL2 C
VSS DQU11
A13
DQL3 VDD D
VDD DQU12 NC A14 DQL4 VSS E
DQU14 DQU13 A12
A11
DQL5 DQL6 F
DQU15
A
A15
WDQL7 G
7A 9A 8
A10
H
DC
NC
NC VDD
VSS
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or
electric elds; however, it is advised that normal precautions be taken to avoid application of any
voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic elds. Precautions should be taken
to avoid application of any magnetic eld more intense than the maximum eld intensity specied
in the maximum ratings.
MR0A16A Rev. 5, 12/20114
Parameter Symbol Value Unit
Supply voltage2VDD -0.5 to 4.0 V
Voltage on any pin2VIN -0.5 to VDD + 0.5 V
Output current per pin IOUT ±20 mA
Package power dissipation3PD0.600 W
Temperature under bias
MR0A16A (Commercial)
MR0A16AC (Industrial)
MR0A16AV (Extended)
TBIAS
-10 to 85
-45 to 95
-45 to 110
°C
Storage Temperature Tstg -55 to 150 °C
Lead temperature during solder (3 minute max) TLead 260 °C
Maximum magnetic eld during write
MR0A16A (All Temperatures)
Hmax_write 2000 A/m
Maximum magnetic eld during read or standby Hmax_read 8000 A/m
1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera-
tion should be restricted to recommended operating conditions. Exposure to excessive voltages or
magnetic elds could aect device reliability.
2 All voltages are referenced to VSS.
3 Power dissipation capability depends on package characteristics and use environment.
Table 2.1 Absolute Maximum Ratings1
MR0A16A
Everspin Technologies © 2011
MR0A16A Rev. 5, 12/20115
Parameter Symbol Min Typical Max Unit
Power supply voltage 1VDD 3.0 3.3 3.6 V
Write inhibit voltage VWI 2.5 2.7 3.0 1 V
Input high voltage VIH 2.2 - VDD + 0.3 2 V
Input low voltage VIL -0.5 3- 0.8 V
Temperature under bias
MR0A16A (Commercial)
MR0A16AC (Industrial)
MR0A16AV (Extended)
TA
0
-40
-40
70
85
105
°C
1 There is a 2 ms startup time once VDD exceeds VDD,(max). See Power Up and Power Down Sequencing below.
2 VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
3 VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
Table 2.2 Operating Conditions
Power Up and Power Down Sequencing
The The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds
VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory
power supplies to stabilize.
The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain
high for the startup time. In most systems, this means that these signals should be pulled up with a resis-
tor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W
should hold the signals high with a power-on reset signal for longer than the startup time.
During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be
observed when power returns above VDD(min).
BROWNOUT or POWER LOSS
NORMAL
OPERATION
V
DD
READ/WRITE
INHIBITED
VWIDD
2 ms
READ/WRITE
INHIBITED
V
IH
STARTUP
NORMAL
OPERATION
2 ms
E
W
RECOVER
V
IH
Figure 2.1 Power Up and Power Down Diagram
MR0A16A
Electrical Specication
Everspin Technologies © 2011
MR0A16A Rev. 5, 12/20116
Parameter Symbol Min Typical Max Unit
Input leakage current Ilkg(I) - - ±1 μA
Output leakage current Ilkg(O) - - ±1 μA
Output low voltage
(IOL = +4 mA)
(IOL = +100 μA)
VOL - - 0.4
VSS + 0.2
V
Output high voltage
(IOH = -4 mA)
(IOH = -100 μA)
VOH
2.4
VDD - 0.2 - - V
Table 2.3 DC Characteristics
Table 2.4 Power Supply Characteristics
Parameter Symbol Typical Max Unit
AC active supply current - read modes1
(IOUT= 0 mA, VDD= max) IDDR 55 80 mA
AC active supply current - write modes1
(VDD= max)
MR0A16A (Commercial)
MR0A16AC (Industrial)
MR0A16AV (Extended)
IDDW
105
105
105
155
165
165
mA
AC standby current
(VDD= max, E = VIH)
no other restrictions on other inputs
ISB1 18 28 mA
CMOS standby current
(E ≥ VDD - 0.2 V and VIn VSS + 0.2 V or ≥ VDD - 0.2 V)
(VDD = max, f = 0 MHz)
ISB2 9 12 mA
1 All active current measurements are measured with one address transition per cycle and at minimum cycle time.
MR0A16A
Electrical Specications
Everspin Technologies © 2011
MR0A16A Rev. 5, 12/20117
MR0A16A
3. TIMING SPECIFICATIONS
Table 3.1 Capacitance1
Parameter Symbol Typical Max Unit
Address input capacitance CIn - 6 pF
Control input capacitance CIn - 6 pF
Input/Output capacitance CI/O - 8 pF
1 f = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.
Table 3.2 AC Measurement Conditions
Figure 3.1 Output Load Test Low and High
Figure 3.2 Output Load Test All Others
Parameter Value Unit
Logic input timing measurement reference level 1.5 V
Logic output timing measurement reference level 1.5 V
Logic input pulse levels 0 or 3.0 V
Input rise/fall time 2 ns
Output load for low and high impedance parameters See Figure 3.1
Output load for all other timing parameters See Figure 3.2
V
Output
L= 1.5 V
RL= 50 Ω
ZD= 50 Ω
Output
435 Ω
590 Ω
5 pF
3.3 V
Everspin Technologies © 2011
MR0A16A
Timing Specications
MR0A16A Rev. 5, 12/20118
Parameter Symbol Min Max Unit
Read cycle time tAVAV 35 - ns
Address access time tAVQV - 35 ns
Enable access time2tELQV - 35 ns
Output enable access time tGLQV - 15 ns
Byte enable access time tBLQV - 15 ns
Output hold from address change tAXQX 3 - ns
Enable low to output active3tELQX 3 - ns
Output enable low to output active3tGLQX 0 - ns
Byte enable low to output active3tBLQX 0 - ns
Enable high to output Hi-Z3tEHQZ 0 15 ns
Output enable high to output Hi-Z3tGHQZ 0 10 ns
Byte high to output Hi-Z3tBHQZ 0 10 ns
1 W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be
minimized or eliminated during read or write cycles.
2 Addresses valid before or at the same time E goes low.
3 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage.
Table 3.3 Read Cycle Timing1
Read Mode
Figure 3.3A Read Cycle 1
Figure 3.3B Read Cycle 2
A (ADDRESS)
Q (DATA OUT)
tAVAV
tAXQX
tAVQV
Previous Data Valid
Note: Device is continuously selected (E≤VIL, G≤VIL).
Data Valid
A (ADDRESS)
E (CHIP ENABLE)
G (OUTPUT ENABLE)
Q (DATA OUT) Data Valid
tAVAV
tAVQV
tELQV
tELQX
tGHQZ
tEHQZ
tGLQV
tGLQX
Everspin Technologies © 2011
MR0A16A
Timing Specications
MR0A16A Rev. 5, 12/20119
Table 3.4 Write Cycle Timing 1 (W Controlled)1
Parameter Symbol Min Max Unit
Write cycle time2tAVAV 35 - ns
Address set-up time tAVWL 0 - ns
Address valid to end of write (G high) tAVWH 18 - ns
Address valid to end of write (G low) tAVWH 20 - ns
Write pulse width (G high) tWLWH
tWLEH
15 - ns
Write pulse width (G low) tWLWH
tWLEH
15 - ns
Data valid to end of write tDVWH 10 - ns
Data hold time tWHDX 0 - ns
Write low to data Hi-Z3tWLQZ 0 12 ns
Write high to output active3tWHQX 3 - ns
Write recovery time tWHAX 12 - ns
1 All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in
steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted
low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
2 All write cycle timings are referenced from the last valid address to the rst transition address.
3 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given
voltage or temperate, tWLQZ(max) < tWHQX(min)
W (WRITE ENABLE)
A (ADDRESS)
E (CHIP ENABLE)
t
AVAV
t
AVWH
t
WHAX
t
AVWL
t
WLEH
t
WLWH
DATA VALID
t
DVWH
t
WHDX
Q (DATA OUT)
D (DATA IN)
t
WLQZ
t
WHQX
Hi -Z Hi -Z
Figure 3.4 Write Cycle Timing 1 (W Controlled)
Everspin Technologies © 2011
MR0A16A
Timing Specications
Everspin Technologies © 2011 MR0A16A Rev. 5, 12/201110
Table 3.5 Write Cycle Timing 2 (E Controlled)1
Figure 3.5 Write Cycle Timing 2 (E Controlled)1
Parameter Symbol Min Max Unit
Write cycle time2tAVAV 35 - ns
Address set-up time tAVEL 0 - ns
Address valid to end of write (G high) tAVEH 18 - ns
Address valid to end of write (G low) tAVEH 20 - ns
Enable to end of write (G high) tELEH
tELWH
15 - ns
Enable to end of write (G low)3tELEH
tELWH
15 - ns
Data valid to end of write tDVEH 10 - ns
Data hold time tEHDX 0 - ns
Write recovery time tEHAX 12 - ns
1 All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in
steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted
low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
2 All write cycle timings are referenced from the last valid address to the rst transition address.
3 If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the
same time or before W goes high, the output will remain in a high-impedance state.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
Q (DATA OUT)
D (DATA IN)
t
AVAV
t
AVEH
t
EHAX
t
ELEH
t
EHDX
t
DVEH
t
AVEL
Hi-Z
t
ELWH
Data Valid
MR0A16A
Timing Specications
MR0A16A Rev. 5, 12/201111
Table 3.6 Write Cycle Timing 3 (LB/UB Controlled)1
Table 3.6 Write Cycle Timing 3 (LB/UBControlled)
Parameter Symbol Min Max Unit
Write cycle time2tAVAV 35 - ns
Address set-up time tAVBL 0 - ns
Address valid to end of write (G high) tAVBH 18 - ns
Address valid to end of write (G low) tAVBH 20 - ns
Write pulse width (G high) tBLEH
tBLWH
15 - ns
Write pulse width (G low) tBLEH
tBLWH
15 - ns
Data valid to end of write tDVBH 10 - ns
Data hold time tBHDX 0 - ns
Write recovery time tBHAX 12 - ns
1 All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
Wgoes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must
remain in steady-state high for a minimum of 2 ns. If both byte control signals are asserted, the two signals must have no
more than 2 ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in
a subsequent cycle is the same as the minimum cycle time allowed for the device.
2 All write cycle timings are referenced from the last valid address to the rst transition address.
Everspin Technologies © 2011
MR0A16A Rev. 5, 12/201112
MR0A16A
4. ORDERING INFORMATION
Figure 4.1 Part Numbering System
Carrier (Blank = Tray, R = Tape & Reel)
Speed (35 ns)
Package (YS = TSOP2, MA = FBGA)
Temperature Range
(Blank= 0 to +70 °C, C= -40 to
+85°C, V= -40 to +105 °C)
Revision
Data Width (16 = 16-bit)
Type (A = Asynchronous)
Density (0 = 1Mb)
Magnetoresistive RAM
(MR)
MR 0 A 16 A V YS 35 R
Part Number Description Temperature
MR0A16AYS35 3.3 V 64Kx16 MRAM 44-TSOP Commercial
MR0A16ACYS35 3.3 V 64Kx16 MRAM 44-TSOP Industrial
MR0A16AVYS35 3.3 V 64Kx16 MRAM 44-TSOP Extended
MR0A16AYS35R 3.3 V 64Kx16 MRAM 44-TSOP T&R Commercial
MR0A16ACYS35R 3.3 V 64Kx16 MRAM 44-TSOP T&R Industrial
MR0A16AVYS35R 3.3 V 64Kx16 MRAM 44-TSOP T&R Extended
MR0A16AMA35 3.3 V 64Kx16 MRAM 48-BGA Commercial
MR0A16ACMA35 3.3 V 64Kx16 MRAM 48-BGA Industrial
MR0A16AVMA35 3.3 V 64Kx16 MRAM 48-BGA Extended
MR0A16AMA35 3.3 V 64Kx16 MRAM 48-BGA T&R Commercial
MR0A16ACMA35 3.3 V 64Kx16 MRAM 48-BGA T&R Industrial
MR0A16AVMA35 3.3 V 64Kx16 MRAM 48-BGA T&R Extended
Table 4.1 Available Parts
Everspin Technologies © 2011
MR0A16A Rev. 5, 12/201113
Figure 5.1 44-TSOP2
MR0A16A
5. MECHANICAL DRAWING
Print Version Not To Scale
1. Dimensions and tolerances per ASME Y14.5M - 1994.
2. Dimensions in Millimeters.
3. Dimensions do not include mold protrusion.
4. Dimension does not include DAM bar protrusions.
DAM Bar protrusion shall not cause the lead width to exceed 0.58.
Everspin Technologies © 2011
MR0A16A Rev. 5, 12/201114
TOP VIEW
BOTTOM VIEW SIDE VIEW
0.41
0.31 0.32
0.22
Figure 5.2 48-FBGA
Print Version Not To Scale
1. Dimensions in Millimeters.
2. Dimensions and tolerances per ASME Y14.5M - 1994.
3. Maximum solder ball diameter measured parallel to DATUM A
4. DATUM A, the seating plane is determined by the spherical crowns
of the solder balls.
5. Parallelism measurement shall exclude any eect of mark on top
surface of package.
MR0A16A
Mechanical Drawings
Everspin Technologies © 2011
MR0A16A
MR0A16A Rev. 5, 12/201115
Revision Date Description of Change
0 Jun 18, 2007 Initial Advanced Information Release
1 Sept 21, 2007 Table 6, Applied Values to TBDs in IDD Specications
2 Nov 12, 2007 Table 2, Changed IDDA to IDDR or IDDW
3 Sep 12, 2008
Reformat Datasheet for EverSpin, Add BGA Packaging Information, Add Tape & Reel Part
Numbers, Add Power Sequencing Info, Correct IOH spec of VOH to -100 uA, Correct ac Test
Conditions.
4 Feb 28, 2011 Add TSOPII Lead Cross-Section, Add Production Note. Converted to new document format.
5 Dec 9, 2011 Figure 2.1 cosmetic update. Figure 5.2 BGA package outline drawing revised for ball size.
Updated logo and contact information. Revised
6. REVISION HISTORY
Information in this document is provided solely to enable system and software implementers to use
Everspin Technologies products. There are no express or implied licenses granted hereunder to design or
fabricate any integrated circuit or circuits based on the information in this document. Everspin Technolo-
gies reserves the right to make changes without further notice to any products herein. Everspin makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does Everspin Technologies assume any liability arising out of the application or use of any product or
circuit, and specically disclaims any and all liability, including without limitation consequential or inci-
dental damages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/
or specications can and do vary in dierent applications and actual performance may vary over time. All
operating parameters including “Typicals” must be validated for each customer application by customer’s
technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights
of others. Everspin Technologies products are not designed, intended, or authorized for use as compo-
nents in systems intended for surgical implant into the body, or other applications intended to support
or sustain life, or for any other application in which the failure of the Everspin Technologies product
could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin
Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Everspin Technologies and its ocers, employees, subsidiaries, aliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such unintended or unauthorized use,
even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture
of the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other
product or service names are the property of their respective owners.
©Everspin Technologies, Inc. 2011
How to Reach Us:
Home Page:
www.everspin.com
E-Mail:
support@everspin.com
orders@everspin.com
sales@everspin.com
USA/Canada/South and Central America
Everspin Technologies
1347 N. Alma School Road, Suite 220
Chandler, Arizona 85224
+1-877-347-MRAM (6726)
+1-480-347-1111
Europe, Middle East and Africa
support.europe@everspin.com
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Filename:
MR0A16A_Datasheet_EST354_Rev5.pdf
Everspin Technologies © 2011