GL424
SD/MMC Flash Card Controller
Datasheet
Revision 1.00
Apr. 18, 2007
Genesys Logic, Inc.
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 2
Copyright:
Copyright © 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be
reproduced in any form or by any means without prior written consent of Genesys Logic, Inc.
Disclaimer:
ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY
KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF
GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND
CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS,
OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT
OF INTELLECTUAL PROPERTY, INCLUDING, WITHOUT LIMITATION, THE X-D PICTURE CARD
TM
LICENSE. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING,
WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS.
PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS.
GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED
THEREIN AT ANY TIME WITHOUT NOTICE.
Trademarks:
Is a registered trademark of Genesys Logic, Inc.
All trademarks are the properties of their respective owners.
Office:
Genesys Logic, Inc.
12F, No. 205, Sec. 3, Beishin Rd., Shindian City,
Taipei, Taiwan
Tel: (886-2) 8913-1888
Fax: (886-2) 6629-6168
http ://www.genesyslogic.com
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 3
Revision History
Revision Date Description
0.90 04/06/2006
First formal release
1.00 04/18/2007
Add Die Pad, 46 PIN LGA, 51PIN LGA
1. Pin Assignment, p.11
2. Package Dimension, p.30
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 4
TABLE OF CONTENTS
CHAPTER 1 GENERAL DESCRIPTION................................................... 7
1.1
CARD
I
NTERFACE
..................................................................................... 8
1.2
F
LASH
A
CCESS
I
NTERFACE
....................................................................... 8
1.3
E
MBEDDED
CPU ........................................................................................ 8
CHAPTER 2 FEATURES.............................................................................. 9
2.1
SD
H
OST
I
NTERFACE
................................................................................. 9
2.2
MMC
H
OST
I
NTERFACE
............................................................................ 9
2.3
F
LASH
M
EMORY
I
NTERFACE
..................................................................... 9
2.4
M
ICRO
C
ONTROLLER AND
A
NALOG
S
YSTEM
......................................... 10
2.5
8KV-ESD
PROTECTION
........................................................................... 10
2.6
D
UAL
C
HANNEL
FLASH
TO REACH TOP
R
EAD
/W
RITE
S
PEED
.............. 10
2.7
D
UAL VOLTAGE APPLICATION
................................................................. 10
2.8
P
RODUCT
P
ACKAGES
............................................................................... 10
2.9
T
ECHNOLOGY
........................................................................................... 10
2.10
M
ANUFACTURE
...................................................................................... 10
CHAPTER 3 PIN ASSIGNMENT .............................................................. 11
3.1
P
INOUT
..................................................................................................... 11
3.2
P
IN
D
ESCRIPTIONS
................................................................................... 16
3.2.1 Regulator Interface......................................................................... 16
3.2.2 Card Interface ................................................................................. 18
3.2.3 Flash Interface................................................................................. 21
3.2.4 System Interface.............................................................................. 24
3.2.5 Test Interface................................................................................... 27
CHAPTER 4 ELECTRICAL CHARACTERISTICS............................... 28
4.1
A
BSOLUTE
M
AXIMUM
R
ATINGS
.............................................................. 28
4.2
B
US
O
PERATING
C
ONDITIONS
................................................................. 28
4.3
D.C.
C
HARACTERISTICS
.......................................................................... 28
CHAPTER 5 PACKAGE DIMENSION..................................................... 30
CHAPTER 6 ORDERING INFORMATION ............................................ 34
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 5
LIST OF FIGURES
F
IGURE
1.
1
-
GL424
B
LOCK
D
IAGRAM
.............................................................................. 8
F
IGURE
3.1
-
46
P
IN
LQFN
P
INOUT
.................................................................................. 11
F
IGURE
3.2
-
54
P
IN
VFBGA
P
INOUT
............................................................................... 12
F
IGURE
3.3
–
D
IE
P
AD
P
INOUT
.......................................................................................... 13
F
IGURE
3.4
–
46
P
IN
LGA
P
INOUT
.................................................................................... 14
F
IGURE
3.5
–
51
P
IN
LGA
P
INOUT
.................................................................................... 15
F
IGURE
5.1-
46
P
IN
LQFN
P
ACKAGE
D
IMENSION
........................................................... 30
F
IGURE
5.2-
54
P
IN
VFBGA
P
ACKAGE
D
IMENSION
......................................................... 31
F
IGURE
5.3-
46
PIN
LGA
P
ACKAGE
D
IMENSION
............................................................. 32
F
IGURE
5.4-
51
PIN
LGA
P
ACKAGE
D
IMENSION
............................................................. 33
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 6
LIST OF TABLES
T
ABLE
3.1
-
46
PIN
LQFN
R
EGULATOR
I
NTERFACE
....................................................... 16
T
ABLE
3.2
-
54
PIN
VFBGA
R
EGULATOR
I
NTERFACE
.................................................... 16
T
ABLE
3.3
–
D
IE
P
AD
R
EGULATOR
I
NTERFACE
................................................................ 16
T
ABLE
3.4
–
46
PIN
LGA
R
EGULATOR
I
NTERFACE
......................................................... 17
T
ABLE
3.5
–
51
PIN
LGA
R
EGULATOR
I
NTERFACE
......................................................... 17
T
ABLE
3.3
-
46
PIN
LQFN
C
ARD
I
NTERFACE
.................................................................. 18
T
ABLE
3.4
-
54
PIN
VFBGA
C
ARD
I
NTERFACE
............................................................... 18
T
ABLE
3.5
–
D
IE
P
AD
C
ARD
I
NTERFACE
........................................................................... 19
T
ABLE
3.6
-
46
PIN
LGA
C
ARD
I
NTERFACE
..................................................................... 20
T
ABLE
3.7
-
51
PIN
LGA
C
ARD
I
NTERFACE
..................................................................... 20
T
ABLE
3.8
-
46
PIN
LQFN
F
LASH
I
NTERFACE
................................................................. 21
T
ABLE
3.9
-
54
PIN
VFBGA
F
LASH
I
NTERFACE
.............................................................. 21
T
ABLE
3.10
–
D
IE
P
AD
F
LASH
I
NTERFACE
........................................................................ 22
T
ABLE
3.11
–
46
PIN
LGA
F
LASH
I
NTERFACE
................................................................. 23
T
ABLE
3.12
–
51
PIN
LGA
F
LASH
I
NTERFACE
................................................................. 23
T
ABLE
3.13
-
46
PIN
LQFN
S
YSTEM
I
NTERFACE
............................................................ 24
T
ABLE
3.14
-
54
PIN
VFBGA
S
YSTEM
I
NTERFACE
.......................................................... 24
T
ABLE
3.15
-
D
IE
P
AD
S
YSTEM
I
NTERFACE
...................................................................... 25
T
ABLE
3.16
-
46
PIN
LGA
S
YSTEM
I
NTERFACE
............................................................... 26
T
ABLE
3.17
-
51
PIN
LGA
S
YSTEM
I
NTERFACE
............................................................... 26
T
ABLE
3.18
-
54
PIN
VFBGA
T
EST
I
NTERFACE
.............................................................. 27
T
ABLE
3.19
-
D
IE
P
AD
T
EST
I
NTERFACE
........................................................................... 27
T
ABLE
4.1
-
A
BSOLUTE
M
AXIMUM
R
ATINGS
.................................................................... 28
T
ABLE
4.2
-
B
US
O
PERATING
C
ONDITIONS
....................................................................... 28
T
ABLE
4.3
-
D.C.
C
HARACTERISTICS
................................................................................ 28
T
ABLE
6.1-
O
RDERING
I
NFORMATION
.............................................................................. 34
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 7
CHAPTER 1 GENERAL DESCRIPTION
GL424 is a single-chip controller for SD and MMC memory cards. It is designed based on SD1.0/SD1.1/SD2.0
and MMC3.3/MMC4.0 specification. Its unique RAM based firmware strategy provides flexibility for fast
compatibility and performance improvement, therefore, give customers strong support to win in today’s
fast-changing market. With its simple interface, customers can easily apply it to SD and MMC memory cards
manufacturing at the same time.
GL424 manages interface protocol, data storage and retrieval, error detection and correction, defect handling and
diagnostic, as well as power management. With a built-in flash management algorithm, GL424 is applicable for
most types of flash in the market: SAMSUNG, MICRON, ST, TOSHIBA, HYNIX and RENESAS.
GL424 is packaged LQFN-46 and VFBGA-54. Both die and LQFN/VFBGA package are available and
completely meet SD and MMC memory card mechanical thickness requirement. The pin assignment that fits to
card sockets provides easy PCB layout.
GL424 is unique in its three advanced features:
(1) Dual-channel solution as well as normal single channel solution with top access speed;
(2) Dual voltage for both 1.8V and 3.3V interface;
(3) 8KV-ESD protecting the whole card.
VFBGA54 packaged GL424 has a dual channel flash access interface, which remarkably speed up read/write
performance. It supports 16-bit flash also.
GL424 provides 8KV ESD (human body mode) and 15KV ESD (mechanical mode) protection. Especially,
GL424 can also provide such high voltage ESD protection to FLASH on the whole SD/MMC card. Therefore,
greatly improved SD/MMC card’s reliability and high quality in unpredictable application environment.
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 8
Flash Access
IF
CARD
Controller
GL424
Host Interface
HOST
Interface
Flash1
Interface
Flash2
Interface
Figure 1. 1 - GL424 Block Diagram
1.1 CARD Interface
The card controller, complied with SD/MMC specification, explains commands from SD/MMC host and
transfers data between SD/MMC host and flash.
1.2 Flash Access Interface
The flash access interface communicates with CPU. It also manages two channels of flash, based on flash
commands. Moreover, it implements defect processing, ECC, and address mapping, etc.
1.3 Embedded CPU
Embedded CPU performs arithmetic and logical operations. In addition, it extracts instruction from ROM and
SRAM, decodes and executes them. It also manages control and status signals between flash access interface and
itself.
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 9
CHAPTER 2 FEATURES
2.1 SD Host Interface
‧
Complies with SD Specification, Version 2.0
‧
Complies with SD Specification, Version 1.1
‧
Complies with SD Specification, Version 1.0
‧
Supports SPI mode and CPRM functions
‧
Supports clock rate up to 25 MHz for SD1.0
‧
Supports clock rate up to 52 MHz for SD1.1 and SD2.0
‧
Buffers for multi-block flash memory programming
‧
DMA operation between buffers and flash memory
‧
Supports automatic CRC16 generation and verification on DATA3-0
‧
Supports SD card exceed 4Gbytes capacity
2.2 MMC Host Interface
‧
Complies with MultiMediaCard System Specification, Version 4.0
‧
Complies with MultiMediaCard System Specification, Version 3.3
‧
Supports SPI mode and CPRM functions
‧
Supports clock rate up to 20 MHz for MMC3.3
‧
Supports clock rate up to 52 MHz for MMC4.0
‧
Buffers for multi-block flash memory programming
‧
DMA operation between buffers and flash memory
‧
Supports automatic CRC16 generation and verification on DATA7-0
2.3 Flash Memory Interface
‧
Direct interface to NAND/AND flash chips (SAMSUNG / TOSHIBA / HITACHI / RENESAS /
MICRON / ST / HYNIX)
‧
Supports dual-channel, 16 bits flash (VFBGA54 package and die)
‧
Drives up to 4 flash memory chips, respectively (VFBGA54 package and die)
‧
Supports 64M / 128M / 256M / 512M / 1G / 2G / 4G / 8G bits flash chips
‧
Embedded firmware support for flash file system (FTL)
‧
Built-in flash management algorithm
‧
Powerful ECC for error detection and correction up to 6 bytes per 512bytes
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 10
2.4 Micro Controller and Analog System
‧
RISC core with fast speed and less code size
‧
Flexibility to update system code
‧
Ability to add customers’ own feature
2.5 8KV-ESD protection
‧
8KV human body ESD protection (contact discharge mode) for the whole card (not only controller
chip itself)
‧
15KV mechanical mode ESD protection (air discharge mode) for the whole card (not only
controller chip itself)
2.6 Dual Channel FLASH to reach top Read/Write Speed
‧
GL424 provides dual channel flash access solution. This can reach the read/write speed almost
doubled compared with single channel solution.
2.7 Dual voltage application
‧
GL424 provides the solution for dual voltage application. This means MMC4.0 card with GL424
can work with either 1.8V or 3.3V host interface.
2.8 Product Packages
‧
46-pin LQFN package
‧
54-pin VFBGA package
‧
46-pin LGA package
‧
51-pin LGA package
2.9 Technology
‧
0.18um process
2.10 Manufacture
‧
Easy firmware development environment
‧
Supports firmware upgrade tool via PC
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 11
CHAPTER 3 PIN ASSIGNMENT
3.1 Pinout
Figure 3.1 - 46 Pin LQFN Pinout
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 12
Figure 3.2 - 54 Pin VFBGA Pinout
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 13
GND
PAD_HCLK
PAD_HCMD
PAD_HDATA0
VCC
PAD_HDATA1
PAD_HDATA2
PAD_HDATA3
GND
PAD_DA0
PAD_DA4
PAD_DA3
PAD_DA2
PAD_DA1
PAD_DA6
PAD_DA5
PAD_DA7
PAD_BUSY_B
VDDIN
PAD_T0
PAD_T4
PAD_T3
PAD_T2
PAD_T1
PAD_T6
PAD_T5
PAD_T7
PAD_CE1_B
PAD_WE_B
PAD_ALE
PAD_CLE
PAD_CE0_B
PAD_WP_B
PAD_RE_B
VDDIN
GNDIN
PAD_OSCO
PAD_Prt_B
V18IN
PAD_DETECT
PAD_DETECT
PAD_HDATA2
PAD_HDATA3
PAD_HCMD
PAD_HCLK
PAD_HDATA1
PAD_HDATA0
PAD1
5
PAD1
6
PAD1
7
PAD1
8
PAD1
9
PAD2
0
PAD2
1
PAD2
2
PAD2
3
PAD2
4
PAD2
5
PAD2
6
PAD2
7
PAD2
8
PAD2
9
PAD3
0
PAD3
1
PAD3
2
PAD3
3
PAD3
4
PAD3
5
PAD3
6
PAD3
7
PAD3
8
PAD3
9
PAD4
0
PAD4
1
PAD4
2
PAD4
3
PAD4
4
PAD4
5
PAD4
7
PAD4
9
PAD5
1
PAD5
3
PAD5
5
PAD5
6
PAD4
6
PAD4
8
PAD5
0
PAD5
2
PAD5
4
PAD5
8
PAD6
0
PAD6
1
PAD5
7
PAD5
9
Figure 3.3 – Die Pad Pinout
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 14
GL424
46 PIN LGA
Figure 3.4 – 46 Pin LGA Pinout
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 15
GL424
51 PIN LGA
Figure 3.5 – 51 Pin LGA Pinout
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 16
3.2 Pin Descriptions
3.2.1 Regulator Interface
Table 3.1 - 46 PIN LQFN Regulator Interface
Pin No. Pin Name Type Description
1 R1 A External Resistor pad
2 R2 A External Resistor pad
3 V18OUT O 1.8V output (Max.100mA)
4 VIN P 3.3V power
5 GND P Ground
6 GNDOUT P Ground output
Table 3.2 - 54 PIN VFBGA Regulator Interface
Pin No. Pin Name Type
Description
A6 R1 A External Resistor pad
A5 R2 A External Resistor pad
B5 V18OUT O 1.8V output (Max.100mA)
C4 V18Fsh O 1.8V output (Max.30mA)
A4 VIN P 3.3V power
B4 GND P Ground
G5 GNDX P Ground
Table 3.3 – Die Pad Regulator Interface
Pad No. Pad Name Type Description
PAD1 R1 A External Resistor pad
PAD2 R2 A External Resistor pad
PAD3 V18-out2 O 1.8V output (Max.100mA)
(Double Bonding)
PAD4 V18-out2 O Regulator 1.8V output
(Double Bonding)
PAD5 V18-out1 O 1.8V output (Max.40mA)
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 17
PAD6 VIN P 3.3V power
(Tri-bonding )
PAD7 VIN P 3.3V power
(Tri-bonding )
PAD8 VIN P 3.3V power
(Tri-bonding )
PAD9 GND P Ground
(Double Bonding)
PAD10 GND P Ground
(Double Bonding)
PAD11 GNDOUT P Ground output when enhanced 8KV-ESD protected
Table 3.4 – 46 PIN LGA Regulator Interface
Pin No. Pin Name Type
Description
16 R1 A External Resistor pad
17 R2 A External Resistor pad
18 V18OUT O 1.8V output (Max.100mA)
19 VIN P 3.3V power
20 GND P Ground
21 GNDOUT P Ground
Table 3.5 – 51 PIN LGA Regulator Interface
Pin No. Pin Name Type
Description
17 R1 A External Resistor pad
18 R2 A External Resistor pad
19 V18 O 1.8V output (Max.100mA)
48 V18Fsh O 1.8V output (Max.30mA)
20 VIN P 3.3V power
21 GND P Ground
22 GNDX P Ground
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 18
Note : A: Analog
I: Input
O: Output
P: Power supply
B: Bi-direction
3.2.2 Card Interface
Table 3.3 - 46 PIN LQFN Card Interface
Pin No. Pin Name Type Description
20 HCLK I HCLK from HOST
18 HCMD B SD/MMC mode: HCMD from/to HOST
SPI mode: Data-in signal from HOST
22 HDATA0 B SD/MMC mode: HDATA0 from/to HOST.
SPI mode: Data-out signal to HOST
23 HDATA1 B SD/MMC mode: HDATA1 from/to HOST.
SPI mode: not connected
16 HDATA2 B SD/MMC mode: HDATA2 from/to HOST.
SPI mode: not connected
17 HDATA3 B SD/MMC mode: HDATA3 from/to HOST.
SPI mode: CS signal
25 HDATA4 B MMC mode: HDATA4 from/to HOST.
26 HDATA5 B MMC mode: HDATA5 from/to HOST.
27 HDATA6 B MMC mode: HDATA6 from/to HOST.
28 HDATA7 B MMC mode: HDATA7 from/to HOST.
Table 3.4 - 54 PIN VFBGA Card Interface
Pin No. Pin Name Type Description
H1 HCLK I HCLK from HOST
F2 HCMD B SD/MMC mode: HCMD from/to HOST
SPI mode: Data-in signal from HOST
J2 HDATA0 B SD/MMC mode: HDATA0 from/to HOST.
SPI mode: Data-out signal to HOST
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 19
J1 HDATA1 B SD/MMC mode: HDATA1 from/to HOST.
SPI mode: not connected
E1 HDATA2 B SD/MMC mode: HDATA2 from/to HOST.
SPI mode: not connected
F1 HDATA3 B SD/MMC mode: HDATA3 from/to HOST.
SPI mode: CS signal
J3 HDATA4 B MMC mode: HDATA4 from/to HOST.
H2 HDATA5 B MMC mode: HDATA5 from/to HOST.
H4 HDATA6 B MMC mode: HDATA6 from/to HOST.
H3 HDATA7 B MMC mode: HDATA7 from/to HOST.
Table 3.5 – Die Pad Card Interface
Pad No. Pad Name Type Description
PAD54 PAD_HCLK B HCLK from HOST
PAD55 PAD_HCLK B Backup PAD
(No Bonding)
PAD51 PAD_HCMD B SD/MMC mode: HCMD from/to HOST
SPI mode: Data-in signal from HOST
PAD52 PAD_HCMD B Backup PAD
(No Bonding)
PAD59 PAD_HDATA0 B SD/MMC mode: HDATA0 from/to HOST.
SPI mode: Data-out signal to HOST
PAD58 PAD_HDATA0 B Backup PAD
(No Bonding)
PAD61 PAD_HDATA1 B SD/MMC mode: HDATA1 from/to HOST.
SPI mode: not connected
PAD60 PAD_HDATA1 B Backup PAD
(No Bonding)
PAD47 PAD_HDATA2 B SD/MMC mode: HDATA2 from/to HOST.
SPI mode: not connected
PAD48 PAD_HDATA2 B Backup PAD
(No Bonding)
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 20
Table 3.6 - 46 PIN LGA Card Interface
Pin No. Pin Name Type Description
37 HCLK I HCLK from HOST
35 HCMD B SD/MMC mode: HCMD from/to HOST
SPI mode: Data-in signal from HOST
39 HDATA0 B SD/MMC mode: HDATA0 from/to HOST.
SPI mode: Data-out signal to HOST
40 HDATA1 B SD/MMC mode: HDATA1 from/to HOST.
SPI mode: not connected
33 HDATA2 B SD/MMC mode: HDATA2 from/to HOST.
SPI mode: not connected
34 HDATA3 B SD/MMC mode: HDATA3 from/to HOST.
SPI mode: CS signal
42 HDATA4 B MMC mode: HDATA4 from/to HOST.
43 HDATA5 B MMC mode: HDATA5 from/to HOST.
44 HDATA6 B MMC mode: HDATA6 from/to HOST.
45 HDATA7 B MMC mode: HDATA7 from/to HOST.
Table 3.7 - 51 PIN LGA Card Interface
Pin No. Pin Name Type Description
38 HCLK I HCLK from HOST
36 HCMD B SD/MMC mode: HCMD from/to HOST
SPI mode: Data-in signal from HOST
40 HDATA0 B SD/MMC mode: HDATA0 from/to HOST.
SPI mode: Data-out signal to HOST
41 HDATA1 B SD/MMC mode: HDATA1 from/to HOST.
SPI mode: not connected
34 HDATA2 B SD/MMC mode: HDATA2 from/to HOST.
SPI mode: not connected
35 HDATA3 B SD/MMC mode: HDATA3 from/to HOST.
SPI mode: CS signal
42 HDATA4 B MMC mode: HDATA4 from/to HOST.
43 HDATA5 B MMC mode: HDATA5 from/to HOST.
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 21
44 HDATA6 B MMC mode: HDATA6 from/to HOST.
45 HDATA7 B MMC mode: HDATA7 from/to HOST.
3.2.3 Flash Interface
Table 3.8 - 46 PIN LQFN Flash Interface
Pin No. Pin Name Type Description
11 CE0_ B ‘0’ for FLASH chip 0 to select active (low-active).
12 CE1_ B ‘0’ for FLASH chip 1 to select active (low-active).
14 CLE B FLASH command latch enable
13 ALE B FLASH address latch enable
46 RE_ B FLASH read enable (low active)
45 WE_ B FLASH write enable (low active)
44 BUSY_ B FLASH ready when high, busy when low.
15 WP_ B FLASH write protect (low active)
33 DA0 B FLASH bus bit0
34 DA1 B FLASH bus bit1
35 DA2 B FLASH bus bit2
36 DA3 B FLASH bus bit3
38 DA4 B FLASH bus bit4
41 DA5 B FLASH bus bit5
42 DA6 B FLASH bus bit6
43 DA7 B FLASH bus bit7
Table 3.9 - 54 PIN VFBGA Flash Interface
Pin No. Pin Name Type Description
B6 CE0_ B ‘0’ for FLASH chip 0 to select active (low-active).
C5 CE1_ B ‘0’ for FLASH chip 1 to select active (low-active).
C6 ALE B FLASH address latch enable
D5 CLE B FLASH command latch enable
D6 RE_ B FLASH read enable (low active)
E6 WE_ B FLASH write enable (low active)
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 22
E5 BUSY_ B FLASH ready when high, busy when low.
D4 WP_ B FLASH write protect (low active)
J5 DA0 B FLASH bus bit0
J6 DA1 B FLASH bus bit1
H5 DA2 B FLASH bus bit2
H6 DA3 B FLASH bus bit3
G6 DA4 B FLASH bus bit4
F5 DA5 B FLASH bus bit5
F6 DA6 B FLASH bus bit6
E4 DA7 B FLASH bus bit7
Table 3.10 – Die Pad Flash Interface
Pad No. Pad Name Type Description
PAD25 PAD_CE0_B B ‘0’ for FLASH chip 0 to select active (low-active).
PAD26 PAD_CE1_B B ‘0’ for FLASH chip 1 to select active (low-active).
PAD28 PAD_CLE B FLASH command latch enable
PAD27 PAD_ALE B FLASH address latch enable
PAD30 PAD_RE_B B FLASH read enable (low active)
PAD31 PAD_WE_B B FLASH write enable (low active)
PAD32 PAD_BUSY_B B FLASH ready when high, busy when low.
PAD29 PAD_WP_B B FLASH write protect (low active)
PAD43 PAD_DA0 B FLASH bus bit0
PAD42 PAD_DA1 B FLASH bus bit1
PAD41 PAD_DA2 B FLASH bus bit2
PAD40 PAD_DA3 B FLASH bus bit3
PAD38 PAD_DA4 B FLASH bus bit4
PAD35 PAD_DA5 B FLASH bus bit5
PAD34 PAD_DA6 B FLASH bus bit6
PAD33 PAD_DA7 B FLASH bus bit7
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 23
Table 3.11 – 46 PIN LGA Flash Interface
Pin No. Pin Name Type Description
26 CE0_ B ‘0’ for FLASH chip 0 to select active (low-active).
27 CE1_ B ‘0’ for FLASH chip 1 to select active (low-active).
28 ALE B FLASH address latch enable
29 CLE B FLASH command latch enable
31 RE_ B FLASH read enable (low active)
32 WE_ B FLASH write enable (low active)
15 BUSY_ B FLASH ready when high, busy when low.
30 WP_ B FLASH write protect (low active)
4 DA0 B FLASH bus bit0
5 DA1 B FLASH bus bit1
6 DA2 B FLASH bus bit2
7 DA3 B FLASH bus bit3
9 DA4 B FLASH bus bit4
12 DA5 B FLASH bus bit5
13 DA6 B FLASH bus bit6
14 DA7 B FLASH bus bit7
Table 3.12 – 51 PIN LGA Flash Interface
Pin No. Pin Name Type Description
11 CE0_ B ‘0’ for FLASH chip 0 to select active (low-active).
12 CE1_ B ‘0’ for FLASH chip 1 to select active (low-active).
14 ALE B FLASH address latch enable
13 CLE B FLASH command latch enable
10 RE_ B FLASH read enable (low active)
15 WE_ B FLASH write enable (low active)
9 BUSY_ B FLASH ready when high, busy when low.
16 WP_ B FLASH write protect (low active)
1 DA0 B FLASH bus bit0
2 DA1 B FLASH bus bit1
3 DA2 B FLASH bus bit2
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 24
4 DA3 B FLASH bus bit3
5 DA4 B FLASH bus bit4
6 DA5 B FLASH bus bit5
7 DA6 B FLASH bus bit6
8 DA7 B FLASH bus bit7
3.2.4 System Interface
Table 3.13 - 46 PIN LQFN System Interface
Pin No. Pin Name Type Description
7 MCLK I Main clock input.
8 Rst_ I Power-on reset, low active
9 OSCO O Main clock output
31 OSC_E I Oscillator enable
10 VDDIN P Power supply for IO
39 VDDIN P Power supply for IO
40 V18IN P Digital 1.8V power supply
37 GNDIN P Digital GND
19 VCC P 3.3V power supply
29 VCC P 3.3V power supply
21 GND P Ground
32 GND P Ground
24 CVDD18 P 1.8V power supply
30 VDDOUT P 3.3V power output
Table 3.14 - 54 PIN VFBGA System Interface
Pin No. Pin Name Type Description
B3 MCLK I Main clock input.
A3 Rst_ I Power-on reset, low active
C3 OSCO O Main clock output
E2 OSC_E I Oscillator enable
D2 VDDIN P Power supply for flash interface IO
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 25
F4 V18IN P Digital 1.8V power supply
F3 VCC P 3.3V power supply
G3 VCC P 3.3V power supply
G4 GND P Ground
G2 CVDD18 P 1.8V power supply
J4 VDDOUT P 3.3V power output
E3 Prt_ B Protect
G1 DETECT O Power detect
Table 3.15 - Die Pad System Interface
Pad No. Pad Name Type Description
PAD13 PAD_rst_B I Power-on reset input, low active
PAD14 PAD_rst_o O Power-on reset output
PAD44 PAD_Prt_B B Protect
PAD15 PAD_OSCO O Clock output for test
PAD12 PAD_MCLK I Main clock input.
PAD45 PAD_DETECT B Card detect
PAD46 PAD_DETECT B Backup PAD
(No Bonding)
PAD74 PAD_OSC_E I Oscillator enable
PAD73 PAD_OSC_E I Backup PAD
(No Bonding)
PAD23 VDDIN P Power supply for flash interface IO
PAD37 VDDIN P Power supply for flash interface IO
PAD36 V18IN P Digital 1.8V power supply
PAD39 GNDIN P Ground input
PAD53 VCC P 3.3V power supply
PAD56 GND P Ground
PAD57 GND P Ground
PAD62 CVDD18 P 1.8V power supply
PAD71 VCC P 3.3V power supply
PAD72 V33OUT P 3.3V power output when enhanced 8KV-ESD protected
PAD75 GND P Ground
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 26
Table 3.16 - 46 PIN LGA System Interface
Pin No. Pin Name Type Description
22 MCLK I Main clock input.
23 Rst_ I Power-on reset, low active
24 OSCO O Main clock output
2 OSC_E I Oscillator enable
10 VDDIN P Power supply for flash interface IO
25 VDDIN P Power supply for flash interface IO
1 VDDOUT P 3.3V power output
36 VCC P 3.3V power supply
46 VCC P 3.3V power supply
3 GND P Ground
38 GND P Ground
8 GNDIN P Ground
11 V18IN P 1.8V power supply
41 CVDD18 P 1.8V power supply
Table 3.17 - 51 PIN LGA System Interface
Pin No. Pin Name Type Description
51 MCLK I Main clock input.
23 Rst_ I Power-on reset, low active
49 OSCO O Main clock output
47 OSC_E I Oscillator enable
32 VDDIN P Power supply for flash interface IO
37 VCC P 3.3V power supply
39 GND P Ground
46 VDDOUT P 3.3V power output
33 Prt_ B Protect
50 DETECT O Power detect
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 27
3.2.5 Test Interface
Table 3.18 - 54 PIN VFBGA Test Interface
Pin No. Pin Name Type Description
A1 T0 B
A2 T1 B
B2 T2 B
B1 T3 B
C2 T4 B
C1 T5 B
D3 T6 B
D1 T7 B
Flash2 bus bit0 to bit7 when dual channel mode;
Flash bus bit8 to bit15 when 16-bit flash mode;
Test mode input when testing mode.
(On-chip pulled-up).
Table 3.19 - Die Pad Test Interface
Pad No. Pad Name Type Description
PAD16 PAD_T0 B
PAD17 PAD_T1 B
PAD18 PAD_T2 B
PAD19 PAD_T3 B
PAD20 PAD_T4 B
PAD21 PAD_T5 B
PAD22 PAD_T6 B
PAD24 PAD_T7 B
Flash2 bus bit0 to bit7 when dual channel mode;
Flash bus bit8 to bit15 when 16-bit flash mode;
Test mode input when testing mode.
(On-chip pulled-up).
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 28
CHAPTER 4 ELECTRICAL CHARACTERISTICS
4.1 Absolute Maximum Ratings
Table 4.1 - Absolute Maximum Ratings
Parameter Symbol
Min Max.
Unit
Remark
Supply Voltage V
DD
2.0 3.6 V CMD0, 15,55, ACMD41
Supply Voltage Differentials (V
ss1
, V
ss2
)
-0.3 0.3 V
Storage Temperature -40 85
o
C
Junction Temperature 95
o
C
4.2 Bus Operating Conditions
Table 4.2 - Bus Operating Conditions
Parameter Symbol
Min Max.
Unit Remark
Peak Voltage on all Lines V
DD
2.6 3.6 V
Ground Voltage 0 V
Operation Temperature -25 85
o
C
Operation Moisture and Corrosion 95% Rel. humidity
4.3 D.C. Characteristics
Table 4.3 - D.C. Characteristics
Parameter Symbol
Condition Min
Typ.
Max
Unit
Supply voltage
V
CC
2.0 3.3 3.6 V
Input Leakage Current
(HCLK, HCMD and HDATA2-0 to
Ground)
I
I
0< V
IN
< V
CC
0.2 - 0.3 µA
Input Leakage Current
(HCLK, HCMD and HDATA2-0 to V
DD
) I
I
0< V
IN
< V
CC
0.2 - 0.3 µA
Input Leakage Current at HDATA3 to
Ground I
I
0< V
IN
< V
CC -
- 0.43
µA
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 29
Output High Voltage at HCMD V
OH
Clock = 20MHz
- - 3588
mV
Output High Voltage at HDATA V
OH
Clock = 20MHz
- - 3586
mV
Output Low Voltage at HCMD V
OL
Clock = 20MHz
39 - - mV
Output Low Voltage at HDATA V
OL
Clock = 20MHz
39 - - mV
Read/Write Current I
CC
- - mA
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 30
CHAPTER 5 PACKAGE DIMENSION
Figure 5.1- 46 Pin LQFN Package Dimension
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 31
Figure 5.2- 54 Pin VFBGA Package Dimension
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 32
Figure 5.3- 46 PIN LGA Package Dimension
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 33
Figure 5.4- 51 PIN LGA Package Dimension
GL424 SD/MMC Flash Card Controller
©2000-2007 Genesys Logic Inc. - All rights reserved. Page 34
CHAPTER 6 ORDERING INFORMATION
Table 6.1- Ordering Information
Part Number Package Normal/Green Version Status
GL424-PMGXX 46-Pin LQFN
Green Package XX Available
GL424-PMGXX 54-Pin VFBGA
Green Package XX Available
GL424-WMGXX 46-Pin LGA Green Package XX Available
GL424-WOGXX 51-Pin LGA Green Package XX Available
