SPICE Device Model Si4840DY N-Channel 40-V (D-S) MOSFET Characteristics * N-channel Vertical DMOS * Macro-Model (Sub-circuit) * Level 3 MOS * Applicable for Both Linear and Switch Mode * Applicable Over a -55 to 125C Temperature Range * Models Gate Charge, Transient, and Diode Reverse Recovery Characteristics Description capacitance network is used to model gate charge characteristics while avoiding convergence problems of switched Cgd model. Model parameter values are optimized to provide a best fit to measure electrical data and are not intended as an exact physical description of a device. The attached SPICE Model describes typical electrical characteristics of the n-channel vertical DMOS. The sub-circuit model was extracted and optimized over a 25C to 125C temperature range under pulse conditions for 0 to 10 volts gate drives. Saturated output impedance model accuracy has been maximized for gate biases near threshold. A novel gate-to-drain feedback Model Sub-circuit D 4 R1 M2 M1 G CGS 3 DBD 1 2 S This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Siliconix 4/16/01 Document: 71483 1 SPICE Device Model Si4840DY Model Evaluation N-Channel Device (TJ=25C Unless Otherwise Noted) Parameter Static Gate Threshold Voltage On-State Drain Current a Drain-Source On-State Resistance a Symbol Test Conditions Typical Unit VGS(th) ID(on) rDS(on) VDS = VGS, ID= 250A VDS 5V, VGS = 10V VGS = 10V, ID = 14A VGS = 4.5V, ID = 12A VDS = 15V, ID = 14A IS = 2.8A, VGS = 0V 1.37 672 0.0066 0.0097 49 0.74 V A Forward Transconductance a Diode Forward Voltage a Dynamic b Total Gate Charge Gate-Source Charge gfs VSD Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Qgd td(on) tr td(off) Fall Time Source-Drain Reverse Recovery Time Qg Qgs tf trr VDS = 20V, VGS = 5V, ID = 14A VDD = 20V, RL = 20 ID 1A, VGEN =10V, RG = 6 IF = 2.8A, di/dt=100A/s S V 18.7 6 nC 7.5 10 12 38 ns 68 38 Notes: a) Pulse test; pulse width 300 s, duty cycle 2% b) Guaranteed by design, not subject to production testing Siliconix 4/16/01 Document: 71483 2 SPICE Device Model Si4840DY Comparison of Model with Measured Data (TJ=25C Unless Otherwise Noted) 50 Vgs= 10,7,6,5,4V 50 125C ID - Drain Current (A) Ids (A) 40 30 20 Vgs=3V 10 -55C 40 30 20 10 25C 0 0 0 1 2 3 Vds (V) 4 5 8 0 6 0.100 0.020 6 0.075 0.016 4 0.050 2 0.025 0.5 1 1.5 2 2.5 3 Vgs - Gate-to-Source Voltage (V) 3.5 4 Rds (ohm) Rds (ohm) Sqrt (Ids) (A) Sqrt( Ids ) 0.012 Vgs=4.5V 0.008 Vgs=10V 0.004 Rds 0 0 2 4 6 0.000 10 8 0.000 0 Vgs ( V ) 10 20 30 40 50 Ids (A) 3000 20 10 Vds Vgs 2000 16 8 12 6 8 4 4 2 1500 1000 500 Coss Crss 0 0 Siliconix 4/16/01 Document: 71483 8 16 24 Vds ( V ) 32 40 0 0 7 14 21 28 Qg (nC) 3 0 35 Vgs (V) Ciss Vds (V) Capacitance (pF) 2500