M29W320DB70N6E - STMicroelectronics

1/44May 2003

M29W320DT

M29W320DB

32 Mbit (4Mb x8 or 2Mb x16, Boot Block)

3V S uppl y F l ash M emory

FEATURES SUMM ARY

■SUPPLY VOLTAGE

–V

CC = 2.7V to 3.6V for Program, Erase and

Read

–V

PP =12V for Fast Program (optional)

■ACCESS TIME: 70, 90ns

■PRO GRAMMING TI ME

– 10µs per Byte/Word typical

■67 MEMORY BLOCKS

– 1 Boot Block (Top or Bottom Locat ion)

– 2 Parameter and 64 Main Blocks

■PROGRAM/E RA SE CONTROLLER

– Embedded Byt e/Word Program algorithms

■ERASE SUSPEND and RESUM E MOD ES

– Read and Program another Block during

Erase Su spend

■UNLOCK BYPASS PROGRAM COMMAND

– Fas ter Production/Batc h Prog ramm ing

■VPP/WP PIN fo r FAST PRO GRAM and WRITE

PROTECT

■TEMPORARY BLOCK UNPROT ECTION

MODE

■COMMON FLASH INTE RFACE

– 64 bit Security Code

■LOW POWER CONSUM PTION

– Standby and Autom atic Standby

■100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h

– Top Device Code M29 W320DT : 22CAh

– Bottom Device Code M2 9W320DB: 2 2CB h

Figure 1. Packages

TSOP48 (N)

12 x 20mm

TFBGA63 (ZA)

63 ball array

FBGA

M29W320DT, M29W320DB
2/44
TABLE OF CONT ENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table  1. Signal Nam es  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP  Connec tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . 6
Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 1 0
Addre ss Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
D ata Inputs/Ou tputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
D ata Inputs/Ou tputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
D ata Input/Output or Address Input (DQ15A– 1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 10
Out put Enabl e (G).  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
W rite Enable (W).  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VPP/Write Protect  (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
R eady/Busy  Out put (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Byte/W ord Organization  Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VCC Supply Volt age (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
V
SS Ground.  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 11
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 1 2
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Disab le. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Standby .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Autom at ic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Special Bus Operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ele ctronic Signature. . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Protect a nd Chip Unprotect.  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Protect a nd Chip Unprotect.  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2. Bus Operations, BYTE = V IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Bus Operations, BYTE = V IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
COMMAND INTERFACE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
R ead/Res et Comm and.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Auto Se lect Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 1 4
Unlock Bypass Command.  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3/44
M29W320DT, M29W320DB
C hip Erase Comm and.  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5
Block Erase  Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Erase S uspend Com ma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table  4. Comm and s, 16-bit mode, BYT E  = VIH  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table  5. Comm and s, 8-bit mode, B Y TE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table  6. Program , Erase Times  and Prog ram, Erase Enduranc e Cyc les . . . . . . . . . . . . . . . . . . . . 19
STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Toggl e Bit (DQ6). .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9
Error Bit (DQ5).  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0
Alternative Tog gle Bit (DQ2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table  7. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table  8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table  9. Operating and AC M easurem ent  Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. AC Measurement I/O Waveform  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table  10. Device Capacitanc e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table  11. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table  12. Read AC  Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Write AC Wav eforms,  Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table  13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. Write AC Characteristics, Ch ip Enable Controlled  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. Accelerated Program Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PAC KAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16. TSOP48 Lead Plast ic Thin Small Out line, 12x20 mm,  Bottom View Package O utline  . 29
Figure 16. TSOP48 Lead Plast ic Thin Small Out line, 12x20 mm,  Bottom View Package O utline  . 29
Figure 17. TFBGA6 3 7x11mm  - 6x8 active ball a rray, 0.8mm  pitch, Package Ou tline . . . . . . . . . . 30
Table 17. TFBGA63 7x11mm - 6x8 act iv e ball arr ay, 0.8mm pitch, P ackage Mechanical Dat a . . . 30
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table  18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

M29W320DT, M29W320DB
4/44
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table  19. Top Boot  Block Addres ses, M29 W320DT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20. Bottom Boot Blo ck Addresses, M29W320DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
APPENDIX B. COMMON FLASH INTER FACE (CFI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table  21. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table  22. CFI Query Identification String  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table  23. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table  24. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table  25. Pri mary Algorithm -Spe cific Extende d Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table  26. Secu rity Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7
APPENDIX C. BLOCK PROTEC TION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
In-System Technique  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table  27. Prog ramm er Techni que Bu s Operations , BYTE  = VIH or VIL  . . . . . . . . . . . . . . . . . . . . . 38
Figure 18. Progra mmer Equipment Block Protect Flowchart  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 19. Programmer Equipment Chip Unprotect Flowcha rt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 20. In-System Equipment Block Protect Flowchart  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 21. In-System Equipment Chip Unprotect Flowcha rt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 28. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

5/44

M29W320DT, M29W320DB

SUMMARY DESCRIPTION

The M29W320D is a 32 Mbit (4Mb x8 or 2Mb x16)

non-volatile memory that can be read, erased and

reprogrammed. These operations can be per-

formed using a single low voltage (2.7 to 3.6V)

supply. On power-up the memory defaults to its

Read mode where it can be read in the same way

as a ROM or EPROM.

The memory is divided into blocks that can be

erased independently so it is pos sible to preserv e

valid data while old dat a is erased. Each block can

be protected independently to prevent accidental

Program or Erase commands from modifying the

memory. P rogram and Eras e com m ands are wri t-

ten to the Com mand Interface of t he memory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of al l of the special operations that are

required to update the mem ory con tents. The end

of a program or erase op eration can be detected

and any error conditions identified. The c om m and

set required to control the memory is consistent

with JEDEC standards.

The blocks in the memory are asymmetrically ar-

ranged, see Figures 5 and 6 and Tables 19 and

20. The first or last 64 Kbytes have been di vided

into four additional blocks. The 16 Kbyte Boot

Block can be used for small initialization code to

start the microprocessor, t he two 8 Kbyte Param -

eter Blocks can be used f or par ameter storage and

the remaining 32 Kbyte is a small Main Block

where the application may be stored.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic .

The memory is offered in TSOP48 (12 x 20mm) and

TFBGA63 (7x11mm, 0.8mm pitch) packages. The

memory is supplied with all the bits erased (set to

1).

Figure 2. Logic Diagram Tabl e 1. Signal Names

AI90189B

A0-A20

DQ0-DQ14

VCC

M29W320DT

M29W320DB

VSS

DQ15A–1

VPP/WP

BYTE

A0-A20 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

DQ8-DQ14 Data Inputs/Outputs

DQ15A–1 Data Input/Output or Address Input

EChip Enable

GOutput Enable

WWrite Enable

RP Reset/Block Temporary Unprotect

RB Ready/Busy Output

BYTE Byte/Word Organization Select

VCC Supply Voltage

VPP/WP VPP/Write Protect

VSS Ground

NC Not Connected Internally

M29W320DT, M29W320DB

6/44

Figu re 3. TSOP C onnecti on s

DQ3

DQ9

DQ2

A6 DQ0

DQ6

A9 DQ13

A17

A10 DQ14

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

DQ7

VPP/WP

AI90190

M29W320DT

M29W320DB

24 25

DQ8

A20

A19

A18

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15

A14 VSS

VSS

7/44

M29W320DT, M29W320DB

Figure 4. TFBGA Connections (Top view through package)

Note: 1. Ball s are short ed toget her via the subs trate but not connected to t he die.

654321

VSS

A15

A14

A12

A13

DQ3

DQ11

DQ10

A18

VPP

DQ1

DQ9

DQ8

DQ0

A17

DQ2

DQ6

DQ13

DQ14

A10

DQ4

VCC

DQ12

DQ5

A19

A11

DQ7

VSS

A5 A20

A16

BYTE

DQ15

A–1

NC(1)

AI05525B

M29W320DT, M29W320DB

8/44

Figure 5. Block Add resse s (x8)

Note: Also see A ppendix A, T ables 19 and 20 for a f ul l l is t i ng of the Bl ock Add resses .

AI90192

16 KByte

3FFFFFh

3FC000h

64 KByte

01FFFFh

010000h

64 KByte

00FFFFh

000000h

M29W320DT

Top Boot Block Addresses (x8)

32 KByte

3F7FFFh

3F0000h

64 KByte

3E0000h

3EFFFFh

Total of 63

64 KByte Blocks

16 KByte

3FFFFFh

3F0000h 64 KByte

64 KByte

003FFFh

000000h

M29W320DB

Bottom Boot Block Addresses (x8)

32 KByte

3EFFFFh

01FFFFh 64 KByte

3E0000h

010000h

Total of 63

64 KByte Blocks

00FFFFh

008000h

8 KByte

3FBFFFh

3FA000h

3F9FFFh

3F8000h

8 KByte

007FFFh

006000h

005FFFh

004000h

9/44

M29W320DT, M29W320DB

Figure 6. Block Addresses (x16)

Note: Also see A ppendix A, T ables 19 and 20 for a f ul l l is t i ng of the Bl ock Add resses .

AI90193

8 KWord

1FFFFFh

1FE000h

32 KWord

00FFFFh

008000h

32 KWord

007FFFh

000000h

M29W320DT

Top Boot Block Addresses (x16)

16 KWord

1FBFFFh

1F8000h

32 KWord

1F0000h

1F7FFFh

Total of 63

32 KWord Blocks

8 KWord

1FFFFFh

1F8000h 32 KWord

32 KWord

001FFFh

000000h

M29W320DB

Bottom Boot Block Addresses (x16)

16 KWord

1F7FFFh

00FFFFh 32 KWord

1F0000h

008000h

Total of 63

32 KWord Blocks

007FFFh

004000h

4 KWord

1FDFFFh

1FD000h

1FCFFFh

1FC000h

4 KWord

003FFFh

003000h

002FFFh

002000h

M29W320DT, M29W320DB

10/44

SIGNA L DESCRIPTIONS

See Figure 2, Logic Diag ram, and T able 1, Sign al

Names, for a brief overview of the s ignals connect -

ed to this device.

Address Inputs (A0-A20). The Address Inputs

select the cell s in the memory arra y to access dur-

ing Bus Read operations. During Bus Writ e opera-

tions they control the commands sent to the

Comman d Interface of the internal state ma chine.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation. During Bus Write

operations they represent the commands sent to

the Command Interface of the internal state ma-

chine.

Data Inputs/Output s (DQ8-DQ14). The Data I/O

outputs the data stored at the selected address

during a Bus Re ad operation when B Y TE is High,

VIH. When BYTE is Low, VIL, these pins are not

used and are high impedance. During Bus Write

operations the Command Register does not use

these bits. When reading the Status Register

these bits should be ignored.

Data Input/Output or Address Input (DQ15A–1).

When BYTE is High, VIH, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, VIL, this pin behav es as an address

pin; DQ15A–1 Low wil l select t he LSB of the Word

on the other addresses, DQ15A–1 High will select

the MSB. Throughout the t ext consider references

to the Data Input/Output to include this pin when

BYTE is High and references to the Address In-

puts to inclu de this pin when B YTE is Low e xcept

when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates

the memor y, allowing Bus Read and Bus Wr ite op-

erations to be performed. When Chip Enable is

High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-

trols th e Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

ma nd Inte r face .

VPP/Write Protect (VPP/WP). The VPP/Write

Protect

pin provides two functions. The VPP f unc-

tion allows the memory to use an external high

volt age po wer su pply to r educ e the time req ui re d

for Unlock Bypass Program operations. The

Wri t e Pro tec t fu nct io n prov i des a ha rd ware me th-

od of protecting the 16 Kbyte Boot Block. The

VPP/Write Protect pin must not be left floating or

unconnected.

When VPP/Write Prote ct i s L ow , VIL, the me mo r y

protects the 16 Kbyte Boot Block; Program and

Erase operations in this block are ignored while

VPP/Write Protect is Low.

W hen VPP/Write P rotect is High, VIH, the memor y

reverts to the previou s protection status of the 16

Kbyte boot block. Program and Erase operations

can now modify the data in the 16 Kbyte Boot

Block unless the block is protected using Block

Protection.

When VPP/Write Protect is raised t o VPP the mem-

ory automat ically enters the Unlock Bypass mode.

When V PP/Write Protect returns to VIH or VIL nor-

mal operation resumes. During Unlock Bypass

Program operations the memory draws IPP from

the pin to supply the progr amming circuits. See the

description of th e Unlock B y pass c ommand in the

Command Interface section. The transitions from

VIH to VPP and from VPP to VIH must be slower

than tVHVPP, see Figure 15.

Never raise VPP/Write Protect to VPP from any

mode except Read mode, otherwise the memory

may be left in an indeterm inat e state.

A 0.1µF capacitor should be connected between

the VPP/Write Protect pin and the VSS Ground pin

to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the curren ts required during Unlock Bypass

Program, IPP.

Reset/Block Temporar y Unprotect (RP). The

Reset/Block Temporary Unprotect pin can be

used to apply a Hardwar e Reset to the memory or

to temporarily u nprotect al l Block s that have been

protected.

Note that if VPP/WP is at VIL, then the 16 KByte

outermost boot block will remain protect even if RP

is at VID.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, VIL, for at least

tPLPX. After Reset/Block Temporary Unprotect

goes High, V IH, the memory will be ready for Bus

Read and Bus Write operations after tPHEL or

tRHEL, whichever occurs last. See the Ready/ Busy

Output section, Table 15 and Figure 14, Reset/

Temporary Unprot ect AC Characte ristics for more

details.

Holding RP at VID will temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from VIH to VID must be slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to identify

when the device is performing a Program or Erase

operation. During Program or Erase operations

Ready/Busy is Low, V OL. Ready/Busy is high-im-

pedance during Read mode, Auto Select mode

and Erase Suspend m ode.

11/44

M29W320DT, M29W320DB

Note that if VPP/WP is at VIL, then the 16 KByte

outermost boot block will remain protect even if RP

is at VID.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes h igh-impeda nc e. See Tabl e 15 and Figure

14, Reset/Temporary Unprotect AC Characteris-

tics.

The use of an open-drain out put allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or m ore, of the memories is busy.

Byte/Word Organization Select (BYTE). The

Byte/Word Organization Select pin is used to

switch between the x8 and x 16 Bus modes of the

memory. When Byte/Word Organization Select is

Low, VIL, the memory is in x8 mode, when it is

High, VIH, the memory is in x16 mode.

VCC Supply Voltage (2.7V to 3.6V). VCC pro-

vides the power supply for all operations (Read,

Program and Eras e).

The Command Interface is dis abled when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This prevent s Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being alt ered will be invalid.

A 0.1µF capacitor should be connected between

the V CC Supply Voltage pin and the VSS Ground

pin to decoupl e the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during Program and

Erase operations, I CC3.

VSS Ground. VSS is the reference for all voltage

measurements.

M29W320DT, M29W320DB

12/44

BUS OPERATIONS

There are five standard bus operations that control

the device. These are Bus Read, Bus Wri te, Out-

put Disable, Standby and Automatic Standby. See

Tables 2 and 3, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chi p Enable

or Write Enable are ignored by the memory and do

not affec t bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desi red address on the Address

Inputs, appl ying a Low s ig nal, VIL, to C hip Enable

and Output Enable and keeping Write Enable

High, VIH. The Data Input s/Ou tputs will outp ut the

value, see Figure 11, Read Mode AC Waveforms,

and Table 12, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desire d address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Dat a Input s/Outpu ts a re latched by the Com -

mand Interface on the rising edge of Chip Enab le

or Write Enable, whichever occurs first. Output En-

able must remai n High, VIH, du ring the whole Bus

Write operat ion. See Figures 12 and 13, Write AC

Waveforms, and Tables 13 and 14, Write AC

Characteristics, for details of the timing require-

ments.

Outp ut Disable . The Data Inputs/Outputs are in

the high impedance state when Output Enable is

High, VIH.

Standby. When Chip Enable is High, VIH, the

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high-imped-

ance state. To reduce the Supply Current to the

Standby Supply Current, ICC2, Chip Enable should

be held within VCC ± 0.2V. For t he Standby current

level see Table 11, DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, ICC3, for Program or Erase operations un-

til the operat ion com pletes .

Automatic Standby. If CMOS levels (VCC ± 0.2V)

are used to drive the bus and the bus is inactive for

300ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the Standby Supply Current, ICC2. The

Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

Special Bus Operati ons

Additional bus operations can be performed to

read the Electronic Signature and also to apply

and remove Block Protection. These bus opera-

tions are intended for use by programmi ng eq uip-

ment and are not usually used in applications.

They require VID to be appl ied to some pins.

Electronic Sign atur e. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These co des can be re ad by app lying the signals

listed in T able s 2 and 3, Bus Operations.

Block Protect and

Chip Unprotect.

Each block

can be separately protected against accidental

Program or Erase. T he who le chip can be unpro-

tected to allow the data inside the blocks to be

changed.

Block Protect and Chip Unprotect operations are

described in Appendix C.

13/44

M29W320DT, M29W320DB

Table 2. Bus Operations, BYTE = VIL

No te: X = VIL or VIH.

Table 3. Bus Operations, BYTE = VIH

No te: X = VIL or VIH.

Operation E G W Address Inputs

DQ15A–1, A0-A20 Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Bus Read VIL VIL VIH Cell Address Hi-Z Data Output

Bus Write VIL VIH VIL Command Address Hi-Z Data Input

Output Disable X VIH VIH X Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH Hi-Z 20h

Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL,

A9 = VID, Others VIL or VIH Hi-Z CAh (M29W320DT)

CBh (M29W320DB)

Operation E G W Address Inputs

A0-A20 Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Bus Read VIL VIL VIH Cell Address Data Output

Bus Write VIL VIH VIL Command Address Data Input

Output Disable X VIH VIH X Hi-Z

Standby VIH X X X Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH 0020h

Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID,

Others VIL or VIH 22CAh (M29W320DT)

22CBh (M29W320DB)

M29W320DT, M29W320DB

14/44

COMMAND INTERFACE

All Bus Write operations t o the memory are in ter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a vali d sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

The address used for the commands changes de-

pending on whether the mem ory is in 16-bit or 8-

bit mode. See e ither Table 4, or 5, depending on

the configuration that is being used, for a summary

of the com m ands .

Read/Reset Comm and. The Read/Reset com-

mand returns the memory to its Read mode where

it behaves like a ROM or EPROM, unless other-

wise stated. It also reset s the errors in th e Status

can be used to is sue the Read/Reset command.

The Read/Reset Command can be issued, be-

tween Bus Write cycles before the start of a pro-

gram or erase operation, to return the device to

read mode. Once the program or eras e o perati on

has started the Read/Res et comm and is no longer

accepted. The Read/Reset command will not

abort an Erase operation when issued while in

Erase Suspend.

Auto Select Co mmand. The Auto Select com-

mand i s us ed to read the Man ufacturer Code, the

Device Code and the Block Protection Status.

Three consecutive Bus Write operations are re-

quired to issue the Auto Select command. Once

the Auto Select command is issued the memory

remains in Auto Select mode until a Read/Reset

command is issued. Read CFI Query and Read/

Reset commands are accepted in Auto Select

mode, all other commands are ignored .

From the Auto Select mode the Manufacturer

Code can be read using a Bus Read operation

with A 0 = VIL and A1 = VIL. The other address bits

may be set to eith er VIL or VIH. The Ma nufa cturer

Code for STMicroelectronics is 0020h.

The Device Code can b e read using a Bus Read

operation with A0 = VIH and A1 = VIL. The other

address bits may be set to either V IL or VIH. The

Device Code for the M29W320DT is 22CAh and

for the M29W320DB is 22CB h.

T he Block P rotec tion S t atus o f each block can be

read using a Bus Read operation with A0 = VIL,

A1 = VIH, and A12 -A 2 0 s p ecifyi ng th e addr ess of

th e block. The other address bits may be set to ei-

ther VIL or VIH. If th e addr ess ed bloc k is p rot ecte d

then 01h is output on Data Inputs/Outputs DQ0-

DQ7, otherwise 00h is output.

Read CFI Query Comman d . The Read CFI

Query Command is used to read data from the

Common Flash Interface (CFI) Memory Area. This

command is valid when the device i s in the Read

Array mode, or when the device is i n Autoselected

mode.

One Bus Write cycle is required to issue the Read

CFI Query Command. Once the command is is-

sued subsequen t Bus Read ope ratio ns read from

the Common Flash Interface Memory Area .

The Read/Reset command must be issued to re-

turn the device to the previous mode (the Read Ar-

ray mode or Autoselected mode). A second Read/

Reset command would be needed if the device is

to be put in the Read Array mode from Aut oselect-

ed mode.

See Appendix B, Tables 21, 22, 23, 24, 25 and 26

for details on the information contained in the

Common Flash Interface (CFI) memory area.

Progra m Command . The Program command

can be used to program a value to one address in

the memory array at a time. The command re-

quires four Bus Write operations, the final write op-

eration latches the address and data in the internal

state machine and starts the Program/Erase Con-

troller.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is never read and

no error condition is given.

During the program o peration the memory will ig-

nore all co mmands. I t is not poss ible t o issue any

command to abort or pause the operation. Typical

program times are given in T able 6. Bus Read op-

erations during the program operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be i ssued to re-

set th e error condition and return to Read mode.

Note that t he Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole memory from ’0’ to ’1’.

Unlock Bypass Comma nd. The Unlock Bypass

command is used in conjunction with the Unlock

Bypass Program c ommand to program the memo-

ry. When the cycle time to the device is long (as

with some EPROM programmers) considerable

time saving can be made by using these com-

mands. Three Bus Write operations are required

to issue the Unlock Bypass comm and.

Once the Unlock Bypass command has been is-

sued the memory will only accept the Unlock By-

15/44

M29W320DT, M29W320DB

pass Program command and the Unlock Bypass

Reset command. The memory can be read as if in

Read mode.

The memory offers accelerated program opera-

tions through the VPP/Write Protect pin. When the

system asserts V PP on the VPP/Write Prot ect pin,

the memory automatically enters the Unlock By-

pass mode. The system may then write the two-

cycle Unlock Bypass program command se-

quence. The memory uses the higher voltage on

the VPP/Write Protect pin, to accelerate the Unlock

Bypass Program opera tion.

Never raise VPP/Write Protect to VPP from any

mode except Read mode, otherwise the memory

may be left in an indeterm inat e state.

Unlock Bypass Prog ram Comm an d. The Un-

lock Bypass Program command can be used to

program one address in the memory array at a

time. The command requires tw o Bus Write oper-

ations, the final write operation latches the ad-

dress and data in the internal state machine and

starts the Program/Erase Controller.

The Program operation using the Unlock Bypass

Program c ommand behaves identically to the Pro-

gram oper at ion using the Program command. The

operation cannot be aborted, the Status Register

is read and protected blocks cannot be pro-

grammed. Errors must be reset using the Read/

Reset command, which leaves the device in Un-

lock Bypass Mode. See the Program command for

details on the behavior.

Unlock Bypass Reset Comman d. The Unlock

Bypass Re se t command can be used to ret urn to

Read/Reset mode from Unlock Bypass Mode.

Two Bus Write operations are required to issue the

Unlock Bypass Reset command. Read/Reset

command does not exit from Unlock Bypass

Mode.

Chip Erase Command. The Chip Erase com-

mand can be used to erase the entire chip. Six Bus

Write operations are required to issue the Chip

Erase Command and start the Program/Erase

Controller.

If an y blocks are protected then these are ignored

and all the other blocks are erased. If all of the

blocks a re p rote cted the Chip Erase op erat i on ap-

pears to start but will terminate within about 100µs,

leaving the data unchange d. No error co ndition is

given when protected blocks are ignored.

During the erase operation the memory wi ll ignore

all commands , including the E rase Suspen d com-

mand. It is no t possible to i ssue any c ommand t o

abort the operation. Typical chip erase times are

given in Table 6. All Bus Read operations during

the Chip Erase operation will output the Status

tion on the Status Register for more details.

After the Chip Erase opera tion has com pleted the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be i ssued to re-

set th e error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’1’. All previous

data is lost.

Block Erase Command. The Block Erase com-

mand can be used to erase a list of one or more

blocks. Six Bus Write operations are required to

select the first block in the list. Each additional

block in the list can be selected by repeating the

sixth Bus Wr ite operation using the addres s of the

additional block. The Bl ock Erase operation st arts

the Program/Erase Controller about 50µs after the

last Bus Write operation. Once the Program/Erase

Controller starts it is not possible to select any

more blocks. Each additional block must therefore

be selected within 50µs of the last block. The 50µs

timer r estarts when an additional block is select ed.

The Status Register can be read after the sixth

Bus Write operati on. See the Stat us Register sec-

tion for details on how to identify if the Program/

Erase Controller has started the Block Erase oper-

ation.

If any selected blocks are protected then these are

ignored and all the other selected blocks are

erased. If all of the selected blocks are protected

the Block Erase operation appears to s tart but will

terminate within about 100µs, l eaving the data un-

changed. No error condition is given when protect-

ed blocks are igno red.

During the Blo ck Erase ope ra tion the me mory will

ignore all commands except the Erase Suspend

command. Typical block e rase tim es are given in

Table 6. All Bus Read operations during the Block

Erase op eration will ou t pu t the Status R eg i st er o n

the Data Inputs/Outputs. See the section on the

Status Regist er for more details.

After the Block Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be i ssued to re-

set the error condition and return to Read mode.

The Block Erase Command sets all of the bits in

the unprotected selec ted blocks to ’1’. All previous

data in the selected blocks is lost.

Erase Suspend Comm and. The Erase Suspend

Comman d m ay be used to temporari ly sus pend a

Block Erase operation and return the memory to

Read mode. The command requires one Bus

Write operation.

The Prog ram/Eras e Controlle r will sus pend within

the Erase Suspend Latency Time (refer t o Table 6

M29W320DT, M29W320DB

16/44

for value) o f the Erase Suspend Command being

issued. Once the Program/Erase Controller has

stopped the memory will be set t o Read mode and

the Erase will be suspended. If the Erase Suspend

command is issued during the period when the

memory is waiting for an additional block (before

the Program/Erase Controller starts) then the

Erase is susp ended i mmedi ately and wi ll start im-

mediately when the Erase Resume Command is

issued. It is not possible to select any further

blo cks to erase a fte r th e Eras e Resume.

During Erase Suspend it is possible to Read and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these blocks. If any attempt is made to

program in a protec ted bl ock or in the suspended

block then the Program command is ignored and

the data remains unchanged. The Status Register

is not read and no error condi tio n is given. Read-

ing from blocks that are being erased will output

the Status Register.

It is also possible to issue the Auto Select, Read

CFI Query and Unlock Bypass commands during

an Erase Suspend. The Read/Reset command

must be i ssued to return the device to Read Array

mode before the Resume command will be ac-

cepted.

Erase Resum e Command. The Erase Resume

command must be used to restart the Program/

Erase Controller after an Erase Suspend. The de-

vice must be in Read Array mode before the Re-

sume command will be accepted. An erase can be

suspended and resum ed more than onc e.

Block Protect and

Chip Unprotect Commands.

Each block can be separately protected against

accidental Progra m or E rase. The whol e c hip can

be unprotect ed to allow the data inside the blo cks

to be changed.

Block Protect and Chip Unprotect operations are

described in Appendix C.

17/44

M29W320DT, M29W320DB

Table 4. Command s, 16-bit mode, BYTE = VIH

Note: X Don’t Care, PA P rogram A ddre ss , P D Program Da ta, BA Any address in th e Block. Al l values i n the table are in hexadec i mal.

Th e Com ma nd Inte rfac e onl y us es A – 1, A0-A 1 0 and DQ 0-D Q7 to v erify the co mman ds ; A1 1-A2 0, D Q8- DQ14 and DQ 15 are D on’t

Care. DQ15A–1 i s A–1 wh en BYTE is VIL or DQ15 when BY TE is VIH.

Read/Reset. A fter a Read/ Re set com man d, rea d the m emor y as no rmal un til an ot her comm and is iss ued . Read /Res et co mmand is

ignored durin g al gorithm exec ut i on.

Auto Select. Aft er an Auto S elec t c om mand, read Manufact urer ID , Device ID or Block Protection Sta tus.

Pro gram , Unl ock By pass Progra m, Ch ip E rase, Blo ck Eras e . A fter these com mands read the S tatus Regi st er until t he Program /

Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional

Bus Write Operations until T i meout Bit is set.

Unlo ck Byp as s. After the Unlo ck Bypas s command issue Unlock Bypass Pr ogram or Unl ock By pass Reset comman ds.

Unlo ck Byp as s Re s et. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-

mands on no n-era sing bloc ks as nor m al .

Erase Resume. Af t er the Erase Resume comman d the suspended Er ase operati on resum es, read the Status Register until th e Pro-

gram/Er ase Cont rolle r complet es an d the memo r y returns to Re ad Mo de.

CFI Qu e r y. Co m m and is va l i d when de vice is re ady to read array data or when de vi ce is in au tosel ected mode.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3 555 AA 2AA 55 X F0

Auto Select 3 555 AA 2AA 55 555 90

Program 4 555 AA 2AA 55 555 A0 PA PD

Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock Bypass

Program 2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Read CFI Query 1 55 98

M29W320DT, M29W320DB

18/44

Table 5. Commands, 8-bi t mode, BYTE = VIL

Note: X Don’t Care, PA P rogram A ddre ss , P D Program Da ta, BA Any address in th e Block. Al l values i n the table are in hexadec i mal.

Th e Com ma nd Inte rfac e onl y us es A – 1, A0-A 1 0 and DQ 0-D Q7 to v erify the co mman ds ; A1 1-A2 0, D Q8- DQ14 and DQ 15 are D on’t

Care. DQ15A–1 i s A–1 wh en BYTE is VIL or DQ15 when BY TE is VIH.

Read/Reset. A fter a Read/ Re set com man d, rea d the m emor y as no rmal un til an ot her comm and is iss ued . Read /Res et co mmand is

ignored durin g al gorithm exec ut i on.

Auto Select. Aft er an Auto S elec t c om mand, read Manufact urer ID , Device ID or Block Protection Sta tus.

Pro gram , Unl ock By pass Progra m, Ch ip E rase, Blo ck Eras e . A fter these com mands read the S tatus Regi st er until t he Program /

Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional

Bus Write Operations until T i meout Bit is set.

Unlo ck Byp as s. After the Unlo ck Bypas s command issue Unlock Bypass Pr ogram or Unl ock By pass Reset comman ds.

Unlo ck Byp as s Re s et. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-

mands on no n-era sing bloc ks as nor m al .

Erase Resume. Af t er the Erase Resume comman d the suspended Er ase operati on resum es, read the Status Register until th e Pro-

gram/Er ase Cont rolle r complet es an d the memo r y returns to Re ad Mo de.

CFI Qu e r y. Co m m and is va l i d when de vice is re ady to read array data or when de vi ce is in au tosel ected mode.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3 AAA AA 555 55 X F0

Auto Select 3 AAA AA 555 55 AAA 90

Program 4 AAA AA 555 55 AAA A0 PA PD

Unlock Bypass 3 AAA AA 555 55 AAA 20

Unlock Bypass

Program 2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Read CFI Query 1 AA 98

19/44

M29W320DT, M29W320DB

Table 6. Program , Erase Times and Progra m , Erase Endu ran ce Cycles

No te : 1. Typ i cal values mea sured at r oom temperature and nomi nal voltages.

2. Sampled, but not 100% tested.

3. Max imum value mea sured at w orst case condi tions for both temperature and VCC a ft er 100,00 program/erase cy cles.

4. Max imum value mea sured at w orst case condi tions for both temperature and V CC.

STATUS REGISTER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations. It is also read during Erase Sus-

pend when an address within a block being erased

is acce ssed .

The bits in the Status Register are s um marized in

Table 7, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is re ad.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read oper ations from t he ad-

dress just programmed output DQ7, not its com-

plement.

During Erase ope rations the Data Po lling Bit out-

puts ’0’, the complement of the erased state of

DQ7. Aft er s uc cessful completion of the Erase op-

eration the memory returns to R ead Mod e.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Read operation within a

block being erased. The Data Polling Bit will

change f rom a ’0’ to a ’1’ when the Program/Erase

Controller has sus pe nded the Erase operat ion.

Figure 7, Data Polling Flowcha rt, gives an exam-

ple of how to use the Data Polling Bit. A V alid Ad-

dress is the address being programmed or an

address wit hin the bl ock being erased.

Toggle Bit (DQ6). The Togg le Bit can be used to

identify whether the Program/Erase Controller has

successfully completed its operation or if it has re-

sponded to an Erase Suspend. The Toggle Bit is

output on DQ6 when the Status Register is re ad.

During Program and Erase operations the Toggle

Bit changes f rom ’0 ’ to ’ 1’ to ’ 0’, et c., with succes-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will

output when addressing a cell within a block being

erased. The Toggle Bit will stop toggling when the

Program/Erase Controller has suspended the

Erase operation.

If any attempt is ma de to erase a protected bl ock,

the o peration is aborted, no error i s sig nalled and

DQ6 toggles for approximately 100µs. If any at-

tempt is made to program a protected block or a

suspended b lock, the operatio n is aborted, no er-

ror is signalled and DQ6 toggles for approxi mately

1µs.

Figure 8 , Data Toggle Flowchart, g ives an exam-

ple of how to u se the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Error Bit is set to ’1’ when a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Rea d/Re se t comm and must be iss ued

Parameter Min Typ (1, 2) Max(2) Unit

Chip Erase 40 200(3) s

Block Erase (64 KBytes) 0.8 6(4) s

Erase Suspend Latency Time 15 25(4) µs

Program (Byte or Word) 10 200(3) µs

Accelerated Program (Byte or Word) 8 150(3) µs

Chip Program (Byte by Byte) 40 200(3) s

Chip Program (Word by Word) 20 100(3) s

Program/Erase Cycles (per Block) 100,000 cycles

Data Retention 20 years

M29W320DT, M29W320DB

20/44

before other command s are issued. The Error bit

is output on DQ5 when the Status Register is read.

Note that t he Program command cannot change a

bit set to ’0’ back to ’1’ and attempting to do so will

set DQ5 to ‘1’. A Bus Read operation to that ad-

dres s w ill s how the bit is s ti ll ‘0’. On e of the E r as e

commands must be used to set all the bits in a

block or in the w hole m emo ry from ’0’ to ’1’.

Erase Timer Bit (DQ3). The Erase Timer Bit can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the Erase Ti mer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is set to ’0’ and additional block s to be erased

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Alternative T oggle Bit (D Q2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase controller during Erase operations. The Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is re ad.

During Chip Erase and Block Erase operations the

Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Re ad operations from addresses

within the blocks being erased. A protected block

is treated the same as a block not being erased.

Once the operation completes the memory returns

to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks being erased. Bus Read operations to ad-

dresses within blocks not being erased will ou tput

the memory cell data as i f in Read mode.

After an Erase operation that c auses t he Error Bit

to be set the Alternative Toggle Bit can be used to

identify which block or bl ocks have caused t he er-

ror. The Altern ative Toggle Bit ch anges from ’0’ to

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alternative Toggle Bit does

not change if the addressed block has erased cor-

rectly.

Table 7. Status Register Bits

No te : Unspeci f i ed data bi ts should be ignored.

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any Address DQ7 Toggle 0 ––0

Program During Erase

Suspend Any Address DQ7 Toggle 0 – – 0

Program Error Any Address DQ7 Toggle 1 – – 0

Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before

timeout Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Block Erase Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erase Suspend Erasing Block 1 No Toggle 0 – Toggle 1

Non-Erasing Block Data read as normal 1

Erase Error Good Block Address 0 Toggle 1 1 No Toggle 0

Faulty Block Address 0 Toggle 1 1 Toggle 0

21/44

M29W320DT, M29W320DB

Figu re 7. Da ta Po lli ng Fl owch a rt Figu r e 8. Da ta To ggle F l owchar t

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL PASS

AI90194

DQ7

DATA YES

YES

DQ5

= 1

DQ7

DATA YES

READ DQ6

START

READ DQ6

TWICE

FAIL PASS

AI01370C

DQ6

TOGGLE NO

YES

DQ5

= 1

YES

DQ6

TOGGLE

READ

DQ5 & DQ6

M29W320DT, M29W320DB

22/44

MAX I MUM R A TI N G

Stressing the device ab ove t he rating listed in the

Absolute Maxi mum Ratings table m ay cause per-

manent damage to the device. Exposure to Abso-

lute Maximum Rating conditions for extended

periods may affect device reliability. These are

stress ratings only and operation of the device at

these or any other conditions above t hose indicat -

ed in the Operating sections of this specification is

not implied. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 8. Absolute Maximum Ratings

Note: 1. M in i m um voltage may un dershoot to –2V during transition and fo r l ess than 20ns duri ng trans i tions.

2. Max imum voltage may overshoot to VCC +2V du ri ng trans i tion and for less t han 20ns during transitions.

Symbol Parameter Min Max Unit

TBIAS Temperature Under Bias –50 125 °C

TSTG Storage Temperature –65 150 °C

VIO Input or Output Voltage (1,2) –0.6 VCC +0.6 V

VCC Supply Voltage –0.6 4 V

VID Identification Voltage –0.6 13.5 V

VPP Program Volta ge –0.6 13.5 V

23/44

M29W320DT, M29W320DB

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, a nd the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 9, Operating and

AC Measurement Conditions. Designers should

check t hat the operating cond itions in their circuit

match the operating conditions when relying on

the quot ed parameters.

Table 9. Operating and AC Measurem en t Conditions

Figure 9. AC Measurement I/O Wavefo rm Figure 10. AC Measure ment Lo ad Circuit

Table 10. Device Capacitance

No te : Sam pled only, not 100% tested .

Parameter

M29W320D

Unit70 90

Min Max Min Max

VCC Supply Voltage 3.0 3.6 2.7 3.6 V

Ambient Operati ng Temperatur e –40 85 –40 85 °C

Load Capacitance (CL)30 30 pF

Input Rise and Fall Times 10 10 ns

Input Pulse Voltages 0 to VCC 0 to VCC V

Input and Output Timing Ref. Voltages VCC/2 VCC/2 V

AI90196

VCC

VCC/2

AI90197

CL includes JIG capacitance

DEVICE

UNDER

TEST

25kΩ

VCC

25kΩ

VCC

0.1µF

VPP

0.1µF

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 6pF

OUT Output Capacitance VOUT = 0V 12 pF

M29W320DT, M29W320DB

24/44

Table 11. DC Characteristics

Not e: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Typ. Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leaka ge Curren t 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Curre nt (Read) E = VIL, G = VIH,

f = 6MHz 510mA

CC2 Supply Curre nt (Standby) E = VCC ±0.2V,

RP = VCC ±0.2V 35 100 µA

ICC3 (1) Su pply Curre nt (Program/

Erase)

Program/

Erase

Controller

active

VPP/WP =

VIL or VIH 20 mA

VPP/WP =

VPP 20 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7VCC VCC +0.3 V

VPP Voltage for VPP/WP

Program Acceleration VCC = 3.0V ±10% 11.5 12.5 V

IPP Current for VPP/WP

Program Acceleration VCC = 3.0V ±10% 10 mA

VOL Output Low Vol tage IOL = 1.8mA 0.45 V

VOH Output High Volta ge IOH = –100µAVCC –0.4 V

VID Identification Voltage 11.5 12.5 V

IID Identification Current A9 = VID 100 µA

VLKO Program/Erase Lockout

Supply Volta ge 1.8 2.3 V

25/44

M29W320DT, M29W320DB

Figure 11. Read Mode AC Waveforms

Table 12. Read AC Characteristi cs

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter Test Condition M29W320D Unit

70 90

tAVAV tRC Address Valid to Next Address Valid E = VIL,

G = VIL Min 70 90 ns

tAVQV tACC Address Valid to Output Valid E = VIL,

G = VIL Max 70 90 ns

tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G = VIL Max 70 90 ns

tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 35 ns

tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 25 30 ns

tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 25 30 ns

tEHQX

tGHQX

tAXQX tOH Chip Enable, Output Enable or Address

Transition to Output Transition Min 0 0 ns

tELBL

tELBH tELFL

tELFH Chip Enable to BYTE Low or High Max 5 5 ns

tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 30 ns

tBHQV tFHQV BYTE High to Output Valid Max 30 40 ns

AI90198

tAVAV

tAVQV tAXQX

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

A0-A20/

A–1

DQ0-DQ7/

DQ8-DQ15

tELQV tEHQX

tGHQZ

VALID

tBHQV

tELBL/tELBH tBLQZ

BYTE

M29W320DT, M29W320DB

26/44

Figure 12. Write AC Waveforms, Wr ite Enable Controlled

Table 13. Write AC Characteristics, Write Enable Controlle d

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29W320D Unit

70 90

tAVAV tWC Address Valid to Next Address Valid Min 70 90 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 45 50 ns

tDVWH tDS Input Valid to Write Enable High Min 45 50 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 30 30 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 45 50 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns

tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs

AI90199

A0-A20/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

tWHRL

27/44

M29W320DT, M29W320DB

Figure 13. Write AC Wavefo rms, Chip Enable Controlled

Table 14. W rite AC Characteristics, Chip Enable Controlled

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29W320D Unit

70 90

tAVAV tWC Address Valid to Next Address Valid Min 70 90 ns

tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 45 50 ns

tDVEH tDS Input Valid to Chip Enable High Min 45 50 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 30 30 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 45 50 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns

tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs

AI90200

A0-A20/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

tEHRL

M29W320DT, M29W320DB

28/44

Figure 14. Reset/Block Tem porary Unp rotec t AC Wavefo rms

Table 15. Reset/Block Temporary Unprotect AC Characteri stics

Not e: 1. Sampled only, not 100% tested.

Figure 15. Accelera ted Progr am Timing Wavefo rm s

Symbol Alt Parameter M29W320D Unit

70 90

tPHWL (1)

tPHEL

tPHGL (1) tRH RP High to Write Enable Low, Chip Enable Low,

Output Enable Low Min 50 50 ns

tRHWL (1)

tRHEL (1)

tRHGL (1) tRB RB High to Write Enable Low, Chip Enable Low,

Output Enable Low Min 0 0 ns

tPLPX tRP RP Pulse Width Min 500 500 ns

tPLYH (1) tREADY RP Low to Read Mode Max 10 10 µs

tPHPHH (1 ) tVIDR RP Rise Time to VID Min 500 500 ns

tVHVPP (1) VPP Rise and Fall Time Min 250 250 ns

AI02931B

RP tPLPX

tPHWL, tPHEL, tPHGL

tPLYH

tPHPHH

E, G

tRHWL, tRHEL, tRHGL

AI90202

VPP/WP

VPP

VIL or VIH tVHVPP tVHVPP

29/44

M29W320DT, M29W320DB

PACKAGE MECHANICAL

Figure 16. TS O P4 8 Lead Plastic Thin Smal l Outline , 12x20 mm, Bottom View P ackag e Outlin e

Note: Drawing not to scale.

Table 16. TS OP 48 Lea d Plastic Thin Sm all Outline, 12x20 mm , Packag e Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.100 0.050 0.150 0.0039 0.0020 0.0059

A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.220 0.170 0.270 0.0087 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.080 0.0031

D1 12.000 11.900 12.100 0.4724 0.4685 0.4764

E 20.000 19.800 20.200 0.7874 0.7795 0.7953

E1 18.400 18.300 18.500 0.7244 0.7205 0.7283

e 0.500 – – 0.0197 – –

L 0.600 0.500 0.700 0.0236 0.0197 0.0276

L1 0.800 0.0315

α305305

TSOP-G

DIE

LA1 α

M29W320DT, M29W320DB

30/44

Figure 17. TF BGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Packa ge Ou tline

Not e: Drawing is not to scale.

Table 17. TFBG A63 7x11mm - 6x8 active ball array, 0.8mm pitch , Packag e Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.250 0.0098

A2 0.900 0.0354

b 0.350 0.450 0.0138 0.0177

D 7.000 6.900 7.100 0.2756 0.2717 0.2795

D1 5.600 – – 0.2205 – –

ddd – – 0.100 – – 0.0039

E 11.000 10.900 11.100 0.4331 0.4291 0.4370

E1 8.800 – – 0.3465 – –

e 0.800 – – 0.0315 – –

FD 0.700 – – 0.0276 – –

FE 1.100 – – 0.0433 – –

SD 0.400 – – 0.0157 – –

SE 0.400 – – 0.0157 – –

BGA-Z33

ddd

BALL "A1"

31/44

M29W320DT, M29W320DB

PAR T NUMBERING

Table 18. Ordering Information Scheme

Devices are shipped from the fac tory with the memory content bits erased to ’1’.

For a list of availabl e options (S peed, P ack age, et c...) or for further information on any aspect of this de-

vice, pleas e contact the ST Sales Office nearest to you.

Example: M29W320DB 90 N 1 T

Device Type

M29

Operating Voltage

W = VCC = 2.7 to 3.6V

Device Function

320D = 32 Mbit (x8/x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

70 = 70 ns

90 = 90 ns

Package

N = TSOP48: 12 x 20 mm

ZA = TFBGA63: 7x11mm, 0.80 mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = Lead-free Package, Standard Packing

F = Lead-free Package, Tape & Reel Packing

M29W320DT, M29W320DB

32/44

APPENDIX A. BL OCK ADDRESS TABLE

Table 19. T op Boot Block Addresse s,

M29W320DT

#Size

(KByte/

KWord)

Add ress R ange

(x8) Address Range

(x16)

66 16/8 3FC000h-3FFFFFh 1FE000h-1FFFFFh

65 8/4 3FA000h-3FBFFFh 1FD000h-1FDFFFh

64 8/4 3F8000h-3F9FFFh 1FC000h-1FCFFFh

63 32/16 3F0000h-3F7FFFh 1F8000h-1FBFFFh

62 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh

61 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh

60 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh

59 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh

58 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh

57 64/32 390000h-39FFFFh 1C8000h-1CFFFFh

56 64/32 380000h-18FFFFh 1C0000h-1C7FFFh

55 64/32 370000h-37FFFFh 1B8000h-1BFFFFh

54 64/32 360000h-36FFFFh 1B0000h-1B7FFFh

53 64/32 350000h-35FFFFh 1A8000h-1AFFFFh

52 64/32 340000h-34FFFFh 1A0000h-1A7FFFh

51 64/32 330000h-33FFFFh 198000h-19FFFFh

50 64/32 320000h-32FFFFh 190000h-197FFFh

49 64/32 310000h-31FFFFh 188000h-18FFFFh

48 64/32 300000h-30FFFFh 180000h-187FFFh

47 64/32 2F0000h-2FFFFFh 178000h-17FFFFh

46 64/32 2E0000h-2EFFFFh 170000h-177FFFh

45 64/32 2D0000h-2DFFFFh 168000h-16FFFFh

44 64/32 2C0000h-2CFFFFh 160000h-167FFFh

43 64/32 2B0000h-2BFFFFh 158000h-15FFFFh

42 64/32 2A0000h-2AFFFFh 150000h-157FFFh

41 64/32 290000h-29FFFFh 148000h-14FFFFh

40 64/32 280000h-28FFFFh 140000h-147FFFh

39 64/32 270000h-27FFFFh 138000h-13FFFFh

38 64/32 260000h-26FFFFh 130000h-137FFFh

37 64/32 250000h-25FFFFh 128000h-12FFFFh

36 64/32 240000h-24FFFFh 120000h-127FFFh

35 64/32 230000h-23FFFFh 118000h-11FFFFh

34 64/32 220000h-22FFFFh 110000h-117FFFh

33 64/32 210000h-21FFFFh 108000h-10FFFFh

32 64/32 200000h-20FFFFh 100000h-107FFFh

31 64/32 1F0000h-1FFFFFh 0F8000h-0FBFFFh

30 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh

29 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh

28 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh

27 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh

26 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh

25 64/32 190000h-19FFFFh 0C8000h-0CFFFFh

24 64/32 180000h-18FFFFh 0C0000h-0C7FFFh

23 64/32 170000h-17FFFFh 0B8000h-0BFFFFh

22 64/32 160000h-16FFFFh 0B0000h-0B7FFFh

21 64/32 150000h-15FFFFh 0A8000h-0AFFFFh

20 64/32 140000h-14FFFFh 0A0000h-0A7FFFh

19 64/32 130000h-13FFFFh 098000h-09FFFFh

18 64/32 120000h-12FFFFh 090000h-097FFFh

17 64/32 110000h-11FFFFh 088000h-08FFFFh

16 64/32 100000h-10FFFFh 080000h-087FFFh

15 64/32 0F0000h-0FFFFFh 078000h-07FFFFh

14 64/32 0E0000h-0EFFFFh 070000h-077FFFh

13 64/32 0D0000h-0DFFFFh 068000h-06FFFFh

12 64/32 0C0000h-0CFFFFh 060000h-067FFFh

11 64/32 0B0000h-0BFFFFh 058000h-05FFFFh

10 64/32 0A0000h-0AFFFFh 050000h-057FFFh

9 64/32 090000h-09FFFFh 048000h-04FFFFh

8 64/32 080000h-08FFFFh 040000h-047FFFh

7 64/32 070000h-07FFFFh 038000h-03FFFFh

6 64/32 060000h-06FFFFh 030000h-037FFFh

5 64/32 050000h-05FFFFh 028000h-02FFFFh

4 64/32 040000h-04FFFFh 020000h-027FFFh

3 64/32 030000h-03FFFFh 018000h-01FFFFh

2 64/32 020000h-02FFFFh 010000h-017FFFh

1 64/32 010000h-01FFFFh 008000h-00FFFFh

0 64/32 000000h-00FFFFh 000000h-007FFFh

33/44

M29W320DT, M29W320DB

Table 20. Bottom Boot Block Addresses,

M29W320DB

#Size

(KByte/

KWord)

Add ress R ange

(x8) Address Range

(x16)

66 64/32 3F0000h-3FFFFFh 1F8000h-1FFFFFh

65 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh

64 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh

63 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh

62 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh

61 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh

60 64/32 390000h-39FFFFh 1C8000h-1CFFFFh

59 64/32 380000h-18FFFFh 1C0000h-1C7FFFh

58 64/32 370000h-37FFFFh 1B8000h-1BFFFFh

57 64/32 360000h-36FFFFh 1B0000h-1B7FFFh

56 64/32 350000h-35FFFFh 1A8000h-1AFFFFh

55 64/32 340000h-34FFFFh 1A0000h-1A7FFFh

54 64/32 330000h-33FFFFh 198000h-19FFFFh

53 64/32 320000h-32FFFFh 190000h-197FFFh

52 64/32 310000h-31FFFFh 188000h-18FFFFh

51 64/32 300000h-30FFFFh 180000h-187FFFh

50 64/32 2F0000h-2FFFFFh 178000h-17FFFFh

49 64/32 2E0000h-2EFFFFh 170000h-177FFFh

48 64/32 2D0000h-2DFFFFh 168000h-16FFFFh

47 64/32 2C0000h-2CFFFFh 160000h-167FFFh

46 64/32 2B0000h-2BFFFFh 158000h-15FFFFh

45 64/32 2A0000h-2AFFFFh 150000h-157FFFh

44 64/32 290000h-29FFFFh 148000h-14FFFFh

43 64/32 280000h-28FFFFh 140000h-147FFFh

42 64/32 270000h-27FFFFh 138000h-13FFFFh

41 64/32 260000h-26FFFFh 130000h-137FFFh

40 64/32 250000h-25FFFFh 128000h-12FFFFh

39 64/32 240000h-24FFFFh 120000h-127FFFh

38 64/32 230000h-23FFFFh 118000h-11FFFFh

37 64/32 220000h-22FFFFh 110000h-117FFFh

36 64/32 210000h-21FFFFh 108000h-10FFFFh

35 64/32 200000h-20FFFFh 100000h-107FFFh

34 64/32 1F0000h-1FFFFFh 0F8000h-0FBFFFh

33 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh

32 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh

31 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh

30 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh

29 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh

28 64/32 190000h-19FFFFh 0C8000h-0CFFFFh

27 64/32 180000h-18FFFFh 0C0000h-0C7FFFh

26 64/32 170000h-17FFFFh 0B8000h-0BFFFFh

25 64/32 160000h-16FFFFh 0B0000h-0B7FFFh

24 64/32 150000h-15FFFFh 0A8000h-0AFFFFh

23 64/32 140000h-14FFFFh 0A0000h-0A7FFFh

22 64/32 130000h-13FFFFh 098000h-09FFFFh

21 64/32 120000h-12FFFFh 090000h-097FFFh

20 64/32 110000h-11FFFFh 088000h-08FFFFh

19 64/32 100000h-10FFFFh 080000h-087FFFh

18 64/32 0F0000h-0FFFFFh 078000h-07FFFFh

17 64/32 0E0000h-0EFFFFh 070000h-077FFFh

16 64/32 0D0000h-0DFFFFh 068000h-06FFFFh

15 64/32 0C0000h-0CFFFFh 060000h-067FFFh

14 64/32 0B0000h-0BFFFFh 058000h-05FFFFh

13 64/32 0A0000h-0AFFFFh 050000h-057FFFh

12 64/32 090000h-09FFFFh 048000h-04FFFFh

11 64/32 080000h-08FFFFh 040000h-047FFFh

10 64/32 070000h-07FFFFh 038000h-03FFFFh

9 64/32 060000h-06FFFFh 030000h-037FFFh

8 64/32 050000h-05FFFFh 028000h-02FFFFh

7 64/32 040000h-04FFFFh 020000h-027FFFh

6 64/32 030000h-03FFFFh 018000h-01FFFFh

5 64/32 020000h-02FFFFh 010000h-017FFFh

4 64/32 010000h-01FFFFh 008000h-00FFFFh

3 32/16 008000h-00FFFFh 004000h-007FFFh

2 8/4 006000h-007FFFh 003000h-003FFFh

1 8/4 004000h-005FFFh 002000h-002FFFh

0 16/8 000000h-003FFFh 000000h-001FFFh

M29W320DT, M29W320DB

34/44

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system sof tware t o query the device to det ermine

various electrical and timing parameters, density

information and functions supported by t he mem-

ory. The system can interface easily with the de-

vice, enabling the s oftware to upgrad e itse lf when

necessary.

When the CFI Query Command is issued the de-

vice enters CFI Query mode and the data structure

is read from the memory. Tables 21, 22, 23, 24, 25

and 26 show the addresses used to retrieve the

data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 26, Security Code area). This area

can be accessed only in Read mode by the final

user. It is impos sible to change t he secu ri ty num-

ber after it has been written by ST. Issue a Read

command to return to Read mode.

Table 21. Query Structure Overview

Note: Query data are always presented on the lowest order data outputs.

Table 22. CFI Query Identification String

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Address Sub-section Name Description

x16 x8

10h 20h CFI Query Identification String Command set ID and algorithm data offset

1Bh 36h System Interface Information Device timing & voltage information

27h 4Eh Device Geometry Definition Flash device layout

40h 80h Primary Algorithm-specific Extended

Query table Additional information specific to the Primary

Algorithm (optional)

61h C2h Security Code Area 64 bit unique device number

Address Data Description Value

x16 x8

10h 20h 0051h “Q”

11h 22h 0052h Query Unique ASCII String "QRY" "R"

12h 24h 0059h "Y"

13h 26h 0002h Primary Algorithm Command Set and Control Interface ID code 16 bit

ID code defining a specific algori thm AMD

Compatible

14h 28h 0000h

15h 2Ah 0040h Address for Primary Algorithm extended Query table (see Table 24) P = 40h

16h 2Ch 0000h

17h 2Eh 0000h Alternate Vendor Command Set and Control Interface ID Code second

vendor - specified algorithm supported NA

18h 30h 0000h

19h 32h 0000h Address for Alternate Algorithm extended Query table NA

1Ah 34h 0000h

35/44

M29W320DT, M29W320DB

Table 23. CFI Query System In terface Information

Address Data Description Value

x16 x8

1Bh 36h 0027h VCC Logic Supply Minimum Program/Erase voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV 2.7V

1Ch 38h 0036h VCC Logic Supply Maximum Program/Erase voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV 3.6V

1Dh 3Ah 00B5h VPP [Programming] Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV 11.5V

1Eh 3Ch 00C5h VPP [Programming] Supply Maximum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV 12.5V

1Fh 3Eh 0004h Typical timeout per single byte/word program = 2n µs 16µs

20h 40h 0000h Typical timeout for minimum size write buffer program = 2n µs NA

21h 42h 000Ah Typical timeout per individual block erase = 2n ms 1s

22h 44h 0000h Typical timeout for full chip erase = 2n ms NA

23h 46h 0005h Maximum timeout for byte/word program = 2n times typical 512µs

24h 48h 0000h Maximum timeout for write buffer program = 2n times typical NA

25h 4Ah 0004h Maximum timeout per individual block erase = 2n times typical 16s

26h 4Ch 0000h Maximum timeout for chip erase = 2n times typical NA

M29W320DT, M29W320DB

36/44

Table 24. Device Geometry Definition

Address Data Description Value

x16 x8

27h 4Eh 0016h Device Size = 2n in number of bytes 4 MByte

28h

29h 50h

52h 0002h

0000h Flash Device Interface Code description x8, x16

Async.

2Ah

2Bh 54h

56h 0000h

0000h Maximum number of bytes in multi-byte program or page = 2n NA

2Ch 58h 0004h Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing

contiguous Erase Blocks of the same size. 4

2Dh

2Eh 5Ah

5Ch 0000h

0000h Region 1 Information

Number of identical size erase block = 0000h+1 1

2Fh

30h 5Eh

60h 0040h

0000h Region 1 Information

Block size in Region 1 = 0040h * 256 byte 16 Kbyte

31h

32h 62h

64h 0001h

0000h Region 2 Information

Number of identical size erase block = 0001h+1 2

33h

34h 66h

68h 0020h

0000h Region 2 Information

Block size in Region 2 = 0020h * 256 byte 8 Kbyte

35h

36h 6Ah

6Ch 0000h

0000h Region 3 Information

Number of identical size erase block = 0000h+1 1

37h

38h 6Eh

70h 0080h

0000h Region 3 Information

Block size in Region 3 = 0080h * 256 byte 32 Kbyte

39h

3Ah 72h

74h 003Eh

0000h Region 4 Information

Number of identical-size erase block = 003Eh+1 63

3Bh

3Ch 76h

78h 0000h

0001h Region 4 Information

Block size in Region 4 = 0100h * 256 byte 64 Kbyte

37/44

M29W320DT, M29W320DB

Table 25. Primary Algorithm- Speci fic Extended Qu ery Ta ble

Table 26. Security Code Area

Address Data Description Value

x16 x8

40h 80h 0050h

Primary Algorithm extended Query table unique ASCII string “PRI”

"P"

41h 82h 0052h "R"

42h 84h 0049h "I"

43h 86h 0031h Major version number, ASCII "1"

44h 88h 0030h Minor version number, ASCII "0"

45h 8Ah 0000h Address Sensitive Unlock (bits 1 to 0)

00 = required, 01= not required

Silicon Revision Number (bits 7 to 2)

Yes

46h 8Ch 0002h Erase Suspend

00 = not supported, 01 = Read only, 02 = Read and Write 2

47h 8Eh 0001h Block Protection

00 = not supported, x = number of blocks in per group 1

48h 90h 0001h Temporary Block Unprotect

00 = not supported, 01 = supported Yes

49h 92h 0004h Block Protect /Unprotect

04 = M29W400B 4

4Ah 94h 0000h Simultaneous Operations, 00 = not supported No

4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No

4Ch 98h 0000h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No

4Dh 9Ah 00B5h VPP Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

11.5V

4Eh 9Ch 00C5h VPP Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

12.5V

4Fh 9Eh 000xh Top/Bottom Boot Block Flag

02h = Bottom Boot device, 03h = Top Boot device –

Address Data Description

x16 x8

61h C3h, C2h XXXX

64 bit: unique device number

62h C5h, C4h XXXX

63h C7h, C6h XXXX

64h C9h, C8h XXXX

M29W320DT, M29W320DB

38/44

APPENDIX C. BLOCK PRO TECTION

Block protection ca n be used to prevent any oper-

ation from modifying the dat a stored in the Flash.

Each Block can be protected individually. Once

protected, Program and Erase operations on the

block fail to change the data.

There are three techniques that can be used to

control Block Protection, these are the Program-

mer technique, the In- System technique and Tem-

porary Unprotection. Temporary Unprotection is

controlled by the Reset/Block Temporary Unpro-

tection pin, RP; this is des cribed in the S ign al De-

scriptions section.

Unlike the Command Interface of the Program/

Erase Cont roller, the techniques for protecting and

unprotecting blocks change between different

Flash memory suppliers. For example, the tech-

niques for AMD parts will not work on STMicro-

electronics parts. Care should be taken when

changing drivers for one part to work on another.

Programm er Technique

The Programmer technique uses high (VID) volt-

age levels on some of the bus pins. These cannot

be achieved using a standar d microproces sor bus,

therefore the technique is recommended only for

use in Programmi ng Equipment.

To protect a block follow the flowchart in Figure 18,

Programmer Equipment Block Protect Flowchart.

To unprotect the whole chip it is necessary to pro-

tect all of the blocks f irst, then all blocks can be un-

protected at the same time. To unprotect the chip

follow Figure 19, Programmer Equipment Chip

Unprotect Flowchart. Table 27, Programmer

Technique Bus Operations, gives a summary of

each operation.

The timing on these flowcharts is critical. Care

should be taken t o ensure that, where a pau se is

specified, it is followed as cl osely as possible. Do

not abort the procedure be fore reaching the end.

Chip Unprotect can take several seconds and a

user message should be provided to show that the

operation is progressing.

In-System Technique

The In-System technique requires a high voltage

level on the Reset/Blocks Temporary Unprotect

pin, RP . This can be achieved without violating the

maximum ratings of the components on the micro-

processor bus, therefore this tec hniqu e is suitable

for use after the Flash has been fitted to the sys-

tem.

To protect a block follow the flowchart in Figure 20,

In-System Block Protect Flowchart. To unprotect

the whole c hip it is necessary to protect all of the

blocks f irst, then all the blocks can be unprotected

at the same time. To unprotect the chip foll ow Fig-

ure 21, I n-System Chi p Unprot ect Flowchart.

The timing on these flowcharts is critical. Care

should be taken t o ensure that, where a pau se is

specified, it is followed as cl osely as possible. Do

not allow the m icroprocessor t o service interrupts

that will upset the timing and do not abort the pro-

cedure before reaching the end. Chip Unprotect

can take several seconds and a user message

should be provided to show that the operation is

progressing.

Table 27. Program mer Tech niqu e Bus Op erati ons, BYTE = VIH or VIL

Operation E G W Address Inputs

A0-A20 Data Input s/Out puts

DQ15 A–1, DQ14 -DQ0

Block Protect VIL VID VIL Pulse A9 = VID, A12-A20 Block Address

Others = X X

Chip Unprotect VID VID VIL Pulse A9 = VID, A12 = VIH, A15 = VIH

Others = X X

Block Protection

Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIL, A9=V

ID,

A12-A20 Block Address

Others = X

Pass = XX01h

Retry = XX00h

Block Unprotection

Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = V IH, A9 = VID,

A12-A20 Block Address

Others = X

Retry = XX01h

Pass = XX00h

39/44

M29W320DT, M29W320DB

Figure 18. Programmer Equi pment Block Protect Flowchart

ADDRESS = BLOCK ADDRESS

AI03469

G, A9 = VID,

E = VIL

n = 0

Wait 4µs

Wait 100µs

W = VIL

W = VIH

E, G = VIH,

A0, A6 = VIL,

A1 = VIH

A9 = VIH

E, G = VIH

++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

W = VIH

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

Verify Protect Set-upEnd

A9 = VIH

E, G = VIH

M29W320DT, M29W320DB

40/44

Fi gure 19. Pr ogram m er Eq uipment C hip Unprotec t Fl owchart

PROTECT ALL BLOCKS

AI03470

A6, A12, A15 = VIH(1)

E, G, A9 = VID

DATA

W = VIH

E, G = VIH

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1, A6 = VIH

Wait 10ms

00h

INCREMENT

CURRENT BLOCK

n = 0

CURRENT BLOCK = 0

Wait 4µs

W = VIL

++n

= 1000

START

YES

YESNO

NO LAST

BLOCK

YES

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

FAIL PASS

Verify Unprotect Set-upEnd

A9 = VIH

E, G = VIH A9 = VIH

E, G = VIH

41/44

M29W320DT, M29W320DB

Figure 20. In-System Equipment Block Protect Flowchart

AI03471

WRITE 60h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

n = 0

Wait 100µs

WRITE 40h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

RP = VIH ++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

RP = VIH

Wait 4µs

Verify Protect Set-upEnd

READ DATA

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

WRITE 60h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

M29W320DT, M29W320DB

42/44

Figure 21. In-System Equipment Chip Unprotect Flowchart

AI03472

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

n = 0

CURRENT BLOCK = 0

Wait 10ms

WRITE 40h

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIH

RP = VIH

++n

= 1000

START

FAIL PASS

YES

DATA

00h

YESNO

RP = VIH

Wait 4µs

READ DATA

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIH

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PROTECT ALL BLOCKS

INCREMENT

CURRENT BLOCK

LAST

BLOCK

YES

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

Verify Unprotect Set-upEnd

43/44

M29W320DT, M29W320DB

RE VISION HISTORY

Table 28. D ocum ent Revision History

Date Version Revision Details

March-2001 -01 First Issue (Brief Data)

08-Jun-2001 -02 Document expanded to full Product Preview

22-Jun-2001 -03 Minor text corrections to Read/Reset and Read CFI commands and Status Register Error

and Toggle Bits.

27-Jul-2001 -04

Document type: from Product Preview to Preliminary Data

TFBGA connections and Block Addresses (x16) diagrams clarification

Write Protect and Block Unprotect clarification

CFI Primary Algorithm table, Block Protection change

05-Oct-2001 -05

Added Block Protection Appendix

“Write Protect/VPP” pin renamed to “VPP/Write Protect” to be consistent with abbre viation.

Changes to the VPP/WP pin description, Figure 15 and Table 15. IPP added to Table 11

and ICC3 clarified. Modified description of VPP/WP operation in Unloc k Bypass Command

section. Adde d VPP/WP decoupling capacitor to Figure 10.

Clarified Read/Reset operation during Erase Suspend.

07-Feb-2002 -06 TFBGA package changed from 48 ball to 63 ball

05-Apr-2002 -07 Description of Ready/Busy signal clarified (and Figure 14 modified)

Clarified allowable commands during block erase

Clarified the mode the device returns to in the CFI Read Query command section

19-Nov-2002 7.1

Erase Suspend Latency Time (typical and maximum) added to Program, Erase Times

and Program, Erase Endurance Cycles table.

Typical values added for Icc1 and Icc2 in DC characteristics table.

Logic Diagram and Data Toggle Flowchart corrected.

Revision numbering modified: a minor revision will be indicated by incrementing the digit

after the dot, and a major revision, by incrementing the digit before the dot (revision

version 07 equals 7.0). Document promoted to full datasheet.

26-May-2003 7.2

Data Retention added to Table 6, Program, Erase Times and Program, Erase Endurance

Cycles, and Typical after 100k W/E Cycles column removed. TSOP48 package

mechanical updated. Lead-free package options E and F added to Table 18, Ordering

Information Scheme.

M29W320DT, M29W320DB

44/44

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