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1. General description

The EM773 is an ARM Cortex-M0 based , low-cost 32-bit energy metering IC, designed for

8/16-bit smart metering applications. The EM773 offers programmability and on-chip

metrology fu nctionality combined with a low power, simple instruction set and memory

addressing with reduced code size compared to existing 8/16-bit architectures.

The EM773 operates at CPU frequencies of up to 48 MHz.

The peripheral complement of the EM773 includes up to 32 kB of flash memory, up to

8 kB of data memory, one Fast-mode Plus I2C- bus in te rface, on e RS-485/EIA- 48 5 UART,

one SPI interface with SSP features, three general purpose counter/timers, up to 25

general purpose I/O pins, and a metrology engine for energy measurement.

2. Features and benefits

System:

ARM Cortex-M0 processor, running at frequencies of up to 48 MHz.

ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

Serial Wire Debug.

System tick timer.

Memory:

32 kB on-chip flash programming memory.

8 kB SRAM.

In-System Programming (ISP) and In- A pplication Programming (IAP) via on-chip

bootloader software.

Digital peripherals:

Up to 25 General Purpose I/O (GPIO) pi ns with configurable pull-up/pull-down

resistors.

GPIO pins can be used as edge and level sensitive interrupt sources.

High-current output driver (20 mA) on one pin.

High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.

Three general purpose counter/timers with a total of two capture inputs and 10

match outpu ts.

Programmable WatchDog Timer (WDT).

Analog peripherals:

Metrology Engine for Smart Metering with two current inputs and a voltage input.

EM773

Energy metering IC; up to 32 kB flash and 8 kB SRAM

Rev. 1 — 1 September 2010 Objective data sheet

Objective data sheet Rev. 1 — 1 September 2010 2 of 45

NXP Semiconductors EM773

Energy metering IC

Serial interfaces:

UART with fractional baud rate generation, internal FIFO, and RS-485 support.

One SPI controller with SSP features and with FIFO and multi-protocol capabilities.

I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a

data rate of 1 Mbit/s with multiple address recognition and monitor mode.

Clock generation :

12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used

as a system clock.

Crystal oscillator with an operating range of 1 MHz to 25 MHz.

Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.

PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator or the internal RC

oscillator.

Clock output function with divider that can reflect the system oscillator clock, IRC

clock, CPU clock, and the Watchdog clock.

Power control:

Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, and Deep power-down modes.

Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

Processor wake-up from Deep-sleep mode via a dedicated start logic using up to

13 of the functional pins.

Power-On Reset (POR).

Brownout detect with four separate thresholds for interrupt and forced reset.

Unique device serial number for identification.

Single 3.3 V power supply (1.8 V to 3.6 V).

Available as 33-pin HVQFN package.

3. Applications

Smart Metering

4. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

EM773FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat

package; no leads; 33 terminals; body 7 × 7 × 0.85 mm n/a

Objective data sheet Rev. 1 — 1 September 2010 3 of 45

NXP Semiconductors EM773

Energy metering IC

5. Block diagram

Fig 1. EM773 block di agram

SRAM

8 kB

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

FLASH

32 kB

HIGH-SPEED

GPIO

AHB TO APB

BRIDGE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

XTALIN

XTALOUT

RESET

clocks and

controls

SWD

EM773

em773_002aae696

slave

slave slave

ROM

slave

AHB-LITE BUS

GPIO ports

PIO0/1/2/3

CLKOUT

IRC

POR

SPI0

METROLOGY ENGINE

UART

32-bit COUNTER/TIMER 0

I2C-BUS

WDT

IOCONFIG

CT32B0_MAT[2:0]

I_LOWGAIN

I_HIGHGAIN

VOLTAGE

CT32B0_CAP0

SDA

SCL

RXD

TXD

DTR, CTS, RTS

SYSTEM CONTROL

PMU

32-bit COUNTER/TIMER 1

CT32B1_MAT[3:0]

16-bit COUNTER/TIMER 0

CT16B0_MAT[2:0]

CT16B0_CAP0

SCK0, SSEL0

MISO0, MOSI0

system bus

Objective data sheet Rev. 1 — 1 September 2010 4 of 45

NXP Semiconductors EM773

Energy metering IC

6. Pinning information

6.1 Pinning

Fig 2. Pin configuration HVQFN 33 package

EM773_002aae698

Transparent top view

PIO0_8/MISO0/CT16B0_MAT0

PIO1_8

PIO0_2/SSEL0/CT16B0_CAP0

PIO0_9/MOSI0/CT16B0_MAT1

VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2

XTALOUT I_LOWGAIN

XTALIN I_HIGHGAIN

PIO0_1/CLKOUT/CT32B0_MAT2 VOLTAGE

RESET/PIO0_0 R/PIO1_1/CT32B1_MAT0

PIO2_0/DTR R/PIO1_2/CT32B1_MAT1

PIO0_3

PIO0_4/SCL

PIO0_5/SDA

PIO1_9

PIO3_4

PIO3_5

PIO0_6/SCK0

PIO0_7/CTS

PIO1_7/TXD/CT32B0_MAT1

PIO1_6/RXD/CT32B0_MAT0

PIO1_5/RTS/CT32B0_CAP0

VDD

PIO3_2

PIO1_11

PIO1_4/CT32B1_MAT3/WAKEUP

SWDIO/PIO1_3/CT32B1_MAT2

8 17

7 18

6 19

5 20

4 21

3 22

2 23

1 24

terminal 1

index area

33 VSS

EM773 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Objective data sheet Rev. 1 — 1 September 2010  5 of 45
NXP Semiconductors EM773
Energy metering IC
6.2 Pin description
 
Table 2. EM773 pin description table (HVQFN33 package) 
Symbol Pin Start 
logic 
input
Type Reset 
state
[1]
Description
PIO0_0 to PIO0_10 I/O Port 0 — Port 0 is a 12-bit I/O port with individual 
direction and function controls for each bit. The 
operation of port 0 pins depends on the function 
selected through the IOCONFIG register block. Pin 
PIO0_11 is not available.
RESET/PIO0_0 2[2] yes I I;PU RESET — External reset input: A LOW on this pin 
resets the device, causing I/O ports and peripherals to 
take on their default states, and processor execution to 
begin at address 0. 
I/O - PIO0_0 — General purpose digital input/output pin.
PIO0_1/CLKOUT/
CT32B0_MAT2 3[3] yes I/O I;PU PIO0_1 — General purpose digital input/output pin. A 
LOW level on this pin during reset starts the ISP 
command handler .
O- CLKOUT — Clock out pin.
O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 8[3] yes I/O I;PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave select for SPI0.
I-CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 9[3] yes I/O I;PU PIO0_3 — General purpose digital input/output pin. 
PIO0_4/SCL 10[4] yes I/O IA PIO0_4 — General purpose digital input/output pin 
(open-drain).
I/O - SCL — I2C-bus, open-drain clock input/output. 
High-current sink only if I2C Fast-mode Plus is selected 
in the I/O configuration register.
PIO0_5/SDA 11[4] yes I/O IA PIO0_5 — General purpose digital input/output pin 
(open-drain).
I/O - SDA — I2C-bus, open-drain data input/output. 
High-current sink only if I2C Fast-mode Plus is selected 
in the I/O configuration register.
PIO0_6/SCK0 15[3] yes I/O I;PU PIO0_6 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
PIO0_7/CTS 16[3] yes I/O I;PU PIO0_7 — General purpose digital input/output pin 
(high-current output driver).
I-CTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 17[3] yes I/O I;PU PIO0_8 — General purpose digital input/output pin.
I/O - MISO0 — Master In Slave Out for SPI0.
O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 18[3] yes I/O I;PU PIO0_9 — General purpose digital input/output pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

EM773 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Objective data sheet Rev. 1 — 1 September 2010  6 of 45
NXP Semiconductors EM773
Energy metering IC
SWCLK/PIO0_10/SCK0/
CT16B0_MAT2 19[3] yes I I;PU SWCLK — Serial wire clock.
I/O - PIO0_10 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
I_HIGHGAIN 21[5] no I I;PU I_HIGHGAIN — High gain curre nt input for metrology 
engine.
PIO1_1 to PIO1_9; 
PIO1_11 I/O Port 1 — Port 1 is a 12-bit I/O port with individual 
direction and function controls for each bit. The 
operation of port 1 pins depends on the function 
selected through the IOCONFIG register block. Pins 
PIO1_0 and PIO1_10 are not available.
VOLTAGE 22[5] no I I;PU VOLTAGE — Voltage input for the metrology engine.
R/PIO1_1/
CT32B1_MAT0 23[5] no O I;PU R — Reserved. Configure for an alternate functi on in 
the IOCONFIG block.
I/O - PIO1_1 — General purpose digital input/output pin.
O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R/PIO1_2/
CT32B1_MAT1 24[5] no I I;PU R — Reserved. Configure for an alternate function in 
the IOCONFIG block.
I/O - PIO1_2 — General purpose digital input/output pin.
O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/
CT32B1_MAT2 25[5] no I/O I;PU SWDIO — Serial wire debug input/output.
I/O - PIO1_3 — General purpose digital input/output pin.
O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_4/
CT32B1_MAT3/WAKEUP 26 no I/O I;PU PIO1_4 — General purpose digital input/output pin.
O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
I-WAKEUP — Deep power-down mode wake-up pin. 
This pin must be pulled HIGH externally to enter Deep 
power-down mode and pulled LOW to exit Deep 
power-down mode.
PIO1_5/RTS/
CT32B0_CAP0 30[3] no I/O I;PU PIO1_5 — General purpose digital input/output pin.
O- RTS — Request To Send output for UART.
I-CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO1_6/RXD/
CT32B0_MAT0 31[3] no I/O I;PU PIO1_6 — General purpose digital input/output pin.
I-RXD — Receiver input for UART.
O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7/TXD/
CT32B0_MAT1 32[3] no I/O I;PU PIO1_7 — General purpose digital input/output pin.
O- TXD — Transmitter output for UART.
O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0. 
PIO1_8 7[3] no I/O I;PU PIO1_8 — General purpose digital input/output pin.
PIO1_9 12[3] no I/O I;PU PIO1_9 — General purpose digital input/output pin.
I_LOWGAIN 20 no I I;PU I_LOWGAIN — Low gain current input for metrology 
engine.
Table 2. EM773 pin description table (HVQFN33 package)  …continued
Symbol Pin Start 
logic 
input
Type Reset 
state
[1]
Description

Objective data sheet Rev. 1 — 1 September 2010 7 of 45

NXP Semiconductors EM773

Energy metering IC

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled.

[2] See Figure 24 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to

reset the chip and wake up from Deep power-down mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 23).

[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

PIO1_11 27 no I/O I;PU PIO1_11 — General purpose digital input/output pin.

PIO2_0 I/O Port 2 — Port 2 is a 12-bit I/O port with individual

direction and function controls for each bit. The

operation of port 2 pins depends on the function

selected through the IOCONFIG register block. Pins

PIO2_1 to PIO2_11 are not available.

PIO2_0/DTR 1[3] no I/O I;PU PIO2_0 — General purpose digital input/output pin.

O- DTR — Data Terminal Ready output for UART.

PIO3_0 to PIO3_5 no I/O Port 3 — Port 3 is a 12-bit I/O port with individual

direction and function controls for each bit. The

operation of port 3 pins depends on the function

selected through the IOCONFIG register block. Pins

PIO3_0, PIO3_1, PIO3_3 and PIO3_6 to PIO3_11 are

not available.

PIO3_2 28[3] no I/O I;PU PIO3_2 — General purpose digital input/output pin.

PIO3_4 13[3] no I/O I;PU PIO3_4 — General purpose digital input/output pin.

PIO3_5 14[3] no I/O I;PU PIO3_5 — General purpose digital input/output pin.

VDD 6; 29 - I - 3.3 V supply voltage to the internal regulator, the

external rail, and the metrology engine.

XTALIN 4[6] - I - Input to the oscillator circuit and internal clock generator

circuits. Input voltage must not exceed 1.8 V.

XTALOUT 5[6] - O - Output from the oscillator amplifier.

VSS 33 - - - Thermal pad. Connect to ground.

Table 2. EM773 pin description table (HVQFN33 package) …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Objective data sheet Rev. 1 — 1 September 2010 8 of 45

NXP Semiconductors EM773

Energy metering IC

7. Functional description

7.1 ARM Cortex-M0 processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption.

7.2 On-chip flash program memory

The EM773 contains 32 kB of on-chip flash memory.

7.3 On-chip SRAM

The EM773 contains a total of 8 kB on-chip static RAM memory.

7.4 Memory map

The EM773 incorporates several distinct memory regions, shown in the following figures.

Figure 3 shows the overall map of the entire address space from the user program

viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128

peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32

peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows

simplifying the address decoding for each peripheral.

Objective data sheet Rev. 1 — 1 September 2010 9 of 45

NXP Semiconductors EM773

Energy metering IC

7.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

7.5.1 Features

•Controls system exceptions and peripheral interrupts.

•In the EM773, the NVIC supports 32 vectored interrupts including up to 13 inputs to

the start logic from individual GPIO pins.

Fig 3. EM773 memory map

0x5000 0000

0x5001 0000

0x5002 0000

0x5020 0000

AHB peripherals

16-127 reserved

GPIO PIO1

4-7

0x5003 0000

0x5004 0000

GPIO PIO2

GPIO PIO3

8-11

12-15

GPIO PIO0

0-3

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4008 0000

0x4001 C000

0x4001 4000

0x4000 0000

WDT

32-bit counter/timer 0

32-bit counter/timer 1

UART

PMU

I2C-bus

13 - 7 reserved

31 - 19 reserved

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x1000 2000

0x1FFF 0000

0x1FFF 4000

0x2000 0000

0x4000 0000

0x4008 0000

0x5000 0000

0x5020 0000

0xFFFF FFFF

reserved

APB peripherals

AHB peripherals

8 kB SRAM

0x1000 0000

EM773

0x0000 8000

32 kB on-chip flash

16 kB boot ROM

0x0000 0000

0x0000 00C0

active interrupt vectors

em773_002aae699

SPI0

reserved

16-bit counter/timer 0

IOCONFIG

system control

flash controller

Objective data sheet Rev. 1 — 1 September 2010 10 of 45

NXP Semiconductors EM773

Energy metering IC

•Four programmable interrupt priority levels, with hardware priority level masking.

•Software interrupt generation .

7.5.2 Interrupt sources

Each peripheral devi ce has one interrupt line conne cted to the NVIC but may have several

interrupt flags. Individual interrup t flags may also represent more than one interrupt

source.

Any GPIO pin (total of up to 25 pins) regardless of the selected function, can be

programmed to generate an interrupt on a level, or rising edge or falling edge, or both.

7.6 IOCONFIG block

The IOCONFIG block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be conn ected to th e appro priate pins prior to being activated and prior

to any related interrup t(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.7 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamica lly configured as input s or outputs. Multip le outputs

can be set or cleared in on e wr ite op e ra tio n.

EM773 uses accelerated GPIO functions:

•GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing

can be achiev ed .

•Entire port value can be written in one instruction.

Additionally, any GPIO pin (total of up to 25 pins) providing a digital function can be

programmed to generate an interrupt on a level, a rising or falling edge, or both.

7.7.1 Features

•Bit level port registers allow a single instruction to set or clear any number of bits in

one write operation.

•Direction control of individual bits.

•All I/O default to inputs with pull-ups enabled after reset.

•Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG

block for each GPIO pin.

7.8 UART

The EM773 contains one UART.

Support for RS-4 85 /9 -b it mo d e allo ws bo th software addr ess detection and auto m at ic

address detection using 9-bit mode.

Objective data sheet Rev. 1 — 1 September 2010 11 of 45

NXP Semiconductors EM773

Energy metering IC

The UART includes a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.8.1 Features

•Maximum UART data bit rate of 3.125 MBit/s.

•16 Byte Receive and Transmit FIFOs.

•Register locations conform to 16C550 industry standard .

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud ra te generator covering wide range of baud rates without a

need for external crystals of particular values.

•FIFO control mechanism that enables software flow control implementation.

•Support for RS -485 /9 -b it mo d e.

•Support for modem control.

7.9 SPI serial I/O controller

The EM773 contains one SPI controller.

The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bu s. Only a sing le mas te r and a si ng le

slave can communicate on the bus during a given data transfer. The SPI supports full

duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. In practice, often only one of these data flows

carries meaningful data.

7.9.1 Features

•Maximum SPI speed of 25 Mbit/s (maste r) or 4.17 Mbit/s (slave) (in SSP mode)

•Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

•Synchronous serial communication

•Master or slave operation

•8-frame FIFOs for both transmit and receive

•4-bit to 16-bit frame

7.10 I2C-bus serial I/O controller

The EM773 contains one I2C-bus controller.

The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line

(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and

can operate as either a r eceiver-only de vice ( e.g., an LCD driver) or a tra nsmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can oper ate in eithe r master or sl ave mo de, dependin g on whe ther th e chip ha s

to initiate a data transfer or is only addressed. The I2C is a multi-master bus an d ca n be

controlled by more than one bus master connected to it.

Objective data sheet Rev. 1 — 1 September 2010 12 of 45

NXP Semiconductors EM773

Energy metering IC

7.10.1 Features

•The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The

I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.

•Easy to configure as master, slave, or master/slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake me chanism to suspend and

resume serial transfer.

•The I2C-bus can be used for test an d diagnostic purposes.

•The I2C-bus controller supports multiple address recog nition and a bus mo nitor mode .

7.11 Metrology engine

The EM773 contains a metrology engine d esigned to co llect voltage and current in puts to

calculate the active power, reactive power, apparent power and power factor of a load.

The purpose of the metrology engine is for non-billing applications such as plug meters,

smart appliances, industrial and consumer sub-meters, etc.

7.11.1 Features

•1 % accurate for scalable input sources up to 230 V/50 Hz/16 A and

110 V/60 Hz/20 A while maintaining this accuracy with a factor of 1 to 400 down from

this maximum current.

•Automatically calculates active power in W, reactive power in VAr, apparent power in

VA, power factor ratio, Vrms and Irms without ARM CPU intervention.

•Standard API for initializing, starting, stopping and reading data from the metrology

engine using the ARM Cortex M0.

7.12 General purpose external event counter/timers

The EM773 includes two 32-bit counter/timers and one 16-bit counter/timers. The

counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. Each counter/timer also includes one capture input to trap the timer value

when an input signal transitions, optionally generating an interrupt.

7.12.1 Features

•A 32-bit/16-bit timer/counter with a prog rammable 32-bit/16-bit prescaler.

•Counter or time r op er a tion .

•One capture channel per timer, that can take a snapshot of the timer value when an

input signal transitions. A capture event may also generate an interrupt.

Objective data sheet Rev. 1 — 1 September 2010 13 of 45

NXP Semiconductors EM773

Energy metering IC

•Four match re gis ter s pe r tim er that allow :

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional inter rupt generation.

•Up to four external outputs corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

7.13 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).

7.14 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a selectable time

period.

7.14.1 Features

•Internally resets chip if not periodically reloaded.

•Debug mode.

•Enabled by soft ware but requires a hardwar e reset or a watchdog reset/interrupt to be

disabled.

•Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 24-bit tim er with internal prescaler.

•Selectable time period from (Tcy(WDCLK) ×256 ×4) to (Tcy(WDCLK) ×224 ×4) in

multiples of Tcy(WDCLK) ×4.

•The W atchdog Clock (WDCLK) source can be selected from the Internal RC oscillator

(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential

timing choices of Watchdog operation under different power reduction conditions. It

also provides the ability to run the WDT from an entirely internal source that is not

dependent on an external crystal and its associated components an d wiring for

increased reliability.

7.15 Clocking and power control

7.15.1 Crystal oscillators

The EM773 includes three independent oscillators. These are the system oscillator, the

Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for

more than one purpose as required in a particular application.

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NXP Semiconductors EM773

Energy metering IC

Following reset, the EM773 will operate from the Internal RC oscillator until switched by

software. This allows systems to operate without any external crystal and the bootloader

code to operate at a known frequency.

See Figure 4 for an overview of the EM773 clock generation.

7.15.1.1 Internal RC oscillator

The IRC may be used as th e clock source for th e WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequ ency is 12 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the EM773 uses the IRC as the clock source. Softwa re

may later switch to one of the other available clock sources.

7.15.1.2 System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using

the PLL.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL.

Fig 4. EM773 clock gen eration block diagram

SYSTEM PLL

IRC oscillator

system oscillator

watchdog oscillator

IRC oscillator

watchdog oscillator

MAINCLKSEL

(main clock select)

SYSPLLCLKSEL

(system PLL clock select)

SYSTEM CLOCK

DIVIDER

AHB clock 0

(system)

AHBCLKCTRL[1:18]

(AHB clock enable)

AHB clocks 1 to 18

(memories

and peripherals)

SPI0 PERIPHERAL

CLOCK DIVIDER SPI0

UART PERIPHERAL

CLOCK DIVIDER UART

WDT CLOCK

DIVIDER WDT

WDTUEN

(WDT clock update enable)

watchdog oscillator

IRC oscillator

system oscillator CLKOUT PIN CLOCK

DIVIDER CLKOUT pin

CLKOUTUEN

(CLKOUT update enable)

em773_002aae514

main clock

system clock

IRC oscillator

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NXP Semiconductors EM773

Energy metering IC

7.15.1.3 Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the

watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is

programmable between 7.8 kHz and 1.7 MHz. The frequency spread over p rocessing and

temperature is ±40 %.

7.15.2 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The output

divider may be set to divide by 2, 4, 8, or 16 to produce th e ou tp ut clock. Since the

minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.

The PLL is turned off and bypassed following a chip reset and may be enabled by

software. The program must configure and activate the PLL, wait for the PLL to lock, and

then connect to the PLL as a clock source. The PLL settling time is 100 μs.

7.15.3 Clock output

The EM773 features a clock output function that routes the IRC oscillator, the system

oscillator, the watchdog oscillator, or the main clock to an output pin.

7.15.4 Wake-up process

The EM773 begins operation at power-up and when awakened from Deep power-down

mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation

to resume quickly. If the system oscillator or the PLL is needed by the application,

software will need to enable these features and wait for them to stabilize before they are

used as a clock source.

7.15.5 Power control

The EM773 support s a variety of power control fe atures. There are three specia l modes of

processor power r eduction: Sleep mode, Deep-sleep mode, and Deep power-down mode.

The CPU clock rate may also be controlled as needed by changing clock sources,

reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a

trade-off of power versus processing speed based on application requirements. In

addition, a register is provided for shutting down the clocks to individual on-chip

peripherals, allowing fine tuning of power consumption by eliminating all dynamic power

use in any periph era ls th at ar e no t req uir ed for the a pplica tion. Selected periph erals have

their own clock divide r wh ich pr ovides even better power control.

7.15.5.1 Sleep mode

When Sleep mode is entered, the clock to the core is stoppe d. Resumption from the Sleep

mode does not need an y special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

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NXP Semiconductors EM773

Energy metering IC

7.15.5.2 Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in add ition all analo g blocks are sh ut

down. As an exception, the user has the option to keep the watchdog oscillator and the

BOD circuit running for se lf-timed wake- up and BOD protection. Dee p-sleep mod e allows

for additiona l powe r sa vin gs.

Up to 13 pins total serve as external wake-up pins to the start logic to wake up the chip

from Deep-sleep mode.

Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source

should be switched to IRC before entering Deep-sleep mode, because the IRC can be

switched on and off glitch-free.

7.15.5.3 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

WAKEUP pin. The EM773 can wake up from Deep power-down mode via the WAKEUP

pin.

7.16 System control

7.16.1 Start logic

The start logic connects external pins to corresponding interrupts in the NVIC. Each pin

shown in Table 2 as input to the start logic has an individual interrupt in the NVIC interru pt

vector table. The start logic pins can serve as external interrupt pins when the chip is

running. In addition, an input signal on the start logic pins can wake up the chip from

Deep-sleep mode when all clocks are sh ut down.

The start logic must be configured in the system configuration block and in the NVIC

before being used.

7.16.2 Reset

Reset has four sources on the EM773: the RESET pin, the Watchdog reset, Power-On

Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip re set by a ny source, on ce the opera tin g voltage attains

a usable level, starts the IRC and initializes the flash controller.

When the internal Reset is removed, th e processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

7.16.3 Brownout detection

The EM773 includes four levels for monitoring the voltage on the VDD pi n. If this volta ge

falls below one of the four selected levels, the BOD asserts an interrupt signal to the

NVIC. This signal can be enabled fo r interrupt in the In terrupt Enable Register in the NVIC

in order to cause a CPU interrupt; if not, software can monitor the signal by reading a

dedicated st atus register. Four additional threshold levels can be selected to cause a

forced reset of the chip.

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NXP Semiconductors EM773

Energy metering IC

7.16.4 Code security (Code Read Protection - CRP)

This feature of the EM773 allows user to enable different levels of security in the system

so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and

In-System Programming (ISP) can be restri cted. When needed, CRP is invoked by

programming a specific pattern into a dedicated flash location. IAP commands are not

affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For

details see the EM773 user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and flash field updates are needed but all sectors can

not be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to the ch ip

via the SWD pins and the ISP. This mode effectively disables ISP override using

PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update

mechanism using IAP calls or call reinvoke ISP command to enable flash update via

the UART.

In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be

disabled. For details see the EM773 user manual.

7.16.5 APB interface

The APB peripherals are located on one APB bus.

7.16.6 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main

static RAM, and the Boot ROM.

7.16.7 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs.

7.17 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four

breakpoints and two watchpoints is supported.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

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NXP Semiconductors EM773

Energy metering IC

8. Limiting values

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] Dependent on package type.

[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD supply voltage (core and external rail) 1.8 3.6 V

VIinput voltage 5 V tolerant I/O

pins; only valid

when the VDD

supply voltage is

present

[2] −0.5 +5.5 V

IDD supply current per supply pin [3] - 100 mA

ISS ground current per ground pin [3] - 100 mA

Ilatch I/O latch-up current −(0.5VDD) < VI <

(1.5VDD);

Tj < 125 °C

- 100 mA

Tstg storage temperature [4] −65 +150 °C

Tj(max) maximum junction temperature - 150 °C

Ptot(pack) total power dissipation (per package) based on package

heat transfer, not

device power

consumption

-1.5W

VESD electrostatic discharge voltage human body

model; all pins [5] −6500 +6500 V

EM773 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Objective data sheet Rev. 1 — 1 September 2010  19 of 45
NXP Semiconductors EM773
Energy metering IC
9. Static characteristics
 
Table 4. Static characteristics
Tamb =
−
40
°
C to +85
°
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
VDD supply voltage (core 
and external rail) 1.8 3.3 3.6 V
IDD supply current  Active mode; code
while(1){}
executed from flash
system clock = 12 MHz
VDD = 3.3 V
[2][3][4]
[5][6] -3-mA
system clock = 50 MHz
VDD = 3.3 V
[2][3][5]
[6][7] -9-mA
Sleep mode; 
system clock = 12 MHz
VDD = 3.3 V
[2][3][4]
[5][6] -2-mA
Deep-sleep mode; 
VDD = 3.3 V [2][3][8] -6-μA
Deep power-down mode; 
VDD = 3.3 V [2][9] -220-nA
Standard port pins, RESET
IIL LOW-level input current VI= 0 V; on-chip pull-up 
resistor disabled - 0.5 10 nA
IIH HIGH-level input 
current VI=V
DD; on-chip 
pull-down resistor 
disabled
- 0.5 10 nA
IOZ OFF-state output 
current VO=0V; V
O=V
DD; 
on-chip pull-up/down 
resistors disabled
- 0.5 10 nA
VIinput voltage pin configured to provide 
a digital function [10][11]
[12] 0- 5.0V
VOoutput voltage  output active 0 - VDD V
VIH HIGH-level input 
voltage 0.7VDD --V
VIL LOW-level input voltage - - 0.3VDD V
Vhys hysteresis voltage - 0.4 - V
VOH HIGH-level output 
voltage 2.0 V ≤ VDD ≤ 3.6 V; 
IOH =−4 mA VDD − 0.4--V
1.8 V ≤ VDD < 2.0 V; 
IOH =−3 mA VDD − 0.4--V
VOL LOW-level output 
voltage 2.0 V ≤ VDD ≤ 3.6 V; 
IOL =4 mA --0.4V
1.8 V ≤ VDD < 2.0 V; 
IOL =3 mA --0.4V

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NXP Semiconductors EM773

Energy metering IC

IOH HIGH-level output

current VOH =V

DD −0.4 V;

2.0 V ≤ VDD ≤ 3.6 V

−4--mA

1.8 V ≤ VDD < 2.0 V −3--mA

IOL LOW-level output

current VOL =0.4V

2.0 V ≤ VDD ≤ 3.6 V 4--mA

1.8 V ≤ VDD < 2.0 V 3--mA

IOHS HIGH-level short-circuit

output current VOH =0V [13] --−45 mA

IOLS LOW-level short-circuit

output current VOL =V

DD [13] --50mA

Ipd pull-down curre nt VI=5V 10 50 150 μA

Ipu pull-up current VI=0V;

2.0 V ≤ VDD ≤ 3.6 V

−15 −50 −85 μA

1.8 V ≤ VDD < 2.0 V −10 −50 −85 μA

VDD <V

I<5V 000μA

High-drive output pin (PIO0_7)

IIL LOW-level input current VI= 0 V; on-chip pull-up

resistor disabled - 0.5 10 nA

IIH HIGH-level input

current VI=V

DD; on-chip

pull-down resistor

disabled

- 0.5 10 nA

IOZ OFF-state output

current VO=0V; V

O=V

DD;

on-chip pull-up/down

resistors disabled

- 0.5 10 nA

VIinput voltage pin configured to provide

a digital function [10][11]

[12] 0- 5.0V

VOoutput voltage output active 0 - VDD V

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage 0.4 - - V

VOH HIGH-level output

voltage 2.5 V ≤ VDD ≤ 3.6 V;

IOH =−20 mA VDD − 0.4--V

1.8 V ≤ VDD < 2.5 V;

IOH =−12 mA VDD − 0.4--V

VOL LOW-level output

voltage 2.0 V ≤ VDD ≤ 3.6 V;

IOL =4 mA --0.4V

1.8 V ≤ VDD < 2.0 V;

IOL =3 mA --0.4V

IOH HIGH-level output

current VOH =V

DD −0.4 V;

2.5 V ≤ VDD ≤ 3.6 V 20--mA

1.8 V ≤ VDD < 2.5 V 12 - - mA

Table 4. Static characteristics …continued

Tamb =

−

C to +85

C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Objective data sheet Rev. 1 — 1 September 2010 21 of 45

NXP Semiconductors EM773

Energy metering IC

IOL LOW-level output

current VOL =0.4V

2.0 V ≤ VDD ≤ 3.6 V 4--mA

1.8 V ≤ VDD < 2.0 V 3--mA

IOLS LOW-level short-circuit

output current VOL =V

DD [13] --50mA

Ipd pull-down curre nt VI=5V 10 50 150 μA

Ipu pull-up current VI=0V

2.0 V ≤ VDD ≤ 3.6 V

−15 −50 −85 μA

1.8 V ≤ VDD < 2.0 V −10 −50 −85 μA

VDD <V

I<5V 000μA

I2C-bus pins (PIO0_4 and PIO0_5)

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage - 0.5VDD -V

IOL LOW-level output

current VOL =0.4V; I

2C-bus pins

configured as standard

mode pins

2.0 V ≤ VDD ≤ 3.6 V

4--mA

1.8 V ≤ VDD < 2.0 V 3 - -

IOL LOW-level output

current VOL =0.4V; I

2C-bus pins

configure d as Fast -mo de

Plus pins

2.0 V ≤ VDD ≤ 3.6 V

20--mA

1.8 V ≤ VDD < 2.0 V 16 - -

ILI input leakage current VI=V

DD [14] -24μA

VI=5V - 10 22 μA

Table 4. Static characteristics …continued

Tamb =

−

C to +85

C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Objective data sheet Rev. 1 — 1 September 2010 22 of 45

NXP Semiconductors EM773

Energy metering IC

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[2] Tamb =25°C.

[3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[4] IRC enabled; system oscillator disabled; system PLL disabled.

[5] BOD disabled.

[6] All peripherals disabled in the AHBCLKCT RL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block.

[7] IRC disabled; system oscillator enabled; system PLL enabled.

[8] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0xFFFF FDFF.

[9] WAKEUP pin pulled HIGH externally.

[10] Including voltage on outputs in 3-state mode.

[11] VDD supply voltage must be present.

[12] 3-state outputs go into 3-state mode in Deep power-down mode.

[13] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[14] To VSS.

Oscillator pins

Vi(xtal) crystal input voltage −0.5 1.8 1.95 V

Vo(xtal) crystal output volt age −0.5 1.8 1.95 V

Table 4. Static characteristics …continued

Tamb =

−

C to +85

C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Objective data sheet Rev. 1 — 1 September 2010 23 of 45

NXP Semiconductors EM773

Energy metering IC

9.1 BOD static characteristics

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see EM773

user manual.

9.2 Power consumption

Power measurement s in Active, Sleep , and Deep-sleep modes wer e performed under the

following conditions (see EM773 us er man u al ):

•Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.

•Configure GPIO pins as outputs using the GPIOnDIR registers.

•Write 0 to all GPIOnDATA registers to drive the outputs LOW.

Table 5. BOD static characteristics[1]

Tamb =25

Symbol Parameter Conditions Min Typ Max Unit

Vth threshold voltage interrupt level 0

assertion - 1.65 - V

de-assertion - 1.80 - V

interrupt level 1

assertion - 2.22 - V

de-assertion - 2.35 - V

interrupt level 2

assertion - 2.52 - V

de-assertion - 2.66 - V

interrupt level 3

assertion - 2.80 - V

de-assertion - 2.90 - V

reset level 0

assertion - 1.46 - V

de-assertion - 1.63 - V

reset level 1

assertion - 2.06 - V

de-assertion - 2.15 - V

reset level 2

assertion - 2.35 - V

de-assertion - 2.43 - V

reset level 3

assertion - 2.63 - V

de-assertion - 2.71 - V

Objective data sheet Rev. 1 — 1 September 2010 24 of 45

NXP Semiconductors EM773

Energy metering IC

Conditions: Tamb = 25 °C; active mode entered executing code

while(1){}

from flash; all

peripherals disabled in the AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks

disabled; internal pull-up resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC e nabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 5. Active mode: Typical supply current IDD versus supply voltage VDD for different

system clock frequencies

Conditions: VDD = 3.3 V; active mode entered executing code

while(1){}

from flash; all

peripherals disabled in the AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks

disabled; internal pull-up resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC e nabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 6. Active mode: Typical supply current IDD versus temperature for different system

clock frequencies

VDD (V)

1.8 3.63.02.4

002aaf390

IDD

(mA)

12 MHz(1)

24 MHz(2)

36 MHz(2)

48 MHz(2)

temperature (°C)

−40 853510 60−15

002aaf391

IDD

(mA)

12 MHz(1)

24 MHz(2)

36 MHz(2)

48 MHz(2)

Objective data sheet Rev. 1 — 1 September 2010 25 of 45

NXP Semiconductors EM773

Energy metering IC

Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the

AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up

resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC e nabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 7. Sleep mode: Typical supply current IDDversus temp erature for different system

clock frequencies

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0xFFFF FDFF).

Fig 8. Deep-sleep mode: Typical supply current IDD versus temperature for different

supply vo ltages VDD

002aaf392

temperature (°C)

−40 853510 60−15

IDD

(mA)

12 MHz(1)

36 MHz(2)

48 MHz(2)

24 MHz(2)

002aaf394

temperature (°C)

−40 853510 60−15

IDD

(μA)

3.6 V

3.3 V

2.0 V

1.8 V

Objective data sheet Rev. 1 — 1 September 2010 26 of 45

NXP Semiconductors EM773

Energy metering IC

9.3 Electrical pin characteristics

Fig 9. Deep power-down mode: Typical supply current IDD versus temperatu re for

different supply voltages VDD

002aaf457

0.2

0.6

0.4

0.8

IDD

(μA)

temperature (°C)

−40 853510 60−15

VDD = 3.6 V

3.3 V

2.0 V

1.8 V

Conditions: VDD = 3.3 V; on pin PIO0_7.

Fig 10. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level

output current IOH.

IOH (mA)

0 60402010 5030

002aae990

2.8

2.4

3.2

3.6

VOH

(V)

T = 85 °C

25 °C

−40 °C

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NXP Semiconductors EM773

Energy metering IC

Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.

Fig 11. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus

LOW-level output voltage VOL

Conditions: VDD = 3.3 V; standard port pins and PIO0_7.

Fig 12. Typical LOW-level output current IOL versus LOW-level output voltage VOL

VOL (V)

0 0.60.40.2

002aaf019

IOL

(mA)

T = 85 °C

25 °C

−40 °C

VOL (V)

0 0.60.40.2

002aae991

IOL

(mA)

T = 85 °C

25 °C

−40 °C

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NXP Semiconductors EM773

Energy metering IC

Conditions: VDD = 3.3 V; standard port pins.

Fig 13. Typical HIGH-level output voltage VOH versus HIGH-level output source current

IOH

Conditions: VDD = 3.3 V; standard port pins.

Fig 14. Typical pull-up current Ipu versus input voltage VI

IOH (mA)

0 24168

002aae992

2.8

2.4

3.2

3.6

VOH

(V)

T = 85 °C

25 °C

−40 °C

VI (V)

0 54231

002aae988

−30

−50

−10

Ipu

(μA)

−70

T = 85 °C

25 °C

−40 °C

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NXP Semiconductors EM773

Energy metering IC

Conditions: VDD = 3.3 V; standard port pins.

Fig 15. Typical pull-down current Ipd versus input voltage VI

VI (V)

0 54231

002aae989

Ipd

(μA)

T = 85 °C

25 °C

−40 °C

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Energy metering IC

10. Dynamic characteristics

10.1 Flash memory

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash

in blocks of 256 bytes.

10.2 External clock

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply

voltages.

Table 6. Flash characteristics

Tamb =

−

C to +85

C, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance [1] 10000 - - cycles

tret retention time powered 10 - - years

unpowered 20 - - years

ter erase time sector or multiple

consecutive

sectors

95 100 105 ms

tprog programming

time [2] 0.95 1 1.05 ms

Table 7. Dynamic characteristic: external clock

Tamb =

−

C to +85

C; VDD over specified ranges.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc oscillator frequency 1 - 25 MHz

Tcy(clk) clock cycle time 40 - 1000 ns

tCHCX clock HIGH time Tcy(clk) ×0.4--ns

tCLCX clock LOW time Tcy(clk) ×0.4--ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Fig 16. External clock timing (with an amplitu de of at least Vi(RMS) = 200 mV)

tCHCL tCLCX

tCHCX

Tcy(clk)

tCLCH

002aaa907

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NXP Semiconductors EM773

Energy metering IC

10.3 Internal oscillators

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply

voltages.

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply

voltages.

[2] The typical frequency spread over processing and temperature (Tamb = −40 °C to +85 °C) is ±40 %.

[3] See the EM773 user manual.

Table 8. Dynamic characteristic: internal oscillators

Tamb =

−

C to +85

C; 2.7 V

≤

VDD

≤

3.6 V.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc(RC) internal RC oscillator frequency - 11.88 12 12.12 MH z

Conditions: Frequency values are typical values. 12 MHz ± 1 % accuracy is guaranteed for

2.7 V ≤ VDD ≤ 3.6 V and Tamb =−40 °C to +85 °C. Variations between parts may cause the IRC to

fall outside the 12 MHz ± 1 % accuracy specification for voltages below 2.7 V.

Fig 17. Internal RC oscillator frequency vs. temperature

Table 9. Dynamic characteristics: Watchdog oscillator

Symbol Parameter Conditions Min Typ[1] Max Unit

fosc internal oscillator

frequency DIVSEL = 0x1F, FREQSEL = 0x1

in the WDTOSCCTRL register; [2][3] -7.8 - kHz

DIVSEL = 0x00, FREQSEL = 0xF

in the WDTOSCCTRL register [2][3] - 1700 - kHz

002aaf403

11.95

12.05

12.15

(MHz)

11.85

temperature (°C)

−40 853510 60−15

VDD = 3.6 V

3.3 V

3.0 V

2.7 V

2.4 V

2.0 V

EM773 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Objective data sheet Rev. 1 — 1 September 2010  32 of 45
NXP Semiconductors EM773
Energy metering IC
10.4 I/O pins 
 
[1] Applies to standard port pins and RESET pin.
10.5 I2C-bus
 
[1] See the I2C-bus specification UM10204 for details.
[2] Parameters are valid over operating temperature range unless otherwise specified. 
[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission 
and the acknowledge.
[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the 
VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
[5] Cb = total capacitance of one bus line in pF.
Table 10. Dynamic characteristic: I/O pins[1]
Tamb =
−
40
°
C to +85
°
C; 3.0 V 
≤
 VDD  
≤
 3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
trrise time pin 
configured as 
output
3.0 - 5.0 ns
tffall time pin 
configured as 
output
2.5 - 5.0 ns
Table 11. Dynamic characteristic: I2C-bus pins[1]
Tamb =
−
40
°
C to +85
°
C.[2] 
Symbol Parameter Conditions Min Max Unit
fSCL SCL clock 
frequency Standard-mode 0 100 kHz
Fast-mode 0 400 kHz
Fast-mode Plus 0 1 MHz
tffall time [4][5][6][7] of both SDA and 
SCL signals
Standard-mode
-300ns
Fast-mode 20 + 0.1 × Cb300 ns
Fast-mode Plus - 120 ns
tLOW LOW period of 
the SCL clock Standard-mode 4.7 - μs
Fast-mode 1.3 - μs
Fast-mode Plus 0.5 - μs
tHIGH HIGH period of 
the SCL clock Standard-mode 4.0 - μs
Fast-mode 0.6 - μs
Fast-mode Plus 0.26 - μs
tHD;DAT data hold time [3][4][8] Standard-mode 0 - μs
Fast-mode 0 - μs
Fast-mode Plus 0 - μs
tSU;DAT data set-up 
time 
 
[9][10] Standard-mode 250 - ns
Fast-mode 100 - ns
Fast-mode Plus 50 - ns

Objective data sheet Rev. 1 — 1 September 2010 33 of 45

NXP Semiconductors EM773

Energy metering IC

[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8] The maximum tHD;DAT could be 3.45 μs and 0.9 μs for S tandard-mode and Fast-mode but must be less than

the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I2C-bus device can be used in a S tandard-mode I2C-bus system but the requirement tSU;DAT =

250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period

of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next

data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus

specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

10.6 SPI interfaces

Fig 18. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

HD;DAT

SCL

1 / f

SCL

70 %

30 %

70 %

30 %

VD;DAT

HIGH

LOW

SU;DAT

Table 12. Dynamic characteristics of SPI pins in SPI mode

Symbol Parameter Conditions Min Typ Max Unit

SPI master (in SPI mode)

Tcy(clk) clock cycle time when only receiving [1] 40 - - ns

when only transmitting [1] 27.8 ns

tDS data set-up time in SPI mode

2.4 V ≤ VDD ≤ 3.6 V

[2] 15 - - ns

2.0 V ≤ VDD < 2.4 V [2] 20 ns

1.8 V ≤ VDD < 2.0 V [2] 24 - - ns

tDH data hold time in SPI mode [2] 0-- ns

tv(Q) data output valid time in SPI mode [2] --10 ns

th(Q) data output hold time in SPI mode [2] 0-- ns

SPI slave (in SPI mode)

Tcy(PCLK) PCLK cycle time 20 - - ns

Objective data sheet Rev. 1 — 1 September 2010 34 of 45

NXP Semiconductors EM773

Energy metering IC

[1] Tcy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),

and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).

[2] Tamb = −40 °C to 85 °C.

[3] Tcy(clk) = 12 × Tcy(PCLK).

[4] Tamb = 25 °C; for normal voltage supply range: VDD = 3.3 V.

tDS data set-up time in SPI mode [3][4] 0-- ns

tDH data hold time in SPI mode [3][4] 3 × Tcy(PCLK) + 4 - - ns

tv(Q) data output valid time in SPI mode [3][4] --3 × Tcy(PCLK) + 11 ns

th(Q) data output hold time in SPI mode [3][4] --2 × Tcy(PCLK) + 5 n s

Table 12. Dynamic characteristics of SPI pins in SPI mode

Symbol Parameter Conditions Min Typ Max Unit

Pin names SCK, MISO, and MOSI r e fer to pins for both SPI peripherals, SPI0 and SPI1.

Fig 19. SPI master timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk) tclk(H) tclk(L)

tDS tDH

tv(Q)

DATA VALID DATA VALID

th(Q)

SCK (CPOL = 1)

DATA VALID DATA VALID

MOSI

MISO

tDS tDH

DATA VALID DATA VALID

th(Q)

DATA VALID DATA VALID

tv(Q)

CPHA = 1

CPHA = 0

002aae829

Objective data sheet Rev. 1 — 1 September 2010 35 of 45

NXP Semiconductors EM773

Energy metering IC

Pin names SCK, MISO, and MOSI r e fer to pins for both SPI peripherals, SPI0 and SPI1.

Fig 20. SPI slave timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

cy(clk)

clk(H)

clk(L)

v(Q)

DATA VALID DATA VALID

h(Q)

SCK (CPOL = 1)

DATA VALID DATA VALID

MOSI

MISO

v(Q)

DATA VALID DATA VALID

h(Q)

DATA VALID DATA VALID

CPHA = 1

CPHA = 0

002aae830

Objective data sheet Rev. 1 — 1 September 2010 36 of 45

NXP Semiconductors EM773

Energy metering IC

11. Application information

11.1 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommende d that the inpu t be coupled th rough a cap acitor wi th

Ci = 100 pF. To limit the input voltage to the specified range, choose an addi tional

capacitor to ground Cg which attenuates the input volt age by a facto r Ci/(Ci + Cg). In slave

mode, a minimum of 200 mV(RMS) is needed.

In slave mode the input clock signal should be coup led by means of a cap acitor of 100 pF

(Figure 21), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 22 and in

Table 13 and Table 14. Since the feedback resistance is integrated on chip, only a crystal

and the capacitances CX1 and CX2 need to be connected exter nally in case of

fundamental mode oscillation (the fundamental frequency is represented by L, CL and

RS). Capacitance CP in Figure 22 represent s the p arallel p ackage cap acitance and should

not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal

manufacturer (see Table 13).

Fig 21. Slave mode operation of the on-chip oscillator

EM773

XTALIN

100 pF

em773_002aae788

Objective data sheet Rev. 1 — 1 September 2010 37 of 45

NXP Semiconductors EM773

Energy metering IC

11.2 XTAL Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load cap acitors Cx1, Cx2, and Cx3 in ca se o f

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be made as small as possible in

Fig 22. Oscillator modes and models: oscillation mode of operation and externa l crystal

model used for CX1/CX2 evaluation

Table 13. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

1 MHz - 5 MHz 10 pF < 300 Ω18 pF, 18 pF

20 pF < 300 Ω39 pF, 39 pF

30 pF < 300 Ω57 pF, 57 pF

5 MHz - 10 MHz 10 pF < 300 Ω18 pF, 18 pF

20 pF < 200 Ω39 pF, 39 pF

30 pF < 100 Ω57 pF, 57 pF

10 MHz - 15 MHz 10 pF < 160 Ω18 pF, 18 pF

20 pF < 60 Ω39 pF, 39 pF

15 MHz - 20 MHz 10 pF < 80 Ω18 pF, 18 pF

Table 14. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) high frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

15 MHz - 20 MHz 10 pF < 180 Ω18 pF, 18 pF

20 pF < 100 Ω39 pF, 39 pF

20 MHz - 25 MHz 10 pF < 160 Ω18 pF, 18 pF

20 pF < 80 Ω39 pF, 39 pF

em773_002aaf424

EM773

XTALIN XTALOUT

CX2

CX1

XTAL

=CLCP

Objective data sheet Rev. 1 — 1 September 2010 38 of 45

NXP Semiconductors EM773

Energy metering IC

order to keep the noise coup le d in via the PCB as sm all as po ss ible . A lso parasitics

should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

11.3 Standard I/O pad configuration

Figure 23 shows the possible pin modes for standard I/O pins with analog input function:

•Digital output driver

•Digital input: Pull-up enabled/disabled

•Digital input: Pull-down enabled/disabled

•Digital input: Repeater mode enabled/di sabled

•Analog input

Fig 23. St a ndard I/O pad configuration

VDD

ESD

VSS

ESD

VDD

weak

pull-up

weak

pull-down

output enable

repeater mode

enable

output

pull-up enable

pull-down enable

data input

analog input

select analog input

002aaf304

pin configured

as digital output

driver

pin configured

as digital input

pin configured

as analog input

Objective data sheet Rev. 1 — 1 September 2010 39 of 45

NXP Semiconductors EM773

Energy metering IC

11.4 Reset pad configuration

Fig 24. Reset pad configuration

VSS

reset

002aaf274

VDD

Rpu ESD

ESD

20 ns RC

GLITCH FILTER PIN

Objective data sheet Rev. 1 — 1 September 2010 40 of 45

NXP Semiconductors EM773

Energy metering IC

12. Package outline

Fig 25. Package outline (HVQFN33)

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

- - -

hvqfn33_po

09-03-17

09-03-23

Unit

max

nom

min

1.00

0.85

0.80

0.05

0.02

0.00

0.2

7.1

7.0

6.9

4.85

4.70

4.55

7.1

7.0

6.9

0.65 4.55

0.75

0.60

0.45

0.1

A(1)

Dimensions

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;

33 terminals; body 7 x 7 x 0.85 mm

A1b

0.35

0.28

0.23

(1) DhE(1) Eh

4.85

4.70

4.55

1e2

4.55

0.1

0.05

0.08

0 2.5 5 mm

scale

terminal 1

index area

detail X

AC B

terminal 1

index area Dh

9 16

Objective data sheet Rev. 1 — 1 September 2010 41 of 45

NXP Semiconductors EM773

Energy metering IC

13. Abbreviations

Table 15. Abbreviations

Acronym Description

AHB Advanced High-performance Bus

AMBA Advanced Microcontroller Bus Architecture

APB Advanced Peripheral Bus

BOD BrownOut Detection

GPIO General Purpose Input/Output

PLL Phase-Locked Loop

RC Resistor-Capacitor

SPI Serial Peripheral Interface

SSI Serial Synchronous Interface

SSP Synchronous Serial Port

TTL Transistor-Transistor Logic

UART Universal Asynchronous Receiver/Transmitter

Objective data sheet Rev. 1 — 1 September 2010 42 of 45

NXP Semiconductors EM773

Energy metering IC

14. Revision history

Table 16. Revision history

Document ID Release date Data sheet status Change notic e Supersedes

EM773 v.1 <tbd> Objective data sheet - -

Objective data sheet Rev. 1 — 1 September 2010 43 of 45

NXP Semiconductors EM773

Energy metering IC

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be lia ble for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability t owards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or cust omer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo mer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly ob jects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objecti ve specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Objective data sheet Rev. 1 — 1 September 2010 44 of 45

NXP Semiconductors EM773

Energy metering IC

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qua lif ied nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims result ing from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors EM773
Energy metering IC
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 September 2010
Document identifier: EM773
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’. 
Contents
General description. . . . . . . . . . . . . . . . . . . . . .  1
Features and benefits . . . . . . . . . . . . . . . . . . . .  1
Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . .  2
Ordering information. . . . . . . . . . . . . . . . . . . . .  2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .  3
Pinning information. . . . . . . . . . . . . . . . . . . . . .  4
1  Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4
2  Pin description . . . . . . . . . . . . . . . . . . . . . . . . .  5
Functional description  . . . . . . . . . . . . . . . . . . .  8
1  ARM Cortex-M0 processor. . . . . . . . . . . . . . . .  8
2  On-chip flash program memory . . . . . . . . . . . .  8
3  On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . .  8
4  Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . .  8
5  Nested Vectored Interrupt Controller (NVIC) . .  9
5.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
5.2  Interrupt sources. . . . . . . . . . . . . . . . . . . . . . .  10
6  IOCONFIG block  . . . . . . . . . . . . . . . . . . . . . .  10
7  Fast general purpose parallel I/O . . . . . . . . . .  10
7.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
8  UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
8.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11
9  SPI serial I/O controller . . . . . . . . . . . . . . . . . .  11
9.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11
10 I2C-bus serial I/O controller  . . . . . . . . . . . . . .  11
10.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
11  Metrology engine . . . . . . . . . . . . . . . . . . . . . .  12
11.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
12  General purpose external event counter/timers . . 
12
12.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
13  System tick timer . . . . . . . . . . . . . . . . . . . . . .  13
14  Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . .  13
14.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
15  Clocking and power control . . . . . . . . . . . . . .  13
15.1  Crystal oscillators . . . . . . . . . . . . . . . . . . . . . .  13
15.1.1  Internal RC oscillator  . . . . . . . . . . . . . . . . . . .  14
15.1.2  System oscillator  . . . . . . . . . . . . . . . . . . . . . .  14
15.1.3  Watchdog oscillator  . . . . . . . . . . . . . . . . . . . .  15
15.2  System PLL . . . . . . . . . . . . . . . . . . . . . . . . . .  15
15.3  Clock output . . . . . . . . . . . . . . . . . . . . . . . . . .  15
15.4  Wake-up process . . . . . . . . . . . . . . . . . . . . . .  15
15.5  Power control . . . . . . . . . . . . . . . . . . . . . . . . .  15
15.5.1  Sleep mode  . . . . . . . . . . . . . . . . . . . . . . . . . .  15
15.5.2  Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . .  16
15.5.3  Deep power-down mode  . . . . . . . . . . . . . . . .  16
16  System control . . . . . . . . . . . . . . . . . . . . . . . .  16
16.1  Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
16.2  Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   16
16.3  Brownout detection . . . . . . . . . . . . . . . . . . . .   16
16.4  Code security (Code Read Protection - CRP)  17
16.5  APB interface. . . . . . . . . . . . . . . . . . . . . . . . .   17
16.6  AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   17
16.7 External interrupt inputs. . . . . . . . . . . . . . . . .   17
17  Emulation and debugging . . . . . . . . . . . . . . .   17
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .   18
Static characteristics . . . . . . . . . . . . . . . . . . .   19
1  BOD static characteristics . . . . . . . . . . . . . . .   23
2  Power consumption   . . . . . . . . . . . . . . . . . . .   23
3  Electrical pin characteristics. . . . . . . . . . . . . .   26
Dynamic characteristics. . . . . . . . . . . . . . . . .   30
1  Flash memory . . . . . . . . . . . . . . . . . . . . . . . .   30
2  External clock. . . . . . . . . . . . . . . . . . . . . . . . .   30
3  Internal oscillators . . . . . . . . . . . . . . . . . . . . .   31
4  I/O pins  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   32
5 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   32
6  SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . .   33
Application information . . . . . . . . . . . . . . . . .   36
1  XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . .   36
2  XTAL Pri nted Circuit Board (PCB) layout 
guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . .   37
3  Standard I/O pad configuration  . . . . . . . . . . .   38
4  Reset pad configuration. . . . . . . . . . . . . . . . .   39
Package outline. . . . . . . . . . . . . . . . . . . . . . . .   40
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .   41
Revision history  . . . . . . . . . . . . . . . . . . . . . . .   42
Legal information . . . . . . . . . . . . . . . . . . . . . .   43
1  Data sheet status. . . . . . . . . . . . . . . . . . . . . .   43
2  Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .   43
3  Disclaimers  . . . . . . . . . . . . . . . . . . . . . . . . . .   43
4  Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .   44
Contact information . . . . . . . . . . . . . . . . . . . .   44
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   45