128K x 8 Static RAM
CY7C1019BV33
CY7C1018BV33
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Ju ne 11, 200 1
019V33
Features
• High speed
—tAA = 10 ns
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory ex pans ion with CE and OE options
• Functional ly equivalent to CY7C1019V3 3 and/or
CY7C1018V33
Functional Description
The CY7C1019BV33/CY7C1018BV33 is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
memory e xpansio n is prov ided b y an activ e LO W Chi p Enabl e
(CE), an activ e LOW Output Enable (OE), and three-state driv-
ers. This device has an automatic power-down feature that
significantly reduces power consumption when deselect ed.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enab le (WE) inputs LO W . Data on the eight I/O
pins (I/O 0 through I/O7) is then written into the location speci-
fied on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enab le (CE) and Out put Enable (OE) LOW while f orcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the mem ory location spe cifie d b y the a ddre ss pins w ill a ppear
on the I/O pins.
The eight inp ut/o utp ut pin s (I/O0 thro ug h I/ O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIG H ), or du r i n g a write
operation (CE LOW, and WE LOW).
The CY7C1019BV33 is available in standard 32-pin TSOP
Type II and 400-mil-wide package. The CY7C1018BV33 is
available in a standard 300-mil-wide package.
Selection Guide
7C1019BV33-10
7C1018BV33-10 7C1019BV33-12
7C1018BV33-12 7C1019BV33-15
7C1018BV33-15
Maximum Access Time (ns) 10 12 15
Maximum Operating Current (mA) 175 160 145
Maximum Standby Current (mA) 5 5 5
L−0.5 0.5
14
15
Logic Block Diagram Pin Configurations
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
I/O1
I/O2
I/O3
512 x 256 x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A11
A13
A12
A
A10
CE
A
A16
A9
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
SOJ / TSOPII
12
13
29
32
31
30
16
15 17
18
A
7
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
A
13
A
16
A
15
OE
I/O
7
I/O
6
A
12
A
11
A
10
A
9
I/O
2
A
0
A
4
A
5
A
6
I/O
4
V
CC
I/O
5
A
8
I/O
3
WE
V
SS
A
14
V
SS
CY7C1019BV33
CY7C1018BV33
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Pow er Appl ie d............. ...... ..... .....................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1]....................................–0.5 V to VCC + 0.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range Ambient
Temperature[2] VCC
Commercial 0°C to +70°C 3.3V ± 10%
Electrical Characteristics Over the Op erating Range
Te st Conditions
7C1019BV33-10
7C1018BV33-10 7C1019BV33-12
7C1018BV33-12 7C1019BV33-15
7C1018BV33-15
Parameter Description Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min.,
IOH = – 4.0 mA 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min.,
IOL = 8.0 mA 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC
+ 0.3 2.2 VCC
+ 0.3 2.2 VCC
+ 0.3 V
VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Load Current GND < VI < VCC –1+1–1+1–1+1µA
IOZ Output Leakage
Current GND < VI < VCC,
Output Di sa bled –5+5–5+5–5+5µA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
175 160 145 mA
ISB1 Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
20 20 20 mA
ISB2 Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
555mA
L−0.5 0.5
Capacitance[3]
Parameter Description Te st Conditions Max. Unit
CIN Input Capa cit anc e TA = 25°C, f = 1 MHz,
VCC = 5.0V 6pF
COUT Output Capacitance 8 pF
Notes:
1. VIL (min.) = –2.0V for pulse duration s of less than 20 ns.
2. TA is the “Instant On” case temper ature .
3. Tested initially and after any design or process changes that may affect these parameters.
CY7C1019BV33
CY7C1018BV33
3
AC Test Loads and Waveforms
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
3.3V
OUTPUT
5 pF
INCLUDING
JIG AN D
SCOPE
(a) (b)
≤ 3 ns ≤3ns
OUTPUT
R1 480ΩR1 480 Ω
R2
255 Ω R2
255 Ω
167 Ω
Equivalent to: VENIN EQUIVALENT
1.73V
THÉ
Switching Characteristi cs[4] Over the Operating Range
7C1019BV33-10
7C1018BV33-10 7C1019BV33-12
7C1018BV33-12 7C1019BV33-15
7C1018BV33-15
Parameter Description Min.Max.Min.Max.Min.Max.Unit
READ CYCLE
tRC Read Cycle Time 10 12 15 ns
tAA Address to Data Valid 10 12 15 ns
tOHA Data Hold from Address Change 3 3 3 ns
tACE CE LOW to Data Valid 10 12 15 ns
tDOE OE LO W to Data Valid 5 6 7 ns
tLZOE OE LOW to Low Z 0 0 0 ns
tHZOE OE HIGH to High Z[5, 6] 567ns
tLZCE CE LOW to Low Z[6] 333ns
tHZCE CE HIGH to High Z[5, 6] 567ns
tPU CE LOW to Power-Up 0 0 0 ns
tPD CE HIGH to Power-Down 10 12 15 ns
WRITE CYCLE[7, 8]
tWC Write Cycle Time 10 12 15 ns
tSCE CE LOW to Write End 8 9 10 ns
tAW Address Set-Up to Write End 7 8 10 ns
tHA Address H old from Write End 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 ns
tPWE WE Pulse Width 7 8 10 ns
tSD Data Set-Up to Write End 5 6 8 ns
tHD Data Hold from Write End 0 0 0 ns
tLZWE WE HIGH to Low Z[6] 333ns
tHZWE WE LOW to H igh Z[5, 6] 567ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference lev els of 1.5V, input pulse lev els of 0 to 3.0V, and output loading of the specified
IOL/IOH an d 30-pF load cap acit ance.
5. tHZOE, tHZCE, and tHZWE are specified wi th a load capacitance of 5 pF as in part (b) of AC Tes t Loads. Tr ansition is measu red ±5 00 mV from steady-st ate vo ltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and t HZWE is less than tLZWE f or any giv en de vice .
7. Th e in ternal w rite ti me of th e memory is defi ned by the o v erla p of CE L OW and WE LOW . CE and WE m ust be LO W to initiate a write , and the tr ansition of any of these
signals can terminat e the write . The input data set- up and hold timing shoul d be refer enced to the leading edge of the signal th at terminat es th e write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
CY7C1019BV33
CY7C1018BV33
4
Data Retention Characteristics Over the Operating Range (L Version Only)
Parameter Description Conditions Min. Max. Unit
VDR VCC for Data Retention No input may exceed VCC + 0.5V
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
2.0 V
ICCDR Data Retention Current 150 µA
tCDR[3] Chip Deselect to Data Retention Time 0 ns
tROperation Recovery Time 200 µs
Data Retention Waveform
3.0V3.0V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC
Switching Waveforms
Read Cycle No. 1[9, 10]
Read Cycle No. 2 (OE Controlled)[10, 11]
Notes:
9. Device is continuously selected. OE, CE = VIL.
10. WE is HIGH for read c ycle .
11. Address valid prior to or coincident with CE transi tion LOW.
PREVIOUS DATA VALID DATA VALI D
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
CY7C1019BV33
CY7C1018BV33
5
Write Cycle No. 1 (CE Contr olle d) [12, 13]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13]
Notes:
12. Data I/O is high impedance if OE = VIH.
13. If CE goe s HIGH simultan eously with W E going HIGH , the output remains in a high-imp edance stat e.
14. During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE
ADDRESS
WE
DATA I/O
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 14
CY7C1019BV33
CY7C1018BV33
6
Write Cycle No. 3 (WE Controlled, OE LOW)[13]
Switching Waveforms (continued)
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATA I/O NOTE 14
Truth Table
CE OE WE I/O0–I/O7Mode Power
H X X High Z Power-Down Standby (ISB)
X X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Sele cted, Outputs Disabled Active (ICC)
CY7C1019BV33
CY7C1018BV33
7
Ordering Information
Speed
(ns) Ordering Code Package
Name Packa ge Type Operating
Range
10 CY7C1018V33-10VC V32 32-Lead 300-Mil Molded SOJ Commercia l
CY7C1019BV33-10VC V33 32-Lead 400-Mil Molded SOJ
CY7C1019 BV33-10ZC ZS32 32-Lead TS OP Type II
12 CY7C1018BV33-12VC V32 32-Lead 300-Mil Molded SOJ
CY7C1018BV33L-12VC V32 32-Lead 300-Mil Molded SOJ
CY7C1019BV33-12VC V33 32-Lead 400-Mil Molded SOJ
CY7C1019 BV33-12ZC ZS32 32-Lead TS OP Type II
CY7C1019BV33L-12VC V33 32-Lead 400-Mil Molded SOJ
CY7C1019 BV33L-12ZC ZS32 32-Lea d TSOP Type II
15 CY7C1018BV33-15VC V32 32-Lead 300-Mil Molded SOJ
CY7C1018BV33L-15VC V32 32-Lead 300-Mil Molded SOJ
CY7C1018BV33-15VI V32 32-Lead 300-Mil Molded SOJ
CY7C1019BV33-15VC V33 32-Lead 400-Mil Molded SOJ
CY7C1019 BV33-15ZC ZS32 32-Lead TS OP Type II
CY7C1019BV33L-15VC V33 32-Lead 400-Mil Molded SOJ
CY7C1019 BV33L-15ZC ZS32 32-Lea d TSOP Type II
CY7C1019BV33-15VI V33 32-Lead 400-Mil Molded SOJ
CY7C1019 BV33-15ZI ZS32 32-Lead TSOP Type II Industrial
Document #: 38-01053-*B
CY7C1019BV33
CY7C1018BV33
8
Package Diagram
51-85041-A
32-Lead (400-Mil) Molded SOJ V33
32-Lead (300-Mil) Molded SOJ V32
51-85041
CY7C1019BV33
CY7C1018BV33
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other than circ uitry embo died in a Cypr ess Semiconductor p roduct. Nor does it conv ey or imply an y license under pa tent or other rights. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
32-Lead TSOP II ZS32
51-85095
