PAC1921-1-AIA-TR - MICROCHIP TECHNOLOGY

 2012-2016 Microchip Technology Inc. DS20005293D-page 1

PAC1921

Features

• Configurable Measurement Type Output: Power,

Current or Bus Voltage

• Configurable Voltage Output (3V, 2V, 1.5V, 1V)

- All output values also available over SMBus

• New Device Topology

- Provides integrated average power

measurement

- Power measurements provided to

microcontroller with ADC inputs

- Unique lossless integrating architecture

allows operation at low sense voltages

- Output voltage proportional to selected

measurement

• High-Side Current Sensor

- 100 mV full-scale current sense voltage range

- Second-order delta-sigma ADC with 11-bit or

14-bit resolution

- Selectable current binary gain ranges: 1x

through 128x

• 1% Power Measurement Accuracy

• Auto-Zero Offset

• Auto Sleep State

- Automatically shifts to low-power state

(3.5 µA)

• Power Supply

-V

DD = 3.3V nominal (operational range 3.0V

to 5.5V)

• Bus Range 0V to 32V

• No Input Filters Required

• Available in a 10-pin 3 mm x 3 mm VDFN RoHS

Compliant Package

Applications

• Diagnostic Equipment

•Servers

• Power Supplies

• Industrial and Power Management Systems

• Notebook and Desktop Computers

Description

The PAC1921 is a dedicated power-monitoring device

with a configurable analog output that can present

power, current or voltage. The PAC1921 is designed for

power measurement and diagnostic systems that

cannot allow for latency when performing high-speed

power management. Measurements are accumulated

in large lossless registers, allowing for integration

periods of 500 µs to 2.9 seconds. The measurement is

averaged and presented on the analog output with a

full scale range of 3V, 2V, 1.5V or 1.0V.

The PAC1921 has a READ/INT pin for host control of the

measurement integration period. This pin can be used to

synchronize readings of multiple buses between several

devices. Alternatively, PAC1921 is able to provide

outputs in a free-running mode. Information is provided

on the OUT pin and is available via SMBus if desired.

Data sampling and output attributes, such as the internal

ADC resolution (11-bit or 14-bit) and sample rate, are

configurable. The SMBus interface has more selections

for user-configurable options.

The PAC1921 is a 1% accurate power measurement

device that measures and cancels the zero offset from

the input pins. The PAC1921 was designed to monitor

power rails from 0-32V with a full-scale capability of

100 mV across the sense resistor. No input filters are

required for this device.

Package Types

SENSE -

SENSE +

OUT

SM_DATA

READ/INT

7RESERVED

SM_CLKV

5ADDR_SEL

GND

PAC1921

3x3 VDFN*

*Includes Exposed Thermal Pad (EP), see Tabl e 3- 1

High-Side Power/Current Monitor with Analog Output

PAC1921

DS20005293D-page 2  2012-2016 Microchip Technology Inc.

Device Block Diagram

Diff Current

Amplifier

V Buffer/

Divider

Digital Control

VDD GND

SENSE+

SENSE-

OUT

READ/INT

ADDR_SEL

11-bit or

14-bit

ADC

and

MUX

10-bit

DAC

SM_CLK

SM_DATA

Resistor

Decoder

RESERVED

 2012-2016 Microchip Technology Inc. DS20005293D-page 3

PAC1921

1.0 ELECTRICAL CHARACTERISTICS

1.1 Electrical Specifications

Absolute Maximum Ratings(†)

VDD pin............................................................................................................................................................-0.3 to 6.0V

Voltage on SENSE- and SENSE+ pins............................................................................................................-0.3 to 42V

Voltage on ADDR_SEL pin .............................................................................................................................-0.3 to 2.6V

Voltage on any other pin to GND ....................................................................................................................-0.3 to 6.0V

Voltage between Sense pins (|(SENSE+ – SENSE-)|) ...............................................................................................40V

Input current to any pin except VDD ......................................................................................................................±10 mA

Output short circuit current.............................................................................................................................. Continuous

Package Power Dissipation (Note) ...............................................................................................0.5W up to TA = +85°C

Junction to Ambient (JA)....................................................................................................................................+78°C/W

Operating Ambient Temperature Range .......................................................................................................-40 to +85°C

Storage Temperature Range.......................................................................................................................-55 to +150°C

ESD Rating - All pins - HBM ...................................................................................................................................2000V

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at those or any other conditions above those indicated

in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended

periods may affect device reliability.

Note: The Package Power Dissipation specification assumes a recommended thermal via design consisting of a

2 x 2 matrix of 0.3 mm (12 mil) vias at 1.0 mm pitch connected to the ground plane with a 1.6 mm x 2.3 mm

thermal landing

PAC1921

DS20005293D-page 4  2012-2016 Microchip Technology Inc.

TABLE 1-1: ELECTRICAL CHARACTERISTICS

Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40°C to +85°C, VDD = 3V to 5.5V,

VBUS = 0V to 32V; typical values are at TA = +25°C, VDD = 3.3V, VBUS = 24V, VSENSE = (SENSE+ – SENSE-) = 0V

Characteristic Sym. Min. Typ. Max. Unit Conditions

Power Supply

VDD Range VDD 3.0 — 5.5 V

VDD Integrate Current IDD — 450 900 µA Output unloaded

VDD Read Current IREAD — 300 450 µA Output unloaded

VDD Sleep Current ISLEEP — 3.5 15 µA

VDD Rise Rate VDD_RISE 0.05 — 1000 V/ms 0 to 3V in 60 ms

Analog Input Characteristics

Bus Voltage Range VBUS 0 — 32 V Common-mode voltage on

SENSE pins, referenced to

ground

VSENSE Differential

Input Voltage Range

VSENSE_DIF 0—100mV

ADC Data Resolution ADC_RES — — 14 bits

VSENSE

LSB Step Size

VSENSE_LSB — 6.1 — µV 14-bit resolution

— 48.8 — µV 11-bit resolution

VBUS LSB Step Size VBUS_LSB — 1.95 — mV 14-bit resolution

— 15.6 — mV 11-bit resolution

VSENSE

Gain Accuracy

VSENSE_ GAIN_ERR — ±0.2 ±0.4 % Gain = 1

VSENSE

Offset Accuracy,

Referenced to Input

VSENSE_ OFFSET_ERR — ±25 ±100 µV 14-bit resolution

VBUS

Gain Accuracy

VBUS_GAIN_ERR — — ±0.4 % Measured at ADC output,

Gain = 1

SENSE+, SENSE-

Pin Leakage

Current

ISENSE +, ISENSE- —— 1.0 µAV

BUS = 24V, VSENSE = 0V

Sleep state

SENSE+, SENSE-

Pin Leakage Current

ISENSE +, ISENSE- —— 1.0 µAV

DD = 0V

SENSE+ Pin Bias

Current

ISENSE+_BIAS —34 — µAV

BUS = 24V,

VSENSE =100mV

Integrate state,

Power measurement

SENSE- Pin Bias

Current

ISENSE-_BIAS —— 1.0 µAV

BUS = 24V,

VSENSE = 0 to 100 mV

Integrate state

 2012-2016 Microchip Technology Inc. DS20005293D-page 5

PAC1921

DAC and OUT Amplifier Characteristics

Output Voltage

Swing

VOUT 03.0V

DD-0.15 V 3V FSR maximum

equation in effect when VDD

falls below 3.15V

Output Gain Error OUTGAIN_ERR ——±0.2%

Output Offset Error,

Referenced to

Output

OUTOFFSET_ ERR —±3 ±6 mV3V FSR

Output Settling Time tSETTLE — — 42 µs Output swing from 0V to

3.0V driving up to 50 pF

Output Load COUT — — 50 pF

Output Current Drive IOUT — — ±3 mA DC

OUT Short Circuit IOUT_SHORT — — 20 mA Device cannot be

damaged when OUT pin is

short circuited to GND

OUT Power Supply

Rejection Ratio, DC,

Referenced to Input

OUTPSRR_DC —69 — dB

Integration and Read Timing

Time to First

Communications

tINT_T — 14.25 20 ms Time after power-up before

ready to begin

communications and

measurement

Update Pulse tUPDATE 1.25 — 9.2 µs READ/INT pin low pulse width

range to guarantee transfer of

digital value to DAC and not

enter Read state

Read Pulse tREAD 9.8 — — µs READ/INT pin minimum low

pulse width to guarantee

entry into Read state

Read State Time for

Auto-Sleep State

tSLEEP 1.088 1.14 1.203 s

Transition From

Sleep State to Start

of Integration Period

tSLEEP_TO_INT — — 86 µs

Transition From

Read State to Start

of Integration Period

tREAD_TO_INT — — 30 µs

TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40°C to +85°C, VDD = 3V to 5.5V,

VBUS = 0V to 32V; typical values are at TA = +25°C, VDD = 3.3V, VBUS = 24V, VSENSE = (SENSE+ – SENSE-) = 0V

Characteristic Sym. Min. Typ. Max. Unit Conditions

PAC1921

DS20005293D-page 6  2012-2016 Microchip Technology Inc.

Digital I/O Pins (READ/INT, SMBus pins)

Output Low Voltage VOL — — 0.4 V Sinking 8 mA

Input High Voltage VIH 2.0 — — V

Input Low Voltage VIL —— 0.8 V

Leakage Current ILEAK -5 — 5 µA Powered or unpowered,

TA< +85°C maximum

TABLE 1-2: SMBUS MODULE SPECIFICATIONS

Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40°C to +85°C, VDD = 3V to 5.5V,

VBUS = 0V to 32V; typical values are at TA = +25°C, VDD = 3.3V, VBUS = 24V, VSENSE = (SENSE+ – SENSE-) = 0V

Characteristic Sym. Min. Typ. Max. Units Conditions

SMBus Interface

Input Capacitance CIN —410pF

SMBus Timing

Clock Frequency fSMB 10 — 400 kHz

Spike Suppression tSP 0 — 50 ns Pulse width of spikes that

must be suppressed by the

input filter

Bus Free Time

Stop to Start

tBUF 1.3 — — µs

Start Setup Time tSU:STA 0.6 — — µs

Start Hold Time tHD:STA 0.6 — — µs

Stop Setup Time tSU:STO 0.6 — — µs

Data Hold Time tHD:DAT 0 — — µs When transmitting to the

master

Data Hold Time tHD:DAT 0.3 — — µs When receiving from the

master

Data Setup Time tSU:DAT 0.6 — — µs

Clock Low Period tLOW 1.3 — — µs

Clock High Period tHIGH 0.6 — — µs

Clock/Data Fall Time tFALL — — 300 ns Minimum = 20 + 0.1 CLOAD ns

Clock/Data Rise Time tRISE — — 300 ns Minimum = 20 + 0.1 CLOAD ns

Capacitive Load CLOAD — — 400 pF Total per bus line

Time Out tTIMEOUT 25 — 35 ms Disabled by default

Idle Reset tIDLE_RESET 350 — — µs Disabled by default (see

Section 5.2 “SMBus

Timeout”)

TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40°C to +85°C, VDD = 3V to 5.5V,

VBUS = 0V to 32V; typical values are at TA = +25°C, VDD = 3.3V, VBUS = 24V, VSENSE = (SENSE+ – SENSE-) = 0V

Characteristic Sym. Min. Typ. Max. Unit Conditions

 2012-2016 Microchip Technology Inc. DS20005293D-page 7

PAC1921

FIGURE 1-1: SMBus Timing.

SMDATA

SMCLK

TLOW

TRISE

THIGH

TFALL

TBUF

THD:STA

PSS - Start Condition P - Stop Condition

THD:DAT TSU:DA

TSU:STA

THD:STA

TSU:STO

PAC1921

DS20005293D-page 8  2012-2016 Microchip Technology Inc.

NOTES:

 2012-2016 Microchip Technology Inc. DS20005293D-page 9

PAC1921

2.0 TYPICAL OPERATING CURVES

Note: Unless otherwise specified, maximum values are at TA = -40°C to 85°C, VDD = 3V to 5.5V, VBUS = 0V to 32V;

typical values are at TA = 25°C, VDD = 3.3V, VBUS = 24V, VSENSE = (SENSE+ - SENSE-) = 0V

FIGURE 2-1: Integrate State IDD vs. VDD

(VBUS = 24V, VSENSE = 0V).

FIGURE 2-2: Read State IDD vs. VDD

(VBUS = 24, VSENSE = 0V).

FIGURE 2-3: Sleep State IDD vs. VDD

(VBUS = 24, VSENSE = 0V).

FIGURE 2-4: ISENSE+ Input Current vs.

VSENSE - Integrate State.

FIGURE 2-5: ISENSE- Input Current vs.

VSENSE - Integrate State (VBUS = 24V, VSENSE =

100 mV).

FIGURE 2-6: ISENSE+ Input Current vs.

Common-Mode Voltage (VBUS) Integrate State

(VDD = 3.3V, VSENSE = 100 mV).

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

300

320

340

360

380

400

420

440

460

480

500

3.0 3.5 4.0 4.5 5.0

5.5

(μA)

VDD (V)

+85°C

+25°C

-40°C

200

220

240

260

280

300

320

340

360

380

400

3.0 3.5 4.0 4.5 5.0

5.5

(μA)

VDD (V)

+85° C

+25° C

-40° C

3.0 3.5 4.0 4.5 5.0

5.5

(μA)

VDD (V)

+85° C

+25° C

-40° C

020406080

100

SENSE+

(μA)

VSENSE FSR (%)

+85°C

+25°C

-40°C

0.00

0.10

0.20

0.30

0.40

0.50

020406080

100

SENSE

- (μA)

VSENSE FSR (%)

-40°C

+25°C

+85°C

0 4 8 1216202428

SENSE

+ (μA)

VBUS (V)

-40°C

+25°C

+85°C

VDD = 3.3V Crossover Point

PAC1921

DS20005293D-page 10  2012-2016 Microchip Technology Inc.

FIGURE 2-7: Current Sense Offset vs.

Temperature (VBUS = 24V, VSENSE = 100 mV).

FIGURE 2-8: Current Sense Gain Error

vs. Temperature (VBUS = 24V, VSENSE = 98 mV).

FIGURE 2-9: VBUS Voltage Measurement

Accuracy vs. Temperature (VDD = 3.3V, VSENSE

= 98 mV).

FIGURE 2-10: Current Sense Offset vs.

Temperature (VBUS = 32V, VSENSE = 98 mV).

FIGURE 2-11: VOUT vs. VSENSE (VDD =

3.3V, VBUS = 24V).

FIGURE 2-12: DAC Setting Time.

-30

-25

-20

-15

-10

-5

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-40 -25 -10 5 20 35 50 65 80

Input V

OFFSET

(μV)

Output V

OFFSET

(mV)

Temperature (°C)

Output Offset

Input Offset

-0.40

-0.30

-0.20

-0.10

0.00

0.10

0.20

0.30

0.40

-40 -15 10 35 60

Gain Error (%)

Temperature (°C)

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 4 8 12 16 20 24 28

BUS

Error (%)

VBUS (V)

-40°C

+25°C

+85°C

-0.20

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

0.20

-40 -15 10 35 60

Error (%)

Temperature (°C)

500

1,000

1,500

2,000

2,500

3,000

0.000 0.020 0.040 0.060 0.080

0.100

OUT

(mV)

VSENSE (V)

3V Range

2V Range

1.5V Range

1V Range

 2012-2016 Microchip Technology Inc. DS20005293D-page 11

PAC1921

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

3.1 Positive Power Supply Voltage

(VDD)

Power supply input Voltage ranging from 3.0 to 5.5 VDC.

3.2 VBUS/VSENSE+ Input/VSENSE– Input

(SENSE+/SENSE-)

These two pins form the differential input for measuring

voltage across a sense resistor in the application. The

positive input (Sense+) also acts as the input pin for

bus voltage.

3.3 Measurement Output Voltage (Out)

The OUT pin provides an analog voltage based on the

upper 10 bits of the latest calculation. This pin can be

programmed for 1.0, 1.5, 2.0 and 3.0V output swings.

3.4 Ground (GND)

System ground.

3.5 SMBus/I2C Address (ADDR_SEL)

Address selection for the SMBus Slave address, based

on the pull-down resistor.

3.6 COMM_SEL

Reserved for future use, connect to VDD for SMBus

operability.

3.7 Power States (READ/INT)

This pin controls the current state of the device, either

in the INTEGRATE state, or in the READ state.

3.8 SMBus/I2C Data (SM_DATA)

This is the bidirectional SMBus data pin. This pin is

open-drain and requires a pull-up resistor.

3.9 SMBus/I2C Clock (SM_CLK)

This is the SMBus clock pin. This pin is open-drain and

requires a pull-up resistor.

3.10 Exposed Thermal Pad (EP)

This pad should be connected to ground for noise

immunity.

TABLE 3-1: PIN DESCRIPTION

PAC1921

3x3 VDFN Symbol Type

(See Table 3-2)Function

DD Power Positive Power Supply Voltage

2 SENSE+ AIO40 VBUS/VSENSE+ input

3 SENSE– AIO40 VSENSE– input

4 OUT AIO5 Measurement Output Voltage

5 GND Power Ground

6 ADDR_SEL AIO2 Selects SMBus/I2C Address

7 RESERVED DI (5V) Reserved for future use. Connect to VDD for SMBus

functionality.

8READ/INT DI Controls power states

9 SM_DATA DIOD SM_DATA: SMBus/I2C Data - requires pull-up resistor

10 SM_CLK DI (5V) SM_CLK: SMBus/I2C Clock - requires pull-up resistor

11 EP - Not internally connected, but recommend grounding.

TABLE 3-2: PIN TYPES DESCRIPTION

Pin Type Description

Power This pin is used to power to the device.

AIO40 Analog Input/Output - this pin is used as

an I/O for analog signals. Maximum volt-

age is 40V.

AIO5 Analog Input Output - this pin is used as

an I/O for analog signals. Maximum volt-

age is 5V.

AIO2 Analog Input/Output - this pin is used as

an I/O for analog signals. Maximum volt-

age is 2V.

DI Digital Input - this pin is used for digital

inputs.

DIOD Digital Input/Output Open-Drain - this pin

is used for digital I/O and is open-drain.

PAC1921

DS20005293D-page 12  2012-2016 Microchip Technology Inc.

NOTES:

 2012-2016 Microchip Technology Inc. DS20005293D-page 13

PAC1921

4.0 GENERAL DESCRIPTION

The PAC1921 is a dedicated power monitoring device

with a configurable output: Power, Current, or Voltage.

The OUT pin supplies data for systems that cannot

tolerate the latencies inherent in embedded

communications buses. MCU-based systems

equipped with ADC inputs can sample the value

presented on the OUT pin for immediate use in thermal

or power control algorithms. Output values are also

available in a digital format via the SMBus interface.

The PAC1921 contains a high-side precision

current-sensing circuit and a precision bus voltage

measurement circuit. The current-sensing circuit

contains a differential amplifier that continuously

measures the voltage (VSENSE) developed across an

external sense resistor to represent the high-side

supply current. The full-scale range of VSENSE is from

0 mV to 100 mV. For power, the current and voltage

data is multiplied and accumulated, scaled with two

digital gain parameters, then applied to the OUT pin

through a 10-bit DAC and a gain output buffer for the

output FSR.

The integration time is variable depending on the

measurement type, the resolution setting (11-bit or

14-bit), the post filter settings and the number of

samples. A system diagram using the PAC1921 in

SMBus mode is shown in Figure 4-1.

FIGURE 4-1: PAC1921 System Diagram – SMBus Mode.

4.1 VDD Pin RC Filter

For optimal rejection of AC power supply noise, an RC

filter comprised of a 100Ω resistor and a 1 µF capacitor

is required on the 3.3V VDD pin.

4.2 OUT Pin RC Filter

To minimize the effect of circuit noise induced on the

OUT signal trace between the PAC1921 and the

receiving ADC, an RC filter comprised of a 100-150Ω

resistor and a 1 nF capacitor is recommended on the

OUT pin. This RC filter should ideally be placed near

the measurement ADC input.

4.3 Use Cases

The following examples illustrate application of the

PAC1921 device. Figure 4-2 demonstrates how to syn-

chronize the power measurement of multiple supply

rails using a single GPIO to control the READ/INT pins.

SENSE+ SENSE-

ADDR_SEL

3.0V to 5.5V

OUT

READ/INT

SMCLK

SM_DATA

MCU

PAC1921

GND

BUS

= 0V to 32V

SENSE

SM_CLK

GPIO

ADC

SM_DATA

BUS

Load

SENSE

3.0V to 5.5V

RESERVED

PAC1921

DS20005293D-page 14  2012-2016 Microchip Technology Inc.

FIGURE 4-2: Usage Model.

Figure 4-3 shows some of the math when filling the

registers with maximum values.

FIGURE 4-3: Maximum Value Example.

28V

DC-DC

MCU

ADC

GPIO

PWR_OUT1

PWR_OUT3

PWR_OUT2

READ# / INT

ADC

PAC

1921

SMCLK

SM_CLK

SMDATA

SM_DATA

VDD

Load 12V

DC-DC

PAC

1921

Load 3.3V

DC-DC

PAC

1921

Load

IMAX =10A

VSENSE =0.01Ω x 10A = 0.10V = 100 mV (max ILOAD)

VSENSE Result Registers (12h, 13h) = FF80h

VMAX =32V

VBUS =32V (max V

BUS)

VBUS Result Registers (10h, 11h) = FF80h

Power = 10A x 32V = 320W

VPOWER Result Registers (1Dh, 1Eh) = FF80h (Upper 10 bits of VPOWER Result)

OUT Pin (3V FSR) = VPOWER Result 65472 x OUT Pin FSR

= FF80h/65472 x 3.0V

= 2.997V

Calculated Power using OUT pin = OUT Pin/OUT Pin FSR x IMAX x VMAX

= 2.997/3.0 x 10 x 32

=319.68W

SENSE+ SENSE-

ADDR_SEL

3.0V to 5.5V

OUT

READ/INT

SMCLK

SM_DATA

MCU

PAC1921

VDD

GND

VBUS = 0V to 32V RSENSE = 0.01Ω

SM_CLK

GPIO

ADC

SM_DATA

VBUS

32V

IBUS

10A

ISENSE

3.0V to 5.5V

RESERVED

 2012-2016 Microchip Technology Inc. DS20005293D-page 15

PAC1921

Figure 4-4 illustrates dynamic operating conditions by

changing the DI_GAIN value.

FIGURE 4-4: DI_GAIN Effects on OUT Voltage.

In this example, the load current decreases from 40A to

less than 1A over time. The user is notified of a change

through the change in the OUT voltage. The DI_GAIN

value is then adjusted to center the measurements

again. In this example, the changes in current were fac-

tors of four apart. Using the DI_GAIN parameter to

adjust the Full Scale value, the analog output maintains

good resolution throughout the entire range.

IMAX =50A

VMAX =32V

PMAX = 1600W

OUT FSR = 3V

VBUS =24V

OUT Pin

VPOWER Result

represents

READ/INT Pin

ILOAD

9973h

(265Ch without DI_GAIN)

240W

ILOAD =40A

ILOAD =10A

ILOAD = 2.5A

ILOAD = 0.625A

DI_GAIN

9973h

960W

9973h

(997h without DI_GAIN)

60W

9973h

(265h without DI_GAIN)

15W

00h (1X) 02h (4X) 04h (16X) 06h (64X)

1.8V 1.8V 1.8V 1.8V

SENSE+ SENSE-

ADDR_SEL

3.0V to 5.5V

OUT

READ/INT

SMCLK

SM_DATA

MCU

PAC1921

VDD

GND

VBUS = 0V to 32V RSENSE = 0.02Ω

SM_CLK

GPIO

ADC

SM_DATA

VBUS

24V

IBUS

(X)A

ISENSE

3.0V to 5.5V

RESERVED

PAC1921

DS20005293D-page 16  2012-2016 Microchip Technology Inc.

4.4 Power States

The PAC1921 has three power states, as described in

the following paragraphs.

4.4.1 INTEGRATE STATE

In the Integrate state, the device is fully active and inte-

grating in one of two modes: pin-controlled or free-run

(see Section 4.7 “Integration”). When the READ/INT

pin is driven high, the device is in the Integrate state.

Alternatively, when using SMBus, the device can be

placed in the Integrate state by enabling the pin override

(READ/INT_OVR = 1) and setting the INT_EN bit to ‘1’.

4.4.2 READ STATE

The Read state is a lower-power state. When the

READ/INT pin is driven low for at least tREAD time (see

Section 1.0 “Electrical Characteristics”), the device

is in the Read state. When using SMBus, the device

can also be placed in the Read state by enabling the

pin override (READ/INT_OVR = 1) and setting the

INT_EN bit to ‘0’. The Read state terminates integra-

tion, starts the internal sleep timer, transfers the

selected measurement to the output DAC, and places

the device in a low-power state. The OUT pin will output

the latest measurement voltage in the voltage range

defined by VOUT until the next time the device enters

the Read state (next falling edge of READ/INT, or

INT_EN set to ‘1’ and then back to ‘0’) or until the sleep

timer expires and the device enters the Sleep state.

4.4.3 SLEEP STATE

The Sleep state is the lowest-power state. While in this

state, the device will draw a supply current of ISLEEP

from the VDD pin. By default, the device enters the

Sleep state automatically when the READ/INT pin (or

INT_EN bit if READ/INT_OVR = 1) is held low for longer

than tSLEEP

. In SMBus mode, the device can also be put

in the Sleep state by setting the SLEEP bit (see

device will reset all measurement registers and turn off

unnecessary internal biasing and drive circuits to

reduce quiescent current to ISLEEP

. The device will stay

in the Sleep state until it is placed in the Integrate state.

The device will transition from Sleep to the start of inte-

gration in tSLEEP_TO_INT and start accumulating current

and voltage information again. An example of the timing

required to enter the Sleep state is shown in Figure 4-5.

FIGURE 4-5: Sleep State Timing.

4.5 Measurement Modes

The PAC1921 can measure the source-side voltage,

VBUS, and the voltage across an external current sense

resistor, VSENSE. The device can be configured to per-

form one of three sets of calculations: Power (see

Section 4.5.1 “Power Measurement”), VSENSE (see

Section 4.5.2 “VSENSE Measurement”) or VBUS (see

Section 4.5.3 “VBUS Measurement”). The results of

these digital calculations are applied to the analog OUT

pin as well as stored in registers available via the com-

munications bus. Figure 4-6 shows the data flow.

Sleep

State

tSETTLE

OUT Pin

Internal

Intergrator

READ/INT

READ

tSLEEP

tSLEEP_TO_INT

 2012-2016 Microchip Technology Inc. DS20005293D-page 17

PAC1921

FIGURE 4-6: PAC1921 Data Flow.

4.5.1 POWER MEASUREMENT

VBUS and VSENSE are sampled and multiplied during

the integration period, resulting in the sum of power for

all samples. The power full-scale range is defined in

Equation 4-1. The instantaneous values are summed

over the integration period. The summed value is then

divided by the number of samples, and stored in the

VPOWER Results registers.

The VPOWER Results registers result can be converted

directly to watts using the conversion described in

Equation 4-2 for 1 LSB. This result is also sent to the

DAC which drives the proportional voltage output on

the OUT pin, if it is the selected output.

EQUATION 4-1: POWER FSR

CALCULATION

Note: Registers not required for the selected measurement type are not populated.

26-bit VSUM Accumulator

Registers

10-bit VBUS Result

Registers (10 MSBs)

10-bit VSENSE Result

Registers (10 MSBs)

10-bit DAC

DV_GAIN

VBUS Average

(divide by # samples)

10-bit Power Result

Registers (10 MSBs)

26-bit ISUM Accumulator

Registers

I V

40-bit PSUM Accumulator

Registers

DI_GAIN X DV_GAIN

VPOWER Average

(divide by # samples)

DI_GAIN

VSENSE Average

(divide by # samples)

OUT Pin

Measurement

Type = Power?

Measurement

Type = VSENSE?

Measurement

Type = VBUS?

Yes Yes Yes

Digital Multiply

PowerFSR 0.1VR



DI_GAIN

-----------------------------





32V

DV_GAIN

---------------------------







Where:

0.1V = Maximum VSENSE voltage input

RΩ=R

SENSE resistor value

DI_GAIN = Digital current gain

32V = Maximum device bus voltage input

DV_GAIN = Digital voltage gain

PAC1921

DS20005293D-page 18  2012-2016 Microchip Technology Inc.

EQUATION 4-2: POWER LSB WEIGHT

4.5.2 VSENSE MEASUREMENT

When VSENSE is selected as the measurement type,

free-run integration is used (see Section 4.7.3

“Free-Run Integration”). The VSENSE voltage is digi-

tized and summed in the ISUM Accumulator Registers,

The average is then taken at the end of the integration

period. Finally, digital gain is applied by adjusting the

parameter DI_GAIN. The upper 10-bit resultant value

represents the average VSENSE voltage measured and

is used to drive the DAC. The PAC1921 should be kept

in the Integrate state for continuous output in this

mode. The value of one LSB in amps can be calculated

according to Equation 4-3.

EQUATION 4-3: VSENSE LSB VALUE IN

AMPS

The value of one LSB in volts can be calculated accord-

ing to Equation 4-4.

EQUATION 4-4: VSENSE LSB VALUE IN

VOLTS

4.5.3 VBUS MEASUREMENT

When VBUS is selected as the measurement type,

free-run integration is used (see Section 4.7.3

“Free-Run Integration”). The VBUS voltage is digi-

tized and summed in the VSUM Accumulator Registers.

The average is taken at the end of the integration

period and digital gain is applied by adjusting the

parameter DV_GAIN. The upper 10-bit resultant value

represents the average VBUS voltage measured and is

used to drive the DAC. The PAC1921 should be kept in

the Integrate state for continuous output in this mode.

The value of one LSB in volts can be calculated accord-

ing to Equation 4-5.

EQUATION 4-5: VBUS LSB VALUE IN

VOLTS

4.6 OUT Pin and Measurement Type

The OUT pin is driven by a buffered 10-bit DAC. The

OUT pin signal is typically sent to an MCU with ADC

inputs to supply data for algorithms that cannot tolerate

the latencies inherent in embedded communications

buses. After a DAC update, the OUT pin can be polled

after tSETTLE. The output voltage can also be

expressed as a result of the DAC, as shown in

Equation 4-6.

EQUATION 4-6: OUT PIN VALUE

1LSB

0.1V



DI GAIN



-------------------------------------- 32V

DV_GAIN

---------------------------



1023 26



------------------------------------------------------------------------=

Where:

0.1V = Maximum VSENSE

voltage input

RΩ=R

SENSE resistor value

DI_GAIN = Digital current gain

32V/DV_GAIN = Maximum device bus

voltage input

DV_GAIN = Digital voltage gain

1LSB

0.1V



DI_GAIN



----------------------------------------

1023 26



----------------------------------------=

Where:

0.1V = Maximum VSENSE voltage input

RΩ=R

SENSE resistor value

DI_GAIN = Digital current gain

1023 x 26= FSR x scale offset

1LSB

0.1V

DI_GAIN

-------------------------

1023 26



-------------------------=

Where:

0.1V = Maximum VSENSE voltage input

DI_GAIN = Digital current gain

1023 x 26= FSR x scale offset

1LSB

32V

DV_GAIN

---------------------------

1023 26



---------------------------=

Where:

1LSB = LSB value in volts

32/DV_GAIN = Maximum voltage

1023 x 26= FSR shifted 6 bits

OUT DAC

1023 26



----------------------- OUTFSR



Where:

OUT = Output on OUT pin

DAC = value of the selected

measurement result registers

1023 x 26= FSR x scale offset

OUTFSR = Output FSR

 2012-2016 Microchip Technology Inc. DS20005293D-page 19

PAC1921

The OUT Pin can represent Power, Voltage or Current.

This measurement type is selected by the MXSL<1:0>

bits shown in Ta bl e 4- 1.

To change the MUX_SEL parameter, see Section 4.7.8

“Changing Integration Parameter Settings”.

The OUT buffer FSR is configurable. The OUT FSR is

set by the OFSR<1:0> bits in Control Register 02h, as

shown in Ta b l e 4 - 2 .

4.7 Integration

The PAC1921 has two Integrate state (see

Section 4.4.1 “Integrate State”) operating modes:

pin-controlled and free-run. In pin-controlled mode, the

measurement type is Power. In free-run mode, the

measurement type is Power by default and can be

changed in SMBus mode to Voltage or Current.

If pin-controlled integration mode is selected, the OUT

pin will update to the latest Power value when the

PAC1921 is placed in the Read state or when the

READ/INT pin is held low for tUPDATE. If free-run is cho-

sen, the OUT pin will update at the conclusion of each

integration period. The integration mode is selected by

the MXSL<1:0> bits (see Table 4-1).

4.7.1 PIN-CONTROLLED INTEGRATION

In pin-controlled integration mode, the integration

period is the time the PAC1921 is in the Integrate state

less the state transition time, as shown in Figure 4-7.

The power integration period can be any time between

~0.9 ms and ~1s with 11-bit resolution and between

~2.7 ms and ~2.9s with 14-bit resolution. When the

PAC1921 is placed in the Read state, measurement is

stopped, calculations are made, and the result is

latched into the DAC.

FIGURE 4-7: Pin-Controlled Integration

Period.

To obtain an update to the DAC without entering the Read

state, the READ/INT pin can be held low for tUPDATE. This

eliminates the tREAD_TO_INT delay at the start of the next

integration period which occurs when transitioning from

Read to Integrate, as shown in Figure 4-8.

FIGURE 4-8: Pin-Controlled

Measurement Time.

4.7.2 MAXIMUM SAMPLES

The number of samples is limited to 2048. When the

Samples Registers reach their maximum value (2048),

integration stops, the calculations are performed, the

registers are updated and the results are sent to the

OUT pin.

TABLE 4-1: MUX_SEL MULTIPLEXER

DECODE

MXSL<1:0>

Selected Output

VPOWER pin-controlled

(default)

01VSENSE free-run

10VBUS free-run

11VPOWER free-run

TABLE 4-2: OFSR DECODE - SMBUS

MODE

OFSR<1:0>

FSR for OUT Pin

000 to 3V (default)

01 0 to 2V

10 0 to 1.5V

11 0 to 1V

TABLE 4-3: INT_SEL PIN DECODE

INT_SEL Pin Voltage Integration Mode

GND Pin-controlled

VDD Free-run

Integrate State

(Pin-Controlled Mode)

Read State

Integration Period

Samples < 2048

DAC

Updated

READ_TO_INT

READ/INT Pin

DAC Updated

tREAD_TO_INT

tSLEEP_TO_INT

Integration

Period

tUPDATE

Integration

Period

PAC1921

DS20005293D-page 20  2012-2016 Microchip Technology Inc.

4.7.3 FREE-RUN INTEGRATION

In free-run integration mode, the integration period is

controlled by the selected measurement type, resolu-

tion, filtering, and number of samples (see

Section 4.7.4 “ADC Resolution, Filtering and Sam-

pling”). The number of samples is controlled by the

SMPL bits in the configuration register. The legend for

these bits is shown in Table 4-4.

After each integration period is completed, the output

value is calculated and the result is latched into the

DAC. As long as the device is still in the Integrate state,

the next integration period starts after the calculations

are complete. Integration is disabled whenever the

device enters the Read state.

When the device enters the Read state during an inte-

gration period, that data is discarded, as shown in

Figure 4-9.

FIGURE 4-9: Incomplete Integration Time.

4.7.4 ADC RESOLUTION, FILTERING

AND SAMPLING

ADC resolution can be specified at 11 or 14 bits. In

SMBus mode, the resolution is set independently for

VSENSE and VBUS by using the I_RES and V_RES bits

(see Register 6-1).

ADC post filtering improves signal quality and

increases conversion time by 50%. In SMBus mode,

ADC post filtering can be enabled or disabled by using

the VSFEN and VBFEN bits (see Register 6-2).

When Power is selected as the OUT measurement

type, the bus voltage and sense resistor voltage are

sampled an equal number of times during the integra-

tion period in a round-robin scheme (e.g., a VBUS mea-

surement is taken and then a VSENSE measurement is

taken for each power sample). When VBUS or VSENSE

is selected as the OUT measurement type, only the

selected channel is sampled and digitized.

In free-run integration, the number of samples is select-

able. In free-run SMBus mode, the number of samples

is set by the SMPL<3:0> bits (see Register 6-2).

The free-run integration period is determined by the

selected measurement type, number of samples,

resolution and filtering as shown in Ta bl e 4- 5.

11-bit resolution is recommended if the fastest integra-

tion time is required. 14-bit resolution will provide more

accurate and highly averaged measurements.

TABLE 4-4: SAMPLES IN FREE-RUN

MODE

SMPL<3:0>

Number of Samples

3210

0000 1 (default)

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 512

1010 1024

1011 2048

1100 2048

1101 2048

1110 2048

1111 2048

Integrate State

(Free-Run Mode)

Read State

Integration

Period

Integration

Period

Integration

Period

Samples Samples Samples

DAC

Updated

DAC

Updated

DAC

Updated

tREAD_TO_INT

Samples

Discarded

TABLE 4-5: FREE RUN INTEGRATION

PERIODS

Samples

Integration Period

Power measurement

Integration

Period

VSENSE or VBUS

Measurement

14-bit ADC

Post Filter On

11-Bit ADC

Post Filter Off

Mixed ADC

Post Filter On

14-bit ADC

Post Filters On

11-Bit ADC

Post Filters Off

1 2.72 ms 0.93 ms 2.1 ms 1.41 ms 0.51 ms

2 4.05 ms 1.46 ms 3.1 ms 2.02 ms 0.72 ms

4 6.79 ms 2.41 ms 5.1 ms 3.43 ms 1.24 ms

8 12.2 ms 4.32 ms 9.2 ms 6.06 ms 2.08 ms

16 23 ms 8.05 ms 17.5 ms 11.5 ms 3.95 ms

32 46 ms 16.1 ms 34.9 ms 22.9 ms 7.89 ms

64 92 ms 32.1 ms 70 ms 45.7 ms 15.7 ms

128 184 ms 64.2 ms 139 ms 91.3 ms 31.4 ms

256 368 ms 128.3 ms 278 ms 183 ms 62.7 ms

512 736 ms 257 ms 556 ms 365 ms 126 ms

1024 1471 ms 513 ms 1112 ms 730 ms 251 ms

2048 2941ms 1026 ms 2223 ms 1460 ms 502 ms

 2012-2016 Microchip Technology Inc. DS20005293D-page 21

PAC1921

4.7.5 DI_GAIN SETTING

The DI_GAIN parameter acts as a digital multiplier to

control the effective current gain, as described in

Equation 4-3. DI_GAIN 1X is the setting for the

full-scale range. DI_GAIN can be increased when the

system is designed for a lower VSENSE range. It can

also be used to provide a larger signal when the system

is in a low-power mode.

DI_GAIN is set in the Gain Configuration Register (see

4.7.6 DI_GAIN OVERFLOW

If DI_GAIN is set too high for the input magnitude when

VSENSE or VPOWER is selected as the measurement

type, it will cause an overflow in the results registers

(PSUM_GAINED and IAVG). To provide an indication that

the selected gain is too high, the following occurs:

Overflow status register 1Ch bit 2 (VSOV) is set to 1b

and bit 0 (VPOV) is set to 1b if the power calculation

overflowed, too.

VSENSE Result Registers are set to the maximum value

(12h is set to FFh and 13h is set to C0h).

VPOWER Result Registers are set to the maximum

value (1Dh is set to FFh and 1Eh is set to C0h).

The values in the ISUM Accumulator Registers and

PSUM Accumulator Registers will be accurate. In SMBus

mode, change the DI_GAIN selection (see Register 6-1),

set the RDAC bit (see Register 6-3) and check the results

until an effective current gain is selected.

4.7.7 DV_GAIN SETTING

The DV_GAIN parameter acts as a digital multiplier to

control the effective bus voltage gain. DV_GAIN 1X is

the setting for the full-scale voltage range. DV_GAIN

can be increased when the system is designed for a

lower VBUS range. It can also be used to provide a

larger signal when the system is in a low-power mode.

DV_GAIN is set in the Gain Configuration Register (see

4.7.7.1 DV_GAIN Overflow

If DV_GAIN is too high for the range being measured

when VBUS or VPOWER is selected as the measurement

type, it will cause an overflow in the results registers. To

provide an indication that the selected gain is too high,

the following occurs:

Overflow status register 1Ch bit 1 (VBOV) is set to 1b

and bit 0 (VPOV) is set to 1b if the power calculation

overflowed, too.

VBUS Result Register 10h is set to FFh and VBUS

Result Register 11h is set to C0h.

VPOWER Result Register 1Dh is set to FFh and VPOWER

Result Register 1Eh is set to C0h.

The values in the VSUM Accumulator Registers and

PSUM Accumulator Registers will be accurate. In

SMBus mode, change the DV_GAIN selection in

measured. Set the RDAC bit in the same register and

check the results.

TABLE 4-6: DI_GAIN DECODE

DI_GAIN<2:0> DI_GAIN

Multiplier

Effective

VSENSE Range

210

000 1X

(default)

0 to 100 mV

(default)

001 2X 0 to 50 mV

010 4X 0 to 25 mV

011 8X 0 to 12.5 mV

100 16X 0 to 6.25 mV

101 32X 0 to 3.125 mV

110 64X 0 to 1.56 mV

111 128X 0 to 0.78 mV

TABLE 4-7: DV_GAIN DECODE

DV_GAIN<2:0> DV_GAIN

Multiplier

Effective

VBUS Range

210

000 1X

(default)

0 to 32V

(default)

001 2X 0 to 16V

010 4X 0 to 8V

011 8X 0 to 4V

100 16X 0 to 2V

101 32X 0 to 1V

110 32X 0 to 1V

111 32X 0 to 1V

PAC1921

DS20005293D-page 22  2012-2016 Microchip Technology Inc.

4.7.8 CHANGING INTEGRATION

PARAMETER SETTINGS

The integration parameter settings I_RES, V_RES,

SMPL, VSFEN and VBFEN can be changed by first

putting the device in the Read state (see Section 4.4

“Power States”), then changing the applicable

registers. If one of these parameters is changed while

the device is in the Integrate state, the change will not

take effect until after the device has been placed into

the Read state and then back into the Integrate state.

DI_GAIN and DV_GAIN can also be updated in the

Read state; however, the effects can be seen while in

Read by setting the RDAC bit to recalculate the last

measurement using the new gain settings.

If the integration mode is changed from VPOWER

pin-controlled while the device is in the Integrate state,

the device will terminate the Power measurement,

update the OUT pin and then switch to the new

measurement/integration mode. If the integration mode

is changed from VPOWER free-run, VSENSE or VBUS

while the device is in the Integrate state, the device will

complete the integration period, update the OUT pin

and then switch to the new measurement/integration

mode.

 2012-2016 Microchip Technology Inc. DS20005293D-page 23

PAC1921

5.0 COMMUNICATIONS

PROTOCOL

The PAC1921 communicates with a host controller,

such as an PIC MCU, through the SMBus. The SMBus

is a two-wire serial communication protocol between a

computer host and its peripheral devices. A detailed

timing diagram is shown in Figure 1-1.

For the first 15 ms after power-up, the device may not

respond to SMBus communications.

5.1 SMBus Control Bits

The interaction between clock and data creates special

function bits within the data stream.

5.1.1 SMBUS START BIT

The SMBus Start bit is defined as a transition of the

SMBus Data line from a logic ‘1’ state to a logic ‘0’ state

while the SMBus Clock line is in a logic ‘1’ state.

5.1.2 SMBUS ADDRESS AND RD/WR BIT

The SMBus Address Byte consists of the 7-bit client

address followed by the RD/WR indicator bit. If this

RD/WR bit is a logic ‘0’, the SMBus Host is writing data

to the client device. If this RD/WR bit is a logic ‘1’, the

SMBus Host is reading data from the client device. The

PAC1921 SMBus address is determined by a single

pull-down resistor connected between ground and the

ADDR_SEL pin as shown in Ta bl e 5- 1.

5.1.3 SMBUS DATA BYTES

All SMBus Data bytes are sent most significant bit first

and composed of eight bits of information.

5.1.4 SMBUS ACK AND NACK BITS

The SMBus client will acknowledge all data bytes that

it receives. This is done by the client device pulling the

SMBus data line low after the 8th bit of each byte that

is transmitted.

The host will NACK (not acknowledge) the last data byte

to be received from the client by holding the SMBus data

line high after the 8th data bit has been sent.

5.1.5 SMBUS STOP BIT

The SMBus Stop bit is defined as a transition of the

SMBus Data line from a logic ‘0’ state to a logic ‘1’ state

while the SMBus clock line is in a logic ‘1’ state. When the

device detects an SMBus Stop bit and it has been

communicating with the SMBus protocol, it will reset its

client interface and prepare to receive further

communications.

5.2 SMBus Timeout

The PAC1921 supports SMBus Timeout. If the clock

line is held low for longer than tTIMEOUT

, the device will

reset its SMBus protocol. This function can be enabled

by setting the TIMEOUT bit (see Register 6-3).

5.3 SMBus and I2C Compatibility

The PAC1921 is compatible with SMBus and I2C. The

major differences between SMBus and I2C devices are

highlighted here. For more information, refer to the

SMBus 2.0 and I2C specifications. For information on

using the PAC1921 in an I2C system, refer to AN 14.0

– “Microchip Dedicated Slave Devices in I2C Systems”

(DS00001853).

• PAC1921 supports I2C fast mode at 400 kHz. This

covers the SMBus max time of 100 kHz.

• Minimum frequency for SMBus communications

is 10 kHz.

• The SMBus client protocol will reset if the clock is

held at a logic ‘0’ for longer than 30 ms. This time-

out functionality is disabled by default in the

PAC1921 and can be enabled by writing to the

TIMEOUT bit. I2C does not have a time out.

•I

2C devices do not support the Alert Response

Address functionality (which is optional for SMBus).

•I

2C devices support Block Read and Block Write

differently. I2C protocol allows for an unlimited

number of bytes to be sent in either direction. The

SMBus protocol requires that an additional data

byte indicating number of bytes to read/write is

transmitted. The PAC1921 supports I2C format-

ting only.

TABLE 5-1: ADDR_SEL RESISTOR

SETTING

Resistor (5%) SMBus Address

01001_100(r/w)

120 1001_101(r/w)

220 1001_110(r/w)

330 1001_111(r/w)

470 1001_000(r/w)

620 1001_001(r/w)

820 1001_010(r/w)

1000 1001_011(r/w)

1300 0101_000(r/w)

1800 0101_001(r/w)

2200 0101_010(r/w)

3000 0101_011(r/w)

4300 0101_100(r/w)

6800 0101_101(r/w)

12000 0101_110(r/w)

open 0011_000((r/w)

PAC1921

DS20005293D-page 24  2012-2016 Microchip Technology Inc.

Attempting to communicate with the PAC1921 SMBus

interface with an invalid slave address or invalid proto-

col will result in no response from the device and will

not affect its register contents. Stretching of the SMCLK

signal is supported, provided other devices on the

SMBus control the timing.

5.4 SMBus Protocols

The device supports Send Byte, Read Byte, Write Byte,

Receive Byte, and the Alert Response Address as valid

protocols as shown below.

All of the below protocols use the convention in

Table 5-2.

5.4.1 WRITE BYTE

The Write Byte is used to write one byte of data to the

registers, as shown in Table 5-3.

5.4.2 READ BYTE

The Read Byte protocol is used to read one byte of data

from the registers as shown in Table 5 -4 .

5.4.3 SEND BYTE

The Send Byte protocol is used to set the internal

address register pointer to the correct address location.

No data is transferred during the Send Byte protocol as

shown in Ta b l e 5 - 5 .

TABLE 5-2: PROTOCOL FORMAT

Data Sent to Device Data Sent to the Host

# of bits sent # of bits sent

TABLE 5-3: WRITE BYTE PROTOCOL

START Slave Address WR ACK Register Address ACK Register Data ACK STOP

1  0 YYYY_YYY 0 0 XXh 0 XXh 0 0  1

TABLE 5-4: READ BYTE PROTOCOL

START Slave

Address WR ACK Register

Address ACK START Slave

Address RD ACK Register

Data NACK STOP

1 0 YYYY_YYY 0 0 XXh 0 1  0 YYYY_YYY 1 0 XXh 1 0  1

TABLE 5-5: SEND BYTE PROTOCOL

START Slave Address WR ACK Register Address ACK STOP

1  0 YYYY_YYY 0 0 XXh 0 0  1

 2012-2016 Microchip Technology Inc. DS20005293D-page 25

PAC1921

5.4.4 RECEIVE BYTE

The Receive Byte protocol is used to read data from a

known to be at the right location (e.g. set via Send

Byte). This is used for consecutive reads of the same

5.5 I2C Protocols

The PAC1921 supports I2C Block Read and Block Write.

The protocols listed below use the convention in

Table 5-2.

5.5.1 BLOCK WRITE

The Block Write protocol is used to write multiple data

bytes to a group of contiguous registers, as shown in

Table 5-7.

5.5.2 BLOCK READ

The Block Read protocol is used to read multiple data

bytes from a group of contiguous registers, as shown in

Table 5-8.

TABLE 5-6: RECEIVE BYTE PROTOCOL

START Slave Address RD ACK Register Data NACK STOP

1  0 YYYY_YYY 1 0 XXh 1 0  1

TABLE 5-7: BLOCK WRITE PROTOCOL

START Slave Address WR ACK Register

Address ACK Register Data ACK

1  0 YYYY_YYY 0 0 XXh 0 XXh 0

XXh 0 XXh 0 XXh 0 0  1

TABLE 5-8: BLOCK READ PROTOCOL

START Slave

Address WR ACK Register

Address ACK START Slave

Address RD ACK Register

Data

1  0 YYYY_YYY 0 0 XXh 0 1  0 YYYY_YYY 1 0 XXh

ACK Register

Data ACK Register

Data NACK STOP

0 XXh 0 XXh 0 0 XXh 1 0  1

PAC1921

DS20005293D-page 26  2012-2016 Microchip Technology Inc.

NOTES:

 2012-2016 Microchip Technology Inc. DS20005293D-page 27

PAC1921

6.0 REGISTER DESCRIPTION

The registers shown in Table 6-1 are accessible

through the SMBus. In the individual register tables that

follow, an entry of ‘—’ indicates that the bit is not used

and will always read ‘0’.

TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER

Address

Value

00h Gain

Configuration

I_RES V_RES DIGN2 DIGN1 DIGN0 DVGN2 DVGN1 DVGN0 00h

01h Integration

Configuration

SMPL3 SMPL2 SMPL1 SMPL0 VSFEN VBFEN RIOV INTEN 0Ch

02h Control MXSL1 MXSL0 OFSR1 OFSR0 TOUT SLEEP SLPOV RDAC 00h

10h VBUS Result

High Byte

VBR9 VBR8 VBR7 VBR6 VBR5 VBR4 VBR3 VBR2 00h

11h VBUS Result

Low Byte

VBR1 VBR0 — — — — — — 00h

12h VSENSE Result

High Byte

VSR9 VSR8 VSR7 VSR6 VSR5 VSR4 VSR3 VSR2 00h

13h VSENSE Result

Low Byte

VSR1 VSR0 — — — — — — 00h

14h VSUM Accumulator

High Byte

VSM24 VSM23 VSM22 VSM21 VSM20 VSM19 VSM18 VSM17 00h

15h VSUM Accumulator

Middle High Byte

VSM16 VSM15 VSM14 VSM13 VSM12 VSM11 VSM10 VSM9 00h

16h VSUM Accumulator

Middle Low Byte

VSM8 VSM7 VSM6 VSM5 VSM4 VSM3 VSM2 VSM1 00h

17h VSUM Accumulator

Low Byte

VSM0 — — — — — — — 00h

18h ISUM Accumulator

High Byte

ISM24 ISM23 ISM22 ISM21 ISM20 ISM19 ISM18 ISM17 00h

19h ISUM Accumulator

Mid-high Byte

ISM16 ISM15 ISM14 ISM13 ISM12 ISM11 ISM10 ISM9 00h

1Ah ISUM Accumulator

Mid-low Byte

ISM8 ISM7 ISM6 ISM5 ISM4 ISM3 ISM2 ISM1 00h

1Bh ISUM Accumulator

Low Byte

ISM0 — — — — — — — 00h

1Ch Overflow Status — — — — — VSOV VBOV VPOV 00h

1Dh VPOWER Result High

Byte

VPR9 VPR8 VPR7 VPR6 VPR5 VPR4 VPR3 VPR2 00h

1Eh VPOWER Result

Low Byte

VPR1 VPR0 — — — — — — 00h

21h Samples High Byte SMP11 SMP10 SMP9 SMP8 SMP7 SMP6 SMP5 SMP4 00h

22h Samples Low Byte SMP3 SMP2 SMP1 SMP0 — — — — 00h

23h PSUM Accumulator

High Byte

PSM38 PSM37 PSM36 PSM35 PSM34 PSM33 PSM32 PSM31 00h

24h PSUM Accumulator

Middle-High Byte

PSM30 PSM29 PSM28 PSM27 PSM26 PSM25 PSM24 PSM23 00h

PAC1921

DS20005293D-page 28  2012-2016 Microchip Technology Inc.

6.1 Read Multiple Data Bytes

Data represented by multiple byte data registers are

guaranteed to be synchronized and stable in the Read

and Sleep states after transitioning from the Integrate

state and waiting for tSETTLE time (see Tab le 1 -2 ).

During the Integrate state, the data bytes will be chang-

ing dynamically.

25h PSUM Accumulator

Middle Byte

PSM22 PSM21 PSM20 PSM19 PSM18 PSM17 PSM16 PSM15 00h

26h PSUM Accumulator

Middle-Low Byte

PSM14 PSM13 PSM12 PSM11 PSM10 PSM9 PSM8 PSM7 00h

27h PSUM Accumulator

Low Byte

PSM6 PSM5 PSM4 PSM3 PSM2 PSM1 PSM0 — 00h

FDh Product ID PID7 PID6 PID5 PID4 PID3 PID2 PID1 PID0 5Bh

FEh Manufacturer ID MID7 MID6 MID5 MID4 MID3 MID2 MID1 MID0 5Dh

FFh Revision RID7 RID6 RID5 RID4 RID3 RID2 RID1 RID0 82h

TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED)

Address

Value

 2012-2016 Microchip Technology Inc. DS20005293D-page 29

PAC1921

6.2 Detailed Register Description

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

I_RES V_RES DI_GAIN<2:0> DV_GAIN<2:0>

bit 7 bit 0

Legend:

R = Read bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 I_RES: Sets the VSENSE ADC measurement resolution

1 = VSENSE ADC measurement resolution is 11-bit

0 = VSENSE ADC measurement resolution is 14-bit

bit 6 V_RES: Sets the VBUS ADC measurement resolution

1 = VBUS ADC measurement resolution is 11-bit

0 = VBUS ADC measurement resolution is 14-bit

bit 5-3 DI_GAIN<2:0>: Selects the digital current gain,

000b = 1x

001b = 2x

010b = 4x

011b = 8x

100b = 16x

101b = 32x

110b = 64x

111b = 128x

bit 2-0 DV_GAIN<2:0>: Selects the digital bus voltage gain.

000b = 1x

001b = 2x

010b = 4x

011b = 8x

100b = 16x

101b = 32x

110b = 32x

111b = 32x

PAC1921

DS20005293D-page 30  2012-2016 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0

SMPL<3:0> VSFEN VBFEN RIOV INTEN

bit 7 bit 0

Legend:

RC = Read-then-clear bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 SMPL<3:0>: Controls the number of samples of the selected measurement type.

0000b = 1

0001b = 2

0010b = 4

0011b = 8

0100b = 16

0101b = 32

0110b = 64

0111b = 128

1000b = 256

1001b = 512

1010b = 1024

1011b = 2048

1100b = 2048

1101b = 2048

1110b = 2048

1111b = 2048

bit 3 VSFEN: enables the ADC post filter for VSENSE samples. When the filter is enabled, conversion time is

increased by 50%

1 = Filter enabled

0 = Filter disabled

bit 2 VBFEN: enables the ADC post filter for VBUS samples. When the filter is enabled, conversion time is

increased by 50%

1 = Filter enabled

0 = Filter disabled

bit 1 RIOV: enables the INT_EN bit to override the READ/INT pin.

1 = Override enabled

0 = Override not enabled

bit 0 INTEN: forces the device into integrate mode, overriding the READ/INT pin.

1 = Forced Integrate mode

0 = Forced Read State

 2012-2016 Microchip Technology Inc. DS20005293D-page 31

PAC1921

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

MXSL<1:0> OFSR<1:0> TOUT SLEEP SLPOV RDAC

bit 7 bit 0

Legend:

RC = Read-then-clear bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 MXSL<1:0>: Selects which digital value is used for input to the OUT DAC and the integration mode

00 = VPOWER pin-controlled (default)

01 = VSENSE free-run

10 = VBUS free-run

11 = VPOWER free-run

bit 5-4 OFSR<1:0>: Determines the OUT pin full-scale range

00b = 3V FSR

01b = 2V FSR

10b = 1.5V FSR

11b = 1.0V FSR

bit 3 TOUT: Enables the time out and idle reset functionality of the communications protocol (see

Section 5.2 “SMBus Timeout”).

1 = Time out enabled

0 = Time out disabled

bit 2 SLEEP: When the device is in the Read state, writing this bit to a ‘1’ places the device in Sleep state.

1 = Sleep State

0 = Normal operation

bit 1 SLPOV: Sleep override. Writing a ‘1’ disables the Sleep state timer, allowing the PAC1921 to remain in

the Read state after tSLEEP

1 = Forced Read mode

0 = Normal operation

bit 0 RDAC: Forces the device to recalculate the selected measurement, and output immediately to the

DAC

1 = Forced recalculate/DAC update mode

0 = Normal operation

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VBR<9:2>

bit 15 bit 8

R-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

VBR<1:0> ——————

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-6 VBR<9:0>: These registers contain the most recent digitized value of the average of VBUS samples.

bit 5-0 Unimplemented: Read as ‘0’

PAC1921

DS20005293D-page 32  2012-2016 Microchip Technology Inc.

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VSR<9:2>

bit 15 bit 8

R-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

VSR<1:0> ——————

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-6 VBR<9:0>: These registers contain the most recent digitized value of the average of VSENSE samples

bit 5-0 Unimplemented: Read as ‘0’

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VSM<24:17>

bit 31 bit 24

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VSM<16:9>

bit 23 bit 16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VSM<8:1>

bit 15 bit 8

R-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

VSM0 ———————

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-7 VSM<24:0>: These registers contain the accumulated sum of VBUS samples (VSUM) This is the num-

ber of 14-bit ADC counts. For 11-bit ADC resolution, the bits are shifted left by 3, so 1 count has a bit

weighting of 8 and the lowest 3 bits will not be populated. The register value is only valid in the Read

state.

bit 6-0 Unimplemented: Read as ‘0’

 2012-2016 Microchip Technology Inc. DS20005293D-page 33

PAC1921

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

ISM<24:17>

bit 31 bit 24

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

ISM<16:9>

bit 23 bit 16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

ISM<8:1>

bit 15 bit 8

R-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

ISM0 ———————

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-7 ISM<24:0>: These registers contain the accumulated sum of VSENSE samples (ISUM). This is the number

of 14-bit ADC counts. For 11-bit ADC resolution, the bits are shifted left by 3, so 1 count has a bit

weighting of 8 and the lowest 3 bits will not be populated. The register value is only valid in the Read state.

bit 6-0 Unimplemented: Read as ‘0’

U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0

————— VSOV VBOV VPOV

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2 VSOV: This bit is set to ‘1’ when the DI_GAIN setting causes the VSENSE Result register to overflow

1 = Overflow occurred

0 = Normal operation

bit 1 VBOV: This bit is set to ‘1’ when the DV_GAIN setting causes the VBUS Result register to overflow.

1 = Overflow occurred

0 = Normal operation

bit 0 VPOV: This bit is set to ‘1’ when the DI_GAIN and/or DV_GAIN settings cause the VPOWER Result

1 = Overflow occurred

0 = Normal operation

PAC1921

DS20005293D-page 34  2012-2016 Microchip Technology Inc.

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VPR<9:2>

bit 15 bit 8

R-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

VPR<1:0> ——————

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-6 VPR<9:0>: These registers store the digitized value of the latest representation of the power relative

to maximum power.

bit 5-0 Unimplemented: Read as ‘0’

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP<11:4>

bit 15 bit 8

R-0 R-0 R-0 R-0 U-0 U-0 U-0 U-0

SMP<3:0> ————

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-4 SMP<11:0>: These register values indicate the number of voltage samples (pairs of samples for

power) taken during the integration period.

bit 3-0 Unimplemented: Read as ‘0’

 2012-2016 Microchip Technology Inc. DS20005293D-page 35

PAC1921

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

PSM<38:31>

bit 39 bit 32

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

PSM<30:23>

bit 31 bit 24

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

PSM<22:15>

bit 23 bit 16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

PSM<14:7>

bit 15 bit 8

R-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

PSM<5:1> —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 39-1 PSM<38:1>: These registers contain the accumulated sum of power samples (PSUM). This is the number

of 14-bit ADC counts. For 11-bit ADC resolution, the bits are shifted left by 6, so 1 count has a bit weighting

of 64 and the lowest 6 bits will not be populated. The register value is only valid in the Read state.

bit 0 Unimplemented: Read as ‘0’

R-0 R-1 R-0 R-1 R-1 R-0 R-1 R-1

PID<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 PID<7:0>: This register contains the Product ID for the PAC1921.

PAC1921

DS20005293D-page 36  2012-2016 Microchip Technology Inc.

R-0 R-1 R-0 R-1 R-1 R-1 R-0 R-1

MID<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 MID<7:0>: The Manufacturer ID register identifies Microchip as the manufacturer of the PAC1921

R-1 R-0 R-0 R-0 R-0 R-0 R-1 R-0

RID<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RID<7:0>: The Revision register identifies the die revision.

 2012-2016 Microchip Technology Inc. DS20005293D-page 37

PAC1921

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

PIN 1

10-Lead VDFN (3x3x0.9 mm) Example

Legend: Y Year code (last digit of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

<R> Package

<COO> Country of origin

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

1CWW

NNNA

PIN 1

1C03

256A

PAC1921

DS20005293D-page 38  2012-2016 Microchip Technology Inc.

0.10 C

(DATUM B)

(DATUM A)

SEATING

PLANE

NOTE 1

TOP VIEW

SIDE VIEW

BOTTOM VIEW

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

NOTE 1

0.10 C

0.05 C

Microchip Technology Drawing C04-206A Sheet 1 of 2

10-Lead Very Thin Plastic Dual Flat, No Lead Package (9Q) - 3x3 mm Body [VDFN]

L10X b

e0.10 C A B

0.05 C

(A3) 10X

 2012-2016 Microchip Technology Inc. DS20005293D-page 39

PAC1921

Microchip Technology Drawing C04-206A Sheet 2 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Number of Terminals

Overall Height

Terminal Width

Terminal Length

Terminal Thickness

Pitch

Standoff

Units

Dimension Limits

(A3)

0.50 BSC

0.20 REF

0.35

0.18

0.80

0.00

0.25

0.40

0.85

0.02

MILLIMETERS

MIN NOM

0.45

0.30

0.90

0.05

MAX

K0.300.25 -

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Pin 1 visual index feature may vary, but must be located within the hatched area.

Package is saw singulated

Dimensioning and tolerancing per ASME Y14.5M

Terminal-to-Exposed-Pad

10-Lead Very Thin Plastic Dual Flat, No Lead Package (9Q) - 3x3 mm Body [VDFN]

Overall Width

Overall Length

Exposed Pad Width

Exposed Pad Length

1.50

2.20

3.00 BSC

2.30

1.60

3.00 BSC

1.70

2.40

PAC1921

DS20005293D-page 40  2012-2016 Microchip Technology Inc.

RECOMMENDED LAND PATTERN

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Microchip Technology Drawing C04-2206A

10-Lead Very Thin Plastic Dual Flat, No Lead Package (9Q) - 3x3 mm Body [VDFN]

SILK SCREEN

(G2)

Dimension Limits

Units

Optional Center Pad Width

Center Pad Chamfer

Optional Center Pad Length

Contact Pitch

2.40

1.70

MILLIMETERS

0.50 BSC

MIN

MAX

0.28

Contact Pad Length (X10)

Contact Pad Width (X10)

0.80

0.30

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

NOM

CContact Pad Spacing 3.00

Contact Pad to Contact Pad (X8) G1 0.20

Contact Pad to Center Pad (X10) G2 0.25 REF

REF: Reference Dimension, usually without tolerances, for reference only.

Thermal Via Diameter V

Thermal Via Pitch VX

Thermal Via Pitch VY

0.30

1.00

2X CH

ØV

For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during

reflow process

Dimensioning and tolerancing per ASME Y14.5M

 2012-2016 Microchip Technology Inc. DS20005293D-page 41

PAC1921

APPENDIX A: REVISION HISTORY

Revision D (October 2016)

• Fixed minor typographical errors.

Revision C (June 2016)

The following is the list of modifications:

• Modified the matrix description from the note in

Section “Absolute Maximum Ratings(†)”

• Fixed various typographical errors for

consistency.

Revision B (April 2015)

The following is the list of modifications:

1. The document has been restructured to comply

with the latest Microchip data sheet standards.

2. Removed notes from Section 1.1 “Electrical

Specifications”.

3. Created separate Section 2.0 “Typical

Operating Curves” chapter; updated plots.

4. Fixed minor typographical errors.

Revision A (May 2014)

Replaced former SMSC version 1.2 (12-21-12).

• All sections updated to Microchip format.

• References to “stand-alone mode” removed.

• References to “lead-free” removed.

Rev 1.2 (December 2012)

• Modified under features in “Ordering

Information” section.

Rev. 1.0 (April 2012)

• Initial document release.

PAC1921

DS20005293D-page 42  2012-2016 Microchip Technology Inc.

NOTES:

 2012-2016 Microchip Technology Inc. DS20005293D-page 43

PAC1921

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. -X -XXX -XX

Tape andPackage SMBus

Address

Device

Device: PAC1921: High-side power/current monitor with analog output

SMBus Address: -1 = selectable address

Package: AIA = 10-lead 3 mm x 3 mm VDFN

Tape and Reel

Option:

TR =4,000 piece Tape and Reel

Examples:

a) PAC1921-1-AIA-TR: High-side current monitor

3x3 VDFN-8 package,

Tape and Reel

Reel

PAC1921

DS20005293D-page 44  2012-2016 Microchip Technology Inc.

NOTES:

 2012-2016 Microchip Technology Inc. DS20005293D-page 45

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate,

dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,

KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,

MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,

RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O

are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company,

ETHERSYNCH, Hyper Speed Control, HyperLight Load,

IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,

BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,

dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,

EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip

Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,

motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,

MPLINK, MultiTRAK, NetDetach, Omniscient Code

Generation, PICDEM, PICDEM.net, PICkit, PICtail,

PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,

Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total

Endurance, TSHARC, USBCheck, VariSense, ViewSpan,

WiperLock, Wireless DNA, and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-0732-4

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITYMANAGEMENTS

YSTEM

CERTIFIEDBYDNV

== ISO/TS16949==

DS20005192C-page 46  2016 Microchip Technology Inc.

AMERICAS

Corporate Office

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Chandler, AZ 85224-6199

Tel: 480-792-7200

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Tel: 905-695-1980

Fax: 905-695-2078

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2943-5100

Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

China - Dongguan

Tel: 86-769-8702-9880

China - Guangzhou

Tel: 86-20-8755-8029

China - Hangzhou

Tel: 86-571-8792-8115

Fax: 86-571-8792-8116

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

ASIA/PACIFIC

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-3019-1500

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Taiwan - Kaohsiung

Tel: 886-7-213-7828

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Dusseldorf

Tel: 49-2129-3766400

Germany - Karlsruhe

Tel: 49-721-625370

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Italy - Venice

Tel: 39-049-7625286

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Poland - Warsaw

Tel: 48-22-3325737

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Sweden - Stockholm

Tel: 46-8-5090-4654

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Worldwide Sales and Service

06/23/16