PCI ExpressTM Clock Generator ICS841S02I DATA SHEET General Description Features The ICS841S02I is a PLL-based clock generator specifically designed for PCI_ExpressTM Clock Generation applications. This device generates a 100MHz HCSL clock. The device offers a HCSL (Host Clock Signal Level) clock output from a clock input reference of 25MHz. The input reference may be derived from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference may be applied to the XTAL_IN pin with the XTAL_OUT pin left floating. * * * * * * * * * * * The device offers spread spectrum clock output for reduced EMI applications. An I2C bus interface is used to enable or disable spread spectrum operation as well as select either a down spread value of -0.35% or -0.5%. Block Diagram 25MHz 2 PLL Divider Network Output frequency: 100MHz RMS period jitter: 3ps (maximum) Output skew: 35ps (maximum) Cycle-to-cycle jitter: 35ps (maximum) I2C support with readback capabilities up to 400kHz Spread Spectrum for electromagnetic interference (EMI) reduction 3.3V operating supply mode -40C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages 2 VSS VDD SRCT2 SRCC2 SRCT1 SRCC1 VSS SRCT[1:2] SRCC[1:2] XTAL_OUT SDATA Pullup SCLK Pullup Crystal oscillator interface: 25MHz Pin Assignment XTAL_IN OSC Two 0.7V current mode differential HCSL output pairs I2C Logic 2 VDD VSS IREF IREF ICS841S02CGI REVISION A JANUARY 24, 2011 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD SDATA SCLK nc XTAL_OUT XTAL_IN VDD VSS VDDA VSS ICS841S02I 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View 1 (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet Table 1. Pin Descriptions Number Name 1, 7, 9, 11, 13 VSS Power Type Description Ground for core and SRC outputs. 2, 8, 14, 20 VDD Power Power supply for core and SRC outputs. 3, 4 SRCT2, SRCC2 Output Differential output pair. HCSL interface levels. 5, 6 SRCT1, SRCC1 Output Differential output pair. HCSL interface levels. 10 IREF Input An external fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode SRCCx, SRCTx clock outputs. 12 VDDA Power Analog power supply. 15, 16 XTAL_IN, XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. 17 nc Unused 18 SCLK Input Pullup I2C SMBus compatible SCLK. This pin has an internal pullup resistor, but is in high-impedance in power-down mode. LVCMOS/LVTTL interface levels. 19 SDATA I/O Pullup I2C SMBus compatible SDATA. This pin has an internal pullup resistor, but is in high-impedance in power-down mode. LVCMOS/LVTTL interface levels. No connect. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k ICS841S02CGI REVISION A JANUARY 24, 2011 Test Conditions 2 Minimum Typical Maximum Units (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore, use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3A. The block write and block read protocol is outlined in Table 3B, while Table 3C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 3A.Command Code Definition Bit 7 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation. 6:5 Chip select address, set to "00" to access device. 4:0 Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be "00000". Table 3B. Block Read and Block Write Protocol Bit 1 2:8 Description = Block Write Start Slave address - 7 bits Bit Description = Block Read 1 Start 2:8 Slave address - 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code - 8 bits 11:18 Command Code - 8 bits 19 Acknowledge from slave 19 Acknowledge from slave Byte Count - 8 bits 20 Repeat start 20:27 28 29:36 37 38:45 46 Acknowledge from slave 21:27 Slave address - 7 bits Data byte 1 - 8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte/Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop 30:37 Byte Count from slave - 8 bits 38 Acknowledge 39:46 Data Byte 1 from slave - 8 bits 47 Acknowledge 48:55 Data Byte 2 from slave - 8 bits 56 Acknowledge Data Bytes from Slave/Acknowledge Data Byte N from slave - 8 bits Not Acknowledge ICS841S02CGI REVISION A JANUARY 24, 2011 3 (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet Table 3C. Byte Read and Byte Write Protocol Bit Description = Byte Write 1 Start 2:8 Bit Description = Byte Read 1 Slave address - 7 bits Start 2:8 Slave address - 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code - 8 bits 11:18 Command Code - 8 bits Acknowledge from slave 19 Acknowledge from slave Data Byte- 8 bits 20 Repeat start 19 20:27 28 Acknowledge from slave 29 Stop 21:27 Slave address - 7 bits 28 Read 29 Acknowledge from slave 30:37 Data from slave - 8 bits 38 Not Acknowledge 39 Stop Control Registers Table 4A. Byte 0: Control Register 0 Bit @Pup Name 7 0 Reserved 6 1 Reserved 5 1 4 1 Table 4B. Byte 1: Control Register 1 Description Bit @Pup Name Description Reserved 7 0 Reserved Reserved Reserved 6 0 Reserved Reserved Reserved Reserved 5 0 Reserved Reserved SRC[T/C]2 Output Enable 0 = Disable (Hi-Z) 1 = Enable 4 0 Reserved Reserved SRC[T/C]2 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved 3 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z) 1 = Enable 2 1 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Table 4C. Byte 2: Control Register 2 NOTE: Pup denotes Power-up. ICS841S02CGI REVISION A JANUARY 24, 2011 4 Bit @Pup Name Description 7 1 SRCT/C Spread Spectrum Selection 0 = -0.35%, 1 = - 0.5% 6 1 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 2 0 SRC 1 1 Reserved Reserved 0 1 Reserved Reserved SRC Spread Spectrum Enable 0 = Spread Off, 1 = Spread On (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet Table 4D. Byte 3:Control Register 3 Table 4G. Byte 6: Control Register 6 Bit @Pup Name Description 7 1 Reserved Reserved 6 0 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 2 1 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved NOTE: Pup denotes Power-up. Table 4E. Byte 4: Control Register 4 Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 1 Reserved Table 4F. Byte 5: Control Register 5 @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved ICS841S02CGI REVISION A JANUARY 24, 2011 @Pup Name Description 7 0 TEST_SEL REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N TEST Clock Mode Entry Control 0 = Normal Operation, 1 = REF/N or Hi-Z Mode 6 0 TEST_MODE 5 0 Reserved Reserved 4 1 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Table 4H. Byte 7: Control Register 7 Reserved Bit Bit 5 Bit @Pup Name Description 7 0 Revision Code Bit 3 6 0 Revision Code Bit 2 5 0 Revision Code Bit 1 4 0 Revision Code Bit 0 3 0 Vendor ID Bit 3 2 0 Vendor ID Bit 2 1 0 Vendor ID Bit 1 0 1 Vendor ID Bit 0 (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 81.3C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 5A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C Symbol Parameter VDD Core Supply Voltage VDDA Analog Supply Voltage IDD IDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VDD - 0.22 3.3 VDD V Power Supply Current 80 mA Analog Supply Current 22 mA Table 5B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current SDATA, SCLK VDD = VIN = 3.465V IIL Input Low Current SDATA, SCLK VDD = 3.465V, VIN = 0V Minimum Typical Maximum 2.2 ICS841S02CGI REVISION A JANUARY 24, 2011 6 -150 Units V 1.0 V 10 A A (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet AC Electrical Characteristics Table 6. AC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C Symbol Parameter fref Crystal Reference Frequency SCLK SCLK Frequency Frequency Tolerance; NOTE 1 Test Conditions Minimum Typical Maximum 25 Units MHz 400 kHz XTAL 50 ppm External Reference 0 ppm 53 % 35 ps 10.0533 ns 35 ps 3 ps 700 ps 20 % odc SRCT/SRCC Output Duty Cycle; NOTE 2, 3 tsk(o) SRCT/C to SRCT/C Output Clock Skew; NOTE 2, 3 tPERIOD Average Period; NOTE 4 47 9.9970 tjit(cc) SRCT/C Cycle-to-Cycle Jitter; NOTE 2, 3 tjit(per) Period Jitter, RMS; NOTE 2, 3, 5 tR / tF SRCT/SRCC Rise/Fall Time; NOTE 6 tRFM Rise/Fall Time Matching; NOTE 7 tDC XTAL_IN Duty Cycle; NOTE 8 tR / tF Rise/Fall Time Variation VHIGH Voltage High 520 VLOW Voltage Low -150 VOX Output Crossover Voltage VOVS Maximum Overshoot Voltage VUDS Minimum Undershoot Voltage VRB Ring Back Voltage 2.42 150 47.5 @ 0.7V Swing 250 52.5 % 145 ps 875 mV mV 550 mV VHIGH + 0.3 V -0.3 V 0.2 V NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: With recommended crystal. NOTE 2: Measured at crossing point VOX. NOTE 3: Measured using a 50 to GND termination. NOTE 4: Measured at crossing point VOX at 100MHz. NOTE 5: If using the RMS period jitter to calculate peak-to-peak jitter, then use the typical RMS period jitter specification times the RMS multiplier. For example, for a bit error rate of 10E-12, the peak-to-peak jitter would be 2.42ps x 14 = 33.38ps. NOTE 6: Measured from VOL = 0.175V to VOH = 0.525V. NOTE 7: Determined as a fraction of 2*(tR - tF) / (tR + tF). NOTE 8: The device will operate reliably with input duty cycles up to 30/70% but the REF clock duty cycle will not be within specification. ICS841S02CGI REVISION A JANUARY 24, 2011 7 (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet Parameter Measurement Information 3.3V5% 3.3V5% HIGH SCOPE VDD 50 VREF VDDA LOW 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements HCSL 50 IREF GND Histogram Reference Point 475 Mean Period (Trigger Edge) (First edge after trigger) 0V 0V 3.3V HCSL Output Load AC Test Circuit RMS Period Jitter SRCCx SRCC[1:2] SRCTx SRCT[1:2] tcycle n tcycle n+1 SRCCy tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles SRCTy tsk(o) Cycle-to-Cycle Jitter Output Skew SRCC[1:2] SRCC[1:2] SRCT[1:2] 80% 80% t PW t odc = VSW I N G PERIOD t PW SRCT[1:2] 20% 20% tF tR x 100% t PERIOD Output Duty Cycle/Pulse Width/Period ICS841S02CGI REVISION A JANUARY 24, 2011 HCSL Output Rise/Fall Time 8 (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet Applications Information Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins Differential Outputs All control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Table 7. Recommended Crystal Specifications Symbol Parameter Value Crystal Cut Fundamental at Cut Resonance Parallel Resonance CL Load Capacitance 18pF CO Shunt Capacitance 5pF - 7pF ESR Equivalent Series Resistance 20 - 50 Output Driver Current The ICS841S02I outputs are HCSL current drive with the current being set with a resistor from IREF to ground. For a 50 pc board trace, the drive current would typically be set with a RREF of 475 which products an IREF of 2.32mA. The IREF is multiplied by a current mirror to an output drive of 6*2.32mA or 13.92mA. See Figure 1 for current mirror and output drive details. IREF RREF RL RL Figure 1. HCSL Current Mirror and Output Drive ICS841S02CGI REVISION A JANUARY 24, 2011 9 (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet Recommended Termination Figure 2A is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination is the standard for PCI ExpressTMand HCSL output types. 0.5" Max L1 Rs All traces should be 50 impedance single-ended or 100 differential. 0-0.2" 22 to 33 +/-5% L1 0.5 - 3.5" 1-14" L2 L4 L2 L4 L5 L5 PCI Expres s PCI Expres s Connector Driver 0-0.2" L3 L3 PCI Expres s Add-in Card 49.9 +/- 5% Rt Figure 2A. Recommended Source Termination (where the driver and receiver will be on separate PCBs) Figure 2B is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will 0.5" Max L1 L1 Rs 0 to 33 0 to 33 be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can range from 0 to 33. All traces should be 50 impedance single-ended or 100 differential. 0-18" 0-0.2" L2 L3 L2 L3 PCI Expres s Driver 49.9 +/- 5% Rt Figure 2B. Recommended Termination (where a point-to-point connection can be used) ICS841S02CGI REVISION A JANUARY 24, 2011 10 (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet Schematic Layout Figure 3 shows an example of ICS841S02I application schematic. In this example, the device is operated at VDD = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The load capacitance C1 = 18pF and C2 = 18pF is recommended for frequency accuracy. Depending on the parasitic of the printed circuit board layout, these values might require a slight adjustment for optimize the frequency accuracy. For this device, the crystal load capacitors are required for proper operation. supply isolation is required. The ICS841S02I provides separate power supplies to isolate noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. As with any high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power SRCT1 SRCC1 SRCC2 SRCT2 VDD R2 33 Zo = 50 + Zo = 50 - R3 50 R4 50 Recommended for PCI Express Add-In Card U1 IREF VSS VDD VSS SRCC1 SRCT1 SRCC2 SRCT2 VDD VSS R5 33 VDD 10 9 8 7 6 5 4 3 2 1 IREF R1 475 VSS VDDA VSS VDD XTAL_IN XTAL_OUT nc SCLK SDATA VDD HCSL Termination Optional 11 12 13 14 15 16 17 18 19 20 SRCT2 VDD VDDA R6 10 SRCC2 R9 R10 0-33 + 0-33 Zo = 50 - VDD C3 10uF C4 0.1u C2 18pF R7 50 VDD HCSL Optional Termination 25MHz X1 F p 8 1 VDD 3.3V R10 SP C2 18pF R8 50 Recommended for PCI Express Point-to-Point Connection BLM18BB221SN1 1 R9 SP Zo = 50 Ferrite Bead C6 C5 0.1uF SCLK SDATA VDD (U1-2) 2 10uF (U1-8) C8 0.1uF (U1-14) C9 0.1uF VDD C7 0.1uF (U1-20) C10 0.1uF Figure 3. ICS841S02I Application Schematic Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, ICS841S02CGI REVISION A JANUARY 24, 2011 good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. 11 (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS841S02I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS841S02I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. The maximum current at 85C is as follows: IDD_MAX = 75mA IDDA_MAX = 20mA * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V *(75mA + 20mA) = 329.175mW * Power (outputs)MAX = 44.5mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 44.5mW = 89mW Total Power_MAX = 329.175mW + 89mW = 418.175mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 81.3C/W per Table 8 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.418W * 81.3C/W = 119C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 8. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS841S02CGI REVISION A JANUARY 24, 2011 0 1 2.5 81.3C/W 76.9C/W 74.8C/W 12 (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 4. VDD IOUT = 17mA VOUT RREF = 475 1% RL 50 IC Figure 4. HCSL Driver Circuit and Termination HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD_MAX. Power = (VDD_MAX - VOUT) * IOUT, since VOUT - IOUT * RL = (VDD_MAX - IOUT * RL) * IOUT = (3.465V - 17mA * 50) * 17mA Total Power Dissipation per output pair = 44.5mW ICS841S02CGI REVISION A JANUARY 24, 2011 13 (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet Reliability Information Table 9. JA vs. Air Flow Table for a 20 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 81.3C/W 76.9C/W 74.8C/W Transistor Count The transistor count for ICS841S02I is: 1874 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 10. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS841S02CGI REVISION A JANUARY 24, 2011 14 (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet Ordering Information Table 11. Ordering Information Part/Order Number 841S02CGI 841S02CGIT 841S02CGILF 841S02CGILFT Marking ICS841S02CGI ICS841S02CGI ICS841S02CIL ICS841S02CIL Package 20 Lead TSSOP 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C NOTE: Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS841S02CGI REVISION A JANUARY 24, 2011 15 (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet Revision History Sheet Rev A Table Page Description of Change Date Updated die revision from ICS841S02BI to ICS841S02CI with updated specifications to reflect the change (reference PCN #N1101-03). Updated datasheet format. ICS841S02CGI REVISION A JANUARY 24, 2011 16 1/24/11 (c)2011 Integrated Device Technology, Inc. PCI EXPRESSTM CLOCK GENERATOR ICS841S02I Data Sheet We've Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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