TECHNICAL DATA
29
Counter/Divider
High-Voltage Silicon-Gate CMOS
The IW4017B is 5-stage Johnson counter having 10 decoded
outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT
signal. Schmitt trigger action in the CLOCK input circuit provides
pulse shaping that allows unlimited clock input pulse rise and fall
times.
The counter is advanced one count at the positive clock signal
transition if the CLOCK INHIBIT signal is low. Counter advancement
via the clock line is inhibited when the CLOCK INHIBIT signal is
high. A high RESE T signal clears t he counter to i ts zer o co unt. Use of
the Johnson counter configuration permits high-speed operation, 2-
input decode-gating and spike-free decoded outputs. Anti-lock gating
is provided, thus assuring proper counting sequence. The decoded
outputs are normally low and go high only at their respective decoded
time slot. Each decoded output remains high for one full clock cycle. A
CARRY-OUT signal completes one cycle every 10 clock input cycles
in the IW4017B.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
IW4017B
ORDERING INFORMATION
IW4017BN Plastic
IW4017BDW SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
FUNCTION TABLE
Clock Clock
Enable Reset Output State *
L X L no change
X H L no change
X X H reset counter
Q0=H, Q1-Q9=L,
C0=H
L L Advance to next
state
X L no change
XL no change
HL Advance to next
state
* Carry Out=H for Q0,Q1,Q2,Q3 or Q4=H
Carry Out = L otherwise, X=don’t care
IW4017B
30
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±10 mA
PDPower Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
PDPower Dissipation per Output Transistor 100 mW
Tstg Storage Temperature -65 to +150 °C
TLLead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 3.0 18 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types -55 +125 °C
Thi s device contains p rote ction c ircuitr y to guard a gainst damage due to hi gh static voltage s or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
IW4017B
31
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V ≥-55°C25
°C≤125
°CUnit
VIH Minimum High-Level
Input Voltage VOUT=0.5V or VCC - 0.5V
VOUT=1.0V or VCC - 1.0V
VOUT=1.5V or VCC - 1.5V
5.0
10
15
3.5
7
11
3.5
7
11
3.5
7
11
V
VIL Maxi mum Low -Leve l
Input Voltage VOUT=0.5V or VCC - 0.5V
VOUT=1.0V or VCC - 1.0V
VOUT=1.5V or VCC - 1.5V
5.0
10
15
1.5
3
4
1.5
3
4
1.5
3
4
V
VOH Minimum High-Level
Output Voltage VIN=GND or VCC 5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
4.95
9.95
14.95
V
VOL Maxi mum Low-Leve l
Output Voltage VIN=GND or VCC 5.0
10
15
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
IIN Maximum Inpu t
Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA
ICC Maximum Q ui escent
Supply Current
(per Package)
VIN= GND or VCC 5.0
10
15
20
5
10
20
100
5
10
20
100
150
300
600
3000
µA
IOL Min imu m Output Low
(Sink) Current VIN= GND or VCC
UOL=0.4 V
UOL=0.5 V
UOL=1.5 V
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
mA
IOH Min imu m Output
High (Source) Current VIN= GND or VCC
UOH=2.5 V
UOH=4.6 V
UOH=9.5 V
UOH=13.5 V
5.0
5.0
10
15
-2.0
-0.64
-1.6
-4.2
-1.6
-0.51
-1.3
-3.4
-1.15
-0.36
-0.9
-2.4
mA
IW4017B
32
AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200kΩ, Input tr=tf=20 ns)
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C25
°C≤125°CUnit
fmax Maximum Clock Fr equency 5.0
10
15
2.5
5
5.5
2.5
5
5.5
1.25
2.5
2.75
MHz
tPLH, tPHL Maximum Prop agation Del ay, Cloc k to De code
Output (Figure 1 ) 5.0
10
15
650
270
170
650
270
170
1300
540
340
ns
tPLH, tPHL Maximum Propagation Del ay, Clock t o Car ry
Output (Figure 1 ) 5.0
10
15
600
250
160
600
250
160
1200
500
320
ns
tTLH, tTHL Maximum Output Transition Time, Carry
Output or Decode Output (Figur e 1) 5.0
10
15
200
100
80
200
100
80
400
200
160
ns
tPLH, tPHL Maximum Propagation Delay, Reset to Carry
Output or Decode Output (Figur e 1) 5.0
10
15
530
230
170
530
230
170
1060
460
340
ns
CIN Maximum Input Capacitance - 5 pF
TIMING REQUIREMENTS (VCC=5.0V±10%, CL=50pF, Input tr=tf=20 ns, RL=200kΩ )
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C25
°C≤125°CUnit
twMinimum Pulse Width, Clock (Figure 1) 5.0
10
15
200
90
60
200
90
60
400
180
120
ns
tr, tfMa xi mum Input Rise and Fall Times, Clock
(Figure 1) 5.0
10
15
UNLIMITED µs
twMinimum Pulse Width, Reset (Figur e 1) 5.0
10
15
260
110
60
260
110
60
520
220
120
ns
trem Minimum Removal Time, Reset (Fig ure 1) 5.0
10
15
400
280
150
400
280
150
800
560
300
ns
tSU Minimum Setup T i me, Clock Inhibit t o Clock
(Figure 1) 5.0
10
15
230
100
70
230
100
70
460
200
140
ns
IW4017B
33
Figure 1. Switching Waveforms
Timing diagram
IW4017B
34
EXPANDED LOGIC DIAGRAM
