INTEGRATED CIRCUITS DATA SHEET TDA8768 12-bit high-speed Analog-to-Digital Converter (ADC) Preliminary specification Supersedes data of 1998 Feb 25 File under Integrated Circuits, IC02 1998 Aug 26 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) TDA8768 FEATURES APPLICATIONS * 12-bit resolution * High-speed analog-to-digital conversion for * Sampling rate up to 55 MHz - Video signal digitizing * -3 dB bandwidth of 190 MHz - High Definition TV (HDTV) * 5 V power supplies - Imaging (camera scanner) * Binary or twos-complement CMOS outputs - Medical imaging * In-range CMOS-compatible output - Telecommunication * TLL-CMOS compatible static digital inputs - Base-station receiver. * 3 to 5 V CMOS-compatible digital outputs * Differential clock input; Positive Emitter Coupled Logic (PECL)-compatible GENERAL DESCRIPTION The TDA8768 is a bipolar 12-bit Analog-to-Digital Converter (ADC) optimized for telecommunications and professional imaging. It converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 55 MHz. All static digital inputs (SH, CE and OTC) are TTL and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used. * Power dissipation 325 mW (typical) * Low analog input capacitance (typical 2 pF), no buffer amplifier required * Integrated sample-and-hold amplifier * Differential analog input * External amplitude range control * Voltage controlled regulator included. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 3.0 3.3 5.25 V ICCA analog supply current - 33 tbf mA ICCD digital supply current - 30 tbf mA ICCO output supply current fCLK = 4 MHz; fi = 400 kHz - 3.2 tbf mA INL integral non-linearity fCLK = 4 MHz; fi = 400 kHz - 2.0 4.5 LSB DNL differential non-linearity fCLK = 4 MHz; fi = 400 kHz - 0.6 1.0 LSB fCLK(max) maximum clock frequency TDA8768H/4 40 - - MHz TDA8768H/5 55 - - MHz - 325 tbf mW Ptot total power dissipation ORDERING INFORMATION TYPE NUMBER TDA8768H/4 TDA8768H/5 1998 Aug 26 PACKAGE NAME DESCRIPTION VERSION QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 2 SAMPLING FREQUENCY (MHz) 40 55 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) TDA8768 BLOCK DIAGRAM VCCA1 VCCA2 VCCA3 VCCA4 handbook, full pagewidth 2 n.c. 9 3 41 CLK CLK VCCD1 VCCD2 36 35 37 15 OTC CE 18 19 21 D11 1, 5 to 8, 12 to 14, 16 MSB CLOCK DRIVER 22 D10 TDA8768 Vref 23 D9 11 24 D8 25 D7 AMP 26 D6 CMOS OUTPUTS VI VI 27 D5 43 ANALOG-TO-DIGITAL CONVERTER 42 LATCHES 29 D3 30 D2 sampleand-hold SH data outputs 28 D4 31 D1 32 D0 39 33 OVERFLOW/ UNDERFLOW LATCH 44 10 AGND1 AGND2 4 20 CMOS OUTPUT 40 38 17 34 AGND4 DGND1 DGND2 OGND LSB VCCO IR MGR470 AGND3 Fig.1 Block diagram. 1998 Aug 26 3 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) TDA8768 PINNING SYMBOL PIN DESCRIPTION SYMBOL PIN DESCRIPTION n.c. 1 not connected D9 23 data output; bit 9 VCCA1 2 analog supply voltage 1 (+5 V) D8 24 data output; bit 8 VCCA3 3 analog supply voltage 3 (+5 V) D7 25 data output; bit 7 AGND3 4 analog ground 3 D6 26 data output; bit 6 n.c. 5 not connected D5 27 data output; bit 5 n.c. 6 not connected D4 28 data output; bit 4 n.c. 7 not connected D3 29 data output; bit 3 n.c. 8 not connected D2 30 data output; bit 2 VCCA2 9 analog supply voltage 2 (+5 V) D1 31 data output; bit 1 AGND2 10 analog ground 2 D0 32 data output; bit 0 (LSB) Vref 11 reference voltage input VCCO 33 output supply voltage (3 to 5.25 V) n.c. 12 not connected OGND 34 output ground n.c. 13 not connected CLK 35 complementary clock input; active LOW n.c. 14 not connected VCCD2 15 digital supply voltage 2 (+5 V) CLK 36 clock input 37 digital supply voltage 1 (+5 V) n.c. 16 not connected VCCD1 DGND2 17 digital ground 2 DGND1 38 digital ground 1 OTC 18 control input twos complement output; active HIGH SH 39 sample-and-hold enable input (CMOS level; active HIGH) CE 19 chip enable input (CMOS level; active LOW) AGND4 40 analog ground 4 VCCA4 41 analog supply voltage 4 (+5 V) IR 20 in-range output VI 42 positive analog input voltage D11 21 data output; bit 11 (MSB) VI 43 negative analog input voltage D10 22 data output; bit 10 AGND1 44 analog ground 1 1998 Aug 26 4 Philips Semiconductors Preliminary specification 34 OGND n.c. 1 33 VCCO VCCA1 2 32 D0 VCCA3 3 31 D1 AGND3 4 30 D2 n.c. 5 29 D3 TDA8768H 26 D6 VCCA2 9 25 D7 AGND2 10 24 D8 Vref 11 23 D9 5 D10 22 D11 21 IR 20 28 D4 CE 19 OTC 18 8 DGND2 17 n.c. n.c. 16 27 D5 VCCD2 15 7 n.c. 14 n.c. n.c. 13 6 n.c. 12 n.c. Fig.2 Pin configuration. 1998 Aug 26 35 CLK 36 CLK 37 VCCD1 38 DGND1 TDA8768 39 SH 40 AGND4 41 VCCA4 42 VI handbook, full pagewidth 43 VI 44 AGND1 12-bit high-speed Analog-to-Digital Converter (ADC) MGR469 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) TDA8768 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage note 1 -0.3 +7.0 V VCCD digital supply voltage note 1 -0.3 +7.0 V VCCO output supply voltage note 1 -0.3 +7.0 V VCC supply voltage difference VCCA - VCCD -1.0 +1.0 V VCCD - VCCO -1.0 +4.0 V VCCA - VCCO -1.0 +4.0 V VI input voltage at pins 42 and 43 0.3 VCCA V Vi(p-p) input voltage at pins 35 and 36 for differential clock drive (peak-to-peak value) - VCCD V IO output current - 10 mA Tstg storage temperature -55 +150 C Tamb operating ambient temperature -10 +85 C Tj junction temperature - 150 C referenced to AGND Note 1. The supply voltages VCCA, VCCD and VCCO may have any value between -0.3 V and +7.0 V provided that the supply voltage differences VCC are respected. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1998 Aug 26 PARAMETER CONDITION thermal resistance from junction to ambient 6 in free air VALUE UNIT 75 K/W Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) TDA8768 CHARACTERISTICS VCCA = V2 to V44, V9 to V10, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to 70 C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C, VI(p-p) - VI(p-p) = 2.0 V and CL = 10 pF; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 3.0 3.3 5.25 V ICCA analog supply current - 33 45 mA ICCD digital supply current - 30 37 mA ICCO output supply current - 3.2 tbf mA fCLK = 40 MHz; fi = 4.43 MHz - 11 tbf mA fCLK = 4 MHz; fi = 400 kHz Inputs CLK AND CLK (REFERENCED TO DGND) VIL LOW-level input voltage VCCD = 5 V; note 1 3.19 - 3.52 V VIH HIGH-level input voltage VCCD = 5 V; note 1 3.83 - 4.12 V IIL LOW-level input current VCLK or VCLK = 3.19 V -10 - - A IIH HIGH-level input current VCLK or VCLK = 3.83 V - - 10 A Zi input impedance fCLK = 40 MHz 2 - - k Ci input capacitance fCLK = 40 MHz - - 2 pF VCLK(p-p) differential AC input voltage (peak-to-peak value) for switching (VCLK - VCLK) DC voltage level = 2.5 V 0.5 - 2.0 V OTC, SH AND CE (REFERENCED TO DGND); see Tables 1 and 2 VIL LOW-level input voltage 0 - 0.8 V VIH HIGH-level input voltage 2.0 - VCCD V IIL LOW-level input current VIL = 0.8 V -20 - - A IIH HIGH-level input current VIH = 2.0 V - - +20 A VI AND VI (REFERENCED TO AGND); VREF = VCCA - 1.825 V; see Table 1 IIL LOW-level input current - 10 - A IIH HIGH-level input current - 10 - A Ri input resistance fi = 4.43 MHz 100 - - k Ci input capacitance fi = 4.43 MHz - - 2 pF VI(CM) common mode input voltage VI = VI; output code 2047 VCCA = 5 V tbf 3.6 tbf V VCCA = 4.75 V tbf 3.35 tbf V VCCA = 5.25 V tbf 3.85 tbf V 1998 Aug 26 7 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) SYMBOL PARAMETER TDA8768 CONDITIONS MIN. TYP. MAX. UNIT Voltage controlled regulator input Vref (referenced to AGND); note 2 Vref(FS) full-scale fixed voltage Iref input current VI(p-p) - VI(p-p) input voltage amplitude (peak-to-peak value) VCCA = 5 V - - 0.5 10 A Vref = VCCA - 1.825 V - 2.0 - V 0 - 0.5 V 3.175 - V Outputs (referenced to OGND) DIGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO OGND) VOL LOW-level output voltage IOL = 2 mA VOH HIGH-level output voltage IOH = -0.4 mA VCCO - 0.5 - VCCO V Io output current in 3-state output level between 0.5 V and VCCO -20 - +20 A SH = HIGH - - 2 MHz TDA8768H/4 40 - - MHz TDA8768H/5 55 - - MHz Switching characteristics CLOCK FREQUENCY fCLK; see Fig.3 fCLK(min) minimum clock frequency fCLK(max) maximum clock frequency tCLKH clock pulse width HIGH 8.5 - - ns tCLKL clock pulse width LOW 8.5 - - ns Analog signal processing; 50% clock duty factor; VI - VI = 2.0 V; Vref = VCCA - 1.825 V; see Table 1 LINEARITY INL integral non-linearity fCLK = 4 MHz; fi = 400 kHz - 2.0 4.5 LSB DNL differential non-linearity fCLK = 4 MHz; fi = 400 kHz; no missing code - 0.6 1.0 LSB Eoffset offset error VCCA = VCCD = VCCO = 5 V; Tamb = 25 C; VI = VI; output code = 2047 tbf -11 tbf mV EG(FS) gain error amplitude (full scale); spread from device to device VCCA = VCCD = VCCO = 5 V; Tamb = 25 C; VI(p-p) - VI(p-p) = 2.0 V -5 - +5 % -3 dB; full scale input tbf 190 - MHz - - 0 dB - -75 - dB - -70 - dB - -66 - dB BANDWIDTH (fCLK = 55 MHz); note 3 B analog bandwidth HARMONICS (fCLK = 40 MHz) hfund(FS) fundamental harmonics (full scale) fi = 4.43 MHz htot(FS) harmonics (full scale); all components fi = 4.43 MHz second harmonic third harmonic THD 1998 Aug 26 total harmonic distortion fi = 4.43 MHz; note 4 8 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) SYMBOL PARAMETER TDA8768 CONDITIONS MIN. TYP. MAX. UNIT THERMAL NOISE Nth(rms) thermal noise (RMS value) grounded input; fCLK = 40 MHz - 0.25 tbf LSB SPURIOUS FREE DYNAMIC RANGE DRsf spurious free dynamic range fi = 4.43 MHz tbf 69 - dB fi = 10 MHz tbf tbf - dB fi = 20 MHz tbf tbf - dB 67 - dB - 10.3 - bits - tbf - bits - tbf - bits - 9.9 - bits - tbf - bits fi = 15 MHz - tbf - bits fi = 20 MHz - tbf - bits SIGNAL-TO-NOISE RATIO; note 5 S/N signal-to-noise ratio without harmonics; - fCLK = 40 MHz; fi = 4.43 MHz EFFECTIVE NUMBER OF BITS; note 5 Nbit effective number of bits fi = 4.43 MHz TDA8768H/4 (fCLK = 40 MHz) fi = 10 MHz fi = 15 MHz effective number of bits fi = 4.43 MHz TDA8768H/5 (fCLK = 55 MHz) fi = 10 MHz INTERMODULATION; note 6 TTIR two-tone intermodulation rejection fCLK = 40 MHz tbf 66 - dB d3 third order intermodulation distortion fCLK = 40 MHz tbf 67 - dB fCLK = 40 MHz; fi = 4.43 MHz; VI = 16 LSB at code 2047 - 10-15 tbf times/ sample - - 2 ns BIT ERROR RATE BER bit error rate Timing (CL = 10 pF); see Fig.3 and note 7 td(s) sampling delay time th output hold time td output delay time VCCO = 5.25 V 4 - - ns - 10 15 ns 13 18 ns VCCO = 3.0 V 3-state output delay times; see Fig.4 tdZH enable HIGH - 14 18 ns tdZL enable LOW - 16 20 ns tdHZ disable HIGH - 16 20 ns tdLZ disable LOW - 14 18 ns 1998 Aug 26 9 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) TDA8768 Notes 1. The circuit has two clock inputs: CLK and CLK. There are four modes of operation: a) PECL mode 1: (DC level varies 1 : 1 with VCCD) CLK and CLK inputs are at differential PECL levels. b) PECL mode 2: (DC level varies 1 : 1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC level varies 1 : 1 with VCCD) CLK input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.5 V (peak-to-peak value) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor. 2. It is possible with an external reference connected to pin Vref to adjust the ADC input range. This voltage has to be referenced to VCCA. For VCCA - 1.825 V, the differential input voltage amplitude is 2 V (peak-to-peak value). 3. The -3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. 4. THD (total harmonic distortion) is obtained with the addition of the first five harmonics: F THD = 20 log --------------------------------------------------------------------------------------------------------------2 2 2 2 2 (2nd) + (3rd) + (4th) + (5th) + (6th) where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input. 5. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SNR: SNR = Nbit x 6.02 + 1.76 dB. 6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 and 4.53 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (-6 dB below full-scale for each input signal). d3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product. 7. Output data acquisition: the output data is available after the maximum delay of td. 1998 Aug 26 10 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) Table 1 TDA8768 Output coding with differential inputs (typical values to AGND); VI(p-p) - VI(p-p) = 2.0 V; Vref = VCCA - 1.825 V CODE VI(p-p) VI(p-p) BINARY OUTPUTS TWOS COMPLEMENT OUTPUTS D11 TO D0 D11 TO D0 0 000000000000 100000000000 IR Underflow <3.1 >4.1 0 3.1 4.1 1 000000000000 1 0 0 0 0 0 0 0 0 0 00 1 - - 1 000000000001 100000000001 - - 2047 3.6 3.6 1 011111111111 111111111111 - - 4094 - - 1 111111111110 011111111110 4095 4.1 3.1 1 111111111111 011111111111 Overflow >4.1 <3.1 0 111111111111 011111111111 Table 2 Mode selection OTC CE D0 TO D11 AND IR 0 0 binary; active 1 0 twos complement; active X(1) 1 high impedance Note 1. X = don't care. Table 3 Sample-and-hold selection SH SAMPLE-AND-HOLD 1 active 0 inactive; tracking mode 1998 Aug 26 11 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) TDA8768 tCLKL handbook, full pagewidth tCLKH HIGH CLK 50 % LOW sample N + 1 sample N sample N + 2 VI th tds HIGH DATA D0 to D11 DATA N-2 DATA N-1 DATA N DATA N+1 50 % LOW td MGR472 Fig.3 Timing diagram. handbook, full pagewidth V CCD 50 % CE 0V tdHZ tdZH HIGH 90 % output data 50 % LOW tdZL tdLZ HIGH output data 50 % LOW 10 % V CCD 3.3 k S1 TDA8768 15 pF TEST S1 t dLZ t dZL VCCD VCCD t dHZ DGND t dZH DGND CE MBG856 fCE = 100 kHz. Fig.4 Timing diagram and test conditions of 3-state output delay time. 1998 Aug 26 12 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) TDA8768 APPLICATION INFORMATION 5V handbook, full pagewidth SH mode 100 nF 220 nF input 5V 100 nF VI 1:1 CLK 100 VI VCCA R1 10 nF 5V n.c. 100 nF Vref (3) 100 nF 33 32 D0 (LSB) 31 D1 4 30 D2 n.c. 5 29 D3 n.c. 6 28 D4 n.c. 7 27 D5 n.c. 8 26 D6 9 25 D7 10 24 D8 11 23 D9 R2 5V 1 3 100 nF 100 nF 44 43 42 41 40 39 38 37 36 35 34 2 5V (2) 4.7 F (1) CLK 100 TDA8768 12 13 14 15 16 17 18 19 20 21 22 n.c. n.c. n.c. n.c. 5V 100 nF IR D10 D11 (MSB) chip select input output format select The analog, digital and output supplies should be separated and decoupled. (1) Single-ended clock signals can be applied if required. (2) R1 and R2 must be determined in order to obtain a middle voltage of 3.6 V; see common mode input voltage. In addition, to ensure a sufficient analog input stability, the minimum current into these resistors must be approximately 1 mA. (3) Vref must be decoupled to VCCA. Fig.5 Application diagram. 1998 Aug 26 13 MGR471 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) TDA8768 handbook, full pagewidth R2 220 100 nF 270 TTL input (1) R1 500 CLK Z0 = 50 D TRANSLATOR 35 PECL Z0 = 50 CLK 36 R1 500 270 TDA8768 100 nF R2 220 MGL474 If the clock lines are more than 1 inch long they must be matched. In fact, the 27 resistor will be changed by the series connection of R1 and R2, with R1 = Zo placed close to pins CLK and CLK. (1) 50 matched line (Zo, L). Fig.6 Application diagram for differential clock input (PECL-compatible) using a TTL to PECL translator. 100 nF VCCD handbook, full pagewidth R1 82 TTL input (1) R1 82 CLK 35 D TRANSLATOR PECL CLK R2 120 R2 120 36 TDA8768 MGL473 The value of R1 and R2 must be chosen in order to meet the following relations: V CCD x R2 R1 x R2 3 V = ---------------------------- and Z0 = ---------------------R1 + R2 R1 + R2 (1) 50 matched line (Zo, L). Fig.7 Application diagram for differential clock input (PECL-compatible) using a TTL to PECL translator and Thevenin parallel terminations. 1998 Aug 26 14 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) TDA8768 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.10 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 o 10 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT307-2 1998 Aug 26 EUROPEAN PROJECTION 15 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) TDA8768 If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: SOLDERING Introduction * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. 1998 Aug 26 16 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) TDA8768 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Aug 26 17 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) TDA8768 NOTES 1998 Aug 26 18 Philips Semiconductors Preliminary specification 12-bit high-speed Analog-to-Digital Converter (ADC) TDA8768 NOTES 1998 Aug 26 19 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545104/750/02/pp20 Date of release: 1998 Aug 26 Document order number: 9397 750 03378 Select & Go... Go to Philips Semiconductors' home page Start part Catalog & Datasheets Information as of 2000-08-22 Catalog by Function Discrete semiconductors Audio Clocks and Watches Data communications Microcontrollers Peripherals Standard analog Video Wired communications Wireless communications Catalog by System Automotive Consumer Multimedia Systems Communications PC/PC-peripherals TDA8768; 12-bit high-speed Analog-to-Digital Converter (ADC) * Description * Features * Applications * Datasheet * Products, packages, availability and ordering * Find similar products Description The TDA8768 is a bipolar 12-bit Analog-to-Digital Converter (ADC) optimized for telecommunications and professional imaging. It converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 55 MHz. All static digital inputs (SH, CE and OTC) are TTL and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used. Models Features Application notes Selection guides l Other technical documentation l End of Life information l Datahandbook system l l Relevant Links About catalog tree About search About this site Subscribe to eNews Catalog & Datasheets Search TDA8768 TDA8768 To be kept informed on TDA8768, subscribe to eNews. * Cross reference Packages Subscribe to eNews l l l l l l l l l l 12-bit resolution Sampling rate up to 55 MHz -3 dB bandwidth of 190 MHz 5 V power supplies Binary or twos-complement CMOS outputs In-range CMOS-compatible output TLL-CMOS compatible static digital inputs 3 to 5 V CMOS-compatible digital outputs Differential clock input; Positive Emitter Coupled Logic (PECL)-compatible Power dissipation 325 mW (typical) Low analog input capacitance (typical 2 pF), no buffer amplifier required Integrated sample-and-hold amplifier Differential analog input External amplitude range control Voltage controlled regulator included. Applications l High-speed analog-to-digital conversion for - Video signal digitizing - High Definition TV (HDTV) - Imaging (camera scanner) - Medical imaging - Telecommunication - Base-station receiver. Datasheet Type nr. Title TDA8768 12-bit high-speed Analog-to-Digital Converter (ADC) Publication release date 26-Aug-98 Datasheet status Preliminary Specification Page count 20 File size (kB) 126 Datasheet Download Products, packages, availability and ordering Partnumber North American Partnumber Order code (12nc) TDA8768AH/4/C1 9352 628 36551 TDA8768AH/5/C1 9352 628 37551 TDA8768AH/7/C1 9352 628 38551 TDA8768H/4/C1 TDA8768H/5/C1 TDA8768H/4B-T 9352 454 00518 TDA8768H/4B-S 9352 454 00551 TDA8768H/4B 9352 454 00557 TDA8768H/5B-T 9352 454 10518 TDA8768H/5B-S 9352 454 10551 TDA8768H/5B 9352 454 10557 Find similar products: marking/packing Standard Marking * Tray Dry Pack, Bakeable, Single Standard Marking * Tray Dry Pack, Bakeable, Single Standard Marking * Tray Dry Pack, Bakeable, Single Standard Marking * Reel Dry Pack, SMD, 13" Standard Marking * Tray Dry Pack, Bakeable, Single Standard Marking * Tray Dry Pack, Bakeable, Multiple Standard Marking * Reel Dry Pack, SMD, 13" Standard Marking * Tray Dry Pack, Bakeable, Single Standard Marking * Tray Dry Pack, Bakeable, Multiple package device status buy online SOT307 Development - SOT307 Development - SOT307 Development - SOT307 Samples available SOT307 Samples available SOT307 Samples available SOT307 Samples available SOT307 Samples available SOT307 Samples available TDA8768 links to the similar products page containing an overview of products that are similar in function or related to the part number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection guides and products from the same functional category. Copyright (c) 2000 Royal Philips Electronics All rights reserved. Terms and conditions.