FAN6208MY - Fairchild - Product.Network

April 2012

FAN6208 • Rev. 1.0.2

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

FAN6208

Secondary-Side Synchronous Rectifier Controller for

LLC Topology

Features

 Specialized SR Controller for LLC or LC Resonant

Converters

 Secondary-Side Timing Detection with Timing

Estimator

 Gate-Shrink Function to Prevent Shoot-Through

During Load and Line Transient

 Green-Mode Function for Higher Efficiency at Light-

Load Condition

 Programmable Dead Time between Primary-Side

Gate Drive Signal and SR Drive Signal

 Advanced Output-Short / Overload Protection

Based on the Feedback Information

 Internal Over-Temperature Protection (OTP)

 VDD Pin Over-Voltage Protection (OVP)

Applications

 LCD TV

 PC Power

 Open-Frame SMPS

Description

FAN6208 is a synchronous rectification (SR) controller

for isolated LLC or LC resonant converters that can

drive two individual SR MOSFETs emulating the

behavior of rectifier diodes. FAN6208 measures the SR

conduction time of each switching cycle by monitoring

the drain-to-source voltage of each SR and determines

the optimal timing of the SR gate drive. FAN6208 uses

the change of opto-coupler diode current to adaptively

shrink the duration of SR gate drive signals during load

transients to prevent shoot-through. To improve light-

load efficiency, Green-Mode operation is employed,

which disables the SR drive signals, minimizing gate

drive power consumption at light-load condition.

Optimal timing circuits and protection functions are

integrated in an 8-pin SOP package, which allows high-

efficiency power supply design with fewer components.

Related Resources

 Evaluation Board: FEBFAN6208_CP433v1

Ordering Information

Part Number Operating Temperature Range Package Packing Method

FAN6208MY -40°C to +105°C 8-Pin Small Outline Package (SOP) Tape & Reel

FAN6208 • Rev. 1.0.2 2

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Application Diagram

Figure 1. Typical Application

Block Diagram

Figure 2. Block Diagram

FAN6208 • Rev. 1.0.2 3

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Marking Information

Figure 3. Top Mark

Pin Configuration

Figure 4. Pin Assignments

Pin Definitions

Pin # Name Description

1 DETL1

Low Detect provides low-voltage detection of VDS of SR MOSFET1.

2 DETL2

Low Detect provides low-voltage detection of VDS of SR MOSFET2.

3 RP

Dead Time Programming Resistor programs H/L frequency version and dead time.

4 FD

Feedback Detection is used for short-circuit protection and gate shrink.

5 VDD

Power Supply

6 GATE2

Driver Output. The totem-pole output driver for driving the SR MOSFET2.

7 GND

Ground

8 GATE1

Driver Output. The totem-pole output driver for driving the SR MOSFET1.

F- Fairchild Logo

Z- Plant Code

X- Year Code

Y- Week Code

TT: Die Run Code

T - Package Type (M = SOP)

P - Y: Green Package

M - Manufacture Flow Code

6208

TPM

6208

FAN6208 • Rev. 1.0.2 4

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VDD Supply Voltage 30 V

VFD Voltage on FD Pin 30 V

VLV Voltage on DETL1, DETL2, RP Pins -0.3 7.0 V

PD Power Dissipation 350Mw

at TA=90°C

1000mW

at TA=25°C

JA Junction–to-Ambient Thermal Resistance 130 °C/W

JT Junction-to-Top Thermal Characteristics 45 °C/W

TJ Operating Junction Temperature -40 +125 °C

TSTG Storage Temperature Range -55 +150 °C

TL Lead Temperature (Wave Soldering or IR, 10 Seconds) +260 °C

ESD

Human Body Model, JESD22-A114 6

kV

Charged Device Model, JESD22-C101 2

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. Unit

TA Operating Ambient Temperature -40 +105 °C

FAN6208 • Rev. 1.0.2 5

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Electrical Characteristics

VDD=20V, TA=25°C, unless otherwise specified. All voltages are with respect to GND unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Units

VDD Section

VDD DC Supply Voltage VTH-OFF 28 V

IDD-OP1 Operating Current VDD=12V, DETL=50KHz,

CL=6nF, RRP=24K  7.0 8.5 10.0 mA

IDD-OP2 Operating Current VDD=12V, DETL=100KHz 2.4 3.2 4.0 mA

IDD-ST Startup Current VDD=8V 180 300 500 A

VTH-ON1 VTH-ON2 On Threshold Voltage 9.3 9.7 10.1 V

VTH-OFF1

VTH-OFF2 Off Threshold Voltage 8.3 8.8 9.3 V

VDD-OVP1

VDD-OVP2

VCC Over-Voltage

Protection 26 27 28 V

VDD-OVP-HYS1

VDD-OVP-HYS2

VCC Over-Voltage

Protection Hysteresis 1.3 1.8 2.3 V

tOVP1,tOVP2 VCC Over-Voltage-

Protection Debounce 30 60 100 s

DETL Section

VDETL1

VDETL2

Threshold Voltage for LOW

Detection of DETL

VDD=12V, DETL=50KHz,

CL=6nF, RRP=24K 1.7 2.0 2.3 V

tSR-ON-DETL1

tSR-ON-DETL2

Delay from DETL LOW to

SR Gate Turn-On tDB+ tPD+ tR 300 350 400 ns

VDETL-FLOATING1

VDETL-FLOATING2 DETL Floating Voltage VDD=12V, DETL Pin

Floating 4.5 V

IDETL-SOURCE1

IDETL-SOURCE2 DETL Source Current VDETL1=0V 40 50 60 A

tDETL_Green_LF1

tDETL_Green_LF2

DETL LOW Time

Threshold for Green Mode

at Low-Frequency

Operation

VRP < 1.5V 3.50 3.75 4.00 s

tDET(L)_Green_HF1

tDET(L)_Green_HF2

DETL LOW Time

Threshold for Green Mode

at High-Frequency

Operation

VRP > 1.5V 1.75 1.90 2.05 s

Thermal Shutdown

TSHUTDOWN

Shutdown Temperature Temperature Rising,

VDD=15V 140

°C

Hysteresis 20

TSTARTUP Startup Temperature Before Startup 120

Continued on the following page…

FAN6208 • Rev. 1.0.2 6

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Electrical Characteristics

VDD=20V, TA=25°C, unless otherwise specified. All voltages are with respect to GND unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Units

Gate Section

VZ1 VZ2 Gate Output Voltage

Maximum (Clamping) VDD=20V 10 12 14 V

VOL1 VOL2 Gate Output Voltage LOW VDD=12V; IO=100mA 0.5 V

VOH1VOH2 Gate Output Voltage HIGH VDD=12V; IO=100mA 9 V

tR1 tR2 Rising Time VDD=12V; CL=6nF;

VGATE=2V to 9V 30 70 120 ns

tF1 tF2 Falling Time VDD=12V; CL=6nF;

VGATE=9V to 2V 30 50 70 ns

tPD_HIGH_DETL1

tPD_HIGH_DETL2

Propagation Delay to Gate

Output HIGH (DETL

Trigger)

tR: 0V~2V, VDD=12V

(DET Floating) 120 ns

tPD_LOW_ DETL1

tPD_LOW_ DETL2

Propagation Delay to Gate

Output LOW (DETL

Trigger)

tF: 100%~90%, VDD=12V

(DET Floating) 120 ns

tON_MAX1

tON_MAX2 Maximum On-Time Trim Maximum On-Time 9.0 10.5 12.0 s

tINHIBIT_LF1

tINHIBIT_LF2

Gate Inhibit Time (from

Turn-Off to Next Turn-On) VRP < 1.5V 1.8 2.1 2.5 s

tINHIBIT_HF1

tINHIBIT_HF2

Gate Inhibit Time (from

Turn-Off to Next Turn-On) VRP > 1.5V 1.25 1.45 1.70 s

tBLANKING1

tBLANKING2

Blanking Time for SR Turn-

Off Triggered by DETL

High (Minimum On-Time)

300 ns

KR

Gate ON-Time Increase

Rate Between Two

Consecutive Cycles

tON(n) / tON(n-1) % 140 %

Timing Estimator Section

tDW

Detection Window for

Insufficient Dead Time

(from Gate Turn-Off to

DETL HIGH)

80 125 150 ns

tSHRINK-DT Gate Shrink Time by

Insufficienct Dead Time RRP=20K, tDETL=5s 1.00 1.25 1.50 s

tDEAD

Dead Time by Timing

Estimator (70kHz ~

140kHz, VRP < 1.5V)

tDETL=4s, RRP=20K 210 300 390

ns

tDETL=6s, RRP=20K 570 720 870

Dead Time by Timing

Estimator (160kHz ~

240kHz, VRP > 1.5V)

tDETL=2.5s, RRP=43K 220 320 420

tDETL=3.8s, RRP=43K 560 670 780

tDB

DETL HIGH-to-LOW

Debounce Time for Gate

Turn-on Trigger

150 ns

tSHRINK-RNG Gate Shrink by DETL

Ringing around Zero 1.2 s

tGreen_DH DETL Pull-HIGH Time

Threshold for Green Mode 18 24 30 s

Continued on the following page…

FAN6208 • Rev. 1.0.2 7

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Electrical Characteristics

VDD=20V, TA=25°C, unless otherwise specified. All voltages are with respect to GND unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Units

Feedback Detection (F D) Section

V1% V2% Feedback Increase

Threshold for Gate Shrink [(VDD-VFD)n+1/(VDD-VFD)n] 120 %

tSHRINK-FD Gate Shrink by Feedback

Detection 1.4 s

tD-SHRINK-FD Gate-Shrink Duration by

Feedback Detection 60 90 120 s

VDD-VFD.SCP

Short-Circuit Protection

(SCP) Threshold by

Feedback Detection

200 270 340 mV

tDB-SCP Debounce Time for Short-

Circuit Protection (SCP) 12 16 20 s

RP Section

IRP RP Source Current 38.5 41.5 44.5 A

VRPO RP Open Protect 3.40 3.65 3.90 V

VRPS RP Short Protect 0.25 0.30 0.35 V

tRPOS RP Open/Short Debounce 1.6 2.0 2.4 s

VRPHL H/L Frequency Threshold 1.40 1.46 1.52 V

Figure 5. tDEAD vs. tDETL RP Curve for LF Mode Figure 6. tDEAD vs. tDETL RP Curve for HF Mode

FAN6208 • Rev. 1.0.2 8

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Function Description

Operation Principle

FAN6208 is a secondary-side synchronous rectifier

controller for LLC or LC resonant converters that drive

two synchronous rectifier MOSFETs. Figure 7 is the

simplified circuit diagram of an LLC converter. The

FAN6208 determines SR MOSFET turn-on/off timing by

detecting the drain-to-source voltage of each SR

MOSFET. The key waveforms for LLC resonant

converter for below resonance and above resonance

are shown in Figure 8 and Figure 9, respectively.

Figure 7. Simplified Schematic of LLC Converter

Figure 8. Key Waveforms of LLC Resonant Converter for

Below Resonance Operation

Figure 9. Key Waveforms of LLC Resonant Converter for

Above Resonance Operati on

Timing Estimator

Figure 10 shows the timing diagram for FAN6208. Once

the body diode of SR begins conducting, the drain-to-

source voltage drops to zero, which causes DETL pin

voltage to drop to zero. FAN6208 turns on the MOSFET

after tON-ON-DETL (about 350ns), when voltage on DETL

drops below 2V. As depicted in Figure 11, the turn-on

delay (after tSR-ON-DETL) is the sum of debounce time

(150ns) and propagation delay (200ns).

FAN6208 measures the SR conduction duration (tDETL),

during which DETL stays lower than 2V, and uses this

information to determine the turn-off instant of SR gates

of the next switching cycle. The turn-off timing is

obtained by subtracting a dead time (tDEAD) from the

measured SR conduction duration of the previous

switching cycle. The dead time can be programmed

using a resistor on the RP pin and the relationship

between the dead time and SR conduction duration

(tDETL) for different resistor values on RP pin is given in

Figure 5.

FAN6208 • Rev. 1.0.2 9

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

VDET

VGATE

2V

VGATE

tDETL (n) - tDEAD

tDETL (n+1)

tSR-ON-DETL

tDETL (n-1) - tDEAD

tDETL (n)

tSR-ON-DETL

Figure 10. SR Gate Timing Diagram

Figure 11. DETL Debounce (Blanking) Time

Gate-Shrink Functions

In normal operation, the turn-off instant is determined by

subtracting a dead time (tDEAD) from the measured SR

conduction duration of the previous switching cycle, as

shown in Figure 10. This allows proper driving timing for

SR MOSFETS when the converter is in steady state and

the switching frequency does not change much.

However, this control method may cause shoot-through

of SR MOSFETs when the switching frequency

increases fast and switching transition of the primary-

side MOSFETs takes place before the turn-off

command of SR is given. To prevent the shoot-through,

FAN6208 has gate-shrink functions. Gate shrink occurs

under three conditions:

(a) When insufficient dead time is detected in the

previous switching cycle. When the DETL goes

HIGH within 125ns of detection window after SR

gate is turned off, the SR gate drive signal in the

next switching cycle is reduced by tSHRINK-DT (about

1.25µs) to increase the dead time, as shown in

Figure 12.

VDET

VGATE

2V

VGATE

tDETL_LOW (n) –tDEAD–tSHRINK

tDETL_LOW (n+1)

125ns

tDETL_LOW (n-1) - tDEAD

tDETL_LOW (n)

Detection window Shrink

Figure 12. Gate Shrink by Minimum Dead Time

Detection Window

(b) When the feedback information changes fast.

FAN6208 monitors the current through the opto-

coupler diode by measuring the voltage across the

resistor in series with the opto-coupler diode, as

depicted in Figure 13. If the feedback current

through the opto-coupler diode increases by more

than 20% of the feedback current of the previous

switching cycle, the SR gate signal is shrunk by

tSHRINK-FD (about 1.4µs) for tD-SHRINK-FD (about 90µs),

as shown in Figure 14.

Figure 13. Typical Application Circuit

FAN6208 • Rev. 1.0.2 10

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Figure 14. Gate Shrin k by Feed b ack Detection

(c) When the DETL voltage has ringing around zero. As

depicted in Figure 8, the drain voltage of SR has

ringing around zero at light-load condition after the

switching transition of the primary-side switches.

When DETL voltage rises above 2V within 350ns

after DETL voltage drops to zero and stays above

2V longer than 150ns, the gate is shrunk by 1.2µs

(tSHRINK-RNG), as shown in Figure 15.

Figure 15. Gate Shrink by DETL Voltage

Ringing Around Zero

RP Pin Function

The RP pin programs the level of green mode and tDEAD.

Figure 16 shows how the mode is selected by the

voltage on the RP pin (open protection, short protection,

and HF/LF mode). When RRP is less than 36K,

FAN6208 operates in low-frequency mode. Green mode

is enabled when tDETL is smaller than 3.75µs. When RRP

is larger than 36K, high-frequency mode is selected

and green mode is enabled for tDETL < 1.90µs. tDEAD can

be also adjusted by a resistor on the RP pin. Figure 5

shows the relationship between tDEAD and tDETL for

different RP resistors.

Figure 16. RP Pin Operation

To handle abnormal conditions for IC pins, the RP pin

also provides open/short protection. When VRP is less

than VRPS (0.3V) or VRP is higher than VRPO (3.65V), the

protection is triggered. Figure 17 shows the RP pin short

protection timing sequence. If VRP < VRPS (0.3V) for

longer than tRPOS (2µs), FAN6208 is disabled. Figure 18

shows the RP pin open protection timing sequence. If

VRP > VRPO (3.65V) for longer than tRPOS (2µs), FAN6208

is disabled.

Figure 17. RP Pin Short Protection

RP

VRPO

tRPOS tRPOS

GATE1

DETL1

GATE2

DETL2

Soft-Start Area

RP Open Protection Area

VRP = IRP×RRP

Figure 18. RP Pin Open Protection

FAN6208 • Rev. 1.0.2 11

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Green Mode

Switching frequency increases in LLC topology at light-

load condition, which increases the power consumption

for the SR gate drive. Green mode reduces power loss

at light load. FAN6208 has two ways to enable green

mode. Green mode is triggered when DETL voltage is

pulled LOW for less than 3.75µs (LF mode) or 1.90µs

(HF mode) for seven switching cycles. FAN6208

resumes normal SR gate driving when DETL voltage is

pulled LOW for longer than 3.75µs (LF mode) or 1.90µs

(HF mode) for seven switching cycles.

When DETL voltage is pulled HIGH for longer than

24µs. This occurs when the LLC resonant converter

operates in burst mode (skipping mode).

Short-Circuit Protection

As depicted in Figure 13, FAN6208 monitors the current

through the opto-coupler diode by measuring the

voltage across the resistor in series with the opto-

coupler diode. When the output of the power supply is

short circuited, the output voltage drops and the cathode

of the shunt regulator (KA431) is saturated to HIGH. No

current flows through the opto coupler diode. The output

short protection is triggered when the voltage between

VDD and FD is smaller than 0.3V, as shown in Figure 19.

Figure 19. Outpu t Short Protection by Feedback

Detection

VDD Pin Over-Voltage Protection

Over-voltage conditions are usually caused by an open

feedback loop. VDD over-voltage protection prevents

damage of SR MOSFET. When the voltage on the VDD

pin exceeds 27V, FAN6208 disables gate output.

Internal Over-Temperature Protection

Internal over-temperature protection prevents the SR

gate from fault triggering in high temperatures. If the

temperature is over 140°C, the SR gate is disabled until

the temperature drops below 120°C.

FAN6208 • Rev. 1.0.2 12

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Typical Performance Characteristics

Figure 20.

V

TH_ON1 vs. TA Figure 21.

V

TH_ON2 vs. TA

Figure 22.

V

TH_OFF1 vs. TA Figure 23.

V

TH_OFF2 vs. TA

Figure 24. IDD_ST vs. TA Figure 25. IDD_OP1 vs. TA

FAN6208 • Rev. 1.0.2 13

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Typical Performance Characteristics (Continued)

Figure 26. tSR_ON_DETL1 vs. TAFigure 27. tSR_ON_DETL2 vs. TA

Figure 28.

V

Z1 vs. TA Figure 29.

V

Z2 vs. TA

Figure 30.

V

DETL1 vs. TA Figure 31.

V

DETL2 vs. TA

FAN6208 • Rev. 1.0.2 14

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Typical Performance Characteristics (Continued)

Figure 32. tDW1 vs. TA Figure 33. tDW2 vs. T A

Figure 34.

V

SHRINK_DT1 vs. T AFigure 35.

V

SHRINK_DT2 vs. T A

Figure 36. IDETL_Source1 vs. TAFigure 37. IDETL_Source2 vs. TA

FAN6208 • Rev. 1.0.2 15

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Typical Performance Characteristics (Continued)

Figure 38. tDEAD1 (RRP=20k, 6µs) vs. TA Figure 39. tDEAD2 (RRP=20k, 6µs) vs. TA

Figure 40. tDEAD1 (RRP=43k, 2.5µs) vs. TA Figure 41. tDEAD2 (RRP=43k, 2.5µs) vs. TA

Figure 42. IRP vs. T A Figure 43.

V

RPHL vs. TA

FAN6208 • Rev. 1.0.2 16

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Typical Application Circuit (LLC Converter with SR)

Application Fairchild Devices Input Voltage Range Output

TV Power FAN7621

FAN6208 350~400VDC 24V/8A

Figure 44. Application Circuit

FAN6208 • Rev. 1.0.2 17

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology

Physical Dimensions

Figure 45. 8-Lead, SOIC, JEDEC MS-012, .150-Inch Narrow Body

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

8°

0°

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08AREV13

LAND PATTERN RECOMMENDATION

SEATING PLANE

0.10 C

C

GAGE PLANE

x 45°

DETAIL A

SCALE: 2:1

PIN ONE

INDICATOR

4

8

1

C

MBA0.25

B

5

A

5.60

0.65

1.75

1.27

6.20

5.80

3.81

4.00

3.80

5.00

4.80

(0.33)

1.27

0.51

0.33

0.25

0.10

1.75 MAX

0.25

0.19

0.36

0.50

0.25

R0.10

0.90

0.406 (1.04)

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

FAN6208 • Rev. 1.0.2 18

FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology