1
LTC4230
4230f
■
Allows Safe Board Insertion and Removal
from a Live Backplane
■
Controls Three Supply Voltages from 1.7V to 16.5V
with V
CC1
≥ V
CC2
≥ V
CC3
■
Programmable Soft-Start with Inrush Current
Limiting, No External Gate Capacitor Required
■
Faster Turn-Off Time with No Gate Capacitor
■
Dual Level Overcurrent Fault Protection
■
Programmable Overcurrent Response Time
■
Programmable Overvoltage Protection
■
Automatic Retry or Latched Mode Operation
■
Independent N-Channel FET High Side Drivers
■
User-Programmable Supply Voltage Power-Up Rate
■
FB
n
Pin Monitors V
OUT
n
and Signals RESET
n
■
Glitch Filter Eliminates Spurious RESET
n
Signals
The LTC
®
4230 is a 3-channel Hot Swap
TM
controller that
allows a board to be safely inserted and removed from a
live backplane. Internal high side switch drivers control
the gates of external N-channel MOSFETs for supply
voltages ranging from 1.7V to 16.5V. The LTC4230 pro-
vides soft-start and inrush current limiting during the
programmable start-up period.
On-chip current limit comparators provide dual level
circuit breaker protection. The slow comparators trip at
VCC
n
– 50mV and activate in 10µs or are programmed by
an external filter capacitor. The fast comparators trip at
VCC
n
– 150mV and typically respond in 500ns.
Each FB
n
pin monitors its own output supply voltage and
signals its RESET pin. The ON pin turns the chip on and
off and can be used for a reset function. The LTC4230 also
provides additional functions including fault indication,
autoretry or latchoff modes, programmable current limit
response time based on the FAULT and FILTER pins’
functionality.
■
Electronic Circuit Breaker
■
Hot Board Insertion and Removal (Either On
Backplane or On Removable Card)
■
Industrial High Side Switch/Circuit Breaker
Triple Hot Swap Controller
with Multifunction Current Control
, LTC and LT are registered trademarks of Linear Technology Corporation.
3-Channel Hot Swap Controller
Hot Swap is a trademark of Linear Technology Corporation.
RSENSE2
0.007Ω
CX2
100nF
CX1
100nF
RX2
10Ω
Q2
IRF7413
VCC1
ON
FAULT
GND
LTC4230
15
67 8161718543
FB3 1
13
14
12
11
SENSE 1 GATE 1 VCC2 SENSE 2 GATE 2 SENSE 3 GATE 3VCC3
RESET 3 2
RSENSE3
0.007Ω
RX1
10Ω
R8
5.1k
R9
12k
Q3
IRF7413
VOUT1
3.3V
5A
VOUT2
2.5V
5A
VOUT3
1.8V
5A
RSENSE1
0.007Ω
CX3
100nF
RX3
10Ω
CTIMER*
0.1µFCFILTER**
15pF
Q1
IRF7413
Z3***
Z2***
Z1***
* SYSTEM ON TIME: 6.2ms
**CIRCUIT BREAKER RESPONSE TIME: 19.5µs
***OPTIONAL
Z1, Z2, Z3: SMAJ10
RESET 2 19
FB2 20
R7
10k
RESET 1 9
FB1 10
R10
11k
R11
12k R6
10k
R12
18k
R13
12k
4230 TA01
R5
10k
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
VCC1
3.3V
LONG
VCC2
2.5V
LONG
VCC3
1.8V
LONG
SHORT
FAULT
GND LONG
SHORT
R2
10k
R1
10k
PCB CONNECTION SENSE RESET 3
TIMER
FILTER
RESET 2
RESET 1
APPLICATIO S
U
FEATURES
TYPICAL APPLICATIO
U
DESCRIPTIO
U
2
LTC4230
4230f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
Supply Voltage (V
CC1
)●2.700 16.5 V
Supply Voltage (V
CC2
)V
CC2
≤ V
CC1
●2.375 16.5 V
Supply Voltage (V
CC3
)V
CC3
≤ (V
CC1
– 1V) ●1.700 15.5 V
I
CC
Supply Current (I
CC1
) ON = V
CC1
, FB1 = High ●1.8 3 mA
Supply Current (I
CC2
) ON = V
CC1
, FB2 = High ●75 150 µA
Supply Current (I
CC3
) ON = V
CC1
, FB3 = High ●65 150 µA
V
LKO1
Undervoltage Lockout , Channel 1 V
CC1
Low to High Transition ●2.15 2.35 2.52 V
V
LKO2
Undervoltage Lockout , Channel 2 V
CC2
Low to High Transition ●1.98 2.15 2.32 V
V
LKO3
Undervoltage Lockout , Channel 3 V
CC3
Low to High Transition ●1.09 1.19 1.29 V
V
LKOHST1
Undervoltage Lockout Hysteresis, Channel 1 100 mV
V
LKOHST2
Undervoltage Lockout Hysteresis, Channel 2 45 mV
V
LKOHST3
Undervoltage Lockout Hysteresis, Channel 3 35 mV
I
IN, FB
n
FB
n
Pin Input Current 0V ≤ V
FB
n
≤ V
CC
n
●±0.1 ±10 µA
I
IN, ON
ON Pin Input Current 0V ≤ V
ON
≤ V
CC1
●±0.1 ±10 µA
I
IN, SENSE
n
Input Current for SENSE
n
0V ≤ V
SENSE
n
≤ V
CC
n
●±0.1 ±15 µA
V
CB(FAST)
Circuit Breaker
n
Trip Voltage Fast Comparator ●135 150 165 mV
V
CB(SLOW)
Slow Comparator ●40 50 60 mV
I
GATE
n
, UP
GATE
n
Pull-Up Current Charge Pump On, 0 ≤ V
GATE
n
< 0.2V ●–12.5 –10 –6.5 µA
I
GATE
n
, DN
Normal GATE
n
Pull-Down Current ON Low, V
GATE
n
= 5V 200 µA
Fast GATE
n
Pull-Down Curent FAULT Latched and Circuit Breaker 16 mA
Tripped or in UVLO, V
GATE
n
= 5V
I
LEAK
RESET
n
Leakage Current V
RESET
n
= 15V, Pull-Down Device Off ●±0.1 ±2.5 µA
T
JMAX
= 125°C, θ
JA
= 95°C/ W
ORDER PART
NUMBER
Supply Voltage (V
CC
n
) ............................................. 17V
SENSE
n
Pins ............................... –0.3V to (V
CC
+ 0.3V)
FB
n
, ON Pins ............................... –0.3V to (V
CC
+ 0.3V)
TIMER Pin ...................................................–0.3V to 2V
GATE
n
Pins........................... Internally Limited (Note 3)
RESET
n
, FAULT, FILTER Pins ....................–0.3V to 17V
Operating Temperature Range
LTC4230C ............................................... 0°C to 70°C
LTC4230I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
LTC4230CGN
LTC4230IGN
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
(Note 1)
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC1 = 3.3V, VCC2 = 2.5V,VCC3 = 1.8V unless otherwise noted. (Note 2)
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
1
2
3
4
5
6
7
8
9
10
TOP VIEW
GN PACKAGE
20-LEAD PLASTIC SSOP
20
19
18
17
16
15
14
13
12
11
FB3
RESET 3
GATE 3
SENSE 3
V
CC3
V
CC1
SENSE 1
GATE 1
RESET 1
FB1
FB2
RESET 2
GATE 2
SENSE 2
V
CC2
ON
GND
FAULT
TIMER
FILTER
3
LTC4230
4230f
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC1 = 3.3V, VCC2 = 2.5V,VCC3 = 1.8V unless otherwise noted. (Note 2)
ELECTRICAL CHARACTERISTICS
∆V
GATE
n
External N-Channel Gate Drive V
GATE1, 2
– V
CC1, 2
(for V
CC1, 2
= 2.7V, V
CC3
= V
CC1
– 1V) ●4.5 8 V
V
GATE3
– V
CC3
(for V
CC1, 2
= 2.7V, V
CC3
= V
CC1
– 1V) ●5.5 9 V
V
GATE1, 2
– V
CC1, 2
(for V
CC1, 2
= 3.3V, V
CC3
= V
CC1
– 1V) ●510V
V
GATE3
– V
CC3
(for V
CC1, 2
= 3.3V, V
CC3
= V
CC1
– 1V) ●611V
V
GATE
n
– V
CC
n
(for V
CC1, 2
= 5V, V
CC3
= V
CC1
– 1V) ●916V
V
GATE
n
– V
CC
n
(for V
CC1, 2
= 12V or 15V, ●718V
V
CC3
= V
CC1
– 1V)
V
GATE
n
, 0V
GATE
n
Overvoltage Lockout 0.25 V
Threshold
V
FB
n
FB
n
Low Threshold Voltage FB
n
High to Low Transition ●1.209 1.234 1.259 V
∆V
FB
n
FB
n
Line Regulation 2.7V ≤ V
CC1
≤ 16.5V 0.5 mV
V
FB
n
, HST
FB
n
Hysteresis 3mV
V
ONHI
ON High Threshold Voltage ON Low to High Transition ●1.250 1.314 1.380 V
V
ONLO
ON Low Threshold Voltage ON High to Low Transition ●1.172 1.234 1.270 V
V
ONHST
ON Hysteresis 80 mV
I
FILTER
FILTER Pull-Up Current During Slow Fault Condition ●–2.5 –2 –1.3 µA
FILTER Pull-Down Current During Normal and Reset Conditions ●71013 µA
V
FILTER
FILTER Threshold Latched Off Threshold, FILTER Low to High ●1.10 1.26 1.42 V
V
FILTERHST
FILTER Threshold Hysteresis –70 mV
I
TMR
TIMER Pull-Up Current TIMER On ●–23 –20 –17 µA
TIMER Pull-Down Current TIMER Off, V
FAULT
= Low ●0.9 1.6 2.3 µA
V
TIMER
= 1.5V 2.5 mA
V
TMR
TIMER Threshold TIMER Low to High ●1.172 1.234 1.27 V
TIMER High to Low ●0.3 0.5 V
V
FAULT
FAULT Low Threshold Voltage FAULT High to Low ●1.172 1.234 1.27 V
V
FAULT, HST
FAULT Hysteresis FAULT Low to High 50 mV
I
FAULT, UP
FAULT Pull-Up Current ●–2.5 –2 –1.5 µA
V
OLFAULT
Output Low Voltage I
FAULT
= 1.6mA, V
CC1
= 5V ●0.19 0.4 V
V
OLRESET
n
Output Low Voltage I
RESET
n
= 1.6mA, V
CC1
= 5V ●0.19 0.4 V
t
GATEFC
Fast COMP
n
Trip to V
CB
= 0mV to 200mV Step ●0.5 1 µs
GATE
n
Discharging
t
FAULTSC
Slow Comparator Trip to V
CB
= 0mV to 100mV Step, FILTER Floating 10 µs
FILTER High and FAULT Latched 10nF at FILTER Pin to GND ●712 ms
t
OVPFTR
FILTER Comparator Trip to V
FILTER
= 0V to 5V ●812 µs
GATE
n
Discharging
t
EXTFAULT
FAULT Low to GATE Discharging V
FAULT
= 5V to 0V ●1.5 3 4.5 µs
t
RESET
Circuit Breaker Reset Time ON Held Low to Guarantee FAULT High ●15 30 µs
t
OFF
Turn-Off Time ON Goes Low to GATE
n
Off 8 µs
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All current into device pins is positive; all current out of device
pins is negative; all voltages are referenced to ground unless otherwise
specified.
Note 3: An internal zener at the GATE
n
pin clamps the charge pump
voltage to a typical maximum operating voltage of 26V. External overdrive
of the GATE
n
pin beyond the internal zener voltage may damage the part.
The GATE
n
capacitance must be <0.15µF at maximum V
CC
. If a lower
GATE
n
pin voltage is desired, use an external zener diode.
4
LTC4230
4230f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VCC1 SUPPLY VOLTAGE (V)
24 6 8 10 12 14 16 18
SUPPLY CURRENT (mA)
4230 G01
8
7
6
5
4
3
2
1
0
VCC2 = 2.5V
VCC3 = 1.8V
–40°C
25°C
85°C
SUPPLY VOLTAGE (V)
24 6 8 10 12 14 16 18
SUPPLY CURRENT (mA)
4230 G02
0.6
0.5
0.4
0.3
0.2
0.1
0
–40°C
25°C
85°C
CHANNEL 3
CHANNEL 2
TEMPERATURE (°C)
–75
UNDERVOLTAGE LOCKOUT THRESHOLD
VOLTAGE (V)
125
4230 G03
–25 25 75
–50 150
050 100
2.5
2.2
1.9
1.6
1.3
1.0
V
CC3
HIGH
V
CC1
HIGH
V
CC1
LOW
V
CC2
HIGH
V
CC2
LOW
V
CC3
LOW
TEMPERATURE (°C)
–75
FB
n
PIN INPUT CURRENT (nA)
125
4230 G04
–25 25 75
–50 150
050 100
5
4
3
2
1
0
V
FB
n
= 5V
TEMPERATURE (°C)
–75
ON PIN INPUT CURRENT (nA)
125
4230 G05
–25 25 75
–50 150
050 100
6
5
4
3
2
1
0
V
ON
= 5V
TEMPERATURE (°C)
–75
SENSE
n
INPUT CURRENT (nA)
125
4230 G06
–25 25 75
–50 150
050 100
100
90
80
70
60
50
40
30
20
10
0
V
SENSE
n
= 5V
TEMPERATURE (°C)
–75
ON THRESHOLD VOLTAGE (V)
125
4230 G07
–25 25 75
–50 150
050 100
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
V
CC1
= 3.3V
V
CC2
= 2.5V
V
CC3
= 1.8V
ON PIN HIGH
ON PIN LOW
V
CC1
SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
FAST COMPARATOR TRIP VOLTAGE (mV)
4230 G08
152.0
151.5
151.0
150.5
150.0
149.5
149.0
148.5
148.0
–40°C
25°C
85°C
V
CC1
SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
SLOW COMPARATOR TRIP VOLTAGE (mV)
4230 G09
52.0
51.5
51.0
50.5
50.0
49.5
49.0
–40°C
25°C
85°C
Channel 1 Supply Current vs VCC1
Supply Voltage
FB
n
Pin Input Current vs
Temperature
ON Threshold vs Temperature
Channels 2 and 3 Supply Current
vs Supply Voltage UVLO Threshold Voltage vs
Temperature
ON Pin Input Current vs
Temperature SENSE
n
Input Current vs
Temperature
Fast Comparator Threshold vs
VCC1 Supply Voltage Slow Comparator Threshold vs
VCC1 Supply Voltage
5
LTC4230
4230f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VCC1 SUPPLY VOLTAGE (V)
24 6 8 10 12 14 16 18
GATE PULL-DOWN CURRENT (µA)
4230 G10
280
260
240
220
200
180
160
140
120
VCC2 = 2.5V
VCC3 = 1.8V
VGATE
n
= 2.5V
–40°C
25°C
85°C
VCC1 SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
FAST PULL-DOWN CURRENT (mA)
4230 G11
20
18
16
14
12
10
VCC2 = 2.5V
VCC3 = 1.8V
VGATE
n
= 5V
–40°C
25°C
85°C
VCC1 SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
IGATE CURRENT (µA)
4230 G12
12
11
10
9
8
7
6
–40°C
25°C
85°C
VCC1 SUPPLY VOLTAGE (V)
24 6 8 10 12 14 16 18
∆VGATE VOLTAGE (V)
4230 G13
16
14
12
10
8
6
4
2
0
VCC2 = VCC1
VCC3 = VCC1 – 1V
VGATE1 = VGATE2
VGATE3
TEMPERATURE (°C)
–75
V
GATE
– V
CC1
VOLTAGE (V)
125
4230 G14
–25 25 75
–50 150
050 100
16
14
12
10
8
6
4
V
CC1
= 15V
V
CC1
= 5V
V
CC1
= 12V
V
CC1
= 3.3V
V
CC1
= 2.7V
TEMPERATURE (°C)
–75
GATE OVERVOLTAGE LOCKOUT THRESHOLD (V)
125
4230 G15
–25 25 75
–50 150
050 100
0.5
0.4
0.3
0.2
0.1
0
V
CC1
= 3.3V
V
CC2
= 2.5V
V
CC3
= 1.8V
VCC1 SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
4230 G16
0.5
0.4
0.3
0.2
0.1
0
GATE OVERVOLTAGE LOCKOUT THRESHOLD (V)
VCC2 = 2.5V
VCC3 = 1.8V
TEMPERATURE (°C)
–75
V
FB
THRESHOLD VOLTAGE (V)
125
4230 G17
–25 25 75
–50 150
050 100
1.239
1.238
1.237
1.236
1.235
1.234
1.233
1.232
V
FB
n
HIGH
V
FB
n
LOW
V
CC1
= 3.3V
V
CC2
= 2.5V
V
CC3
= 1.8V
V
CC1
SUPPLY VOLTAGE (V)
FB THRESHOLD VOLTAGE (V)
4230 G18
1.238
1.237
1.236
1.235
1.234
1.233 0 2 4 6 8 10 12 14 16 18
FB HIGH
FB LOW
Normal GATE
n
Pull-Down Current
vs VCC1 Supply Voltage
VGATE
n
– VCC
n
vs VCC1 Supply
Voltage
GATE
n
Overvoltage Lockout
Threshold vs VCC1 Supply Voltage
Fast GATE
n
Pull-Down Current vs
VCC1 Supply Voltage GATE
n
Output Source Current
(Pull-Up) vs VCC1 Supply Voltage
VGATE1 – VCC1 vs Temperature GATE
n
Overvoltage Lockout
Threshold vs Temperature
VFB
n
Threshold Voltage vs
Temperature VFB
n
Threshold Voltage vs VCC1
Supply Voltage
6
LTC4230
4230f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
–75
I
FILTER
CURRENT LOW (µA)
125
4230 G19
–25 25 75
–50 150
050 100
–1.6
–1.8
–2.0
–2.2
–2.4
–2.6
V
CC1
= 3.3V
V
CC1
= 2.7V V
CC1
= 5V
V
CC1
= 16.5V V
CC1
= 12V
V
CC2
= 2.5V
V
CC3
= 1.8V
TEMPERATURE (°C)
–75
I
FILTER
CURRENT (µA)
125
4230 G20
–25 25 75
–50 150
050 100
12.0
11.2
10.4
9.6
8.8
8.0
V
CC2
= 2.5V
V
CC3
= 1.8V
V
CC1
= 16.5V
V
CC1
= 12V
V
CC1
= 5V
V
CC1
= 2.7V
V
CC1
= 3.3V
TEMPERATURE (°C)
–75
I
FILTER
THRESHOLD VOLTAGE (V)
125
4230 G21
–25 25 75
–50 150
050 100
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
V
CC2
= 2.5V
V
CC3
= 1.8V
V
CC1
= 16.5V
V
CC1
= 12V
V
CC1
= 5V V
CC1
= 2.7V
V
CC1
= 3.3V
V
CC1
= 16.5V
V
CC1
= 3.3V
V
CC1
= 12V
V
CC1
= 2.7V
I
FILTER
LOW
I
FILTER
HIGH
V
CC1
= 5V
V
CC1
SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
FAULT THRESHOLD VOLTAGE (V)
4230 G22
1.29
1.28
1.27
1.26
1.25
1.24
1.23
–40°C
–40°C
25°C
85°C
85°C
HIGH THRESHOLD
LOW THRESHOLD
25°C
VCC1 SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
FAULT PULL-UP CURRENT (µA)
4230 G23
2.5
2.3
2.1
1.9
1.7
1.5
–40°C
85°C
25°C
VCC1 SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
TIMER PULL-UP CURRENT (µA)
4230 G24
23
22
21
20
19
18
17
–40°C
85°C
25°C
VCC1 SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
TIMER PULL-DOWN CURRENT (µA)
4230 G25
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
–40°C
85°C
25°C
VCC1 SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
TIMER PULL-DOWN CURRENT (mA)
4230 G26
9
8
7
6
5
4
3
2
1
0
–40°C
VTIMER = 1.5V
85°C
25°C
V
CC1
SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
TIMER HIGH THRESHOLD (V)
4230 G27
1.237
1.236
1.235
1.234
1.233
1.232
1.231
1.230
–40°C
85°C
25°C
FILTER Pull-Up Current vs
Temperature
FAULT Threshold Voltage vs VCC1
Supply Voltage
TIMER Pull-Down Current (After
Second Cycle) vs VCC1 Supply
Voltage
FILTER Pull-Down Current vs
Temperature FILTER Threshold Voltage vs
Temperature
TIMER Pull-Up Current (During
First Cycle) vs VCC1 Supply
Voltage
TIMER Fast Pull-Down (End of the
First Cycle) Current vs VCC1
Supply Voltage TIMER High Threshold vs VCC1
Supply Voltage
FAULT Pull-Up Current vs VCC1
Supply Voltage
7
LTC4230
4230f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
V
CC1
SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
TIMER LOW THRESHOLD (V)
4230 G28
0.32
0.31
0.30
0.29
0.28
–40°C
85°C
25°C
V
CC1
SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
V
OL
VOLTAGE (V)
4230 G29
0.25
0.20
0.15
0.10
0.05
0
TEMPERATURE (°C)
V
OL
VOLTAGE (V)
4230 G30
0.25
0.22
0.19
0.16
0.13
0.10
–75 125
–25 25 75
–50 150
050 100
VCC1 SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
FAST COMPARATOR RESPONSE TIME (µs)
4230 G31
650
600
550
500
450
400
350
300
–40°C
85°C
25°C
V
CC1
SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
SLOW COMPARATOR RESPONSE TIME (µs)
4230 G32
14
13
12
11
10
9
8
7
6
–40°C
85°C25°C
VCC1 SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
FILTER COMPARATOR RESPONSE TIME (µs)
4230 G33
10
9
8
7
6
–40°C
85°C
25°C
V
CC1
SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
FAULT LOW TO GATE
n
DISCHARGING (µs)
4230 G34
5
4
3
2
1
0
–40°C
85°C
25°C
VCC1 SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
CIRCUIT BREAKER RESET TIME (µs)
4230 G35
20
18
16
14
12
10
–40°C
85°C
25°C
V
CC1
SUPPLY VOLTAGE (V)
02 4 6 8 10 12 14 16 18
TURN-OFF TIME (µs)
4230 G36
11
10
9
8
7
6
5
–40°C
85°C
25°C
TIMER Low Threshold vs VCC1
Supply Voltage
Fast Comparator Response Time
vs VCC1 Supply Voltage
FAULT Low to GATE
n
Discharging
vs VCC1 Supply Voltage
VOL (RESET
n
, FAULT) vs VCC1
Supply Voltage
Slow Comparator Response Time
(FILTER Floating) vs VCC1 Supply
Voltage FILTER Comparator Response
Time vs VCC1 Supply Voltage
Circuit Breaker Reset Time vs
VCC1 Supply Voltage Turn-Off Time vs VCC1 Supply
Voltage
VOL (RESET
n
, FAULT) vs
Temperture
8
LTC4230
4230f
FB3 (Pin 1): The FB3 (Feedback) pin is an input to the
FBCOMP3 comparator which monitors the V
CC3
output
supply voltage through an external resistor divider. If V
FB3
< 1.234V, RESET 3 pin pulls low. An internal glitch filter at
FBCOMP3’s output prevents triggering a reset condition
due to negative voltage transients. If V
FB3
> 1.237V,
RESET 3 pin goes high after exiting undervoltage lockout.
RESET 3 (Pin 2): An open-drain N-channel device whose
source connects to GND (Pin 14). This pin pulls low if the
voltage at FB3 (Pin 1) falls below the FB3 threshold
(1.234V). This pin requires an external pull-up resistor to
V
OUT3
. If an undervoltage lockout condition occurs,
RESET␣ 3 pulls low independently of FB3 to prevent false
glitches.
GATE 3 (Pin 3): The output signal at this pin is the high side
gate drive for Channel 3’s external N-channel MOSFET
pass transistor. An internal charge pump produces a 4.5V
(minimum) to 18V (maximum) gate drive voltage for V
CC1
supply voltages from 2.7V to 16.5V, respectively.
As shown in the Block Diagram for each channel, an
internal charge pump supplies a 10µA gate current and
sufficient gate voltage drive to the external MOSFET. The
internal charge pump produces a minimum 4.5V gate
drive for V
CC1
< 4.75V. For V
CC1
> 4.75V, the minimum
gate voltage drive is 9V. For V
CC1
≥ 12V, the minimum gate
voltage drive is 7V which is set by an internal zener diode
clamp connected between the GATE 3 pin and GND.
SENSE 3 (Pin 4): Circuit Breaker Sense Pin for Channel 3.
With a sense resistor placed in the power path between
V
CC3
and SENSE 3, Channel 3’s electronic circuit breaker
trips if the voltage across the sense resistor (V
CC3
–
V
SENSE3
) exceeds the thresholds set internally for SLOW
COMP3 and FAST COMP3, as shown in the Block Diagram.
The threshold for SLOW COMP3 is V
CB(SLOW)
= 50mV, and
the electronic circuit breaker trips if the voltage across
R
SENSE3
exceeds 50mV for 10µs, or for the time delay
programmed by C
FILTER
. To adjust SLOW COMP3’s delay,
please refer to the section on Adjusting SLOW COMP
n
’s
Response Time.
Under transient conditions where large step current
changes can and do occur over shorter periods of time, a
PI FU CTIO S
UUU
second (fast) comparator instead trips the electronic
circuit breaker. The threshold for FAST COMP3 is set at
V
CB(FAST)
= 150mV, and the circuit breaker trips if the
voltage across the R
SENSE3
exceeds 150mV for more than
500ns. FAST COMP3’s delay is fixed in the LTC4230 and
cannot be adjusted. To disable Channel 3’s electronic
circuit breaker, connect the V
CC3
and SENSE 3 pins
together.
V
CC3
(Pin 5): Positive Supply Input for Channel 3. V
CC3
operates from 1.7V to 15.5V (V
CC3
≤ V
CC1
– 1V) and its
supply current, I
CC3
, is typically 65µA. The master UVLO
circuit disables all three GATE
n
outputs of the LTC4230
until the voltage at V
CC3
exceeds 1.19V.
V
CC1
(Pin 6): This is the positive supply input to the
LTC4230, the power supply input for Channel 1, and the
power supply input for all three internal charge pumps.
The LTC4230 operates from 2.7V to 16.5V, and the I
CC1
supply current is typically 1.8mA. The master UVLO circuit
disables all three GATE
n
outputs of the LTC4230 if V
CC1
is
less than 2.35V. The internal charge pump outputs are
enabled when V
CC1
> 2.35V, V
CC2
> 2.15V, and
V
CC3
> 1.19V.
SENSE 1 (Pin 7): Circuit Breaker Sense Pin for Channel 1.
With a sense resistor placed in the power path between
V
CC1
and SENSE 1, Channel 1’s electronic circuit breaker
trips if the voltage across the sense resistor (V
CC1
–
V
SENSE1
) exceeds the thresholds set internally for SLOW
COMP1 and FAST COMP1, as shown in the Block Diagram.
The threshold for SLOW COMP1 is V
CB(SLOW)
= 50mV, and
the electronic circuit breaker trips if the voltage across
R
SENSE1
exceeds 50mV for 10µs, or for the time delay
programmed by C
FILTER
. To adjust SLOW COMP1’s delay,
please refer to the section on Adjusting SLOW COMP
n
’s
Response Time.
Under transient conditions where large step current changes
can and do occur over shorter periods of time, a second
(fast) comparator instead trips the electronic circuit breaker.
The threshold for FAST COMP1 is set at V
CB(FAST)
= 150mV,
and the circuit breaker trips if the voltage across the
R
SENSE1
exceeds 150mV for more than 500ns. FAST
COMP1’s delay is fixed in the LTC4230 and cannot be
adjusted. To disable Channel 1’s electronic circuit breaker,
connect the V
CC1
and SENSE 1 pins together.
9
LTC4230
4230f
PI FU CTIO S
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GATE 1 (Pin 8): The output signal at this pin is the high side
gate drive for Channel 1’s external N-channel FET pass
transistor. An internal charge pump produces a 4.5V
(minimum) to 18V (maximum) gate drive voltage for
supplies in the range of 2.7V ≤ V
CC1
≤ 16.5V, respectively.
As shown in the Block Diagram, each channel’s internal
charge pump is powered by V
CC1
and supplies a 10µA gate
current and sufficient gate voltage drive to the external
FET. The internal charge pump produces a minimum 4.5V
gate voltage drive for V
CC1
< 4.75V. For V
CC1
> 4.75V, the
minimum gate voltage drive is 9V. For V
CC1
≥ 12V, the
minimum gate voltage drive is 7V which is set by an
internal zener diode clamp connected between the GATE 1
pin and GND.
RESET 1 (Pin 9): An open-drain N-channel device whose
source connects to GND (Pin 14). This pin pulls low if the
voltage at FB1 (Pin 10) falls below the FB1 threshold
(1.234V). During the start-up cycle, RESET 1 goes high
impedance at the end of the second timing cycle after FB1
goes above the FB1 threshold. This pin requires an exter-
nal pull-up resistor to V
OUT1
. If an undervoltage lockout
condition occurs, RESET 1 pulls low independently of FB1
to prevent false glitches.
FB1 (Pin 10): The FB1 (Feedback) pin is an input to the
FBCOMP1 comparator which monitors the V
CC1
output
supply voltage through an external resistor divider. If V
FB1
< 1.234V, RESET 1 pin pulls low. An internal glitch filter at
FBCOMP3’s output prevents triggering a reset condition
due to negative voltage transients. If V
FB1
> 1.237V after
the second timing cycle, RESET 1 goes high.
FILTER (Pin 11): Overcurrent Fault Timing Pin and Over-
voltage Fault Set Pin. With a capacitor connected from this
pin to ground, the response time of all three SLOW COMP
comparators can be adjusted. Note that the response time
of the SLOW COMP comparators cannot be adjusted
individually.
TIMER (Pin 12): A capacitor connected from this pin to
GND sets the LTC4230’s system timing. The LTC4230’s
initial and second start-up timing cycles and its discharge
mode delay time are controlled by this capacitor.
FAULT (Pin 13): FAULT is a dual function (an input and an
output) internal to the LTC4230. Connected to this pin are
an analog comparator (COMP6) and an open-drain
N-channel FET. During normal operation, if COMP6 is
driven below 1.234V, all electronic circuit breakers trip
and each GATE pin pulls low. Referring to the Block
Diagram, FAULT incorporates an internal 2µA current
source pull up. This allows the LTC4230 to begin a second
timing cycle (V
FAULT
> 1.284V) and start up properly. This
also allows the use of the FAULT pin as a status output.
Under normal operating conditions, the FAULT output is a
logic high. Two conditions cause an active low on FAULT:
1) the LTC4230’s electronic circuit breakers trip because
of an output short circuit (V
OUT
n
= 0V) or because of a fast
output overcurrent transient (FAST COMP
n
trips its circuit
breaker); or 2) V
FILTER
> 1.26V. The FAULT output is driven
to logic low and is latched logic low until the ON pin is
driven to logic low for 30µs (the t
RESET
duration).
GND (Pin 14): Device Ground Connection. Connect this
pin to the system’s analog ground plane.
ON (Pin 15): An active high signal used to enable or disable
LTC4230 operation. As shown in the LTC4230 Block
Diagram, COMP1’s threshold is set at 1.234V and its
hysteresis is set at 80mV. If a logic high signal is applied
to the ON pin (V
ON
> 1.314V), the first timing cycle begins
if an overvoltage condition does not exist on any of the
GATE
n
pins (Pins 3, 8, and 18). If a logic low signal is
applied to the ON pin (V
ON
< 1.234V), each GATE
n
pin is
pulled low by an internal, dedicated 200µA current sink.
The ON pin can also be used to reset all three electronic
circuit breakers. If the ON pin is cycled low for more than␣ 1
t
RESET
n
(MAX)
period and then high following a circuit
breaker trip, all internal circuit breakers are reset and the
LTC4230 begins a new start-up cycle.
V
CC2
(Pin 16): Positive Supply Input for Channel 2. V
CC2
operates from 2.375V to 16.5V and its supply current,
I
CC2
, is typically 75µA. The master UVLO circuit disables
all three GATE
n
outputs of the LTC4230 until the voltage
at V
CC2
exceeds 2.15V.
10
LTC4230
4230f
SENSE 2 (Pin 17): Circuit Breaker Sense Pin for Chan-
nel␣ 2. With a sense resistor placed in the power path
between V
CC2
and SENSE 2, Channel 2’s electronic circuit
breaker trips if the voltage across the sense resistor (V
CC2
– V
SENSE2
) exceeds the thresholds set internally for SLOW
COMP2 and FAST COMP2, as shown in the Block Diagram.
The threshold for SLOW COMP2 is V
CB(SLOW)
= 50mV and
the electronic circuit breaker trips if the voltage across
R
SENSE2
exceeds 50mV for 10µs, or for the time delay
programmed by C
FILTER
. To adjust SLOW COMP2’s delay,
please refer to the section on Adjusting SLOW COMP
n
’s
Response Time.
Under transient conditions where large step current
changes can and do occur over shorter periods of time, a
second (fast) comparator instead trips the electronic
circuit breaker. The threshold for FAST COMP2 is set at
V
CB(FAST)
= 150mV, and the circuit breaker trips if the
voltage across the R
SENSE2
exceeds 150mV for more than
500ns. FAST COMP2’s delay is fixed in the LTC4230 and
cannot be adjusted. To disable Channel 2’s electronic
circuit breaker, connect the V
CC2
and SENSE 2 pins
together.
GATE 2 (Pin 18): The output signal at this pin is the high
side gate drive for Channel 2’s external N-channel FET
pass transistor. An internal charge pump produces a 4.5V
(minimum) to 18V (maximum) gate drive voltage for V
CC1
supply voltages from 2.7V to 16.5V, respectively.
As shown in the Block Diagram for each channel, an
internal charge pump supplies a 10µA gate current and
sufficient gate voltage drive to the external FET. The
internal charge pump produces a minimum 4.5V gate
drive for V
CC1
< 4.75V. For V
CC1
> 4.75V, the minimum
gate voltage drive is 9V. For V
CC1
≥ 12V, the minimum gate
voltage drive is 7V which is set by an internal zener diode
clamp connected between the GATE 2 pin and GND.
RESET 2 (Pin 19): An open-drain N-channel device whose
source connects to GND (Pin 14). This pin pulls low if the
voltage at FB2 (Pin 20) falls below the FB2 threshold
(1.234V). This pin requires an external pull-up resistor to
V
OUT2
. If an undervoltage lockout condition occurs, the
RESET 2 pin pulls low independently of FB2 to prevent
false glitches.
FB2 (Pin 20): The FB2 (Feedback) pin is an input to the
FBCOMP2 comparator which monitors the V
CC2
output
supply voltage through an external resistor divider. If V
FB2
< 1.234V, RESET 2 pulls low. An internal glitch filter at
FBCOMP3’s output prevents triggering a reset condition
due to negative voltage transients. If V
FB2
> 1.237V,
RESET 2 pin goes high after exiting undervoltage lockout.
PI FU CTIO S
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11
LTC4230
4230f
BLOCK DIAGRA
W
–
+TMRBUFFER
1.234V
–
+CHANNEL 2
CONTROL
CHANNEL TWO
FAST COMP2
VCC2
150mV
FASTHI
+
–
–
+FBCOMP2
1.234V 0.25V
POWER BAD
+
–
GATELO
COMPARATOR
VCLAMP2 = VCC2 + 12V
GATELO
FPD
200µA
MG2
–
+SLOW COMP2
VCC2 CPO2
50mV
SLOWHI CUR_LIMIT
+
–
GLITCH
FILTER
FPD
10µA
CHANNEL THREE
(DUPLICATE OF CHANNEL TWO)
–
+CHANNEL 1
CONTROL
CHANNEL ONE
FAST COMP1
VCC1
150mV
FASTHI
+
–
–
+FBCOMP1
1.234V 0.25V
POWER BAD
MR2
MR1
+
–
GATELO
COMPARATOR
VCLAMP1 = VCC1 + 12V
GATELO
FPD
200µA
MG1
–
+SLOW COMP1
VCC1 CPO1
50mV
SLOWHI CUR_LIMIT
+
–
GLITCH
FILTER
ON
10µA
VCC1
2µA
VCC1
2µA
SYSTEM
CONTROL
–
+COMP1
VCC1
ON
COMPARATOR
1.234V
FAULT
M2
M4
M5
–
+
FAULT
COMPARATOR
COMP6
1.234V FAULTLO
DELAY
CHARGE
PUMP 3
VCC1
CHARGE
PUMP 2
VCC1
CPO3
VCC3
VCC2
VCC1
UVLO
0.25V
1.234V
REF
CPO2
CPO1
CHARGE
PUMP 1
OSC
+
–
FILTER
COMPARATOR
FTR_CHARGE
1.26V FTRHI
0.3V
1.234V
+
–
TMRLO
COMPARATOR
TMRLO
TMRHI
–
+
TMRHI
COMPARATOR
10µA
VCC1
20µA
M6
FAULT
1.6µA
19RESET 2
20FB2
17SENSE 2
16VCC2
2RESET 3
1FB3
4SENSE 3
5VCC3
9RESET 1
10FB1
7SENSE 1
FAULT
6VCC1
13
11
15
FILTER
ON
18 GATE 2
3 GATE 3
8 GATE 1
GND
14
TIMER
12
MF2
MF1
12
LTC4230
4230f
HOT CIRCUIT INSERTION
When circuit boards are inserted into or removed from live
backplanes, the supply bypass capacitors can draw huge
transient currents from the backplane power bus as they
charge. The transient currents can cause permanent dam-
age to the connector pins as well as cause glitches on the
system supply, causing other boards in the system to
reset.
The LTC4230 is designed to turn a printed circuit board’s
supply voltages on and off in a controlled manner, allow-
ing the circuit board to be safely inserted or removed from
a live backplane. The device provides a system reset signal
to indicate when board supply voltage drops below a pre-
determined level, as well as a dual function fault monitor.
OUTPUT VOLTAGE MONITOR
The LTC4230 uses a 1.234V bandgap reference, precision
voltage comparators and external resistor dividers to
monitor the output supply voltages as shown in Figure 1.
The operation of the supply monitor in normal mode is il-
lustrated in Figure␣ 2. RESET 1 pulls low during an
undervoltage lockout condition. It remains low until the end
of the soft-start cycle (second timing cycle). FB1 then
assumes control of RESET 1 status. RESET 2 and RESET␣ 3
also pull low during undervoltage lockout. However, FB2
controls RESET 2 and FB3 controls RESET 3 status imme-
diately after clearing UVLO (Figure 2, Time Points 5 and 6).
If the voltage at FB
n
drops below its reset threshold
(1.234V), the FBCOMP comparator output pulls high.
After passing through a glitch filter, RESET
n
changes
state. If the voltage at FB
n
increases above its reset
threshold, the FBCOMP comparator output changes state
and RESET
n
pulls high.
+
SENSE
n
R
SENSE
R2
R1 R3
10k
V
CC
n
V
OUT
GATE
n
LTC4230
15
FB
n
MR
n
GND
ON
4230 F01
RESET
n
C
TIMER
12
TIMER
14
C
LOAD
Q1
LOGIC
TIMER 1.234V
REFERENCE
FBCOMP
n
µP
RESET
4
3
2 1
SHORT
LONG
V
CC
ON/RESET
GND LONG
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
–
+
Figure 1. Supply Voltage Monitor Block Diagram
APPLICATIO S I FOR ATIO
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13
LTC4230
4230f
1 2 5 63 4
SECOND TIMING CYCLE
(SOFT-START CYCLE)
FIRST TIMING CYCLE
1.234V
20µA PULL-UP 20µA PULL-UP
4230 F02
CHECK FOR FILTER LOW (< V
REF
)
CHECK FOR FAULT HIGH (> V
REF
+ 50mV)
FAST COMPARATOR ARMEDOUT OF UVLO
V
CC
n
,
ON
UVLO (INTERNAL SIGNAL)
TIMER
V
OUT1
V
OUT2, 3
RESET 1
RESET 2, RESET 3
GATE
n
GATE
n
< 0.25V
10µA PULL-UP
SLOW COMPARATOR ARMED
NORMAL MODE
(V
FB1
> 1.237V)
(V
FB2
, V
FB3
> 1.237V)
Figure 2. Supply Monitor Waveforms in Normal Mode
APPLICATIO S I FOR ATIO
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14
LTC4230
4230f
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
The LTC4230’s power-on reset circuit initializes the start-
up condition and ensures the chip is in the proper state if
the input supply voltages are too low. If any one of the
input supply voltages falls below its corresponding UVLO
lower threshold (e.g., V
CC1
< 2.25V, V
CC2
< 2.105V or V
CC3
< 1.155V), the LTC4230 enters UVLO mode and all three
GATE
n
pins are each pulled low by internal 200µA current
sinks. Since the LTC4230’s UVLO circuits have hysteresis,
the device restarts when all three supply voltages rise
above their corresponding UVLO high threshold (e.g.,
V
CC1
> 2.35V, V
CC2
> 2.15V and V
CC3
> 1.19V) and the ON
pin goes high.
In addition, users can utilize the ON comparator (COMP1)
or the FAULT comparator (COMP6) to effectively program
a higher undervoltage lockout level. If the FAULT com-
parator is used for this purpose, the system will wait for
the input voltage to increase above the level set by the user
before starting the second timing cycle. Also, if the input
voltage drops below the set level in normal operating
mode, the user must cycle the ON pin or V
CC1
to restart the
system.
GLITCH FILTER FOR RESET
n
Each LTC4230 feedback comparator has a glitch filter to
prevent RESET
n
from generating a system reset if there
are transients on the FB
n
pin. The relationship between
glitch filter time and the feedback transient voltage is
shown in Figure 3.
SYSTEM TIMING
System timing for the LTC4230 is generated in the equiva-
lent circuit shown in Figure 4. If the LTC4230’s internal
timing circuit is off, an internal N-channel FET connects
the TIMER pin to GND. If the timing circuit is enabled, an
internal 20µA current source is then connected to the
TIMER pin to charge C
TIMER
at a rate given by Equation 1:
C Charge -Up Rate
TIMER
=µ20 A
C
TIMER
(1)
When the TIMER pin voltage reaches TMRHI’s threshold
of 1.234V, the TIMER pin is reset to GND. Equation 2 gives
an expression for the timer period:
tV
C
A
TIMER TIMER
=µ
1 234 20
.•
(2)
As a design aid, the LTC4230’s timer period as a function
of the C
TIMER
using standard values from 0.1µF to 10µF is
shown in Table 1.
FEEDBACK TRANSIENT (mV)
0
GLITCH FILTER TIME (µs)
150
200
250
160
4211 F03
100
50
040 80 12020 18060 100 140 200
T
A
= 25°C
Figure 3. FB Comparator Glitch Filter Time
vs Feedback Transient Voltage
–
+
–
+
0.3V
20µA
t
TIMER
LTC4230*
V
CC1
V
REF
1.234V
TMRLO
LOGIC
TMRHI
TIMER
C
TIMER
M6 NORMAL
4230 F04
*ADDITIONAL DETAILS OMITTED FOR CLARITY
Figure 4. LTC4230 System Timing Block Diagram
APPLICATIO S I FOR ATIO
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15
LTC4230
4230f
Ensuring a proper start-up sequence is also dependent on
selecting the most appropriate value for C
TIMER
for the
application. Long timing periods affect overall system
start-up times. A timing period set too short and the
system may never start up. A good starting point is to set
C
TIMER
= 1µF and then adjust its value accordingly for the
application.
OPERATING SEQUENCE
Power-Up, Start-Up Check and Plug-In Timing Cycle
The sequence of operations for the LTC4230 is illustrated
in the timing diagram of Figure 5. When a PC board is first
inserted into a live backplane, the LTC4230 first performs
1 3 6 74 5
FIRST TIMING CYCLE
20µA PULL-UP 20µA PULL-UP
4230 F05
NORMAL MODE
SECOND TIMING
CYCLE
CHECK FOR FILTER LOW (< V
REF
)
CHECK FOR FAULT HIGH (> V
REF
+ 50mV)
2
CHECK FOR GATE
n
< 0.2V FAST COMPARATOR
ARMED
IF ON IS LOW AND
V
FB
n
< 1.234V,
RESET 1, RESET 2 AND RESET 3
PULL LOW, RESPECTIVELY
ON
TIMER
GATE
n
V
OUT
n
RESET 1
RESET 2,
RESET 3
10µA PULL-UP 200µA PULL-DOWN
SLOW COMPARATOR ARMED
8 9
POWER GOOD
(V
FB
n
> 1.237V) POWER BAD
(V
FB
n
< 1.234V)
200µA PULL-DOWN
Figure 5. Normal Power-Up Sequence
Table 1. tTIMER vs CTIMER
C
TIMER
t
TIMER
0.1µF 6.2ms
0.22µF 13.6ms
0.33µF 20.4ms
0.47µF 29ms
0.68µF 42ms
0.82µF 50.6ms
1µF 61.7ms
2.2µF 136ms
3.3µF 204ms
4.7µF 290ms
6.8µF 420ms
8.2µF 506ms
10µF 617ms
APPLICATIO S I FOR ATIO
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16
LTC4230
4230f
a start-up check to make sure the supply voltage is above
its 2.3V UVLO threshold (see Time Point 1). If the input
supply voltage is valid, the gate of the external pass
transistor is pulled to ground by the internal 200µA current
source connected at the GATE
n
pin. The TIMER pin is held
low by an internal N-channel pull-down transistor (see
M6, LTC4230 Block Diagram) and the FILTER pin voltage
is pulled to ground by an internal 10µA current source.
Once V
CC
n
and ON (the ON pin is >1.314V) are valid, the
LTC4230 checks to make sure that GATE
n
is OFF (V
GATE
n
< 0.25V) at Time Point 2. An internal timing circuit is
enabled and the TIMER pin voltage ramps up at the rate
described by Equation 1. At Time Point 3 (the timing period
programmed by C
TIMER
), the TIMER pin voltage equals
V
TMR
(1.234V). Next, the TIMER pin voltage ramps down
to Time Point 4 where the LTC4230 performs two checks:
(1) FILTER pin voltage is low (V
FILTER
< 1.19V) and (2)
FAULT pin voltage is high (V
FAULT
> 1.284V). If both
conditions are met, the LTC4230 begins a second timing
(soft-start) cycle.
Second Timing (Soft-Start) Cycle
At the beginning of the second timing cycle (Time Point␣ 5),
the LTC4230’s FAST COMP
n
is armed and an internal
10µA current source working with an internal charge
pump provides the gate drive to the external pass transis-
tor. An expression for the GATE
n
voltage slew rate is given
by Equation 3:
V Slew Rate dV
dt
A
C
GATE GATE
GATE
nn
n
,=µ10
(3)
where C
GATE
n
= Power MOSFET gate input capacitance
(C
ISS
) for Channel
n
.
For example, a Si4410DY (a 30V N-channel power MOSFET)
exhibits an approximate C
GATE
of 3300pF at V
GS
= 10V. The
LTC4230’s GATE
n
voltage rate-of-change (slew rate) for
this example would be:
V Slew Rate dV
dt
A
pF
V
ms
GATE GATE
nn
,.=µ=
10
3300 303
The inrush current being delivered to the load while the
GATE
n
is ramping is dependent on C
LOAD
n
and C
GATE
n
.
Equation 4 gives an expression for the inrush current
during the second timing cycle:
IdV
dt CA
C
C
INRUSH GATE LOAD LOAD
GATE
==µ
nnn
n
••10
(4)
For example, if C
GATE
n
= 3300pF and C
LOAD
n
= 2000µF, the
inrush current charging C
LOAD
n
is:
IA
F
FA
INRUSH =µ µµ=10 2000
0 0033 606•..
(5)
At Time Point 7, the output voltage trips FBCOMP
n
’s
threshold, signaling an output voltage “power good” con-
dition. RESET␣ 2 and RESET␣ 3 pull high. At Time Point 8,
RESET␣ 1 asserts high, SLOW COMP is armed and the
LTC4230 enters a fault monitor mode.
SOFT-START WITH CURRENT LIMITING
During the second timing cycle, the inrush current is
described by Equation 4. Note that there is a one-to-one
correspondence in the inrush current to C
LOAD
n
. If the
inrush current is large enough to cause a voltage drop
greater than 50mV across the sense resistor, an internal
servo loop controls the operation of the 10µA current
source at the GATE
n
pin to regulate the load current to:
ImV
R
LIMIT SOFTSTART SENSE
()
nn
=50
(6)
For example, the inrush current is limited to 5A when
R
SENSE
n
= 0.01Ω.
In this fashion, the inrush current is controlled and C
LOAD
n
is charged up slowly during the soft-start cycle.
The timing diagram in Figure 6 illustrates the operation of
the LTC4230 in a normal power-up sequence with limited
inrush current as described by Equation 6. At Time Point␣ 5,
the GATE pin voltage begins to ramp indicating that the
power MOSFET is beginning to charge C
LOAD
n
. At Time
Point 5, the inrush current causes a 50mV voltage drop
across R
SENSE
n
and an internal servo loop engages, limit-
ing the inrush current to a fixed level. At Time Point 6, the
GATE
n
pin voltage continues to ramp as C
LOAD
n
charges
until V
OUT
n
reaches its final value. The charging current
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LTC4230
4230f
reduces, and the internal servo loop disengages. At the
end of the soft-start cycle (Time Point 8), all RESET
n
are
high and all SLOW COMP
n
are armed.
Power-Off Cycle
As shown at Time Point 9, an external hard reset is initiated
by pulling the ON pin low (V
ON
< 1.234V). All GATE
n
pin
voltages are ramped to ground by the internal 200µA
current sources, discharging C
GATE
n
and turning off the
pass transistors. As C
LOAD
n
discharges, the output voltage
crosses FBCOMP
n
’s threshold, signaling a “power bad”
condition at Time Point 10. RESET
n
then asserts low.
1 3 765 84
FIRST TIMING CYCLE
20µA PULL-UP 20µA PULL-UP
LOAD CURRENT IS REGULATING AT 50mV/R
SENSE
n
4230 F06
NORMAL MODE
SECOND TIMING
CYCLE
CHECK FOR FILTER LOW (< V
REF
)
CHECK FOR FAULT HIGH (> V
REF
+ 50mV)
2
CHECK FOR GATE
n
< 0.25V FAST COMPARATOR
ARMED
IF ON IS LOW AND
V
FB
n
< 1.234V,
RESET 1, RESET 2 and RESET 3
PULL LOW, RESPECTIVELY
ON
TIMER
GATE
n
V
OUT
n
I
LOAD
n
GATE
n
V
OUT
n
RESET 1
RESET 2,
RESET 3
10µA PULL-UP
200µA PULL-DOWN
SLOW COMPARATOR ARMED
9 10
POWER GOOD
(V
FB
n
> 1.237V) POWER BAD
(V
FB
n
< 1.234V)
200µA PULL-DOWN
Figure 6. Normal Power-Up Sequence (with Current Limiting in Second Timing Cycle)
FREQUENCY COMPENSATION AT SOFT-START
If the external gate input capacitance (C
ISS
) is greater than
600pF, no external gate capacitor is required at GATE
n
to
stabilize the internal current-limiting loop during soft-
start. Otherwise, connect an external gate capacitor be-
tween the GATE
n
and GND pins to increase the total gate
capacitance above 600pF. The servo loop that controls the
external MOSFET during current limiting has a unity-gain
frequency of about 105kHz and phase margin of 80° for
external MOSFET gate input capacitances to 2.5nF.
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LTC4230
4230f
USING AN EXTERNAL GATE CAPACITOR
The LTC4230 automatically limits the inrush current in one
of two ways: by controlling the GATE
n
pin voltage slew rate
or by actively limiting the inrush current. The LTC4230
uses GATE
n
voltage slew rate limiting when C
LOAD
n
is
small and/or the inrush current limit is set high. If GATE
n
voltage slew rate control is preferred with large C
LOAD
n
, an
external capacitor (C
GX
) can be used from GATE
n
to ground,
as shown in Figure 7. According to Equation 3, adding C
GX
slows the GATE
n
voltage slew rate at the expense of slower
system turn-on and turn-off time. Should this technique
be used, values for C
GX
less than 150nF are recommended.
ELECTRONIC CIRCUIT BREAKER
The LTC4230 features an electronic circuit breaker func-
tion. It disconnects loads from power supplies when
shorts or excessive load current conditions occur on any
of the supplies and generates a FAULT signal. If a circuit
breaker trips, its GATE
n
pin is immediately pulled to
ground, the external N-channel MOSFET is quickly turned
OFF and FAULT is latched low.
The circuit breaker trips whenever the voltage across the
sense resistor exceeds two different levels, each level set
by the LTC4230’s SLOW COMP
n
and FAST COMP
n
(see
Block Diagram). The SLOW COMP
n
trips the circuit
breaker if the voltage across the SENSE
n
resistor
(V
CC
n
– V
SENSE
n
= V
CB
) is greater than 50mV for 10µs.
There may be applications where this comparator’s re-
sponse time is not long enough, for example, because of
excessive supply voltage noise. To adjust the response
time of the SLOW COMP
n
, a capacitor is used at the
LTC4230’s FILTER pin (see section on Adjusting SLOW
COMP
n
’s Response Time). The FAST COMP
n
trips the
circuit breaker to protect against fast load overcurrents if
the transient voltage across the sense resistor is greater
than 150mV for 500ns. The response time of the LTC4230’s
FAST COMP
n
is fixed.
The timing diagram of Figure 6 illustrates when the
LTC4230’s electronic circuit breaker is armed. After the
first timing cycle, the LTC4230’s FAST COMP
n
is armed
at Time Point 5. Arming FAST COMP
n
at Time Point 5
ensures that the system is protected against a short-
circuit condition during the second timing cycle after
CLOAD
n
has been fully charged. At Time Point 8, SLOW
COMP
n
is armed when the internal control loop is disen-
gaged.
The timing diagrams in Figures 8 and 9 illustrate the opera-
tion of the LTC4230 when the load current conditions exceed
the thresholds of the FAST COMP
n
(V
CB(FAST)
> 150mV)
and SLOW COMP
n
(V
CB(SLOW)
> 50mV), respectively.
4
3
2 1
M1
Si4410DY
R
SENSE
0.007Ω
C
GX
*
C
LOAD
4230 F07
+
V
CC
n
SENSE
n
LTC4230**
GATE
n
FB
n
R1
36k
V
OUT
5V
5A
V
IN
5V
R2
15k
*
**VALUES ≤150nF SUGGESTED
ADDITIONAL DETAILS OMITTED
FOR CLARITY =
dV
GATE
n
dt
V
GATE
SLEW RATE CONTROL
10µA
C
GATE
+ C
GX
()
Figure 7. Using an External Capacitor at GATE for
GATE Voltage Slew Rate Control and Large CLOAD
An external gate capacitor may also be useful to decrease
or eliminate current spikes through the MOSFET when
power is first applied. At power-up, the instantaneous in-
put voltage step attempts to pull the MOSFET gate up
through the MOSFET’s drain-to-gate capacitance. If the
MOSFET’s C
ISS
is small, the gate can be pulled up high
enough to turn on the MOSFET, thereby allowing a current
spike to the output. This event occurs during the time that
the LTC4230 is coming out of UVLO and getting its intel-
ligence to hold the GATE pin low. An external capacitor
attenuates the voltage to which the GATE is pulled up and
eliminates the current spike. The value required is depen-
dent on the MOSFET capacitance specifications. In typical
applications, this capacitor is not required.
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LTC4230
4230f
1 3 65 74
20µA PULL-UP 20µA PULL-UP
LOAD CURRENT > 150mV/R
SENSE
n
4230 F08
CHECK FOR FILTER LOW (< V
REF
)
CHECK FOR FAULT HIGH (> V
REF
+ 50mV)
2
CHECK FOR GATE
n
< 0.25V FAST COMPARATOR
ARMED SLOW COMPARATOR
ARMED CIRCUIT BREAKER TRIPS,
ALL GATE
n
PINS PULL
LOW IMMEDIATELY
ON
TIMER
FAULT
GATE
n
GATE
n
V
OUT
n
V
OUT
n
I
OUT
n
FILTER
1.6µA PULL-DOWN
8 9
CHECK FOR TIMER < 0.3V
LOAD CURRENT < 50mV/R
SENSE
n
Figure 8. Output Short Circuit Causes Fast Comparator to Trip the Circuit Breaker
APPLICATIO S I FOR ATIO
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RESETTING THE ELECTRONIC CIRCUIT BREAKER
Once the LTC4230’s circuit breaker is tripped, FAULT is
asserted low and the GATE
n
pin is pulled to ground. The
LTC4230 remains latched OFF in this fault state until the
external fault is cleared. To clear the internal fault detect
circuitry and to restart the LTC4230, its ON pin must be
driven low (V
ON
< 1.234V) for at least 30µs, after which
time FAULT goes high. Toggling the ON pin from low to
high (V
ON
> 1.314V) initiates a restart sequence in the
LTC4230. The timing diagram in Figure 10 illustrates a
20
LTC4230
4230f
Figure 9. Output Short-Circuit Causes Slow Comparator to Trip Circuit Breaker
1 3 65 74
20µA PULL-UP 20µA PULL-UP
150mV/RSENSE
n
>
LOAD CURRENT > 50mV/RSENSE
n
4230 F09
CHECK FOR FILTER LOW (< VREF)
CHECK FOR FAULT HIGH (> VREF + 50mV)
2
CHECK FOR GATE
n
< 0.25V FAST COMPARATOR
ARMED SLOW COMPARATOR
ARMED CIRCUIT BREAKER TRIPS,
ALL GATE
n
PINS PULL
LOW IMMEDIATELY
ON
TIMER
FAULT
GATE
n
GATE
n
VOUT
n
VOUT
n
IOUT
n
FILTER
1.6µA PULL-DOWN
10µA PULL-DOWN
1.26V
2µA PULL-UP
8 9
CHECK FOR TIMER < 0.3V
LOAD CURRENT < 50mV/RSENSE
n
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LTC4230
4230f
137
65 84
FIRST TIMING CYCLE
4230 F10
SECOND TIMING CYCLE DISCHARGING MODE
NORMAL MODE
CHECK FOR FILTER LOW (< VREF)
CHECK FOR FAULT HIGH (> VREF + 50mV)
2
CHECK FOR GATE
n
< 0.25V FAST COMPARATOR
ARMED SLOW COMPARATOR
ARMED ONCE VFILTER > 1.26V, CIRCUIT BREAKER TRIPS,
ALL GATE
n
PINS PULL LOW IMMEDIATELY
20µA PULL-UP 1.6µA PULL-DOWN
2µA PULL-UP
VFILTER > 1.26V
10µA PULL-DOWN
LOAD CURRENT < 150mV/RSENSE
n
20µA PULL-UP
CHECK FOR TIMER < 0.3V
910
ON
TIMER
FAULT
GATE
n
VOUT
n
ILOAD
n
FILTER
GATE
n
VOUT
n
LOAD CURRENT IS REGULATING AT 50mV/RSENSE
n
Figure 10. Power-Up into Dead Short in Overcurrent Condition
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LTC4230
4230f
start-up sequence where the LTC4230 is powered up into
a load overcurrent condition. Note that the circuit breaker
trips at Time Point 8 and is reset at Time Point 10.
ADJUSTING SLOW COMP
n
’S RESPONSE TIME
The response time of SLOW COMP
n
is adjusted using a
capacitor connected from the LTC4230’s FILTER pin to
ground. If this pin is left unused, SLOW COMP
n
’s delay
defaults to 10µs. During normal operation, the FILTER
output pin is held low as an internal 10µA pull-down
current source is connected to this pin by transistor M4.
This pull-down current source is turned off when an
overcurrent load condition is detected by SLOW COMP
n
.
During an overcurrent condition, the internal 2µA pull-up
current source is connected to the FILTER pin by transis-
tor M5, thereby charging C
FILTER
. As the charge on the
capacitor accumulates, the voltage across C
FILTER
increases. Once the FILTER pin voltage increases to 1.26V,
the electronic circuit breaker trips and the LTC4230’s
GATE
n
pins are switched quickly to ground by transistor
MF
n
(refer to the Block Diagram). After the circuit breaker
is tripped, M5 is turned off, M4 is turned on and the 10µA
pull-down current then holds the FILTER pin voltage low.
SLOW COMP
n
’s response time from an overcurrent fault
condition to when the circuit breaker trips (GATE
n
OFF) is
given by Equation 7:
tV
C
As
SLOWCOMP FILTER
n
=µ+µ126 210.•
(7)
For example, if C
FILTER
= 1000pF, SLOW COMP
n
’s response
time = 640µs. As a design aid, SLOW COMP
n
’s delay time
(t
SLOW COMP
) versus C
FILTER
for standard values of C
FILTER
from 100pF to 1000pF is illustrated in Table␣ 2.
Table 2. tSLOWCOMP
n
vs CFILTER
C
FILTER
t
SLOWCOMP
n
100pF 73µs
220pF 149µs
330pF 218µs
470pF 306µs
680pF 438µs
820pF 527µs
1000pF 640µs
SENSE RESISTOR CONSIDERATIONS
The fault current level at which the LTC4230’s internal
electronic circuit breakers trip is determined by a sense
resistor connected between the LTC4230’s V
CC
n
and
SENSE
n
pins and two separate trip points. The first trip
point is set by the SLOW COMP
n
’s threshold, V
CB(SLOW)
=
50mV, and the trip occurs if a load current fault condition
exist for more than 10µs. The current level at which the
electronic circuit breaker trips is given by Equation 8:
IV
R
mV
R
TRIP SLOW CB SLOW
SENSE SENSE
() ()
nn
nn
==
50
(8)
The second trip point is set by the FAST COMP
n
’s thresh-
old, V
CB(FAST)
= 150mV, and occurs during fast load
current transients that exist for 500ns or longer. The
current level at which the circuit breaker trips in this case
is given by Equation 9:
IV
R
mV
R
TRIP FAST CB FAST
SENSE SENSE
() ()
nn
nn
==
150
(9)
As a design aid, the currents at which electronic circuit
breaker trips for common values for R
SENSE
are shown in
Table 3.
Table 3. ITRIP(SLOW) and ITRIP(FAST) vs RSENSE
R
SENSE
I
TRIP(SLOW)
I
TRIP(FAST)
0.005Ω10A 30A
0.006Ω8.3A 25A
0.007Ω7.1A 21A
0.008Ω6.3A 19A
0.009Ω5.6A 17A
0.01Ω5A 15A
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4230’s
V
CC
n
and SENSE
n
pins are strongly recommended. The
drawing in Figure 11 illustrates the correct way of making
connections between the LTC4230 and the sense resistor.
PCB layout should be balanced and symmetrical to mini-
mize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
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23
LTC4230
4230f
4
3
2 1
–+
SLOW
COMP
n
V
CC
n
V
OUT
n
V
CB
n
SENSE
n
R
SENSE
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
4230 F12
LTC4230*
V
CB(MAX)
= 60mV
V
CB(NOM)
= 50mV
V
CB(MIN)
= 40mV
I
LOAD(MAX)
V
CC
n
5V
+
–
Figure 12. Circuit Breaker Equivalent Circuit
for Calculating RSENSE
The power rating of the sense resistor should accommo-
date steady-state fault current levels so that the compo-
nent is not damaged before the circuit breaker trips.
Table␣ 4 in the Appendix lists suggested sense resistors
that can be used with the LTC4230’s circuit breaker.
For example:
If a sense resistor with 7mΩ ±5% R
TOL
is used for current
limiting, the nominal trip current I
TRIP(NOM)
= 7.1A. From
Equations 11 and 12, I
TRIP(MIN)
= 5.4A and I
TRIP(MAX)
= 9A
respectively.
For proper operation and to avoid the circuit breaker
tripping unnecessarily, the minimum trip current
(I
TRIP(MIN)
) must exceed the circuit’s maximum operating
load current. For reliability purposes, the operation at the
maximum trip current (I
TRIP(MAX)
) must be evaluated
carefully. If necessary, two resistors with the same R
TOL
can be connected in parallel to yield an R
SENSE(NOM)
value
that fits the circuit requirements.
IRC-TT SENSE RESISTOR
LR251201R010F
OR EQUIVALENT
0.01Ω, 1%, 1W
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
TO
V
CC
n
TO
SENSE
n
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER W
4230 F11
Figure 11. Making PCB Connections to the Sense Resistor
CALCULATING CIRCUIT BREAKER TRIP CURRENT
For a selected R
SENSE
value, the nominal load current that
trips the circuit breaker is given by Equation 10:
IV
R
mV
R
TRIP NOM CB NOM
SENSE NOM SENSE NOM
() ()
() ()
==
50
(10)
The minimum load current that trips the circuit breaker is
given by Equation 11.
IV
R
mV
R
TRIP MIN CB MIN
SENSE MAX SENSE MAX
() ()
() ()
==
40
(11)
where
RR R
SENSE MAX SENSE NOM TOL
() ()
•=+
1100
The maximum load current that trips the circuit breaker is
given in Equation 12.
IV
R
mV
R
TRIP MAX CB MAX
SENSE MIN SENSE MIN
() ()
() ()
==
60
(12)
where
RR R
SENSE MIN SENSE NOM TOL
() ( )
•–=
1100
POWER MOSFET SELECTION CRITERIA
To start the power MOSFET selection process, choose the
maximum drain-to-source voltage, V
DS(MAX)
, and the
maximum drain current, I
D(MAX)
of the MOSFET. The
V
DS(MAX)
rating must exceed the maximum input supply
voltage (including surges, spikes, ringing, etc.) and the
I
D(MAX)
rating must exceed the maximum short-circuit
current in the system during a fault condition. In addition,
consider three other key parameters: 1) the required gate-
source (V
GS
) voltage drive, 2) the voltage drop across the
drain-to-source ON resistance, R
DS(ON)
and 3) the maxi-
mum junction temperature rating of the MOSFET.
Power MOSFETs are classified into two categories: stan-
dard MOSFETs (R
DS(ON)
specified at V
GS
= 10V) and logic-
level MOSFETs (R
DS(ON)
specified at V
GS
= 5V). The absolute
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LTC4230
4230f
maximum rating for V
GS
is typically ±20V for standard
MOSFETs. However, the V
GS
maximum rating for logic-
level MOSFETs ranges from ±8V to ±20V depending upon
the manufacturer and the specific part number. The
LTC4230’s gate overdrive as a function of V
CC
is illustrated
in the Typical Performance curves. Logic-level MOSFETs
are recommended for low supply voltage applications and
standard MOSFETs can be used for applications where
supply voltage is greater than 4.75V.
Note that in some applications, the gate of the external
MOSFET can discharge faster than the output voltage
when the circuit breaker is tripped. This causes a negative
V
GS
voltage on the external MOSFET. Usually, the selected
external MOSFET should have a ±V
GS(MAX)
rating that is
higher than the operating input supply voltage to ensure
that the external MOSFET is not destroyed by a negative
V
GS
voltage. In addition, the ±V
GS(MAX)
rating of the
MOSFET must be higher than the gate overdrive voltage.
Lower ±V
GS(MAX)
rating MOSFETs can be used with the
LTC4230 if the GATE
n
overdrive is clamped to a lower
voltage. The circuit in Figure 13 illustrates the use of zener
diodes to clamp the LTC4230’s GATE
n
overdrive signal if
lower voltage MOSFETs are used.
The R
DS(ON)
of the external pass transistor should be low
to make its drain-source voltage (V
DS
) a small percentage
of V
CC
. At a V
CC
= 2.5V, V
DS
+ V
RSENSE
= 0.1V yields 4%
error at the output voltage. This restricts the choice of
MOSFETs to very low R
DS(ON)
. At higher V
CC
voltages, the
V
DS
requirement can be relaxed in which case MOSFET
package dissipation (P
D
and T
J
) may limit the value of
R
DS(ON)
. Table 5 lists some power MOSFETs that can be
used with the LTC4230.
Power MOSFET junction temperature is dependent on four
parameters: current delivered to the load, I
LOAD
, R
DS(ON)
,
junction-to-ambient thermal resistance, θ
JA
, and the maxi-
mum ambient temperature to which the circuit will be
exposed, T
A(MAX)
. For reliable circuit operation, the maxi-
mum junction temperature (T
J(MAX)
) for a power MOSFET
should not exceed the manufacturer’s recommended value.
This includes normal mode operation, start-up, current-
limit and autoretry mode in a fault condition. For a given
set of conditions, the junction temperature of a power
MOSFET is given by Equation 13:
MOSFET Junction Temperature,
T
J(MAX)
≤ (T
A(MAX)
+ θ
JA
• P
D
) (13)
where
P
D
= (I
LOAD
)
2
• R
DS(ON)
PCB layout techniques for optimal thermal management
of power MOSFET power dissipation help to keep device
θ
JA
as low as possible. See the section on PCB Layout
Considerations for more information.
V
CC
V
OUT
*USER SELECTED VOLTAGE CLAMP
(A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED)
1N4688 (5V)
1N4692 (7V): LOGIC-LEVEL MOSFET
1N4695 (9V)
1N4702 (15V): STANDARD-LEVEL MOSFET
4230 F13
R
SENSE
R
G
200Ω
GATE
D1* D2*
Q1
Figure 13. Optional Gate Clamp for Lower VGS(MAX) MOSFETs
USING STAGGERED PIN CONNECTORS
The LTC4230 can be used on either a printed circuit board
or on the backplane side of the connector, and examples
for both are shown in Figure 14. Printed circuit board edge
connectors with staggered pins are recommended as the
insertion and removal of circuit boards do sequence the
pin connections. Supply voltage and ground connections
on the printed circuit board should be wired to the edge
connector’s long pins or blades. Control and status sig-
nals (like RESET
n
, FAULT and ON) passing through the
card’s edge connector should be wired to short length pins
or blades.
APPLICATIO S I FOR ATIO
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25
LTC4230
4230f
4
3
21
+
VCC
n
RESET
n
SENSE
n
ON
R5
15k
LTC4230*
GATE
n
FB
n
4230 F14a
15
14
12CTIMER
1µF
GND
TIMER
RESET
R4
36k
VOUT
5V
5A
Q1
Si4410DY
RSENSE
0.007Ω
COUT
R6
10k
Z1**
Z1: SMAJ10
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
**OPTIONAL
R1
10Ω
C1
0.1µF
R2
10k
VIN
5V
SHORT
LONG
VCC
RESET
LONG
PCB EDGE
CONNECTOR
(MALE)
SHORT
BACKPLANE
CONNECTOR
(FEMALE)
4
3
21
+
V
CC
n
SENSE
n
ON
R2
100k
RESET
LTC4230*
GATE
n
FB
n
4230 F14b
15
14
12C
TIMER
1µF
R3
10k
GND
TIMER
RESET
n
V
OUT
5V
5A
Q1
Si4410DY
R
SENSE
0.007Ω
C
OUT
R1
36k
R4
10k
R5
10k
PCB
CONNECTION
SENSE
R
X
10Ω
C
X
0.1µF
Z1**
V
CC
5V
SHORT
LONG
SHORT
PCB EDGE
CONNECTOR
(MALE)
LONG
SHORT
BACKPLANE
CONNECTOR
(FEMALE)
Q2
R7
15k
Z1: SMAJ10
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
**OPTIONAL
(14a) Hot Swap Controller On Daughter Board
(14b) Hot Swap Controller on Backplane
Figure 14. Staggered Pin Connections
PCB CONNECTION SENSE
There are a number of ways to use the LTC4230’s ON pin
to detect whether the printed circuit board has been fully
seated in the backplane before the LTC4230 commences
a start-up cycle.
The first example is shown in the schematic on the front
page of this data sheet. In this case, the LTC4230 is
mounted on the PCB and a 10k resistive divider is con-
nected to the ON pin. On the edge connector, R1 is wired
to a short pin. Until the connectors are fully mated, the ON
pin is held low, keeping the LTC4230 in an OFF state. Once
the connectors are mated, the resistive divider is
con
nected to V
CC1
, V
ON
> 1.314V and the LTC4230 begins
a start-up cycle.
In Figure 14a, an LTC4230 is illustrated in a basic configu-
ration on a PCB daughter card. The ON pin is connected
directly to V
CC
on the backplane once the card is seated
into the backplane. R2 is provided to bleed off any potential
static charge which might exist on the backplane, the
connector or during card installation.
A third example is shown in Figure 14b where the LTC4230
is mounted on the backplane. In this example, a 2N2222
transistor and a pair of resistors (R4, R5) form the PCB
connection sense circuit. With the card out of the chassis,
Q2’s base is biased to V
CC
through R5, biasing Q2 on and
driving the LTC4230’s ON pin low. The base of Q2 is also
wired to a socket on the backplane connector. When a card
is firmly seated into the backplane, the base of Q2 is then
grounded through a short pin connection on the card. Q2
is biased off, the LTC4230’s ON pin is pulled-up to V
CC
and
a start-up cycle begins.
APPLICATIO S I FOR ATIO
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26
LTC4230
4230f
In the previous three examples, the connection sense was
hard wired with no processor (low) interrupt capability. As
illustrated in Figure 15, the addition of an inexpensive
logic-level discrete MOSFET and a couple of resistors
offers processor interrupt control to the connection sense.
R4 keeps the gate of M2 at V
CC
until the card is firmly
mated to the backplane. A logic low for the ON/OFF signal
turns M2 off, allows the ON pin to pull high and turns on
the LTC4230.
A more elaborate connection sense scheme is shown in
Figure 16. The bases of Q1 and Q2 are wired to short pins
located on opposite ends of the edge connector because
the installation/removal of printed circuit cards generally
requires rocking the card back and forth. When V
CC
makes connection, the bases of transistors Q1 and Q2 are
pulled high, biasing them on. When both are on, the
LTC4230’s ON pin is held low, keeping the LTC4230 off.
When the short base connector pins of Q1 and Q2 finally
mate to the backplane, their bases are grounded, biasing
the transistors off. The ON pin is then pulled high by R3
enabling the LTC4230 and a power-up cycle begins.
A software-initiated power-down cycle can be started by
momentarily driving transistor M1 with a logic high signal.
This in turn will drive the LTC4230’s ON pin low. If the ON
pin is held low for more than 8µs, the LTC4230’s GATE
n
pin is switched to ground.
APPLICATIO S I FOR ATIO
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+
4
3
2 1
V
CC
n
SENSE
n
LTC4230*
15
12 14
C
LOAD
V
OUT
5V
5A
4230 F15
R6
15k
GATE
n
GNDTIMER
PCB CONNECTION SENSE
C
TIMER
1µF
FB
n
ON
SHORT
LONG
V
CC
5V
GND
ON/OFF
LONG
Z1: SMAJ10
M2: 2N7002LT1 *ADDITIONAL DETAILS
OMITTED FOR CLARITY
RESET
n
R2
10k
R4
10k
M2
R1
10k
R
X
10Ω
R
SENSE
0.007Ω
PCB EDGE
CONNECTOR
(MALE) M1
Si4410DY
Z1
R5
36k R7
10k
µP
LOGIC
RESET
SHORT
C
X
100nF
BACKPLANE
CONNECTOR
(FEMALE)
Figure 15. Connection Sense with ON/OFF Control
+
4
3
21
V
CC
n
SENSE
n
LTC4230*
15
12 14
C
LOAD
V
OUT
5V
5A
4230 F16
R5
15k
GATE
n
GNDTIMER
PCB CONNECTION SENSE
C
TIMER
1µF
FB
n
ON
LONG
V
CC
GND
ON/RESET
LONG
Z1: SMAJ10
M1: 2N7002LT1
Q1, Q2: MMBT3904LT1
*ADDITIONAL DETAILS OMITTED FOR CLARITY
RESET
n
M1
R
X
10Ω
R
SENSE
0.007Ω
PCB EDGE
CONNECTOR
(MALE)
M2
Si4410DY
Z1 R3
10k
R2
10k
R1
10k
R8
10k
R4
36k R7
10k
µP
LOGIC
RESET
SHORT
SHORT
LAST BLADE OR PIN ON CONNECTOR
SHORT
C
X
0.1µF
BACKPLANE
CONNECTOR
(FEMALE)
Q1
Q2
LAST BLADE OR PIN ON CONNECTOR
Figure 16. Connection Sense for Rocking the Daughter Board Back and Forth
27
LTC4230
4230f
4
3
2 1
10µA
FB
n
R
ZX
LTC4230*
V
CC
n
SENSE
n
V
Z
(TYP) = 26V
R
SENSE
V
CC
> 15V
200µA
10µA
CHARGE
PUMP
R2
*ADDITIONAL DETAILS OMITTED FOR CLARITY
4230 F17
R1
V
OUT
LOGIC
Figure 17. Using an External Resistor to Limit
Zener Current in High VCC Applications
Figure 18. Autoretry Application
HIGH SUPPLY VOLTAGE OPERATION
CONSIDERATIONS
The LTC4230 can be used with supply voltages ranging
from 1.7V to 16.5V. At high input supply voltages, the
internal charge pump produces a minimum gate drive
voltage of 7V for V
CC
> 15V. This minimum voltage drive
is derived by an internal zener diode clamp circuit, as
shown in Figure 17. During PC board insertion or removal,
sufficient transient current may flow through this zener
diode. To limit the amount of current during transient
events, an optional small resistor between the LTC4230’s
GATE
n
pin and the gate of the external MOSFET can be
used, as shown in Figure 17. A secondary benefit of this
component is to minimize the possibility of high frequency
parasitic oscillations in the power MOSFET.
APPLICATIO S I FOR ATIO
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PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
V
CC1
3.3V
LONG
V
CC2
2.5V
LONG
V
CC3
1.8V
LONG
SHORT
R
AUTO
1M
FAULT
GND LONG
R
SENSE2
0.007Ω
CX2
100nF
CX1
100nF
RX2
10Ω
M2
IRF7413
V
CC1
GND
ON
FAULT
14
67 8 16171854 3
FB3 1
15
13
SENSE 1 GATE 1
TIMER FILTER
V
CC2
SENSE 2 GATE 2 SENSE 3 GATE 3V
CC3
RESET 3 2
R
SENSE3
0.007Ω
RX1
10Ω
R8
5.1k
R9
12k
M3
IRF7413
V
OUT1
3.3V
5A
V
OUT2
2.5V
5A
V
OUT3
1.8V
5A
R
SENSE1
0.007Ω
CX3
100nF
RX3
10Ω
C
TIMER
*
0.1µFC
FILTER
**
15pF
C
AUTO
0.1µF
M1
IRF7413
Z3
Z2
Z1
* SYSTEM ON TIME: 6.2ms
**CIRCUIT BREAKER RESPONSE TIME: 19.5µs
Z1, Z2, Z3: Z1: SMAJ10
NOTE: M1 MOUNTED TO 300mm COPPER AREA
WITHOUT C
AUTO
YIELDS 8% AND M1 CASE = 65°C
WITH C
AUTO
= 0.1µF YIELDS 4% and M1 CASE = 45°C
RESET 2 19
FB2 20
R7
10k
RESET 1 9
FB1 10
1112
R10
11k
R11
12k R6
10k
R12
18k
R13
12k
4230 F18
R5
10k
MASTER
RESET
3-INPUT
NOR GATE
µP OR
SYSTEM LOGIC
C
OUT3
C
OUT2
C
OUT1
LTC4230
+
+
+
28
LTC4230
4230f
APPLICATIO S I FOR ATIO
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AUTORETRY AFTER A FAULT
To configure the LTC4230 to automatically retry after a
fault condition, the FAULT (which has an internal 2µA pull-
up current source) and ON pins can be connected to-
gether, as shown in Figure 18. In this case, the autoretry
circuitry will attempt to restart the LTC4230 with an 7%
duty cycle, as shown in the timing diagram of Figure 19. To
prevent overheating the external MOSFET and other com-
ponents during the autoretry sequence, adding a capacitor
(C
AUTO
) to the circuit introduces a delay at the ON pin that
adjusts the autoretry duty cycle. Equation 14 gives the
autoretry duty cycle, modified by the external time con-
stant C
AUTO
:
AutoretryDuty Cycle =+t
tt
TIMER
OFF TIMER
14 5 100
.• •%
(14)
where t
TIMER
= LTC4230 system time constant (see TIMER
function) and
tCV
A
OFF AUTO
=µ
•.1 314
2
For the values shown, the external delay equals 65.7ms
and the autoretry duty cycle drops from 7% to 4%.
To increase the RC delay, the user may either increase
C
AUTO
or R
AUTO
.
OVERVOLTAGE TRANSIENT PROTECTION
Good engineering practice calls for bypassing the supply
rail of any analog circuit. Bypass capacitors are often
placed at the supply connection of every active device, in
addition to one or more large value bulk bypass capacitors
per supply rail. If power is connected abruptly, the large
bypass capacitors slow the rate of rise of the supply
voltage and heavily damp any parasitic resonance of lead
or PC track inductance working against the supply bypass
capacitors.
CHECK FOR
TIMER < 0.3V
1 3 765 84
FIRST TIMING CYCLE
4230 F19
SECOND TIMING CYCLE DISCHARGING MODENORMAL MODE
CHECK FOR FILTER LOW (< V
REF
)
CHECK FOR FAULT HIGH (> V
REF
+ 50mV)
2
CHECK FOR GATE
n
< 0.25V FAST COMPARATOR
ARMED SLOW COMPARATOR
ARMED ONCE V
FILTER
> 1.26V, CIRCUIT BREAKER TRIPS,
ALL GATE
n
PINS PULL LOW IMMEDIATELY
20µA PULL-UP 1.6µA PULL-DOWN
2µA PULL-UP
V
FILTER
> 1.26V
V
REF
10µA PULL-DOWN
LOAD CURRENT < 150mV/R
SENSE
n
20µA PULL-UP
9
ON/
TIMER
GATE
n
V
OUT
n
I
LOAD
n
FILTER
FAULT
GATE
n
V
OUT
n
V
SENSE
n
= 50mV
REGULATED
LOAD
CURRENT
Figure 19. Autoretry Timing
29
LTC4230
4230f
Figure 20. Placing Transient Protection
Devices Close to the LTC4230
+
4
3
2 1
V
CC
n
SENSE
n
LTC4230*
1214
C
LOAD
n
V
OUT
4230 F20
15
R2
GATE
n
GND TIMER
C
TIMER
FB
n
ON ON
RESET
n
10Ω
V
IN
R
SENSE
0.007ΩQ
n
Si4410DY
R1
RESET
0.1µF
SMAJ10
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
The opposite is true for LTC4230 Hot Swap circuits
mounted on plug-in cards. In most cases, there is no
supply bypass capacitor present on the powered supply
voltage side of the MOSFET switch. An abrupt connection,
produced by inserting the board into a backplane connec-
tor, results in a fast rising edge applied on the supply line
of the LTC4230.
Since there is no bulk capacitance to damp the parasitic
track inductance, supply voltage transients excite
parasitic resonant circuits formed by the power MOSFET
capacitance and the combined parasitic inductance from
the wiring harness, the backplane and the circuit board
traces. These ringing transients appear as a fast edge on
the input supply line, exhibiting a peak overshoot to 2.5
times the steady-state value. This peak is followed by a
damped sinusoidal response whose duration and period
are dependent on the resonant circuit parameters. Since
the absolute maximum supply voltage of the LTC4230 is
17V, transient protection against VCC > 16.8V supply
voltage spikes and ringing is highly recommended.
I
n these applications, there are two methods for eliminat-
ing these supply voltage transients: using zener diodes to
clip the transient to a safe level and snubber networks.
Snubber networks are series RC networks whose time
constants are experimentally determined based on the
board’s parasitic resonance circuits. As a starting point,
the capacitors in these networks are chosen to be 10× to
100× the power MOSFET’s COSS under bias. The series
resistor is a value determined experimentally and ranges
from 1Ω to 50Ω, depending on the parasitic resonance
circuit. Note that in all LTC4230 circuit schematics,
TransZorb
®
diodes and snubber networks have been
added to each 3.3V and 5V supply rail. These protection
networks should be mounted very close to the LTC4230’s
supply voltage using short lead lengths to minimize lead
inductance. This is shown schematically in Figure 20, and
a recommended layout of the transient protection devices
around the LTC4230 is shown in Figure 21.
ADDITIONAL SUPPLY OVERVOLTAGE
DETECTION/PROTECTION
In addition to using external protection devices around the
LTC4230 for large scale transient protection, low power
zener diodes can be used with the LTC4230’s FILTER pin
to act as a supply overvoltage detection/protection circuit
on either the high side (input) or low side (output) of the
external pass transistor. Recall that internal control cir-
cuitry keeps the LTC4230 GATE
n
voltage from ramping up
if V
FILTER
> 1.26V, or when an external fault condition
(V
FAULT
< 1.234V) causes FAULT to be asserted low.
High Side (Input) Overvoltage Protection
As shown in Figure 22, a low power zener diode can be
used to sense an overvoltage condition on the input
(high) side of the main 5V supply. In this example, a low
APPLICATIO S I FOR ATIO
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V
CC2
4230 F21
NOTE: DRAWING IS NOT TO SCALE!
USE SIMILAR TECHNIQUES FOR V
CC1
AND V
CC3
*ADDITIONAL DETAILS OMITTED FOR CLARITY
SNUBBER
NETWORK
VIAS TO
GND PLANE
C
X
R
X
Z
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC2
ON
GND
LTC4230*
Figure 21. Recommended Layout
for Transient Protection Devices
TransZorb is a registered trademark of General Instruments, GSI.
30
LTC4230
4230f
APPLICATIO S I FOR ATIO
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Figure 22. LTC4230 High Side Overvoltage Protection Implementation
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
VCC1
3.3V
LONG
VCC2
2.5V
LONG
VCC3
1.8V
ON/OFF
LONG
SHORT
FAULT
GND LONG
SHORT
10k
RSENSE2
0.007Ω
CX2
100nF
CX1
100nF
RX2
10Ω
M2
IRF7413
VCC1
GND
ON
FAULT LTC4230
14
FB3 1
15
13
SENSE 1 GATE 1
FILTER TIMER
VCC2 SENSE 2 GATE 2 SENSE 3 GATE 3VCC3
RESET 3 2
RSENSE3
0.007Ω
RX1
10Ω
R8
5.1k
R9
12k
M3
IRF7413
VOUT1
3.3V
5A
VOUT2
2.5V
5A
VOUT3
1.8V
5A
RSENSE1
0.007Ω
CX3
100nF
RX3
10Ω
CFILTER
15pF
CTIMER
0.1µF
R4
10k
OPTIONAL
VCC1
10k
VCC1
R5
10k
M4
VCC1
M1
IRF7413
Z3
VCC1
Z2
Z1
RESET 2 19
FB2 20
R7
10k
RESET 1 9
FB1 10
R10
11k
R11
12k R6
10k
R12
18k
R13
12k
4230 F22
R5
10k
µP OR
SYSTEM LOGIC
MASTER
RESET
3-INPUT
NOR GATE
67 816171854 3
1211
COUT3
COUT2
COUT1
VCC2 VCC3
6.2V
Z4 Z5 Z6
M4: 2N7002LT1
Z1, Z2, Z3: SMAJ10
Z4, Z5, Z6: 1N4691
NOTE: FOR ANY VCC
n
> 7.7V, THE
LTC4230 IS IN OVERVOLTAGE
PROTECTION MODE, FAULT IS PULLED LOW
+
+
+
31
LTC4230
4230f
APPLICATIO S I FOR ATIO
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bias current 1N4691 zener diode is chosen to protect the
system. Here, the zener diode is connected from V
CC
to
the LTC4230’s FILTER pin. If the input voltage to the
system is greater than 6.8V during start-up, the voltage
on the FILTER pin is pulled higher than its 1.19V thresh-
old. As a result, the GATE
n
pin is not allowed to ramp and
the second timing cycle will not commence until the
supply overvoltage condition is removed. Should the
supply overvoltage condition occur during normal op-
eration, internal control logic would trip the electronic
circuit breaker and the GATE would be pulled to ground,
shutting off the external pass transistor. If a lower supply
overvoltage threshold is desired, use a zener diode with
a smaller breakdown voltage.
A timing diagram for illustrating LTC4230 operation under
a high side overvoltage condition is shown in Figure 23.
The start-up sequence in this case (between Time Points
1 and 2) is identical to any other start-up sequence under
normal operating conditions. At Time Point 2, the input
supply voltage causes the zener diode to conduct thereby
forcing V
FILTER
> 1.19V. At Time Point 3, FAULT is asserted
low and the TIMER pin voltage ramps down. At Time
Point␣ 4, the LTC4230 checks if V
FILTER
< 1.19V. FAULT is
asserted low (but not latched) to indicate a start-up failure.
Only if the input overvoltage condition is removed before
Time Point 5 does the start-up sequence resume at the
second timing cycle. At this point in time, the GATE
n
pin
voltage is allowed to ramp up, FAULT is pulled to logic high
and the circuit breaker is armed. Should, at any time after
Time Point 5, a supply overvoltage condition develop
(V
FILTER
> 1.26V), the electronic circuit breaker will trip,
the GATE
n
will be pulled low to turn off the external
MOSFET and FAULT will be asserted low and latched.
Low Side (Output) Overvoltage Protection
A zener diode can be used in a similar fashion to detect/
protect the system against a supply overvoltage condition
on the load (or low) side of the pass transistor. In this case,
the zener diode is connected from the load to the LTC4230’s
FILTER pin, as shown in Figure 24. An additional diode,
D1, prevents the FILTER pin from pulling low during
output short-circuit. Figure 25 illustrates the timing dia-
gram for a low side output overvoltage condition. In this
example, the LTC4230 can only sense the overvoltage
supply condition after Time Point 5 and the GATE
n
pin has
ramped up to its nominal operating value. After Time
Point␣ 5, a supply voltage fault occurs at the load and the
zener diode conducts, causing V
FILTER
to increase. At Time
Point 6, V
FILTER
is greater than 1.26V, the circuit breaker
trips, GATE pulls to ground and FAULT asserts low and is
latched.
In either case, the LTC4230 can be configured to auto-
matically initiate a start-up sequence. Please refer to the
section on AutoRetry After a Fault for additional
information.
PCB LAYOUT CONSIDERATIONS
For proper operation of the LTC4230’s circuit breaker
function, a 4-wire Kelvin connection to the sense resistors
is highly recommended. A recommended PCB layout for
the sense resistor, the power MOSFET and the GATE drive
components around the LTC4230 is illustrated in Fig-
ure␣ 26. In Hot Swap applications where load currents can
reach 10A or more, narrow PCB tracks exhibit more
resistance than wider tracks and operate at more elevated
temperatures. Since the sheet resistance of 1 ounce
copper foil is approximately 0.54mΩ/square, track resis-
tances add up quickly in high current applications. Thus,
to keep PCB track resistance and temperature rise to a
minimum, PCB track width must be appropriately sized.
Consult Appendix A of LTC Application Note 69 for details
on sizing and calculating trace resistances as a function of
copper thickness.
In the majority of applications, it will be necessary to use
plated-through vias to make circuit connections from
component layers to power and ground layers internal to
the PC board. For 1 ounce copper foil plating, a good
starting point is 1A of DC current per via, making sure the
via is properly dimensioned so that solder completely fills
any void. For other plating thicknesses, check with your
PCB fabrication facility.
32
LTC4230
4230f
Figure 23. High Side Overvoltage Protection Timing
1 3 7654
4230 F23
FAULT IS PULLED LOW (BUT NOT LATCHED), SINCE THE
OVERVOLTAGE HAPPENED BEFORE THE END OF THE FIRST TIMING CYCLE
CHECK FOR FILTER LOW (< V
REF
)
CHECK FOR FAULT HIGH (> V
REF
+ 50mV)
2
FAST COMPARATOR
ARMED
IF THE OVERVOLTAGE GOES AWAY,
THE SECOND CYCLE CONTINUES
SLOW COMPARATOR
ARMED
FILTER < 1.19V
ON
TIMER
GATE
n
V
OUT
n
FILTER
FAULT
RESET
GATE
n
V
OUT
n
CHECK FOR
GATE
n
< 0.25V
POWER GOOD
APPLICATIO S I FOR ATIO
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33
LTC4230
4230f
Figure 24. LTC4230 Low Side Overvoltage Protection Implementation
APPLICATIO S I FOR ATIO
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LONG
LONG
LONG
SHORT
LONG
SHORT
10k
R
SENSE2
0.007Ω
CX2
100nF
CX1
100nF
RX2
10Ω
M2
IRF7413
V
CC1
GND
ON
FAULT LTC4230
14 FB3 1
15
13
SENSE 1 GATE 1
FILTER TIMER
V
CC2
SENSE 2 GATE 2 SENSE 3 GATE 3V
CC3
RESET 3 2
R
SENSE3
0.007Ω
RX1
10Ω
R8
5.1k
R9
12k
M3
IRF7413
V
OUT1
3.3V
5A
V
OUT2
2.5V
5A
V
OUT3
1.8V
5A
R
SENSE1
0.007Ω
CX3
100nF
RX3
10Ω
C
FILTER
15pF
C
TIMER
0.1µF
R4
10k
OPTIONAL
V
CC1
10k
V
CC1
R5
10k
M4
V
CC1
M1
IRF7413
Z3
V
OUT1
Z2
Z1
RESET 2 19
FB2 20
R7
10k
RESET 1 9
FB1 10
R10
11k
R11
12k R6
10k
R12
18k
R13
12k
4230 F24
R5
10k
µP OR
SYSTEM LOGIC
MASTER
RESET
3-INPUT
NOR GATE
67 816171854 3
1211
D1: 1N4148
M4: 2N7002LT1
Z1, Z2, Z3: SMAJ10
Z4, Z5, Z6: 1N4691
NOTE: FOR ANY V
OUT
n
> 8.4V, THE
LTC4230 IS IN OVERVOLTAGE
PROTECTION MODE, FAULT IS PULLED LOW
C
OUT3
C
OUT2
C
OUT1
V
OUT2
V
OUT3
6.2V
Z4 Z5 Z6 D1
+
+
+
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
V
CC1
3.3V
V
CC2
2.5V
V
CC3
1.8V
ON/OFF
FAULT
GND
34
LTC4230
4230f
Figure 25. Low Side Overvoltage Protection Timing
1 3 7654
4230 F24
CHECK FOR FILTER LOW (< VREF)
CHECK FOR FAULT HIGH (> VREF + 50mV)
8
FAST COMPARATOR
ARMED
9
FILTER < 1.19V
FILTER < 1.26V
1.234V
ON
TIMER
RESET
n
GATE
n
VOUT
n
FILTER
FAULT
CHECK FOR
TIMER < 0.3V
2
CHECK FOR
GATE
n
< 0.25V
APPLICATIO S I FOR ATIO
WUUU
35
LTC4230
4230f
Figure 26. Recommended Layout for LTC4230 RSENSE, Power MOSFET and Feedback Network
4230 F26
NOTE: DRAWING IS NOT TO SCALE!
USE SIMILAR TECHNIQUES FOR V
CC1
AND V
CC2
**ADDITIONAL DETAILS OMITTED FOR CLARITY
*OPTIONAL COMPONENTS
C
TIMER
C
GX
*
VIA TO
GNDPLANE
R
GX
*
12k
5.1k
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
TIMER
LTC4230**
FB3
RESET 3
GATE 3
SENSE 3
V
CC3
D
D
D
D
G
S
S
S
POWER MOSFET
SO-8
SENSE RESISTOR
(R
SENSE
)
CURRENT FLOW
TO LOAD
TRACK WIDTH W
W
W
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
W
APPLICATIO S I FOR ATIO
WUUU
APPE DIX
U
Table 4 lists some current sense resistors that can be used
with the circuit breaker. Table 5 lists some power MOSFETs
that are available. Table 6 lists the web sites of several
manufacturers. Since this information is subject to change,
please verify the part numbers with the manufacturer.
Table 4. Sense Resistor Selection Guide
CURRENT LIMIT VALUE PART NUMBER DESCRIPTION MANUFACTURER
1A LR120601R050 0.05Ω 0.5W 1% Resistor IRC-TT
2A LR120601R025 0.025Ω 0.5W 1% Resistor IRC-TT
2.5A LR120601R020 0.02Ω 0.5W 1% Resistor IRC-TT
3.3A WSL2512R015F 0.015Ω 1W 1% Resistor Vishay-Dale
5A LR251201R010F 0.01Ω 1.5W 1% Resistor IRC-TT
10A WSR2R005F 0.005Ω 2W 1% Resistor Vishay-Dale
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
36
LTC4230
4230f
LT/TP 0702 2K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2001
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1421 2-Channel Hot Swap Controller 24-Pin, Operates from 3V to 12V and Supports –12V
LTC1422 Single Channel Hot Swap Controller in SO-8 Operates from 2.7V to 12V
LT1641-1/LT1641-2 Positive Voltage Hot Swap Controller Operates from 9V to 80V
LTC1642 Single Channel Hot Swap Controller 16-Pin, Overvoltage Protection to 33V
LTC1644 PCI Hot Swap Controller 3.3V, 5V and ±12V, 1V Precharge, PCI Reset Logic
LTC1647 Dual Channel Hot Swap Controller 8-Pin, 16-Pin, Operates from 2.7V to 16.5V
LTC4211 Single Hot Swap Controller with Multifunction Current Control 2.5V to 16.5V, Similar Features as LTC4230
LT4250L/LT4250H Negative Voltage Hot Swap Controllers in SO-8 Operates from –20V to –80V, Active Current Limiting
LTC4251 –48V Hot Swap Controller in SOT-23 –15V to –100V, Active Current Limiting
U
PACKAGE DESCRIPTIO
GN Package
20-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
Table 5. N-Channel MOSFET Selection Guide
CURRENT LEVEL (A) PART NUMBER DESCRIPTION MANUFACTURER
0 to 2 MMDF3N02HD Dual N-Channel SO-8, R
DS(ON)
= 0.09Ω, C
ISS
= 455pF ON Semiconductor
2 to 5 MMSF5N02HD Single N-Channel SO-8, R
DS(ON)
= 0.025Ω, C
ISS
= 1130pF ON Semiconductor
5 to 10 MTB50N06V Single N-Channel DD Pak, R
DS(ON)
= 0.028Ω, C
ISS
= 1570pF ON Semiconductor
10 to 20 MTB75N05HD Single N-Channel DD Pak, R
DS(ON)
= 0.0095Ω, C
ISS
= 2600pF ON Semiconductor
Table 6. Manufacturers’ Web Sites
MANUFACTURER WEB SITE MANUFACTURER WEB SITE
TEMIC Semiconductor www.temic.com IRC-TT www.irctt.com
International Rectifier www.irf.com Vishay-Dale www.vishay.com
ON Semiconductor www.onsemi.com Vishay-Siliconix www.vishay.com
Intersil www.intersil.com Diodes, Inc. www.diodes.com
APPE DIX
U
0.337 – 0.344*
(8.560 – 8.737)
GN20 (SSOP) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 12
345678910
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1617181920 15 14 13 12 11
0.016 – 0.050
(0.406 – 1.270)
0.015 ± 0.004
(0.38 ± 0.10) × 45°
0° – 8° TYP
0.007 – 0.0098
(0.178 – 0.249)
0.053 – 0.068
(1.351 – 1.727)
0.008 – 0.012
(0.203 – 0.305)
0.004 – 0.0098
(0.102 – 0.249)
0.0250
(0.635)
BSC
0.058
(1.473)
REF
