14
2118A–HIREL–11/05
TS68332
7. Stability is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSS and variation in crystal oscillator frequency increase the Cstab percentage
for a given interval. When clock stability is a critical constraint on control system operation, this parameter should be mea-
sured during functional testing of the final system.
.
Table 7-3. AC Timing. VDD and VDDSYN = 5.0 VDC ± 10% for 16.78 MHz and 5.0 VDC ± 5% for 20.97 MHz; VSS = 0 VDC;
TC = -55°C to +125°C or -40°C to +85°C (1)
Number Symbol Parameter
16.78 MHz 20.97 MHz
UnitMin Max Min Max
F1 f Frequency of operation (32.768 kHz crystal)(2) 0.13 16.78 0.13 20.97 MHz
1t
CYC Clock period 59.6 - 47.7 - ns
1A tEcyc ECLK period 476 - 381 - ns
1B tXcyc External clock input period(3) 59.6 - 47.7 - ns
2, 3 tCW Clock pulse width 24 - 18.8 - ns
2A, 3A tECW ECLK pulse width 236 - 183 - ns
2B, 3B tXCHL External clock input high/low time(3) 29.8 - 23.8 - ns
4, 5 tCrf Clock rise and fall time - 5 - 5 ns
4A, 5A trt Rise and fall time - All outputs except CLKOUT - 8 - 8 ns
4B, 5B TXCrf External clock rise and fall time(4) -5-5ns
6t
CHAV Clock high to address, FC, SIZE, RMC valid 0 29 0 23 ns
7t
CHAZx Clock high to address, Data, FC, SIZE, RMC high
impedance 0 59 0 47 ns
8t
CHAZn Clock high to address, FC, SIZE, RMC invalid 0 - 0 - ns
9t
CLSA Clock low to AS, DS, CS, asserted 2 25 0 23 ns
9A tSTSA AS to DS or CS, asserted (read)(5) -15 15 -10 10 ns
9C tCLIA Clock low to IFETCH, IPIPE asserted 2 22 2 22 ns
11 tAVSA Address, FC, SIZE, RMC valid to AS, CS (and DS
read) asserted 15 - 10 - ns
12 tCLSN Clock low to AS, DS, CS negated 2 29 2 23 ns
12A tCLIN Clock low to IFETCH, IPIPE negated 2 22 2 22 ns
13 tSNAI AS, DS, CS negated to address, FC, SIZE invalid
(address hold) 15 - 10 - ns
14 tSWA AS, CS (and DS read) width asserted 100 - 80 - ns
14A tSWAW DS, CS, width asserted (write) 45 - 36 - ns
14B tSWDW AS, CS (and DS read) width asserted (fast write
cycle) 40 - 32 - ns
15 tSN AS, DS, CS width negated(6) 40 - 32 - ns
16 tCHSZ Clock high to AS, DS, R/W high impedance - 59 - 47 ns
17 tSNRN AS, DS, CS negated to R/W negated 15 - 10 - ns
18 tCHRH Clock high to R/W high 0 29 0 23 ns