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LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL

FANOUT BUFFER ICS85311

IDT™ / ICS™

LVPECL/ECL FANOU T BUFFER 1

ICS85311AM REV. D OCTOBER 22, 2008

General Description

The ICS85311 is a low skew, high perfor- mance

1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL

Fanout Buffer and a member of the HiPerClockS™

family of High Performance Clock Solutions from

IDT. The CLK, nCLK pair can accept most standard

differential input levels.The ICS85311 is characterized to operate

from either a 2.5V or a 3.3V power supply. Guaranteed output and

part-to-part skew characteristics make the ICS85311 ideal for

those clock distribution applications demanding well defined

performance and repeatability.

Features

•Two differential 2.5V/3.3V LVPECL / ECL outputs

•One CLK, nCLK input pair

•CLK, nCLK pair can accept the following differential input levels:

LVDS, LVPECL, LVHSTL, SSTL, HCSL

•Maximum output frequency: 1GHz

•Translates any single ended input signal to 3.3V LVPECL levels

with resistor bias on nCLK input

•Output skew: 15ps (maximum)

•Part-to-part skew: 100ps (maximum)

•Propagation delay: 1.4ns (maximum)

•Additive phase jitter, RMS: 0.14ps (typical), 3.3V

•LVPECL mode operating voltage supply range:

VCC = 2.375V to 3.465V, VEE = 0V

•ECL mode operating voltage supply range:

VCC = 0V, VEE = -2.375V to -3.465V

•0°C to 70°C ambient operating temperature

•Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

HiPerClockS™

ICS

nQ0

nQ1

CLK

nCLK Pullup

Pulldown

VCC

CLK

nCLK

VEE

nQ1

nQ0

ICS85311

8-Lead SOIC

3.90mm x 4.903mm x 1.37mm package body

M Package

Top View

Pin Assignment

Block Diagram

ICS85311

LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPEC L/ECLFANOUT BUFFER

IDT™ / ICS™

LVPECL/ECL FANOU T BUFFER 2

ICS85311AM REV. D OCTOBER 22, 2008

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

1, 2 Q0, nQ0 Output Differential output pair. LVPECL interface levels.

3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels.

EE Power Negative supply pin.

6 nCLK Input Pullup Inverting differential clock input.

7 CLK Input Pulldown Non-inverting differential clock input.

CC Power Positive supply pin.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4 pF

RPULLUP Input Pullup Resistor 51 kΩ

RPULLDOWN Input Pulldown Resistor 51 kΩ

ICS85311

LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPEC L/ECLFANOUT BUFFER

IDT™ / ICS™

LVPECL/ECL FANOU T BUFFER 3

ICS85311AM REV. D OCTOBER 22, 2008

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

DC Electrical Characteristics

Table 3A. Power Supply DC Characteristics, VCC = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = 0°C to 70°C

Table 3B. Differential DC Characteristics, VCC = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = 0°C to 70°C

NOTE 1: VIL should not be less than -0.3V.

NOTE 2: Common mode voltage is defined as VIH.

Item Rating

Supply Voltage, VCC 4.6V

Inputs, VI-0.5V to VCC + 0.5V

Outputs, IO

Continuos Current

Surge Current

50mA

100mA

Storage Temperature, TSTG -65°C to 150°C

Package Thermal Impedance, θJA 112°C/W (0 lfpm)

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VCC Positive Supply Voltage 3.135 3.3 3.465 V

2.375 2.5 2.625 V

IEE Power Supply Current 25 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

IIH Input High Current nCLK VCC = VIN = 3.465V or 2.625V 5 µA

CLK VCC = VIN = 3.465V or 2.625V 150 µA

IIL Input Low Cureent nCLK VCC = 3.465V or 2.625V, VIN = 0V -150 µA

CLK VCC = 3.465V or 2.625V, VIN = 0V -5 µA

VPP

Peak-to-Peak Input Voltage;

NOTE 1 0.15 1.3 V

VCMR

Common Mode Input Voltage;

NOTE 1, 2 VEE + 0.5 VCC – 0.85 V

ICS85311

LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPEC L/ECLFANOUT BUFFER

IDT™ / ICS™

LVPECL/ECL FANOU T BUFFER 4

ICS85311AM REV. D OCTOBER 22, 2008

Table 3C. LVPECL DC Characteristics, VCC = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = 0°C to 70°C

NOTE1: Outputs terminated with 50Ω to VCC – 2V.

AC Electrical Characteristics

Table 4A. AC Characteristics, VCC = 3.3V±5%, VEE = 0V, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal

equilibrium has been reached under these conditions.

All parameters are measured 500MHz unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross

points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.

Using the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Table 4B. AC Characteristics, VCC = 2.5V±5%, VEE = 0V, TA = 0°C to 70°C

See Table 5A for NOTES.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOH Output High Current; NOTE 1 VCC – 1.4 VCC – 0.9 V

VOL Output Low Current; NOTE 1 VCC – 2.0 VCC – 1.7 V

VSWING Peak-to-Peak Output Voltage Swing 0.65 1.0 V

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Maximum Output Frequency 1GHz

tPD Propagation Delay; NOTE 1 ƒ ≤ 1GHz 0.9 1.4 ns

tjit

Buffer Additive Phase Jitter,

RMS; refer to Additive Phase

Jitter Section

156.25MHz, Integration Range

(12kHz – 20MHz) 0.14 ps

tsk(o) Output Skew; NOTE 2, 4 15 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 100 ps

tR / tFOutput Rise/Fall Time 20% to 80% @ 50MHz 300 700 ps

odc Output Duty Cycle 48 52 %

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Maximum Output Frequency 1GHz

tPD Propagation Delay; NOTE 1 ƒ ≤ 1GHz 0.9 1.4 ns

tjit

Buffer Additive Phase Jitter,

RMS; refer to Additive Phase

Jitter Section

156.25MHz, Integration Range

(12kHz – 20MHz) 0.135 ps

tsk(o) Output Skew; NOTE 2, 4 15 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 100 ps

tR / tFOutput Rise/Fall Time 20% to 80% @ 50MHz 300 700 ps

odc Output Duty Cycle 48 52 %