1
©2007 Integrated Device Technology, Inc.
OCTOBER 2008
DSC-3822/04
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
IDT71V547S/XS
Pin Description Summary
The IDT71V547 contains address, data-in and control signal registers.
The outputs are flow-through (no output data register). Output enable is
the only asynchronous signal and can be used to disable the outputs at
any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V547 to
be suspended as long as necessary. All synchronous inputs are
ignored when CEN is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three is not active
when ADV/LD is low, no new memory operation can be initiated and any
burst in progress is stopped. However, any pending data transfers (reads
or writes) will be completed. The data bus will tri-state one cycle after the
chip was deselected or write initiated.
The IDT71V547 has an on-chip burst counter. In the burst mode, the
IDT71V547 can provide four cycles of data for a single address presented
to the SRAM. The order of the burst sequence is defined by the LBO input
pin. The LBO pin selects between linear and interleaved burst sequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/LD = HIGH).
The IDT71V547 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for high board density.
Features
◆◆
◆◆
◆128K x 36 memory configuration, flow-through outputs
◆◆
◆◆
◆Supports high performance system speed - 95 MHz
(8ns Clock-to-Data Access)
◆◆
◆◆
◆ZBTTM Feature - No dead cycles between write and read
cycles
◆◆
◆◆
◆Internally synchronized signal eliminates the need to
control OE
◆◆
◆◆
◆Single R/W (READ/WRITE) control pin
◆◆
◆◆
◆4-word burst capability (Interleaved or linear)
◆◆
◆◆
◆Individual byte write (BW1 - BW4) control (May tie active)
◆◆
◆◆
◆Three chip enables for simple depth expansion
◆◆
◆◆
◆Single 3.3V power supply (±5%)
◆◆
◆◆
◆Packaged in a JEDEC standard 100-pin TQFP package
Description
The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate
dead bus cycles when turning the bus around between reads and writes,
or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus
Turn-around.
Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle, its associated data cycle occurs, be it
read or write.
128K X 36, 3.3V Synchronous
SRAM with ZBT™ Feature, Burst
Counter and Flow-Through Outputs
A
0
- A
16
Address Input s Input Sy nchronous
CE
1
, CE
2
, CE
2
Three Chip Enables Input Sy nchronous
OE Out put Enable Input Asy nchronous
R/WR ead/ Write S ignal Input Sy nchronous
CEN Clock Enable Input Sy nchronous
BW
1
, BW
2
, BW
3
, BW
4
Ind iv idual By te Write Selects Input Sy nchronous
CLK Clock Input N/A
ADV/LD Adv ance Burst Add ress / Load New Address Input Sy nchronous
LBO Linear / Interleav ed Burst O rder Input St atic
I/O
0
- I /O
31
, I/O
P1
-
I/O
P4
Dat a Input /Output I/O Sy nchronous
V
DD
3.3V Pow er Supply St atic
V
SS
Ground Supply Static
3822 tbl 01
2
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol Pin Function I/O Active Description
A
0
- A
16
Address Inputs I N/ A Sy nchr onous Address inputs. The address register is trig gered by a com bination
of t he rising edge of CLK, ADV/LD Low, CEN Low and true chip enables.
ADV/LD Address/Load I N/A ADV/LD is a synchronous input that is used to load the in ternal registers with new
address and control w hen it is sam pled low at t he rising edge of clock with the
ch ip selected. When ADV/LD is low wit h t he chip deselected, any burst in
progress is term inated. When ADV/LD is sam pled high then t he internal burst
counte r is advanced for any burst that was in progress. The external addresses
are ignored w hen ADV/ LD is sam pled high.
R/WRead/Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle
initiated is a Read or Writ e access to the m em ory array. The data bus activ ity for
the current cy cle takes place one clock cy cle later.
CEN Clock Enable I LOW Sy nchronous Clock Enable Input. When CEN is sam pled high, all other
sy nchr onous inputs, including clock are ignored and out puts rem ain unchanged.
The ef fect of CEN sam pled high on t he dev ice output s is as if t he low to high
clock transition did not occu r. For norm al operation, CEN must be sam pled low at
rising edge of clock.
BW
1
- BW
4
Individual Byte
Write Enables I LOW Sy nchronous byt e w rite enables. Enable 9-bit by te has its ow n active low byt e
w rite enable. On loa d write cycles (When R/W and ADV/ LD are sam pled low) the
appropriate byte w rite signal (BW
1
- BW
4
) m ust be v alid. The by te w rite signal
m ust a lso be v alid on each cy cle of a burst w rite. By te Write signals are ignored
w hen R/W is sam pled high. The appropriate by te(s) of dat a are w ritten int o the
dev ice one cycle lat er. BW
1
- BW
4
can a ll be t ied low if a lw ay s doin g w rit e t o t he
entire 36-bit w ord.
CE
1
, CE
2
Chip Enables I LO W Sy nchronous active low chip enable. CE
1
and CE
2
are used w ith CE
2
to
e nable the IDT71V547. (CE
1
or CE
2
sam pled high or CE
2
sam pled low ) and
ADV/LD low at t he rising edge of clock, init iates a deselec t cy cle. This device has
a one cy cle deselect, i. e., the dat a bus w ill t ri-state one clock cycle af ter deselect
is init iat e d.
CE2 Chip Enable I HI GH Sy nchronout act ive high chip enable. CE
2
is used with CE
1
and CE
2
to enable
the chip. CE
2
has inverted polarit y b ut otherw ise identical to CE
1
and CE
2
.
CLK Clock I N/A This is the clock input to the IDT71V547. Except for OE, all tim ing references for
the dev ice are m ade with respect to the rising edge of CLK.
I/O
0
- I /O
31
I/O
P1 -
I/O
P4
Dat a Input/ Output I/ O N/ A Data input/out put (I/ O) pins. The data input path is reg istered, triggered by the
rising edge of CLK. The data out put path is flow -through (no output register).
LBO Linear Burst
Order I LO W Burst ord e r select ion in put . When LBO is high the I nterleav ed burst sequence is
selected. When LBO is low the Linear burs t sequence is selected. LBO is a st at ic
DC input.
OE Output Enable I LOW Asy nchronous output enable. OE m ust be low to read dat a f rom the 71V547.
When OE is high the I/O pins are in a high-impedance state. OE does not need
to be actively controlled for read and write cy cles. I n norm al operation, OE can be
tied low.
V
DD
Pow er Supply N/ A N/ A 3 .3V pow er supply input .
V
SS
Ground N/A N/A Ground pin.
3822 tbl 02
6.42
3
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Functional Block Diagram
Recommended Operating
Temperature and Supply Voltage Recommended DC Operating
Conditions
Clk
DQ
DQ
DQ
Address A [0:16]
Control Logic
Address
Control
DI DO
InputRegister
3822 drw 01
Clock
Data I/O [0:31], I/O P[1:4]
Mux Sel
Gate
OE
CE
1
,CE2CE
2
R/W
CEN
ADV/LD
BWx
LBO 128K x 36 BIT
MEMORY ARRAY
,
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
Grade Temperature V
SS
V
DD
Commercial 0
O
C to +70
O
C0V 3.3V±5%
Industrial -40
O
C to +85
O
C0V 3.3V±5%
3822 tbl 03
Symbol Parameter Min. Typ. Max. Unit
VDD Sup p ly Vo ltage 3.135 3.3 3.465 V
VSS Ground 0 0 0 V
VIH Inp ut Hig h Vo l tag e - Inp uts 2. 0
____
4.6 V
VIH Input High Voltage - I/O 2.0
____
VDD+0.3(2) V
VIL Inp ut Lo w Vo ltag e -0. 5(1)
____
0.8 V
3822 tbl 04
4
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Pin Configuration
Capacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
NOTES:
1. Pin 14 does not have to be connected directly to VSS as long as the input voltage is < VIL.
2. Pins 83 and 84 are reserved for future A17 (8M) and A18 (16M) respectively.
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
V
DD
V
SS
V
SS
V
DD
I/O
27
I/O
26
V
SS
V
DD
I/O
25
I/O
24
V
DD
V
SS
V
SS
V
DD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
DD
V
SS
I/O
23
I/O
22
V
SS
V
DD
I/O
21
I/O
20
V
SS
V
DD
I/O
11
I/O
10
V
DD
V
SS
I/O
9
I/O
8
I/O
7
I/O
6
V
SS
V
DD
I/O
5
I/O
4
PK100-1
3822 drw 02
V
SS
(1)
V
DD
A
15
A
16
I/O
12
I/O
28
V
SS
V
SS
BW
4
BW
3
I/O
P2
I/O
14
I/O
15
I/O
13
I/O
2
I/O
3
I/O
P1
I/O
0
I/O
1
I/O
P4
I/O
30
I/O
31
I/O
29
I/O
19
I/O
18
I/O
P3
I/O
16
I/O
17
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VDD and Input terminals only.
3. I/O terminals.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol Rating Value Unit
V
TERM(2)
Supply Voltage on VDD with
Re s p e c t to G ND –0.5 to + 3.6 V
V
TERM(3)
DC Inp ut Vo ltag e
(5)
–0.5 to V
DDQ
+0.5 V
V
TERM(4)
DC Vo ltag e Ap plie d to Outp uts in
Hig h-Z State
(5)
–0.5 to V
DDQ
+0.5 V
T
A
Operating Temperature 0°C to 70°C °C
T
BIAS
Ambient Temperature with Power
Applied (Temperature Under
Bias)
–55 to + 125 °C
T
STG
Sto rage Te mp e rature –65 to + 150 °C
I
OUT
Curre nt into Outp uts (Low) 20 mA
V
ESD
Static Disc harg e Vo ltag e
(p er MIL-STD-883, Me thod 3015) >2001 V
I
LU
Latch-Up Current >200 m A
5284 tbl 05
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 5 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
3822 tbl 0 6
Top View
TQFP
6.42
5
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Partial T ruth Table for Writes(1)
Synchronous Truth Table(1)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature
of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus
will tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if either one of thechip enable is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
CEN R/WChip
(5)
Enable ADV/LD BWxADDRESS
USED PREVIOUIS CYCLE CURRENT CYCLE I/O
(1 cycle later)
L L Select L Valid Ext ernal X LO AD WRI TE D
(7)
L H Select L X External X LOAD READ Q
(7)
L X X H Valid Internal LOAD WRI TE/
BURST WRITE BURST WRITE
(Adv ance Burst Count er)
(2)
D
(7)
L X X H X Internal LOAD READ/
BURST READ BURST READ
(Adv ance Burst Count er)
(2)
Q
(7)
L X Deselect L X X X DESELECT or STOP
(3)
HiZ
L X X H X X DESELECT / NOOP NOOP HiZ
HXX XXX X SUSPEND
(4)
Previous Value
3822 tbl 07
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
Operation R/WBW1BW2BW3BW4
READ HXXXX
WRITE ALL BYTES LLLLL
WRITE BY TE 1 (I/O [0:7], I/OP1)(2) LLHHH
WRITE BYTE 2 (I/O [8:15], I/OP2)(2) LHLHH
WRITE BYTE 3 (I/O [16:23], I/OP3)(2) LHHLH
WRITE BYTE 4 (I/O [24:31], I/OP4)(2) LHHHL
NO WRITE L H H H H
3 822 t bl 08
6
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Functional Timing Diagram(1)
NOTE:
1. This assumes CEN, CE1, CE2 and CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
n+29
A29
C29
D/Q28
ADDRESS
(A0 - A16)
CONTROL
(R/W,ADV/LD,BWx)
DATA
I/O [0:31], I/O P[1:4]
CYCLE
CLOCK
n+30
A30
C30
D/Q29
n+31
A31
C31
D/Q30
n+32
A32
C32
D/Q31
n+33
A33
C33
D/Q32
n+34
A34
C34
D/Q33
n+35
A35
C35
D/Q34
n+36
A36
C36
D/Q35
(2)
(2)
(2)
3822 drw 03
A37
C37
D/Q36
n+37
.,
Linear Burst Sequence Table (LBO=VSS)
Interleaved Burst Sequence Table (LBO=VDD)
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address000110 11
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11 10 01 00
3 822 t bl 09
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11 00 01 10
3822 tbl 10
6.42
7
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
NOTE:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles(2)
Cycle Address R/WADV/LD CE
(1)
CEN BWxOE I/O Comments
n A0 H L L L X X D1 Load read
n+1 X X H X L X L Q0 Burst read
n+2 A1 H L L L X L Q
0+1
Load read
n+3 X X L H L X L Q1 Deselect or STOP
n+4 X X H X L X X Z NOOP
n+5 A2 H L L L X X Z Load re ad
n+6 X X H X L X L Q2 Burst read
n+7 X X L H L X L Q
2+1
Deselect or STOP
n+8 A3 L L L L L X Z Load write
n+9 X X H X L L X D3 Burst write
n+10 A4 L L L L L X D
3+1
Load write
n+11 X X L H L X X D4 Deselect or STOP
n+12 X X H X L X X Z NOOP
n+13 A 5 L L L L L X Z Lo ad write
n+14 A6 H L L L X X D5 Load read
n+15 A 7 L L L L L L Q6 Lo ad write
n+16 X X H X L L X D7 Burs t write
n+17 A8 H L L L X X D
7+1
Load read
n+18 X X H X L X L Q8 B urst re ad
n+19 A9 L L L L L L Q
8+1
Load write
38 22 t bl 11
8
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Read Operation(1)
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Write Operation(1)
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Read Operation(1)
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation(1)
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
n A0 H L L L X X X Address and Control meet setup
n+1 X X X X X X L Q0 Contents of Address A0 Read Out
3822 tbl 12
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
n A0 H L L L X X X Addres s and Control m eet setup
n+1 X X H X L X L Q0 Address A0 Read Out , Inc. Count
n+2 X X H X L X L Q
0+1
Address A
0+1
Read Out, Inc. Count
n+3 X X H X L X L Q
0+2
Address A
0+2
Read Out, Inc. Count
n+4XXHXLXLQ
0+3
Address A
0+3
Read Out, Load A1
n+5 A1 H L L L X L Q0 Address A0 Read Out, Inc. Count
n+6 X X H X L X L Q1 Address A1 Read Out , Inc. Count
n+7A2HLLLXLQ
1+1
Address A
1+1
Read Out, Load A2
3822 tbl 13
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
n A0 L L L L L X X Address and Control meet setup
n+1 X X X X L X X D0 Write to Address A0
3822 tbl 14
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
n A0 L L L L L X X Address and Control meet setup
n+1 X X H X L L X D0 Address A0 Write, Inc. Count
n+2 X X H X L L X D
0+1
Address A
0+1
Write, Inc. Count
n+3 X X H X L L X D
0+2
Address A
0+2
Write, Inc. Count
n+4 X X H X L L X D
0+3
Address A
0+3
Write, Lo ad A1
n+5 A1 L L L L L X D0 Address A0 Write, Inc. Count
n+6 X X H X L L X D1 Address A1 Write, Inc. Count
n+7 A2 L L LLLXD
1+1
Address A
1+1
Write, Lo ad A2
3822 tbl 15
6.42
9
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Read Operation With Clock Enable Used(1)
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation With Clock Enable Used(1)
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
n A0 H L L L X X X Addres s and Control m eet setup
n+1 X X X X H X X X Clock n+1 Ignored
n+2 A1 H L L L X L Q0 Addre ss A0 Read out , Load A1
n+3 X X X X H X L Q0 Clock Ignore d. Data Q0 is on the bus
n+4 X X X X H X L Q 0 Clock Ignored. D ata Q0 is on the bus
n+5 A2 H L L L X L Q1 Addre ss A1 Read out, Load A2
n+6 A3 H L L L X L Q2 Addre ss A2 Read out, Load A3
n+7 A4 H L L L X L Q3 Addre ss A3 Read out, Load A4
3822 tbl 16
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
n A0 L L L L L X X Address and Control meet setup
n+1 X X X X H X X X Clo ck n+1 Igno red
n+2 A1 L L L L L X D0 Write d ata D0, Lo ad A1
n+3 X X X X H X X X Clo ck Ig no red
n+4 X X X X H X X X Clo ck Ig no red
n+5 A2 L L L L L X D1 Write d ata D1, Lo ad A2
n+6 A3 L L L L L X D2 Write d ata D2, Lo ad A3
n+7 A4 L L L L L X D3 Write d ata D3, Lo ad A4
3 822 t bl 17
10
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
Read Operation with Chip Enable Used(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Chip Enable Used(1)
Cycle Address R/WADV/LD CE
(1)
CEN BWxOE I/O
(3)
Comments
n X X L H L X X ? Deselected
n+1 X X L H L X X Z Deselected
n+2 A0 H L L L X X Z Address A0 and Control meet setup
n+3 X X L H L X L Q0 Address A0 read out. Deselected
n+4 A1 H L L L X X Z Address A1 and Control meet setup
n+5 X X L H L X L Q1 Address A1 Read out. Deselected
n+6 X X L H L X X Z Deselected
n+7 A2 H L L L X X Z Address A2 and Control meet setup
n+8 X X L H L X L Q2 Address A2 read out. Deselected
n+9 X X L H L X X Z Deselected
3822 tbl 18
Cycle Address R/WADV/LD CE
(1)
CEN BWxOE I/O Comments
n X X L H L X X ? Deselected
n+1 X X L H L X X Z Deselected
n+2 A0 L L L L L X Z Address A 0 and Cont rol m eet setup
n+3 X X L H L X X D0 Address D0 Write In. Deselected
n+4 A1 L L L L L X Z Address A 1 and Cont rol m eet set up
n+5 X X L H L X X D1 Address D1 Write In. Deselected
n+6 X X L H L X X Z Deselected
n+7 A2 L L L L L X Z Address A 2 and Cont rol m eet setup
n+8 X X L H L X X D2 Address D2 Write In. Deselected
n+9 X X L H L X X Z Deselected
3822 tbl 19
6.42
11
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Symbol Parameter Test Conditions
S80 S85 S90 S100
UnitCom'l Ind Com'l Ind Com'l Ind Com'l Ind
I
DD
Ope rating Po we r
Supply Current Device Selected, Outputs Open, ADV/LD = X,
V
DD
= Max., V
IN
> V
IH
or < V
IL
, f = f
MAX(2)
250 260 225 235 225 235 200 210 mA
I
SB1
CMOS Standby Power
Supply Current Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
, f = 0
(2)
40 45 40 45 40 45 40 45 mA
I
SB2
Clo ck Runni ng Po we r
Supply Current Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
, f = f
MAX(2)
100 110 95 105 95 105 90 100 mA
I
SB3
Id l e Po we r
Supply Current Device Selected, Outputs Open, CEN > V
IH
V
DD
= Max., V
IN
> V
HD
or < V
LD
, f = f
MAX(2)
40 45 40 45 40 45 40 45 mA
3822 t bl 21
DC Electrical Characteristics Over the Operating T emperature and
Supply Voltage Range (VDD = 3.3V +/-5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Loads AC Test Conditions
DC Electrical Characteristics Over the Operating Temperature
and Supply V oltage Range(1) (VDD = 3.3V +/-5%, VHD = VDD–0.2V, VLD = 0.2V)
1.5V
50Ω
I/O Z0=50Ω
3822 drw 04
+
,
1
2
3
4
20 30 50 100 200
ΔtCD
(Typical, ns)
Capacitance (pF)
80
5
6
3822 drw 05
.
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application.
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| Inp ut Le akag e Curre nt V
DD
= Max., V
IN
=
0V to V
DD
___
5µA
|I
LI
|LBO Input Le akag e Current
(1)
V
DD
= Max., V
IN
=
0V to V
DD
___
30 µA
|I
LO
|
Outp ut Le akag e Curre nt CE > V
IH
or OE > V
IH
, V
OUT
= 0V toV
DD
, V
DD
= Max.
___
5µA
V
OL
Outp ut Lo w Vo ltag e I
OL
= 5mA, V
DD
= Min.
___
0.4 V
V
OH
Outp ut Hig h Voltage I
OH
= -5mA, V
DD
= Min. 2. 4
___
V
3822 tbl 20
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
Inp ut Puls e Le v e ls
Inp ut Ri s e /Fal l Tim e s
Inp ut Tim ing Re fe re nc e Le v e l s
Outp ut Timi ng Re fe re nc e Le v e ls
AC Te st Lo ad
0 to 3V
2ns
1.5V
1.5V
See Figure 1
3822 tbl 22
12
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above 2.0V and LOW below 0.8V.
2. Transition is measured ±200mV from steady-state.
3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 2 ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V). .
Symbol Parameter
71V547S80 71V547S85 71V547S90 71V547S100
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Clock Parameters
t
CYC
Clock Cycle Time 10.5
____
11
____
12
____
15
____
ns
t
CH
(2)
Clock High Pulse Width 3
____
3.9
____
4
____
5
____
ns
t
CL
(2)
Clock Low Pulse Width 3
____
3.9
____
4
____
5
____
ns
Output Param eters
t
CD
Clo c k Hig h to Vali d Data
____
8
____
8.5
____
9
____
10 ns
t
CDC
Clo ck Hig h to Data Chang e 2
____
2
____
2
____
2
____
ns
t
CLZ
(3,4,5)
Clo c k Hig h to Outp ut A ctiv e 4
____
4
____
4
____
4
____
ns
t
CHZ
(3,4,5)
Clo ck Hi g h to Data Hi g h-Z
____
5
____
5
____
5
____
5ns
t
OE
Output Enable Access Time
____
5
____
5
____
5
____
5ns
t
OLZ
(3,4)
Outp ut E nab le Lo w to Data A ctiv e 0
____
0
____
0
____
0
____
ns
t
OHZ
(3.4)
Outp ut E nab l e Hig h to Data Hi gh-Z
____
5
____
5
____
5
____
5ns
Setup Times
t
SE
Clock Enable Setup Time 2.0
____
2.0
____
2.0
____
2.5
____
ns
t
SA
Address Setup Time 2.0
____
2.0
____
2.0
____
2.5
____
ns
t
SD
Data i n Se tup Time 2. 0
____
2.0
____
2.0
____
2.5
____
ns
t
SW
Re ad /Wri te (R/ W) Se tup Tim e 2.0
____
2.0
____
2.0
____
2.5
____
ns
t
SADV
Ad vance /Lo ad (ADV/ LD) Se tup Time 2.0
____
2.0
____
2.0
____
2.5
____
ns
t
SC
Chi p E nabl e /S e lec t S e tup Time 2. 0
____
2.0
____
2.0
____
2.5
____
ns
t
SB
Byte Write Enable (BWx) Setup Time 2.0
____
2.0
____
2.0
____
2.5
____
ns
Hol d T im es
t
HE
Clo ck Enab le Hold Ti me 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HA
Address Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HD
Data i n Ho ld Time 0. 5
____
0.5
____
0.5
____
0.5
____
ns
t
HW
Re ad /Wri te (R/ W) Ho ld Time 0. 5
____
0.5
____
0.5
____
0.5
____
ns
t
HADV
Ad vance /Lo ad (ADV/ LD) Ho ld Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HC
Chip Enable/Se lect Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HB
Byte Write Enable (BWx) Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
3822 tbl 23
6.42
13
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Wa v ef orm of R ead Cy c le(1, 2, 3, 4)
NOTES:
1 . Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the
burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address
and control are loaded into the SRAM.
(CENhigh,eliminates
currentL-Hclockedge)
Q(A2+1)
tCD
Read
tCLZtCHZ
tCD
tCDC
Q(A2+2)
Q(A1)Q(A2)Q(A2+3)Q(A2+3)Q(A2)
BurstRead
Read
DATAOut
(BurstWrapsaround
to initialstate)
tCDC
tHADV
3822drw06
R/W
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2
(
2)
BW
1
-BW
4
OE
tHE
tSE
A1A2
tCH
tCL
tCYC
tSADV
tHW
tSW
tHA
tSA
tHC
tSC
,
14
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Wa veform of Write Cyc les(1,2,3,4,5)
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base
address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in one cycle before the actual data is presented to the SRAM.
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2(2)
BW
1
-BW
4
OE
DATAIn D(A1)D(A2)
tHD
tSD(CENhigh,eliminates
currentL-Hclockedge)
D(A2+1)D(A2+2)D(A2+3)D(A2)
BurstWrite
Write Write
(BurstWrapsaround
to initialstate)
tHD
tSD
tCHtCL
tCYC
tHADV
tSADV
tHW
tSW
tHA
tSA
tHC
tSC
tHB
tSB
3822drw07
B(A1)B(A2)B(A2+1)B(A2+2)B(A2+3)B(A2)
.
6.42
15
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in one cycle before the actual data is presented to the SRAM.
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2
(2)
BW
1
-BW
4
OE
DATAOutQ(A3)
Q(A1)Q(A6)Q(A7)
tCD
ReadRead
ReadRead
tCHZ
3822drw08
Write
tCLZ
D(A2)D(A4)
tCDC
D(A5)
Write
tCHtCL
tCYC
tHW
tSW
tHA
tSA
A4
A3
tHC
tSC
tSDtHD
tHADV
tSADV
A6A7A8
A5A9
DATAIn
tHB
tSB
Write
D(A8)
Write
B(A2)B(A4)B(A5)B(A8)
,
16
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH..
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition
did not occur. All internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in one cycle before the actual data is presented to the SRAM.
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2(2)
BW
1
-BW
4
OE
DATAOutQ(A1)
tCDC
Q(A3)
tCD
tCLZ
Q(A1)Q(A4)
tCDtCDC
tCHZD(A2)
tSDtHD
tCHtCL
tCYC
tHC
tSC
A4A5
tHADV
tSADV
tHW
tSW
tHA
tSA
A3
tHB
tSB
DATAIn
3822drw09
B(A2)
,
6.42
17
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3 . When either one of the Chip enables (CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states one cycle after the initiation
of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in one cycle before the actual data is presented to the SRAM.
R/W
A1
CLK
ADV/LD
ADDRESS
CE
1
,CE
2(2)
OE
DATAOutQ(A1)Q(A2)Q(A4)
tCLZ
Q(A4)
tCD
tCHZ
tCDC
D(A3)
tSDtHD
tCHtCL
tCYC
tHC
tSC
A5
A3
tSB
DATAIn
tHE
tSE
A2
tHA
tSA
A4
tHW
tSW
tHB
CEN
tHADV
tSADV
3822drw10
BW
1
-BW
4B(A3)
.
18
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
OE
DATA Out
tOHZ tOLZ
tOE
QQ
.
3822 drw 11
PlasticThinQuadFlatpack,100pin(PK100-1)
S
Power
XX
Speed
PF
Package
PF
71V5477
80
85
90
100
Access time (t
CD
) in tenths of nanoseconds
3822 drw 12
Device
Type
PART NUMBER t
CD
PARAMETER
71V547S80PF
71V547S85PF
71V547S90PF
71V547S100PF
95 MHz
90 MHz
83 MHz
66 MHz
8ns
8.5 ns
9ns
10 ns
10.5 ns
11 ns
12ns
15 ns
SPEED IN MEGAHERTZ CLOCK CYCLE TIME
X
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
X
XCurrent generation die step optional
Blank First generation or current die step
6.42
19
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
6/15/99 Updated to new format
9/13/99 Pg. 11 Corrected ISB3 conditions
Pg. 19 Added Datasheet Document History
12/31/99 Pp. 3, 11, 12, 18 Added Industrial Temperature range offerings
02/27/07 Pg.18 Added X generation die step to data sheet ordering information
10/16/08 Pg.18 Removed "IDT" from orderable part number
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Rd 800-345-7015 or 408-284-8200 sramhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775 800-345-7015 or
www.idt.com 408/284-4555
