IRF2907ZPbF
IRF2907ZSPbF
IRF2907ZLPbF
07/22/10
www.irf.com 1
HEXFET® is a registered trademark of International Rectifier.
Description
This HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating. These features combine
to make this design an extremely efficient and
reliable device for use in a wide variety of
applications.
Features
lAdvanced Process Technology
lUltra Low On-Resistance
l175°C Operating Temperature
lFast Switching
lRepetitive Avalanche Allowed up to Tjmax
lLead-Free
D2Pak
IRF2907ZSPbF
TO-220AB
IRF2907ZPbF
TO-262
IRF2907ZLPbF
HEXFET® Power MOSFET
VDSS = 75V
RDS(on) = 4.5mΩ
ID = 160A
S
D
G
∗
Absolute Maximum Ratings
Parameter Units
I
D
@ T
C
= 25°C Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
I
D
@ T
C
= 100°C Continuous Drain Current, V
GS
@ 10V (See Fig. 9)
I
D
@ T
C
= 25°C Continuous Drain Current, V
GS
@ 10V
(Wirebond Limited)
I
DM
Pulsed Drain Current
c
P
D
@T
C
= 25°C Maximum Power Dissipation W
Linear Derating Factor W/°C
V
GS
Gate-to-Source Voltage V
E
AS
Single Pulse Avalanche Energy (Thermally Limited)
d
mJ
E
AS
(tested) Single Pulse Avalanche Energy Tested Value
i
I
AR
Avalanche Current
c
A
E
AR
Repetitive Avalanche Energy
h
mJ
T
J
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
Junction-to-Case
k
––– 0.50
l
R
θCS
Case-to-Sink, Flat, Greased Surface 0.50 –––
R
θJA
Junction-to-Ambient ––– 62
R
θJA
Junction-to-Ambient (PCB Mount, steady state)
j
––– 40
A
°C
°C/W
10 lbf•in (1.1N•m)
300
2.0
± 20
Max.
170
120
680
160 *
270
690
See Fig.12a,12b,15,16
300 (1.6mm from case )
-55 to + 175
PD - 95489D
IRF2907Z/S/LPbF
2www.irf.com
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L=0.095mH,
RG = 25Ω, IAS = 75A, VGS =10V.
Part not recommended for use above this value.
ISD ≤ 75A, di/dt ≤ 340A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from
0 to 80% VDSS.
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical
repetitive avalanche performance.
This value determined from sample failure population.
100% tested to this value in production.
This is applied to D2Pak, when mounted on 1" square PCB
( FR-4 or G-10 Material ). For recommended footprint and
soldering techniques refer to application note #AN-994.
Rθ is measured at TJ of approximately 90°C.
TO-220 device will have an Rth of 0.45°C/W.
∗ Calculated continuous current based on maximum
allowable junction temperature. Bond wire current limit is
160A.Note that current limitations arising from heating of
the device leads may occur with some lead mounting
arrangements. (Refer to AN-1140 http://www.irf.com/
technical-info/appnotes/an-1140.pdf)
S
D
G
S
D
G
Static @ T
J
= 25°C (unless otherwise specified)
Parameter Min. T
y
p. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Volta
g
e75––––––V
∆ΒV
DSS
/
∆T
J
Breakdown Volta
g
e Temp. Coefficient ––– 0.069 ––– V/°C
R
DS(on)
Static Drain-to-Source On-Resistance ––– 3.5 4.5 mΩ
V
GS(th)
Gate Threshold Volta
g
e 2.0 ––– 4.0 V
g
fs Forward Transconductance 180 ––– ––– S
I
DSS
Drain-to-Source Leaka
g
e Current ––– ––– 20
µ
A
––– ––– 250
I
GSS
Gate-to-Source Forward Leaka
e ––– ––– 200 nA
Gate-to-Source Reverse Leaka
g
e ––– ––– -200
Q
g
Total Gate Char
g
e ––– 180 270
Q
gs
Gate-to-Source Char
g
e ––– 46 ––– nC
Q
gd
Gate-to-Drain ("Miller") Char
g
e ––– 65 –––
t
d(on)
Turn-On Dela
y
Time –––19–––ns
t
r
Rise Time ––– 140 –––
t
d(off)
Turn-Off Dela
y
Time –––97–––
t
f
Fall Time ––– 100 –––
L
D
Internal Drain Inductance ––– 5.0 ––– nH Between lead,
6mm (0.25in.)
L
S
Internal Source Inductance ––– 13 ––– from packa
g
e
and center of die contact
C
iss
Input Capacitance ––– 7500 ––– pF
C
oss
Output Capacitance ––– 970 –––
C
rss
Reverse Transfer Capacitance ––– 510 –––
C
oss
Output Capacitance ––– 3640 –––
C
oss
Output Capacitance ––– 650 –––
C
oss
eff. Effective Output Capacitance ––– 1020 –––
Diode Characteristics
Parameter Min. T
y
p. Max. Units
I
S
Continuous Source Current
(Body Diode) A
I
SM
Pulsed Source Current
(Body Diode)
c
V
SD
Diode Forward Voltage ––– ––– 1.3 V
t
rr
Reverse Recovery Time ––– 41 61 ns
Q
rr
Reverse Recover
y
Char
g
e ––– 59 89 nC
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
–––
–––
–––
–––
160*
680
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 75V, V
GS
= 0V
V
DS
= 75V, V
GS
= 0V, T
J
= 125°C
Conditions
V
GS
= 0V, I
D
= 250µA
Reference to 25°C, I
D
= 1mA
V
GS
= 10V, I
D
= 75A
f
T
J
= 25°C, I
F
= 75A, V
DD
= 38V
di/dt = 100A/
µ
s
f
T
J
= 25°C, I
S
= 75A, V
GS
= 0V
f
showing the
integral reverse
p-n junction diode.
V
GS
= 0V, V
DS
= 1.0V, ƒ = 1.0MHz
V
GS
= 10V
f
MOSFET symbol
V
GS
= 0V
V
DS
= 25V
V
GS
= 0V, V
DS
= 60V, ƒ = 1.0MHz
Conditions
V
GS
= 0V, V
DS
= 0V to 60V
ƒ = 1.0MHz, See Fig. 5
R
G
= 2.5Ω
I
D
= 75A
V
DS
= 25V, I
D
= 75A
V
DD
= 38V
I
D
= 75A
V
GS
= 20V
V
GS
= -20V
V
DS
= 60V
V
GS
= 10V
f
IRF2907Z/S/LPbF
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Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance
vs. Drain Current
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
≤60µs PULSE WIDTH
Tj = 25°C
4.5V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
4.5V
≤60µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
2 4 6 8 10
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (Α)
TJ = 25°C
TJ = 175°C
VDS = 25V
≤60µs PULSE WIDTH
0 25 50 75 100 125 150
ID,Drain-to-Source Current (A)
0
50
100
150
200
Gfs, Forward Transconductance (S)
TJ = 25°C
TJ = 175°C
VDS = 10V
380µs PULSE WIDTH
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C, Capacitance(pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0 50 100 150 200
QG Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
VGS, Gate-to-Source Voltage (V)
VDS= 60V
VDS= 38V
VDS= 15V
ID= 90A
0.0 0.5 1.0 1.5 2.0 2.5
VSD, Source-to-Drain Voltage (V)
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
1 10 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY RDS(on)
Tc = 25°C
Tj = 175°C
Single Pulse
100µsec
1msec
10msec
DC
Limited by package
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Normalized On-Resistance
vs. Temperature
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 90A
VGS = 10V
1E-006 1E-005 0.0001 0.001 0.01 0.1 1
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) τi (sec)
0.279 0.000457
0.221 0.003019
τJ
τJ
τ1
τ1
τ2
τ2
R1
R1R2
R2
τ
τC
Ci i/Ri
Ci= τi/Ri
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
20
40
60
80
100
120
140
160
180
ID, Drain Current (A)
Limited By Package
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6www.irf.com
QG
QGS QGD
VG
Charge
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage vs. Temperature
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
1K
VCC
DUT
0
L
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VGS(th) Gate threshold Voltage (V)
ID = 250µA
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
200
400
600
800
1000
1200
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 9.0A
13A
BOTTOM 75A
IRF2907Z/S/LPbF
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Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses
0.01
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
50
100
150
200
250
300
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 75A
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8www.irf.com
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P. W .
Period
* V
GS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
VDS
90%
10%
VGS
t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
IRF2907Z/S/LPbF
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TO-220AB Part Marking Information
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
INT ERNAT IONAL PART NUMBER
RECTIFIER
LOT CODE
ASSEMBLY
LOGO
YEAR 0 = 2000
DAT E CODE
WEEK 19
LINE C
LOT CODE 1789
EXAMPLE: THIS IS AN IRF1010
Note: "P" in assembly line pos ition
indicates "L ead - F ree"
IN THE ASSEMBLY LINE "C"
AS S EMBLED ON WW 19, 2000
TO-220AB packages are not recommended for Surface Mount Application.
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF2907Z/S/LPbF
10 www.irf.com
D2Pak (TO-263AB) Part Marking Information
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
DATE CODE
YEAR 0 = 2000
WEEK 02
A = ASSEMBLY SITE CODE
RECT IFIER
INTERNATIONAL PART NUMBER
P = DE S I GN AT E S L E AD - F R E E
PRODUCT (OPTIONAL)
F530S
IN THE ASSEMBLY LINE "L"
AS S EMB L E D ON WW 02, 2000
THIS IS AN IRF530S WITH
LOT CODE 8024 INT ERNAT IONAL
LOGO
RECTIFIER
LOT CODE
AS S E MB L Y YEAR 0 = 2000
PART NUMBER
DAT E CODE
LINE L
WEEK 02
OR
F530S
LOGO
ASSEMBLY
LOT CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF2907Z/S/LPbF
www.irf.com 11
TO-262 Part Marking Information
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
LOGO
RECTIFIE R
INTERNATIONAL
LOT CODE
AS S E MB L Y
LOGO
RECTIFIE R
INTERNAT IONAL
DATE CODE
WE E K 19
YEAR 7 = 1997
PART NUMBER
A = AS S E MB L Y S I T E CODE
OR
PRODUCT (OPT IONAL)
P = DE S IGN AT E S L E AD-F R E E
EXAMPLE: THIS IS AN IR L3103L
LOT CODE 1789
AS S E MB L Y
PART NUMB ER
DAT E CODE
WE E K 19
LINE C
LOT CODE
YEAR 7 = 1997
ASS EMBLED ON WW 19, 1997
IN T HE AS S E MB L Y L INE "C"
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF2907Z/S/LPbF
12 www.irf.com
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/2010
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421)
16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.