February 2006
Copyright © Alliance Semiconductor. All rights reserved.
AS7C4096A
5.0V 512K × 8 CMOS SRAM
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Features
• Pin compatible to AS7C4096
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6 ns output enable access time
• Low power consumption: ACTIVE
- 880mW/max @ 10 ns
• Low power consumption: STANDBY
- 55mW/max CMOS
• Equal access and cycle times
• Easy memory expansion with
CE
,
OE
inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
524,288 × 8
Array
(4,194,304)
Sense amp
Input buffer
I/O8
I/O1
OE
CE
WE
Column decoder
Row decoder
Control
Circuit
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
A10
A11
A12
A13
A14
A15
A16
A17
A18
A9
Pin arrangements
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A15
OE
I/O8
I/O7
GND
V
CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A0
A1
A2
A3
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7 17
18
A8
A9
36
35
34
33
NC
A18
A17
A16
GND
V
CC
I/O6
I/O5
NC
A14
A13
A12
A11
A10
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
I/O8
I/O7
A1
A2
A3
A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A16
A15
A17
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
3
4
1
NC
NC
NC
NC
NC
NC NC
NC
NC
OE
A18
36-pin SOJ (400 mil) 44-pin TSOP 2
Selection guide
–10 –12 –15 –20 Unit
Maximum address access time 10 12 15 20 ns
Maximum outputenable access time 5 6 6 6 ns
Maximum operating current 160 140 120 100 mA
Maximum CMOS standby current 10 10 10 10 mA
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Functional description
The AS7C4096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
524,288 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6 ns are ideal
for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory
systems.
When CE is high the device enters standby mode. The device is guaranteed not to exceed 55mW power consumption in CMOS
standby mode.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is written
on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins
only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5.0V supply voltage. This device is available as
per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND Vt1 –0.5 +7.0 V
Voltage on any pin relative to GND Vt2 –0.5 VCC +0.5 V
Power dissipation PD–1.0W
Storage temperature (plastic) Tstg –65 +150 °C
Temperature with VCC applied Tbias –55 +125 °C
DC current into output (low) IOUT –20mA
Truth table
CE WE OE Data Mode
H X X High Z Standby (ISB, ISB1)
L H H High Z Output disable (ICC)
LHL DOUT Read (ICC)
LLX DIN Write (ICC)
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*VIH max = VCC + 1.5V for pulse width less than 5 nS.
**VIL min = –1.0V for pulse width less than 5 nS.
.
Recommended operating condition
Parameter Symbol Min Nominal Max Unit
Supply voltage VCC(10/12/15/20) 4.5 5.0 5.5 V
Input voltage VIH*2.2 – VCC + 0.5 V
VIL** –0.5 – 0.8 V
Ambient operating
temperature
commercial TA0– 70°C
industrial TA–40 – 85 °C
DC operating characteristics (over the operating range)1
Parameter Symbol Test conditions
–10 –12 –15 –20
Unit NotesMin Max Min Max Min Max Min Max
Input leakage
current |ILI|VCC = Max, VIN = GND to VCC
–1–1–1–1µA
Output leakage
current |ILO|VCC = Max, CE = VIH
VOUT= GND to VCC
–1–1–1–1µA
Operating power
supply current ICC VCC = Max, CE < VIL
f = fMax, IOUT = 0mA –160–140–120–100mA
Standby power
supply current
ISB VCC = Max, CE > VIH
f = fMax, IOUT = 0mA –60–55–50–40mA
ISB1
VCC = Max,
CE ≥ VCC – 0.2V,
VIN ≤ 0.2V or VIN ≥ VCC – 0.2V,
f = 0
–10–10–10–10mA
Output voltage VOL
IOL = 6 mA, VCC = Min –0.4–0.4–0.4–0.4 V4
IOL = 8 mA, VCC = Min –0.5–0.5–0.5–0.5
VOH IOH = –4 mA, VCC = Min 2.4–2.4–2.4–2.4– V 4
Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)4
Parameter Symbol Signals Test con ditions Max Unit
Input capacitance CIN A, CE, WE, OE VIN = 0V 5 pF
I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF
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Key to switching waveforms
Read waveform 1 (address controlled)2,5,6,8
Read waveform 2 (CE, OE controlled)2,5,7,8
Read cycle (over the operating range)2,8
Parameter Symbol
–10 –12 –15 –20
Unit NotesMin Max Min Max Min Max Min Max
Read cycle time tRC 10–12–15–20–ns
Address access time tAA –10–12–15–20ns2
Chip enable (CE) access time tACE –10–12–15–20ns2
Output enable (OE) access time tOE –5–6–6–6ns
Output hold from address change tOH 3–3–3–3–ns4
CE Low to output in low Z tCLZ 3–3–3–3–ns3,4
CE High to output in high Z tCHZ –5–6–7–9ns3,4
OE Low to output in low Z tOLZ 0–0–0–0–ns3,4
OE High to output in high Z tOHZ –5–6–7–9ns3,4
Power up time tPU 0–0–0–0–ns3,4
Power down time tPD –10–12–15–20ns3,4
Undefined/don’t careFalling inputRising input
Address
D
OUT
Data valid
t
OH
t
AA
t
RC
current
Supply
OE
D
OUT
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50% 50%
t
OHZ
Data valid
t
RC1
CE
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Write waveform 1 (WE controlled)9
Write cycle (over the operating range)9
Parameter Symbol
–10 –12 –15 –20
Unit NotesMin Max Min Max Min Max Min Max
Write cycle time tWC 10–12–15–20–ns
Chip enable (CE) to write end tCW 7–8–10–12–ns
Address setup to write end tAW 7–8–10–12–ns
Address setup time tAS 0–0–0–0–ns
Write pulse width (OE = high) tWP1 7–8–10–12–ns
Write pulse width (OE = low tWP2 10–12–15–20–ns
Address hold from end of write tAH 0–0–0–0–ns
Write recovery time tWR 0–0–0–0–ns
Data valid to write end tDW 5–6–7–9–ns
Data hold time tDH 0–0–0–0–ns3,4
Write enable to output in high Z tWZ 25262729ns3,4
Output active from write end tOW 3–3–3–3–ns3,4
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
WR
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Write waveform 2 (CE controlled)9
AC test conditions
Notes
1During V
CC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 For test conditions, see AC Test Conditions.
3t
CLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500 mV from steady-state voltage.
4 This parameter is guaranteed, but not tested.
5WE
is HIGH for read cycle.
6CE
and OE are LOW for read cycle.
7 Address valid prior to or coincident with CE transition Low.
8 All read cycle timings are referenced from the last valid address to the first transitioning address.
9 All write cycle timings are referenced from the last valid address to the first transitioning address.
10 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
t
AW
Address
CE
WE
t
CW
t
DW
t
DH
t
AH
t
WC
t
AS
Data valid
D
IN
t
WR
t
WP
255
Ω
C
10
480
Ω
D
OUT
GND
+5.0V
Figure B: 5.0V Output load
- Output load: see Figure B.
- Input pulse level: GND to VCC - 0.5V. See Figures A and B.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
168
Ω
Thevenin equivalent:
D
OUT
+1.728V
10%
90%
10%
90%
GND
VCC - 0.5V
Figure A: Input pulse
2 ns
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Package dimensions
44-pin TSOP 2
Min(mm) Max(mm)
A1.2
A10.05 0.15
A20.95 1.05
b0.30 0.45
c0.12 0.21
d18.31 18.52
E110.06 10.26
E11.68 11.94
e0.80 (typical)
L0.40 0.60
36-pin SOJ 400
Min(mils) Max(mils)
A0.128 0.148
A10.025 –
A20.105 0.115
b0.015 0.020
b10.026 0.032
c0.007 0.013
D.920 .930
e0.045 0.055
E0.370 BSC
E10.395 0.405
E20.435 0.445
d
E
12
3 4 5 6 7 8 9 10 111213 14
44434241403938 37 36 35 34333231
15 16
30 29
17 1819 20
28 272625
c
L
A
1
A
2
e
44-pin TSOP 2
0–5°
21
24 23
E
1
A
b
Seating
Plane
22
D
Pin 1
e
E
1
E
2
A2
c
A1
b
b
1
A
E
36-pin SOJ
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Note: Add suffix ‘N’ to the above part number for Lead Free Parts. (Ex: AS7C4096A - 10 TIN)
Ordering codes
Package Ver sion 10 ns 12 ns 15 ns 20 ns
SOJ Commercial AS7C4096A-10JC AS7C4096A-12JC AS7C4096A-15JC AS7C4096A-20JC
Industrial AS7C4096A-10JI AS7C4096A-12JI AS7C4096A-15JI AS7C4096A-20JI
TSOP 2 Commercial AS7C4096A-10TC AS7C4096A-12TC AS7C4096A-15TC AS7C4096A-20TC
Industrial AS7C4096A-10TI AS7C4096A-12TI AS7C4096A-15TI AS7C4096A-20TI
Part numbering system
AS7C 4096A –XX J or T X X
SRAM
prefix
Device
number Access time
Packages:
J: SOJ 400 mil
T: TSOP 2
Temperature ranges:
C: Commercial, 0°C to 70°C
I: Industrial, –40°C to 85°C
N=Lead Free Parts
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Revision History
Rev. No. History Revised Date
v1.0 Initial release 11/08/04
v1.1 Included ICC, ISB & ISB1 parameters 05/27/05
Corrected the following: TOE, VIH, VOL & tWZ
v1.2 Removed the title ”PRELIMINARY INFORMATION” 02/21/06
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C4096A
Document Version: v 1.2
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AS7C4096A
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