M25P10-AVMN6TP - Micron Technology, Inc.

M25P10A 1Mb 3V Serial Flash Embedded

Memory

Features

• SPI bus-compatible serial interface

• 1Mb Flash memory

• 50 MHz clock frequency (maximum)

• 2.3V to 3.6V single supply voltage

• Page program (up to 256 bytes) in 1.4ms (TYP)

• Erase capability

– Sector erase: 256Kb in 0.65s (TYP)

– Bulk erase: 1Mb in 1.7s (TYP)

• Deep power-down: 1µA (TYP)

• Electronic signature

– JEDEC-standard 2-byte signature (2011h)

– RES command, 1-byte signature (10h) for back-

ward compatibility

• More than 20 years data retention

• Automotive-certified parts available

• Packages (RoHS-compliant)

– SO8N (MN) 150 mils

– VFQFPN8 (MP) MLP8 6mm x 5mm

– UFDFN8 (MB) 2mm x 3mm

M25P10A Serial Flash Embedded Memory

Features

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Products and specifications discussed herein are subject to change by Micron without notice.

Contents

Functional Description ..................................................................................................................................... 5

Signal Descriptions ........................................................................................................................................... 7

SPI Modes ........................................................................................................................................................ 8

Operating Features ......................................................................................................................................... 10

Page Programming ..................................................................................................................................... 10

Sector Erase, Bulk Erase .............................................................................................................................. 10

Polling during a Write, Program, or Erase Cycle ............................................................................................ 10

Active Power, Standby Power, and Deep Power-Down .................................................................................. 10

Status Register ............................................................................................................................................ 11

Data Protection by Protocol ........................................................................................................................ 11

Software Data Protection ............................................................................................................................ 11

Hardware Data Protection .......................................................................................................................... 11

Hold Condition .......................................................................................................................................... 11

Configuration and Memory Map ..................................................................................................................... 13

Memory Configuration and Block Diagram .................................................................................................. 13

Memory Map – 1Mb Density ........................................................................................................................... 14

Command Set Overview ................................................................................................................................. 15

WRITE ENABLE .............................................................................................................................................. 17

WRITE DISABLE ............................................................................................................................................. 18

READ IDENTIFICATION ................................................................................................................................. 19

READ STATUS REGISTER ................................................................................................................................ 20

WIP Bit ...................................................................................................................................................... 21

WEL Bit ...................................................................................................................................................... 21

Block Protect Bits ....................................................................................................................................... 21

SRWD Bit ................................................................................................................................................... 21

WRITE STATUS REGISTER .............................................................................................................................. 22

READ DATA BYTES ......................................................................................................................................... 24

READ DATA BYTES at HIGHER SPEED ............................................................................................................ 25

PAGE PROGRAM ............................................................................................................................................ 26

SECTOR ERASE .............................................................................................................................................. 27

BULK ERASE .................................................................................................................................................. 28

DEEP POWER-DOWN ..................................................................................................................................... 29

RELEASE from DEEP POWER-DOWN .............................................................................................................. 30

READ ELECTRONIC SIGNATURE .................................................................................................................... 31

Power-Up/Down and Supply Line Decoupling ................................................................................................. 32

Power-Up Timing and Write Inhibit Voltage Threshold Specifications ............................................................... 34

Maximum Ratings and Operating Conditions .................................................................................................. 35

Electrical Characteristics ................................................................................................................................ 36

AC Characteristics .......................................................................................................................................... 37

Package Information ...................................................................................................................................... 43

Device Ordering Information .......................................................................................................................... 46

Standard Parts ............................................................................................................................................ 46

Automotive Parts ........................................................................................................................................ 47

Revision History ............................................................................................................................................. 48

Rev. A – 05/2013 .......................................................................................................................................... 48

M25P10A Serial Flash Embedded Memory

Features

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List of Figures

Figure 1: Logic Diagram ................................................................................................................................... 5

Figure 2: Pin Connections: SO8, VFQFPN, and UFDFPN8 ................................................................................. 6

Figure 3: SPI Modes Supported ........................................................................................................................ 8

Figure 4: Bus Master and Memory Devices on the SPI Bus ................................................................................. 9

Figure 5: Hold Condition Activation ............................................................................................................... 12

Figure 6: Block Diagram ................................................................................................................................ 13

Figure 7: WRITE ENABLE Command Sequence .............................................................................................. 17

Figure 8: WRITE DISABLE Command Sequence ............................................................................................. 18

Figure 9: READ IDENTIFICATION Command Sequence ................................................................................. 19

Figure 10: READ STATUS REGISTER Command Sequence .............................................................................. 20

Figure 11: Status Register Format ................................................................................................................... 20

Figure 12: WRITE STATUS REGISTER Command Sequence ............................................................................. 22

Figure 13: READ DATA BYTES Command Sequence ........................................................................................ 24

Figure 14: READ DATA BYTES at HIGHER SPEED Command Sequence ........................................................... 25

Figure 15: PAGE PROGRAM Command Sequence ........................................................................................... 26

Figure 16: SECTOR ERASE Command Sequence ............................................................................................. 27

Figure 17: BULK ERASE Command Sequence ................................................................................................. 28

Figure 18: DEEP POWER-DOWN Command Sequence ................................................................................... 29

Figure 19: RELEASE from DEEP POWER-DOWN Command Sequence ............................................................. 30

Figure 20: READ ELECTRONIC SIGNATURE Command Sequence .................................................................. 31

Figure 21: Power-Up Timing .......................................................................................................................... 33

Figure 22: AC Measurement I/O Waveform ..................................................................................................... 37

Figure 23: Serial Input Timing ........................................................................................................................ 41

Figure 24: Write Protect Setup and Hold during WRSR when SRWD=1 Timing ................................................. 41

Figure 25: Hold Timing .................................................................................................................................. 42

Figure 26: Output Timing .............................................................................................................................. 42

Figure 27: SO8W 208 mils Body Width ............................................................................................................ 43

Figure 28: VFQFPN8 (MLP8) 6mm x 5mm ...................................................................................................... 44

Figure 29: UFDFPN8 (MLP8) 2mm x 3mm ...................................................................................................... 45

M25P10A Serial Flash Embedded Memory

Features

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List of Tables

Table 1: Signal Names ...................................................................................................................................... 5

Table 2: Signal Descriptions ............................................................................................................................. 7

Table 3: Protected Area Sizes .......................................................................................................................... 11

Table 4: Sectors 3:0 ........................................................................................................................................ 14

Table 5: Command Set Codes ........................................................................................................................ 16

Table 6: READ IDENTIFICATION Data Out Sequence ..................................................................................... 19

Table 7: Status Register Protection Modes ...................................................................................................... 23

Table 8: Power-Up Timing and VWI Threshold ................................................................................................. 34

Table 9: Absolute Maximum Ratings .............................................................................................................. 35

Table 10: Operating Conditions ...................................................................................................................... 35

Table 11: Data Retention and Endurance ........................................................................................................ 35

Table 12: DC Current Specifications ............................................................................................................... 36

Table 13: DC Voltage Specifications ................................................................................................................ 36

Table 14: AC Measurement Conditions ........................................................................................................... 37

Table 15: Capacitance .................................................................................................................................... 37

Table 16: AC Specifications 40 MHz ................................................................................................................ 38

Table 17: AC Specifications 50 MHz ................................................................................................................ 39

Table 18: Instruction Times ........................................................................................................................... 40

Table 19: Part Number Information Scheme ................................................................................................... 46

Table 20: Part Number Information Scheme ................................................................................................... 47

M25P10A Serial Flash Embedded Memory

Features

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Functional Description

The M25P10A is a 1Mb (125Kb x 8) serial Flash memory device with advanced write pro-

tection mechanisms accessed by a high-speed SPI-compatible bus.

The memory can be programmed 1 to 256 bytes at a time using the PAGE PROGRAM

command. It is organized as 4 sectors, each containing 128 pages. Each page is 256

bytes wide. Memory can be viewed either as 512 pages or as 131,072 bytes. The entire

memory can be erased using the BULK ERASE command, or it can be erased one sector

at a time using the SECTOR ERASE command.

Figure 1: Logic Diagram

VCC

HOLD#

VSS

DQ1

DQ0

Table 1: Signal Names

Signal Name Function Direction

C Serial clock Input

DQ0 Serial data input Input

DQ1 Serial data output Output

S# Chip select Input

W# Write protect Input

HOLD# Hold Input

VCC Supply voltage –

VSS Ground –

M25P10A Serial Flash Embedded Memory

Functional Description

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Figure 2: Pin Connections: SO8, VFQFPN, and UFDFPN8

VCC

HOLD#

VSS

DQ1

DQ0

W# C

Note: 1. There is an exposed central pad on the underside of the MLP8 package that is pulled in-

ternally to VSS, and must not be connected to any other voltage or signal line on the

PCB. The Package Mechanical section provides information on package dimensions and

how to identify pin 1.

M25P10A Serial Flash Embedded Memory

Functional Description

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Signal Descriptions

Table 2: Signal Descriptions

Signal Type Description

DQ1 Output Serial data: The DQ1 output signal is used to transfer data serially out of the device.

Data is shifted out on the falling edge of the serial clock (C).

DQ0 Input Serial data: The DQ0 input signal is used to transfer data serially into the device. It

receives commands, addresses, and the data to be programmed. Values are latched on

the rising edge of the serial clock (C).

C Input Clock: The C input signal provides the timing of the serial interface. Commands, ad-

dresses, or data present at serial data input (DQ0) is latched on the rising edge of the

serial clock (C). Data on DQ1 changes after the falling edge of C.

S# Input Chip select: When the S# input signal is HIGH, the device is deselected and DQ1 is at

HIGH impedance. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cy-

cle is in progress, the device will be in the standby power mode (not the DEEP POWER-

DOWN mode). Driving S# LOW enables the device, placing it in the active power

mode. After power-up, a falling edge on S# is required prior to the start of any com-

mand.

HOLD# Input Hold: The HOLD# signal is used to pause any serial communications with the device

without deselecting the device. During the hold condition, DQ1 is High-Z. DQ0 and C

are "Don’t Care." To start the hold condition, the device must be selected, with S#

driven LOW.

W# Input Write protect: The W# input signal is used to freeze the size of the area of memory

that is protected against program or erase commands as specified by the values in

BP1, and BP0 bits of the Status Register.

VCC Power Device core power supply: Source voltage.

VSS Ground Ground: Reference for the VCC supply voltage.

M25P10A Serial Flash Embedded Memory

Signal Descriptions

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SPI Modes

These devices can be driven by a microcontroller with its serial peripheral interface

(SPI) running in either of the following two SPI modes:

• CPOL=0, CPHA=0

• CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of serial clock (C), and

output data is available from the falling edge of C.

The difference between the two modes is the clock polarity when the bus master is in

STANDBY mode and not transferring data:

• C remains at 0 for (CPOL=0, CPHA=0)

• C remains at 1 for (CPOL=1, CPHA=1)

Figure 3: SPI Modes Supported

MSB

CPHA

DQ0

CPOL

DQ1

MSB

Because only one device is selected at a time, only one device drives the serial data out-

put (DQ1) line at a time, while the other devices are HIGH-Z. An example of three devi-

ces connected to an MCU on an SPI bus is shown here.

M25P10A Serial Flash Embedded Memory

SPI Modes

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Figure 4: Bus Master and Memory Devices on the SPI Bus

SPI Bus Master

SPI memory

device

SDO

SDI

SCK

DQ1 DQ0

SPI memory

device

DQ1 DQ0

SPI memory

device

DQ1 DQ0

CS3 CS2 CS1

SPI interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

W# HOLD# HOLD# W# HOLD#

R R R

VCC

VCC VCC VCC

VSS

VSS VSS VSS

Notes: 1. WRITE PROTECT (W#) and HOLD# should be driven HIGH or LOW as appropriate.

2. Resistors (R) ensure that the memory device is not selected if the bus master leaves the

S# line HIGH-Z.

3. The bus master may enter a state where all I/O are HIGH-Z at the same time; for exam-

ple, when the bus master is reset. Therefore, C must be connected to an external pull-

down resistor so that when all I/O are HIGH-Z, S# is pulled HIGH while C is pulled LOW.

This ensures that S# and C do not go HIGH at the same time and that the tSHCH require-

ment is met.

4. The typical value of R is 100 kΩ, assuming that the time constant R × Cp (Cp = parasitic

capacitance of the bus line) is shorter than the time during which the bus master leaves

the SPI bus HIGH-Z.

5. Example: Given that Cp = 50 pF (R × Cp = 5μs), the application must ensure that the bus

master never leaves the SPI bus HIGH-Z for a time period shorter than 5μs.

M25P10A Serial Flash Embedded Memory

SPI Modes

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Operating Features

Page Programming

To program one data byte, two commands are required: WRITE ENABLE, which is one

byte, and a PAGE PROGRAM sequence, which is four bytes plus data. This is followed by

the internal PROGRAM cycle of duration tPP. To spread this overhead, the PAGE PRO-

GRAM command allows up to 256 bytes to be programmed at a time (changing bits

from 1 to 0), provided they lie in consecutive addresses on the same page of memory. To

optimize timings, it is recommended to use the PAGE PROGRAM command to program

all consecutive targeted bytes in a single sequence than to use several PAGE PROGRAM

sequences with each containing only a few bytes.

Sector Erase, Bulk Erase

The PAGE PROGRAM command allows bits to be reset from 1 to 0. Before this can be

applied, the bytes of memory need to have been erased to all 1s (FFh). This can be ach-

ieved a sector at a time using the SECTOR ERASE command, or throughout the entire

memory using the BULK ERASE command. This starts an internal ERASE cycle of dura-

tion tSE or tBE. The ERASE command must be preceded by a WRITE ENABLE command.

Polling during a Write, Program, or Erase Cycle

An improvement in the time to complete the following commands can be achieved by

not waiting for the worst case delay (tW, tPP, tSE, or tBE).

• WRITE STATUS REGISTER

• PROGRAM

• ERASE (SECTOR ERASE, BULK ERASE)

The write in progress (WIP) bit is provided in the status register so that the application

program can monitor this bit in the status register, polling it to establish when the pre-

vious WRITE cycle, PROGRAM cycle, or ERASE cycle is complete.

Active Power, Standby Power, and Deep Power-Down

When chip select (S#) is LOW, the device is selected, and in the ACTIVE POWER mode.

When S# is HIGH, the device is deselected, but could remain in the ACTIVE POWER

mode until all internal cycles have completed (PROGRAM, ERASE, WRITE STATUS

sumption drops to ICC1.

The DEEP POWER-DOWN mode is entered when the DEEP POWER-DOWN command

is executed. The device consumption drops further to ICC2. The device remains in this

mode until the RELEASE FROM DEEP POWER-DOWN command is executed. While in

the DEEP POWER-DOWN mode, the device ignores all WRITE, PROGRAM, and ERASE

commands. This provides an extra software protection mechanism when the device is

not in active use, by protecting the device from inadvertent WRITE, PROGRAM, or

ERASE operations. For further information, see the DEEP POWER DOWN command.

M25P10A Serial Flash Embedded Memory

Operating Features

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Status Register

The status register contains a number of status and control bits that can be read or set

(as appropriate) by specific commands. For a detailed description of the status register

bits, see READ STATUS REGISTER (page 20).

Data Protection by Protocol

Non-volatile memory is used in environments that can include excessive noise. The fol-

lowing capabilities help protect data in these noisy environments.

Power on reset and an internal timer (tPUW) can provide protection against inadvertent

changes while the power supply is outside the operating specification.

PROGRAM, ERASE, and WRITE STATUS REGISTER commands are checked before they

are accepted for execution to ensure they consist of a number of clock pulses that is a

multiple of eight.

All commands that modify data must be preceded by a WRITE ENABLE command to set

the write enable latch (WEL) bit.

In addition to the low power consumption feature, the DEEP POWER-DOWN mode of-

fers extra software protection since all PROGRAM, and ERASE commands are ignored

when the device is in this mode.

Software Data Protection

Memory can be configured as read-only using the block protect bits (BP1, BP0) as

shown in the Protected Area Sizes table.

Hardware Data Protection

Hardware data protection is implemented using the write protect signal applied on the

W# pin. This freezes the status register in a read-only mode. In this mode, the block pro-

tect (BP) bits and the status register write disable bit (SRWD) are protected.

Table 3: Protected Area Sizes

Status Register Content Memory Content

BP Bit 1 BP Bit 0 Protected Area Unprotected Area

0 0 none All sectors (sectors 0 to 3)

0 1 Upper 4th (sector 3) Lower 3/4ths (sectors 0 to 2)

1 0 Upper half (sectors 2 and 3) Lower half (sectors 0 and 1)

1 1 All sectors (sectors 0 to 3) none

Note: 1. 0 0 = unprotected area (sectors): The device is ready to accept a BULK ERASE command

only if all block protect bits (BP1, BP0) are 0.

Hold Condition

The HOLD# signal is used to pause any serial communications with the device without

resetting the clocking sequence. However, taking this signal LOW does not terminate

any WRITE STATUS REGISTER, PROGRAM, or ERASE cycle that is currently in progress.

M25P10A Serial Flash Embedded Memory

Operating Features

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To enter the hold condition, the device must be selected, with S# LOW. The hold condi-

tion starts on the falling edge of the HOLD# signal, if this coincides with serial clock (C)

being LOW. The hold condition ends on the rising edge of the HOLD# signal, if this co-

incides with C being LOW. If the falling edge does not coincide with C being LOW, the

hold condition starts after C next goes LOW. Similarly, if the rising edge does not coin-

cide with C being LOW, the hold condition ends after C next goes LOW.

During the hold condition, DQ1 is HIGH impedance while DQ0 and C are Don’t Care.

Typically, the device remains selected with S# driven LOW for the duration of the hold

condition. This ensures that the state of the internal logic remains unchanged from the

moment of entering the hold condition. If S# goes HIGH while the device is in the hold

condition, the internal logic of the device is reset. To restart communication with the

device, it is necessary to drive HOLD# HIGH, and then to drive S# LOW. This prevents

the device from going back to the hold condition.

Figure 5: Hold Condition Activation

HOLD#

HOLD condition (standard use) HOLD condition (nonstandard use)

M25P10A Serial Flash Embedded Memory

Operating Features

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Configuration and Memory Map

Memory Configuration and Block Diagram

Each page of memory can be individually programmed; bits are programmed from 1 to

0. The device is sector or bulk-erasable, but not page-erasable; bits are erased from 0 to

1. The memory is configured as follows:

• 131,072 bytes (8 bits each)

• 4 sectors (256Kb, 32,768 bytes each)

• 512 pages (256 bytes each)

Figure 6: Block Diagram

HOLD#

W# Control Logic

High Voltage

Generator

I/O Shift Register

Address Register

and Counter

256 Byte

Data Buffer

256 bytes (page size)

X Decoder

Y Decoder

DQ0

DQ1

Status

00000h

1FFFFh

10000h

1FF00h

000FFh

18000h

08000h

Size of the

read-only

memory area

M25P10A Serial Flash Embedded Memory

Configuration and Memory Map

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Memory Map – 1Mb Density

Table 4: Sectors 3:0

Sector

Address Range

Start End

3 0001 8000 0001 FFFF

2 0001 0000 0001 7FFF

1 0008 0000 0000 FFFF

0 0000 0000 0000 7FFF

M25P10A Serial Flash Embedded Memory

Memory Map – 1Mb Density

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Command Set Overview

All commands, addresses, and data are shifted in and out of the device, most significant

bit first.

Serial data input DQ0 is sampled on the first rising edge of serial clock (C) after chip se-

lect (S#) is driven LOW. Then, the one-byte command code must be shifted in to the de-

vice, most significant bit first, on DQ1, each bit being latched on the rising edges of C.

Every command sequence starts with a one-byte command code. Depending on the

command, this command code might be followed by address or data bytes, by address

and data bytes, or by neither address or data bytes. For the following commands, the

shifted-in command sequence is followed by a data-out sequence. S# can be driven

HIGH after any bit of the data-out sequence is being shifted out.

• READ DATA BYTES (READ)

• READ DATA BYTES at HIGHER SPEED

• READ STATUS REGISTER

• READ IDENTIFICATION

• RELEASE from DEEP POWER-DOWN

For the following commands, S# must be driven HIGH exactly at a byte boundary. That

is, after an exact multiple of eight clock pulses following S# being driven LOW, S# must

be driven HIGH. Otherwise, the command is rejected and not executed.

• PAGE PROGRAM

• SECTOR ERASE

• BULK ERASE

• WRITE STATUS REGISTER

• WRITE ENABLE

• WRITE DISABLE

• DEEP POWER-DOWN

All attempts to access the memory array are ignored during a WRITE STATUS REGISTER

command cycle, a PROGRAM command cycle, or an ERASE command cycle. In addi-

tion, the internal cycle for each of these commands continues unaffected.

M25P10A Serial Flash Embedded Memory

Command Set Overview

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Table 5: Command Set Codes

Command Name

One-Byte

Command Code

Bytes

Address Dummy Data

WRITE ENABLE 0000

0110

06h 0 0 0

WRITE DISABLE 0000

0100

04h 0 0 0

READ IDENTIFICATION 1001

1111

9Fh 0 0 1 to 20

1001

1110

9Eh 1 to 20

READ STATUS REGISTER 0000

0101

05h 0 0 1 to ∞

WRITE STATUS REGISTER 0000

0001

01h 0 0 1

READ DATA BYTES 0000

0011

03h 3 0 1 to ∞

READ DATA BYTES at HIGHER SPEED 0000

1011

0Bh 3 1 1 to ∞

PAGE PROGRAM 0000

0010

02h 3 0 1 to 256

SECTOR ERASE 1101

1000

D8h 3 0 0

BULK ERASE 1100

0111

C7h 0 0 0

DEEP POWER-DOWN 1011

1001

B9h 0 0 0

RELEASE from DEEP POWER-DOWN 1010

1011

ABh 0 0 0

M25P10A Serial Flash Embedded Memory

Command Set Overview

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WRITE ENABLE

The WRITE ENABLE command sets the write enable latch (WEL) bit.

The WEL bit must be set before execution of every PROGRAM, ERASE, and WRITE com-

mand.

The WRITE ENABLE command is entered by driving chip select (S#) LOW, sending the

command code, and then driving S# HIGH.

Figure 7: WRITE ENABLE Command Sequence

Don’t Care

DQ[0]

01 2 4 53 76

High-Z

DQ1

MSB

LSB

0 0 0 0 0 011

Command bits

M25P10A Serial Flash Embedded Memory

WRITE ENABLE

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WRITE DISABLE

The WRITE DISABLE command resets the write enable latch (WEL) bit.

The WRITE DISABLE command is entered by driving chip select (S#) LOW, sending the

command code, and then driving S# HIGH.

The WEL bit is reset under the following conditions:

• Power-up

• Completion of any ERASE operation

• Completion of any PROGRAM operation

• Completion of any WRITE REGISTER operation

• Completion of WRITE DISABLE operation

Figure 8: WRITE DISABLE Command Sequence

Don’t Care

DQ[0]

01 2 4 53 76

High-Z

DQ1

MSB

LSB

0 0 0 0 0 001

Command bits

M25P10A Serial Flash Embedded Memory

WRITE DISABLE

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READ IDENTIFICATION

The READ IDENTIFICATION command reads the following device identification data:

• Manufacturer identification (1 byte): This is assigned by JEDEC.

• Device identification (2 bytes): This is assigned by device manufacturer; the first byte

indicates memory type and the second byte indicates device memory capacity.

• A Unique ID code (UID) (17 bytes,16 available upon customer request): The first byte

contains length of data to follow; the remaining 16 bytes contain optional Customized

Factory Data (CFD) content.

Table 6: READ IDENTIFICATION Data Out Sequence

Manufacturer

Identification

Device Identification UID

Memory Type Memory Capacity CFD Length CFD Content

20h 20h 11h 10h 16 bytes

Note: 1. The CFD bytes are read-only and can be programmed with customer data upon demand.

If customers do not make requests, the devices are shipped with all the CFD bytes pro-

grammed to zero.

A READ IDENTIFICATION command is not decoded while an ERASE or PROGRAM cy-

cle is in progress and has no effect on a cycle in progress. The READ IDENTIFICATION

command must not be issued while the device is in DEEP POWER-DOWN mode.

The device is first selected by driving S# LOW. Then the 8-bit command code is shifted

in and content is shifted out on DQ1 as follows: the 24-bit device identification that is

stored in the memory, the 8-bit CFD length, followed by 16 bytes of CFD content. Each

bit is shifted out during the falling edge of serial clock (C).

The READ IDENTIFICATION command is terminated by driving S# HIGH at any time

during data output. When S# is driven HIGH, the device is put in the STANDBY POWER

mode and waits to be selected so that it can receive, decode, and execute commands.

Figure 9: READ IDENTIFICATION Command Sequence

UIDDevice

identification

Manufacturer

identification

High-Z

DQ1

MSB MSB

DOUT DOUT DOUT DOUT

LSB

7 8 15 16 32

MSB

DQ0

LSB

Command

MSB

DOUT DOUT

LSB

Don’t Care

M25P10A Serial Flash Embedded Memory

READ IDENTIFICATION

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READ STATUS REGISTER

The READ STATUS REGISTER command allows the status register to be read. The status

ded to check the write in progress (WIP) bit before sending a new command to the de-

vice. It is also possible to read the status register continuously.

Figure 10: READ STATUS REGISTER Command Sequence

High-Z

DQ1

7 8 9 10 11 12 13 14 15

MSB

DQ0

LSB

Command

MSB

DOUT DOUT DOUT DOUT DOUT

LSB

DOUT DOUT DOUT DOUT

Don’t Care

Figure 11: Status Register Format

SRWD 00 0 BP1 BP0 WEL WIP

status register write protect

block protect bits

write enable latch bit

write in progress bit

M25P10A Serial Flash Embedded Memory

READ STATUS REGISTER

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WIP Bit

The write in progress (WIP) bit indicates whether the memory is busy with a WRITE

STATUS REGISTER cycle, a PROGRAM cycle, or an ERASE cycle. When the WIP bit is set

to 1, a cycle is in progress; when the WIP bit is set to 0, a cycle is not in progress.

WEL Bit

The write enable latch (WEL) bit indicates the status of the internal write enable latch.

When the WEL bit is set to 1, the internal write enable latch is set; when the WEL bit is

set to 0, the internal write enable latch is reset and no WRITE STATUS REGISTER, PRO-

GRAM, or ERASE command is accepted.

Block Protect Bits

The block protect bits are non-volatile. They define the size of the area to be software

protected against PROGRAM and ERASE commands. The block protect bits are written

with the WRITE STATUS REGISTER command.

When one or more of the block protect bits is set to 1, the relevant memory area, as de-

fined in the Protected Area Sizes table, becomes protected against PAGE PROGRAM and

SECTOR ERASE commands. The block protect bits can be written provided that the

HARDWARE PROTECTED mode has not been set. The BULK ERASE command is execu-

ted only if all block protect bits are 0.

SRWD Bit

The status register write disable (SRWD) bit is operated in conjunction with the write

protect (W#) signal. When the SRWD bit is set to 1 and W# is driven LOW, the device is

put in the hardware protected mode. In the hardware protected mode, the non-volatile

bits of the status register (SRWD, and the block protect bits) become read-only bits and

the WRITE STATUS REGISTER command is no longer accepted for execution.

M25P10A Serial Flash Embedded Memory

READ STATUS REGISTER

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WRITE STATUS REGISTER

The WRITE STATUS REGISTER command allows new values to be written to the status

ABLE command must have been executed previously. After the WRITE ENABLE com-

mand has been decoded and executed, the device sets the write enable latch (WEL) bit.

The WRITE STATUS REGISTER command is entered by driving chip select (S#) LOW,

followed by the command code and the data byte on serial data input (DQ0). The

WRITE STATUS REGISTER command has no effect on b6, b5, b4, b1, and b0 of the sta-

tus register. The status register b6 b5, and b4 are always read as ‘0’. S# must be driven

HIGH after the eighth bit of the data byte has been latched in. If not, the WRITE STATUS

Figure 12: WRITE STATUS REGISTER Command Sequence

7 8 9 10 11 12 13 14 15

MSB

DQ0

LSB

Command

MSB

LSB

DIN DIN DIN DIN DIN

DIN DIN DIN DIN

As soon as S# is driven HIGH, the self-timed WRITE STATUS REGISTER cycle is initi-

ated; its duration is tW. While the WRITE STATUS REGISTER cycle is in progress, the sta-

tus register may still be read to check the value of the write in progress (WIP) bit. The

WIP bit is 1 during the self-timed WRITE STATUS REGISTER cycle, and is 0 when the

cycle is completed. Also, when the cycle is completed, the WEL bit is reset.

The WRITE STATUS REGISTER command allows the user to change the values of the

block protect bits (BP1, BP0). Setting these bit values defines the size of the area that is

to be treated as read-only, as defined in the Protected Area Sizes table.

The WRITE STATUS REGISTER command also allows the user to set and reset the status

SRWD bit and the W# signal allow the device to be put in the HARDWARE PROTECED

(HPM) mode. The WRITE STATUS REGISTER command is not executed once the HPM

is entered. The options for enabling the status register protection modes are summar-

ized here.

M25P10A Serial Flash Embedded Memory

WRITE STATUS REGISTER

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Table 7: Status Register Protection Modes

Signal

SRWD

Bit

Protection

Mode (PM)

Status Register

Write Protection

Memory Content

Notes

Protected

Area

Unprotected

Area

1 0 SOFTWARE

PROTECTED mode

(SPM)

Software protection Commands not

accepted

Commands

accepted

1, 2, 3

0 0

1 1

0 1 HARDWARE

PROTECTED mode

(HPM)

Hardware protection Commands not

accepted

Commands

accepted

3, 4, 5,

Notes: 1. Software protection: status register is writable (SRWD, BP1, and BP0 bit values can be

changed) if the WRITE ENABLE command has set the WEL bit.

2. PAGE PROGRAM, SECTOR ERASE, AND BULK ERASE commands are not accepted.

3. PAGE PROGRAM and SECTOR ERASE commands can be accepted.

4. Hardware protection: status register is not writable (SRWD, BP1, and BP0 bit values can-

not be changed).

5. PAGE PROGRAM, SECTOR ERASE, AND BULK ERASE commands are not accepted.

When the SRWD bit of the status register is 0 (its initial delivery state), it is possible to

write to the status register provided that the WEL bit has been set previously by a WRITE

ENABLE command, regardless of whether the W# signal is driven HIGH or LOW. When

the status register SRWD bit is set to 1, two cases need to be considered depending on

the state of the W# signal:

• If the W# signal is driven HIGH, it is possible to write to the status register provided

that the WEL bit has been set previously by a WRITE ENABLE command.

• If the W# signal is driven LOW, it is not possible to write to the status register even if

the WEL bit has been set previously by a WRITE ENABLE command. Therefore, at-

tempts to write to the status register are rejected, and are not accepted for execution.

The result is that all the data bytes in the memory area that have been put in SPM by

the status register block protect bits (BP1, BP0) are also hardware protected against

data modification.

Regardless of the order of the two events, the HPM can be entered in either of the fol-

lowing ways:

• Setting the status register SRWD bit after driving the W# signal LOW

• Driving the W# signal LOW after setting the status register SRWD bit.

The only way to exit the HPM is to pull the W# signal HIGH. If the W# signal is perma-

nently tied HIGH, the HPM can never be activated. In this case, only the SPM is availa-

ble, using the status register block protect bits (BP1, BP0).

M25P10A Serial Flash Embedded Memory

WRITE STATUS REGISTER

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READ DATA BYTES

The device is first selected by driving chip select (S#) LOW. The command code for

READ DATA BYTES is followed by a 3-byte address (A23-A0), each bit being latched-in

during the rising edge of serial clock (C). Then the memory contents at that address is

shifted out on serial data output (DQ1), each bit being shifted out at a maximum fre-

quency fR during the falling edge of C.

The first byte addressed can be at any location. The address is automatically incremen-

ted to the next higher address after each byte of data is shifted out. Therefore, the entire

memory can be read with a single READ DATA BYTES command. When the highest ad-

dress is reached, the address counter rolls over to 000000h, allowing the read sequence

to be continued indefinitely.

The READ DATA BYTES command is terminated by driving S# HIGH. S# can be driven

HIGH at any time during data output. Any READ DATA BYTES command issued while

an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on

the cycle that is in progress.

Figure 13: READ DATA BYTES Command Sequence

Don’t Care

MSB

DQ[0]

LSB

Command

A[MAX]

A[MIN]

7 8 Cx

High-Z

DQ1

MSB

DOUT DOUT DOUT DOUT DOUT

LSB

DOUT DOUT DOUT DOUT

Note: 1. Cx = 7 + (A[MAX] + 1).

M25P10A Serial Flash Embedded Memory

READ DATA BYTES

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READ DATA BYTES at HIGHER SPEED

The device is first selected by driving chip select (S#) LOW. The command code for the

READ DATA BYTES at HIGHER SPEED command is followed by a 3-byte address (A23-

A0) and a dummy byte, each bit being latched-in during the rising edge of serial clock

(C). Then the memory contents at that address are shifted out on serial data output

(DQ1) at a maximum frequency fC, during the falling edge of C.

The first byte addressed can be at any location. The address is automatically incremen-

ted to the next higher address after each byte of data is shifted out. Therefore, the entire

memory can be read with a single READ DATA BYTES at HIGHER SPEED command.

When the highest address is reached, the address counter rolls over to 000000h, allow-

ing the read sequence to be continued indefinitely.

The READ DATA BYTES at HIGHER SPEED command is terminated by driving S# HIGH.

S# can be driven HIGH at any time during data output. Any READ DATA BYTES at

HIGHER SPEED command issued while an ERASE, PROGRAM, or WRITE cycle is in

progress is rejected without any effect on the cycle that is in progress.

Figure 14: READ DATA BYTES at HIGHER SPEED Command Sequence

7 8 Cx

MSB

DQ0

LSB

Command

A[MAX]

A[MIN]

MSB

DOUT DOUT DOUT DOUT DOUT

LSB

DOUT DOUT DOUT DOUT

Dummy cycles

DQ1 High-Z

Don’t Care

Note: 1. Cx = 7 + (A[MAX] + 1).

M25P10A Serial Flash Embedded Memory

READ DATA BYTES at HIGHER SPEED

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PAGE PROGRAM

The PAGE PROGRAM command allows bytes in the memory to be programmed, which

means the bits are changed from 1 to 0. Before a PAGE PROGRAM command can be ac-

cepted a WRITE ENABLE command must be executed. After the WRITE ENABLE com-

mand has been decoded, the device sets the write enable latch (WEL) bit.

The PAGE PROGRAM command is entered by driving chip select (S#) LOW, followed by

the command code, three address bytes, and at least one data byte on serial data input

(DQ0).

If the eight least significant address bits (A7-A0) are not all zero, all transmitted data that

goes beyond the end of the current page are programmed from the start address of the

same page; that is, from the address whose eight least significant bits (A7-A0) are all

zero. S# must be driven LOW for the entire duration of the sequence.

If more than 256 bytes are sent to the device, previously latched data are discarded and

the last 256 data bytes are guaranteed to be programmed correctly within the same

page. If less than 256 data bytes are sent to device, they are correctly programmed at the

requested addresses without any effects on the other bytes of the same page.

For optimized timings, it is recommended to use the PAGE PROGRAM command to

program all consecutive targeted bytes in a single sequence rather than to use several

PAGE PROGRAM sequences, each containing only a few bytes.

S# must be driven HIGH after the eighth bit of the last data byte has been latched in.

Otherwise the PAGE PROGRAM command is not executed.

As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle is initiated; the cy-

cles's duration is tPP. While the PAGE PROGRAM cycle is in progress, the status register

may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during

the self-timed PAGE PROGRAM cycle, and 0 when the cycle is completed. At some un-

specified time before the cycle is completed, the write enable latch (WEL) bit is reset.

A PAGE PROGRAM command is not executed if it applies to a page protected by the

block protect bits BP1, and BP0.

Figure 15: PAGE PROGRAM Command Sequence

7 8 Cx

MSB

DQ[0]

LSB

Command

A[MAX]

A[MIN]

MSB

DIN DIN DIN DIN DIN

LSB

DIN DIN DIN DIN

Note: 1. Cx = 7 + (A[MAX] + 1).

M25P10A Serial Flash Embedded Memory

PAGE PROGRAM

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SECTOR ERASE

The SECTOR ERASE command sets to 1 (FFh) all bits inside the chosen sector. Before

the SECTOR ERASE command can be accepted, a WRITE ENABLE command must have

been executed previously. After the WRITE ENABLE command has been decoded, the

device sets the write enable latch (WEL) bit.

The SECTOR ERASE command is entered by driving chip select (S#) LOW, followed by

the command code, and three address bytes on serial data input (DQ0). Any address in-

side the sector is a valid address for the SECTOR ERASE command. S# must be driven

LOW for the entire duration of the sequence.

S# must be driven HIGH after the eighth bit of the last address byte has been latched in.

Otherwise the SECTOR ERASE command is not executed. As soon as S# is driven HIGH,

the self-timed SECTOR ERASE cycle is initiated; the cycle's duration is tSE. While the

SECTOR ERASE cycle is in progress, the status register may be read to check the value of

the write in progress (WIP) bit. The WIP bit is 1 during the self-timed SECTOR ERASE

cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is

completed, the WEL bit is reset.

A SECTOR ERASE command is not executed if it applies to a sector that is hardware or

software protected.

Figure 16: SECTOR ERASE Command Sequence

7 8 Cx

MSB

DQ0

LSB

Command

A[MAX]

A[MIN]

Note: 1. Cx = 7 + (A[MAX] + 1).

M25P10A Serial Flash Embedded Memory

SECTOR ERASE

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BULK ERASE

The BULK ERASE command sets all bits to 1 (FFh). Before the BULK ERASE command

can be accepted, a WRITE ENABLE command must have been executed previously. Af-

ter the WRITE ENABLE command has been decoded, the device sets the write enable

latch (WEL) bit.

The BULK ERASE command is entered by driving chip select (S#) LOW, followed by the

command code on serial data input (DQ0). S# must be driven LOW for the entire dura-

tion of the sequence.

S# must be driven HIGH after the eighth bit of the command code has been latched in.

Otherwise the BULK ERASE command is not executed. As soon as S# is driven HIGH,

the self-timed BULK ERASE cycle is initiated; the cycle's duration is tBE. While the BULK

ERASE cycle is in progress, the status register may be read to check the value of the write

In progress (WIP) bit. The WIP bit is 1 during the self-timed BULK ERASE cycle, and is 0

when the cycle is completed. At some unspecified time before the cycle is completed,

the WEL bit is reset.

The BULK ERASE command is executed only if all block protect (BP1, BP0) bits are 0.

The BULK ERASE command is ignored if one or more sectors are protected.

Figure 17: BULK ERASE Command Sequence

MSB

DQ0

LSB

Command

M25P10A Serial Flash Embedded Memory

BULK ERASE

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DEEP POWER-DOWN

Executing the DEEP POWER-DOWN command is the only way to put the device in the

lowest power consumption mode, the DEEP POWER-DOWN mode. The DEEP POWER-

DOWN command can also be used as a software protection mechanism while the de-

vice is not in active use because in the DEEP POWER-DOWN mode the device ignores

all WRITE, PROGRAM, and ERASE commands.

Driving chip select (S#) HIGH deselects the device, and puts it in the STANDBY POWER

mode if there is no internal cycle currently in progress. Once in STANDBY POWER

mode, the DEEP POWER-DOWN mode can be entered by executing the DEEP POWER-

DOWN command, subsequently reducing the standby current from ICC1 to ICC2.

To take the device out of DEEP POWER-DOWN mode, the RELEASE from DEEP POW-

ER-DOWN command must be issued. Other commands must not be issued while the

device is in DEEP POWER-DOWN mode. The DEEP POWER-DOWN mode stops auto-

matically at power-down. The device always powers up in STANDBY POWER mode.

The DEEP POWER-DOWN command is entered by driving S# LOW, followed by the

command code on serial data input (DQ0). S# must be driven LOW for the entire dura-

tion of the sequence.

S# must be driven HIGH after the eighth bit of the command code has been latched in.

Otherwise the DEEP POWER-DOWN command is not executed. As soon as S# is driven

HIGH, it requires a delay of tDP before the supply current is reduced to ICC2 and the

DEEP POWER-DOWN mode is entered.

Any DEEP POWER-DOWN command issued while an ERASE, PROGRAM, or WRITE cy-

cle is in progress is rejected without any effect on the cycle that is in progress.

Figure 18: DEEP POWER-DOWN Command Sequence

MSB

DQ0

LSB tDP

Command

Don’t Care

Deep Power-Down ModeStandby Mode

M25P10A Serial Flash Embedded Memory

DEEP POWER-DOWN

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RELEASE from DEEP POWER-DOWN

Once the device has entered DEEP POWER-DOWN mode, all commands are ignored ex-

cept RELEASE from DEEP POWER-DOWN and READ ELECTRONIC SIGNATURE. Exe-

cuting either of these commands takes the device out of the DEEP POWER-DOWN

mode.

The RELEASE from DEEP POWER-DOWN command is entered by driving chip select

(S#) LOW, followed by the command code on serial data input (DQ0). S# must be driven

LOW for the entire duration of the sequence.

The RELEASE from DEEP POWER-DOWN command is terminated by driving S# HIGH.

Sending additional clock cycles on serial clock C while S# is driven LOW causes the

command to be rejected and not executed.

After S# has been driven HIGH, followed by a delay, tRES, the device is put in the STAND-

BY mode. S# must remain HIGH at least until this period is over. The device waits to be

selected so that it can receive, decode, and execute commands.

Any RELEASE from DEEP POWER-DOWN command issued while an ERASE, PRO-

GRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in

progress.

Figure 19: RELEASE from DEEP POWER-DOWN Command Sequence

High-Z

DQ1

MSB

DQ0

LSB tRDP

Command

Don’t Care

Deep Power-Down Mode Standby Mode

M25P10A Serial Flash Embedded Memory

RELEASE from DEEP POWER-DOWN

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READ ELECTRONIC SIGNATURE

Once the device enters DEEP POWER-DOWN mode, all commands are ignored except

READ ELECTRONIC SIGNATURE and RELEASE from DEEP POWER-DOWN. Executing

either of these commands takes the device out of the DEEP POWER-DOWN mode.

The READ ELECTRONIC SIGNATURE command is entered by driving chip select (S#)

LOW, followed by the command code and three dummy bytes on serial data input

(DQ0) . Each bit is latched in on the rising edge of serial clock C. The 8-bit electronic

signature is shifted out on serial data output DQ1 on the falling edge of C; S# must be

driven LOW the entire duration of the sequence for the electronic signature to be read.

However, driving S# HIGH after the command code, but before the entire 8-bit electron-

ic signature has been output for the first time, still ensures that the device is put into

STANDBY mode.

Except while an ERASE, PROGRAM, or WRITE STATUS REGISTER cycle is in progress,

the READ ELECTRONIC SIGNATURE command provides access to the 8-bit electronic

signature of the device, and can be applied even if DEEP POWER-DOWN mode has not

been entered. The READ ELECTRONIC SIGNATURE command is not executed while an

ERASE, PROGRAM, or WRITE STATUS REGISTER cycle is in progress and has no effect

on the cycle in progress.

The READ ELECTRONIC SIGNATURE command is terminated by driving S# high after

the electronic signature has been read at least once. Sending additional clock cycles C

while S# is driven LOW causes the electronic signature to be output repeatedly.

If S# is driven HIGH, the device is put in STANDBY mode immediately unless it was pre-

viously in DEEP POWER-DOWN mode. If previously in DEEP POWER-DOWN mode, the

device transitions to STANDBY mode with delay as described here. Once in STANDBY

mode, the device waits to be selected so that it can receive, decode, and execute instruc-

tions.

• If S# is driven HIGH before the electronic signature is read, transition to STANDBY

mode is delayed by tRES1, as shown in the RELEASE from DEEP POWER-DOWN com-

mand sequence. S# must remain HIGH for at least tRES1(max).

• If S# is driven HIGH after the electronic signature is read, transition to STANDBY

mode is delayed by tRES2. S# must remain HIGH for at least tRES2(max).

Figure 20: READ ELECTRONIC SIGNATURE Command Sequence

7 8 Cx

MSB

DQ0

LSB

Command

MSB

LSB

DQ1 High-Z

Don’t Care

DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT

Dummy cycles

Electronic Signature

Deep Power-Down Standby

tRES2

Note: 1. Cx = 7 + (A[MAX] + 1).

M25P10A Serial Flash Embedded Memory

READ ELECTRONIC SIGNATURE

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Power-Up/Down and Supply Line Decoupling

At power-up and power-down, the device must not be selected; that is, chip select (S#)

must follow the voltage applied on VCC until VCC reaches the correct value:

• VCC,min at power-up, and then for a further delay of tVSL

• VSS at power-down

A safe configuration is provided in the SPI Modes section.

To avoid data corruption and inadvertent write operations during power-up, a power-

on-reset (POR) circuit is included. The logic inside the device is held reset while VCC is

less than the POR threshold voltage, VWI – all operations are disabled, and the device

does not respond to any instruction. Moreover, the device ignores the following instruc-

tions until a time delay of tPUW has elapsed after the moment that VCC rises above the

VWI threshold:

• WRITE ENABLE

• PAGE PROGRAM

• SECTOR ERASE

• BULK ERASE

• WRITE STATUS REGISTER

However, the correct operation of the device is not guaranteed if, by this time, VCC is still

below VCC.min. No WRITE STATUS REGISTER, PROGRAM, or ERASE instruction should

be sent until:

•tPUW after VCC has passed the VWI threshold

•tVSL after VCC has passed the VCC,min level

If the time, tVSL, has elapsed, after VCC rises above VCC,min, the device can be selected

for READ instructions even if the tPUW delay has not yet fully elapsed.

M25P10A Serial Flash Embedded Memory

Power-Up/Down and Supply Line Decoupling

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Figure 21: Power-Up Timing

VCC

VCC,min

VWI

RESET state

of the

device

Chip selection not allowed

PROGRAM, ERASE, and WRITE commands are rejected by the device

tVSL

tPUW

Time

READ access allowed Device fully

accessible

VCC,max

After power-up, the device is in the following state:

• Standby power mode (not the deep power-down mode)

• Write enable latch (WEL) bit is reset

• Write in progress (WIP) bit is reset

• Write lock bit = 0

• Lock down bit = 0

Normal precautions must be taken for supply line decoupling to stabilize the VCC sup-

ply. Each device in a system should have the VCC line decoupled by a suitable capacitor

close to the package pins; generally, this capacitor is of the order of 100 nF.

At power-down, when VCC drops from the operating voltage to below the POR threshold

voltage VWI, all operations are disabled and the device does not respond to any instruc-

tion.

Note: If power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in progress,

some data corruption may result.

M25P10A Serial Flash Embedded Memory

Power-Up/Down and Supply Line Decoupling

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Power-Up Timing and Write Inhibit Voltage Threshold Specifications

Table 8: Power-Up Timing and VWI Threshold

Symbol Parameter Min Max Unit

tVSL VCC(min) to S# LOW 10 – μs

tPUW Time delay to write instruction 1.0 10 ms

VWI Write Inhibit voltage (grade 6) 1.0 2.0 V

VWI Write Inhibit voltage (grade 3) 1.0 2.2 V

Note: 1. Parameters are characterized only.

If the time, tVSL, has elapsed, after VCC rises above VCC(min), the device can be selected

for READ instructions even if the tPUW delay has not yet fully elapsed.

VPPH must be applied only when VCC is stable and in the VCCmin to VCCmax voltage

range.

M25P10A Serial Flash Embedded Memory

Power-Up Timing and Write Inhibit Voltage Threshold Specifi-

cations

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Maximum Ratings and Operating Conditions

Caution: Stressing the device beyond the absolute maximum ratings may cause perma-

nent damage to the device. These are stress ratings only, and operation of the device be-

yond any specification or condition in the operating sections of this data sheet is not

recommended. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

Table 9: Absolute Maximum Ratings

Symbol Parameter Min Max Units Notes

TSTG Storage temperature –65 150 °C

TLEAD Lead temperature during soldering – See note °C 1

VIO Input and output voltage (with respect to ground) –0.6 VCC + 0.6 V 2

VCC Supply voltage –0.6 4.0 V

VESD Electrostatic discharge voltage (Human Body mod-

el)

–2000 2000 V 3

Notes: 1. The TLEAD signal is compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb as-

sembly), the Micron RoHS-compliant 7191395 specification, and the European directive

on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.

2. The minimum voltage may reach the value of –2V for no more than 20ns during transi-

tions; the maximum may reach the value of VCC +2V for no more than 20ns during tran-

sitions.

3. The VESD signal: JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500Ω, R2 = 500Ω).

Table 10: Operating Conditions

Symbol Parameter Min Typical Max Unit Notes

VCC Supply voltage 2.3 – 3.6 V 1

TAAmbient operating temperature (grade 6) –40 – 85 °C 2

TAAmbient operating temperature (grade 3) –40 – 125 °C 3

Notes: 1. Autograde 3 = 2.7V to 3.6V

2. Autograde 6 and standard parts (grade 6) are tested to 85°C. Autograde 6 follows the

high-reliability certified test flow.

3. Autograde 3 is tested to 125°C.

Table 11: Data Retention and Endurance

Symbol Condition Min Max Unit

Program/Erase

Cycles

Grade 6, grade 3, autograde 6 100,000 – Cycles per block

Data Retention at 55°C 20 – Years

M25P10A Serial Flash Embedded Memory

Maximum Ratings and Operating Conditions

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Electrical Characteristics

Table 12: DC Current Specifications

Symbol Parameter Test Conditions Min Max Units

ILI Input leakage current – – ±2 µA

ILO Output leakage current – – ±2 µA

ICC1 Standby current (grade 6) S# = VCC, VIN = VSS or VCC – 50 µA

ICC1 Standby current (grade 3) – 100 µA

ICC2 Deep power-down current (grade

S# = VCC, VIN = VSS or VCC – 5 µA

ICC2 Deep power-down current (grade

– 50 µA

ICC3 Operating current (READ) C = 0.1 VCC / 0.9 VCC at 50 Mhz (grade 6)

or 25 Mhz (grade 3), DQ1 = open

– 8 mA

C = 0.1 VCC / 0.9 VCC at 25 Mhz (grade 6)

or 20 Mhz (grade 3), DQ1 = open

– 4 mA

ICC4 Operating current

(PAGE PROGRAM)

S# = VCC – 15 mA

ICC5 Operating current

(WRITE STATUS REGISTER)

S# = VCC – 15 mA

ICC6 Operating current

(SECTOR ERASE)

S# = VCC – 15 mA

ICC7 Operating current

(BULK ERASE)

S# = VCC – 15 mA

Table 13: DC Voltage Specifications

Symbol Parameter Test Conditions Min Max Units

VIL Input LOW voltage – –0.5 0.3 VCC V

VIH Input HIGH voltage – 0.7 VCC VCC+0.4 V

VOL Output LOW voltage IOL = 1.6mA – 0.4 V

VOH Output HIGH voltage IOH = –100µA VCC–0.2 – V

M25P10A Serial Flash Embedded Memory

Electrical Characteristics

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AC Characteristics

In the following AC specifications, output HIGH-Z is defined as the point where data

out is no longer driven.

Table 14: AC Measurement Conditions

Symbol Parameter Min Max Unit

CLLoad capacitance 30 30 pF

Input rise and fall times – 5 ns

Input pulse voltages 0.2 VCC 0.8 VCC V

Input timing reference voltages 0.3 VCC 0.7 VCC V

Output timing reference voltages VCC / 2 VCC / 2 V

Figure 22: AC Measurement I/O Waveform

Input and output

timing reference levels

Input levels

0.8VCC

0.2VCC

0.7VCC

0.3VCC

0.5VCC

Table 15: Capacitance

Symbol Parameter Test Condition Min Max Unit Notes

COUT Output capacitance (DQ1) VOUT = 0 V – 8 pF 1

CIN Input capacitance (other pins) VIN = 0 V – 6 pF

Note: 1. Values are sampled only, not 100% tested, at TA = 25°C and a frequency of 25 MHz.

M25P10A Serial Flash Embedded Memory

AC Characteristics

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Table 16: AC Specifications 40 MHz

Symbol Alt. Parameter Min Typ Max Unit Notes

fCfCClock frequency for all commands (except READ) D.C. – 40 MHz

fR– Clock frequency for READ command D.C. – 20 MHz

tCH tCLH Clock HIGH time 11 – – ns 2

tCL tCLL Clock LOW time 11 – – ns 2, 3

tCLCH – Clock rise time (peak to peak) 0.1 – – V/ns 4, 5

tCHCL – Clock fall time (peak to peak) 0.1 – – V/ns 4, 5

tSLCH tCSS S# active setup time (relative to C) 5 – – ns

tCHSL S# not active hold time (relative to C) 5 – – ns

tDVCH tDSU Data In setup time 2 – – ns

tCHDX tDH Data In hold time 5 – – ns

tCHSH – S# active hold time (relative to C) 5 – – ns

tSHCH – S# not active setup time (relative to C) 5 – – ns

tSHSL tCSH S# deselect time 100 – – ns

tSHQZ tDIS Output disable time – – 9 ns 4

tCLQV tVClock LOW to output valid – – 9 ns

tCLQX tHO Output hold time 0 – – ns

tHLCH – HOLD# setup time (relative to C) 5 – – ns

tCHHH – HOLD# hold time (relative to C) 5 – – ns

tHHCH – HOLD# setup time (relative to C) 5 – – ns

tCHHL – HOLD# hold time (relative to C) 5 – – ns

tHHQX tLZ HOLD# to output LOW-Z – – 9 ns 4

tHLQZ tHZ HOLD# to output HIGH-Z – – 9 ns 4

tWHSL – WRITE PROTECT setup time 20 – – ns 6

tSHWL – WRITE PROTECT hold time 100 – – ns 6

tDP – S# HIGH to DEEP POWER-DOWN mode – – 3 μs 4

tRES1 – S# HIGH to STANDBY without READ ELECTRONIC SIGNA-

TURE

– – 30 μs 4

tRES2 – S# HIGH to STANDBY with READ ELECTRONIC SIGNATURE – – 30 μs 4

Notes: 1. Applies to entire table: the AC specification values shown here are allowed only on the

VCC range 2.7V to 3.6V. The maximum frequency in the VCC range 2.3V to 2.7V is 40

MHz.

2. The tCH and tCL signal values must be greater than or equal to 1/fC.

3. Typical values are given for TA = 25°C.

4. The tCLCH, tCHCL, tSHQZ, tHHQX, tHLQZ, tDP, and tRDP signal values are guaranteed by charac-

terization, not 100% tested in production.

5. The tCLCH and tCHCL signals clock rise and fall time values are expressed as a slew rate.

6. The tWHSL and tSHWL signal values are only applicable as a constraint for a WRITE STATUS

M25P10A Serial Flash Embedded Memory

AC Characteristics

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Table 17: AC Specifications 50 MHz

Symbol Alt. Parameter Min Typ Max Unit Notes

fCfCClock frequency for all commands (except READ) D.C. – 50 MHz

fR– Clock frequency for READ command D.C. – 25 MHz

tCH tCLH Clock HIGH time 9 – – ns 2

tCL tCLL Clock LOW time 9 – – ns 2, 3

tCLCH – Clock rise time (peak to peak) 0.1 – – V/ns 4, 5

tCHCL – Clock fall time (peak to peak) 0.1 – – V/ns 4, 5

tSLCH tCSS S# active setup time (relative to C) 5 – – ns

tCHSL S# not active hold time (relative to C) 5 – – ns

tDVCH tDSU Data In setup time 2 – – ns

tCHDX tDH Data In hold time 5 – – ns

tCHSH – S# active hold time (relative to C) 5 – – ns

tSHCH – S# not active setup time (relative to C) 5 – – ns

tSHSL tCSH S# deselect time 100 – – ns

tSHQZ tDIS Output disable time – – 8 ns 4

tCLQV tVClock LOW to output valid – – 8 ns

tCLQX tHO Output hold time 0 – – ns

tHLCH – HOLD# setup time (relative to C) 5 – – ns

tCHHH – HOLD# hold time (relative to C) 5 – – ns

tHHCH – HOLD# setup time (relative to C) 5 – – ns

tCHHL – HOLD# hold time (relative to C) 5 – – ns

tHHQX tLZ HOLD# to output LOW-Z – – 8 ns 4

tHLQZ tHZ HOLD# to output HIGH-Z – – 8 ns 4

tWHSL – WRITE PROTECT setup time 20 – – ns 6

tSHWL – WRITE PROTECT hold time 100 – – ns 6

tDP – S# HIGH to DEEP POWER-DOWN mode – – 3 μs 4

tRES1 – S# HIGH to STANDBY without READ ELECTRONIC SIGNA-

TURE

– – 30 μs 4

tRES2 – S# HIGH to STANDBY with READ ELECTRONIC SIGNATURE – – 30 μs 4

Notes: 1. Applies to entire table: the AC specification values shown here are allowed only on the

VCC range 2.7V to 3.6V. The maximum frequency in the VCC range 2.3V to 2.7V is 40

MHz.

2. The tCH and tCL signal values must be greater than or equal to 1/fC.

3. Typical values are given for TA = 25°C.

4. The tCLCH, tCHCL, tSHQZ, tHHQX, tHLQZ, tDP, and tRDP signal values are guaranteed by charac-

terization, not 100% tested in production.

5. The tCLCH and tCHCL signals clock rise and fall time values are expressed as a slew rate.

6. The tWHSL and tSHWL signal values are only applicable as a constraint for a WRITE STATUS

M25P10A Serial Flash Embedded Memory

AC Characteristics

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Table 18: Instruction Times

Symbol Parameter Min Typ Max Units Notes

tWWRITE STATUS REGISTER cycle time – 5 15 ms

tPP PAGE PROGRAM cycle time (256 bytes) – 1.4 5 ms on page

tPP PAGE PROGRAM cycle time (n bytes) – See note

tSE SECTOR ERASE cycle time – 0.65 3 s

tBE BULK ERASE cycle time – 1.7 6 s

Notes: 1. When using the PAGE PROGRAM command to program consecutive bytes, optimized

timings are obtained in one sequence that includes all the bytes rather than in several

sequences of only a few bytes (1 < n < 256).

2. 4us + 8us*[int(n-1)/2+1]+4us*[int(n-1)/2].

M25P10A Serial Flash Embedded Memory

AC Characteristics

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Figure 23: Serial Input Timing

DQ0

MSB IN

DQ1

tDVCH

high impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

Figure 24: Write Protect Setup and Hold during WRSR when SRWD=1 Timing

DQ0

DQ1

High-Z

tWHSL tSHWL

M25P10A Serial Flash Embedded Memory

AC Characteristics

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Figure 25: Hold Timing

tCHHL

tHLCH

tHHCH

tHHQXtHLQZ

DQ1

DQ0

HOLD#

tCHHH

Figure 26: Output Timing

DQ1

LSB OUT

DQ0 ADDRESS

LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

M25P10A Serial Flash Embedded Memory

AC Characteristics

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Package Information

Figure 27: SO8W 208 mils Body Width

0.1 MAX

1.70 MIN/

1.91 MAX 1.78 MIN/

2.16 MAX 0.15 MIN/

0.25 MAX

5.08 MIN/

5.49 MAX

5.08 MIN/

5.49 MAX

0.5 MIN/

0.8 MAX

0.05 MIN/

0.25 MAX 0º MIN/

10º MAX

7.70 MIN/

8.10 MAX

0.36 MIN/

0.48 MAX

1.27 TYP

Note: 1. Drawing is not to scale.

M25P10A Serial Flash Embedded Memory

Package Information

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Figure 28: VFQFPN8 (MLP8) 6mm x 5mm

12°

0.20 TYP

0 MIN/

0.05 MAX

5.75 TYP

Pin one

indicator 1.27

TYP

4 +0.30

-0.20

0.60 +0.15

-0.10

0.85 +0.15

-0.05

0.40 +0.08

-0.05

3.40 ±0.20

0.10 MAX/

0 MIN

6 TYP

4.75 TYP

0.05

5 TYP

0.65 TYP

0.10 C B

0.10 C A

0.15 C B

0.10 C A B

0.15 C A

Note: 1. Drawing is not to scale.

M25P10A Serial Flash Embedded Memory

Package Information

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Figure 29: UFDFPN8 (MLP8) 2mm x 3mm

0.55 -0.10

+0.05

0.25 -0.05

+0.05

0.02 -0.02

+0.03

0.50 TYP

0.15 MAX

0.30 MIN

0.08 MAX

2.00 -0.10

+0.10

1.60 -0.10

+0.10

3.00 -0.10

+0.10 0.20 -0.10

+0.10

0.45 -0.05

+0.05

Note: 1. Drawing is not to scale.

M25P10A Serial Flash Embedded Memory

Package Information

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Device Ordering Information

Standard Parts

Micron Serial NOR Flash devices are available in different configurations and densities.

Valid part numbers are at Micron’s part catalog (www.micron.com), and feature and

specification comparisons are at www.micron.com/products. Contact your sales repre-

sentative for devices not found.

For more information on how to identify products and top side marking by the process

identification letter, refer to technical note, TN-12-24: Serial Flash Memory Device

Marking for the M25P, M25PE, M45PE,M25PX, and N25Q Product Families.

Micron recommends the use of the automotive grade device in the automotive environ-

ment, autograde 6 and grade 3. The high reliability certified flow (HRCF) is described in

the quality note QNEE9801. Ask your Micron sales office for a copy. For further informa-

tion on line items not listed here or on any aspect of this device, contact your nearest

representative.

Table 19: Part Number Information Scheme

Part Number

Category Category Details Notes

Device type M25P = Serial Flash memory for code storage

Density 10-A = 1Mb (128Kb x 8)

Operating voltage V = VCC = 2.3V to 3.6V

Package MN = SO8N (150 mils width)

MP = VFQFPN8 6mm x 5mm (MLP8)

Device Grade 6 = Industrial temperature range: –40°C to 85°C. Device tested with standard test flow. 1

Packing Option – = Standard packing

T = Tape and reel packing

Plating technology P or G = RoHS-compliant

Lithography /Y TY redesigned 1

Note: 1. Exposed pad of 3mm x 3mm.

Note: The category of second Level Interconnect is marked on the package and on the

inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings re-

lated to soldering conditions are also marked on the inner box label.

M25P10A Serial Flash Embedded Memory

Device Ordering Information

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Automotive Parts

Table 20: Part Number Information Scheme

Part Number

Category Category Details Notes

Device type M25P = Serial Flash memory for code storage

Density 10-A = 1Mb (128Kb x 8)

Operating voltage V = VCC = 2.7V to 3.6V

Package MN = SO8N (150 mils width)

MB = UFDFN8 (2mm x 3mm)

Device Grade 6 = Industrial temperature range: –40°C to 85°C. Device tested with high reliability test

flow.

3 = Automotive temperature range: –40°C to 125°C. Device tested with high reliability

test flow.

Packing Option – = Standard packing

T = Tape and reel packing

Plating technology P or G = RoHS-compliant 2

Lithography Y = T7Y, 150nm technology (option available only with Device Grade Option = 6)

/Y = T7Y, 150nm technology (option available only with Device Grade Option = 3) Fab 13

diffusion plant

Automotive Grade A = Automotive: –40°C to 85°C part. Only with temperature grade 6. Device tested with

high reliability test flow.

– = Automotive: –40°C to 125°C.

Notes: 1. Micron recommends the use of the automotive grade device in the automotive environ-

ment, autograde 6 and grade 3.

2. Contact your Micron sales representative for available options.

M25P10A Serial Flash Embedded Memory

Device Ordering Information

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Revision History

Rev. A – 05/2013

• Initial Micron rebrand.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

M25P10A Serial Flash Embedded Memory

Revision History

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