User Guide Rev. 1.02 / November 2012 ZSPM8010-KIT Open-Loop Evaluation Board For Evaluation of the ZSPM9010 High-Performance DrMOS Power and Precision ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 Restrictions: Zentrum Mikroelektronik Dresden AG's ZSPM8010-KIT Open-Loop Evaluation Board is designed for evaluation of the ZSPM9010, laboratory setup, and module development only. The Evaluation Board must not be used for module production and production test setups. Zentrum Mikroelektronik Dresden AG (ZMD AG, ZMDI) shall not be liable for any damages arising out of defects resulting from (i) delivered hardware (ii) non-observance of instructions contained in this manual, or (iii) misuse, abuse, use under abnormal conditions or alteration by anyone other than ZMD AG. To the extent permitted by law, ZMD AG hereby expressly disclaims and User expressly waives any and all warranties, whether express, implied, or statutory, including, without limitation, implied warranties of merchantability and of fitness for a particular purpose, statutory warranty of non-infringement and any other warranty that may arise by reason of usage of trade, custom, or course of dealing. ! Important Safety Reminder: These procedures can result in high currents, which can cause severe injury or death and/or equipment damage. Only trained professional staff should connect external equipment and operate the software. For more information, contact ZMDI via SPM@zmdi.com. Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 2 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 Contents 1 Introduction ...........................................................................................................................5 1.1. ZSPM8010-KIT Open-Loop Evaluation Board Overview ................................................5 2 Evaluation Board Description ...............................................................................................7 2.1. User-Selected Input and Output Capacitors....................................................................9 2.2. Recommended Values for Key Passive Components ................................................... 10 3 Test Setup and Procedure .................................................................................................. 11 3.1. Test Setup..................................................................................................................... 11 3.2. Evaluation Board Setup and Evaluation Procedures .................................................... 13 3.3. Evaluation Board Operation and Part Description ......................................................... 15 3.3.1. SMOD# Operation ................................................................................................... 15 3.3.2. Filter Resistor R4 between VDRV and VCIN ........................................................... 15 3.3.3. Decoupling Capacitors C3 and C1 on VDRV and VCIN .......................................... 16 3.3.4. Bootstrap Capacitor C5 and Series Bootstrap Resistor R9 ..................................... 16 3.3.5. Resistor R8 between the PHASE Pin and VSWH Node .......................................... 16 3.3.6. Resistor R7 Open Footprint (Not Applicable to the ZSPM9010) .............................. 17 3.3.7. Pull-up Resistor R1 from SMOD# to VCIN .............................................................. 17 3.3.8. Pull-up Resistor R6 from DISB# to VCIN ................................................................. 17 3.3.9. Pull-up Resistor R12 from THWN# to VCIN ............................................................ 17 3.3.10. Resistor R11 between DISB# and THWN# ............................................................. 17 3.3.11. R2 Pull-up and R5 Pull-down Resistors on PWM .................................................... 18 3.3.12. RC Snubber Components R13 and C34.................................................................. 18 3.3.13. RC Filter Components R14, C42, and C43 .............................................................. 18 4 Evaluation Board Performance ........................................................................................... 19 4.1. Efficiency and Power Loss Calculation ......................................................................... 19 4.2. Efficiency and Power Loss Measurement ..................................................................... 20 4.3. Switching Waveform Measurements ............................................................................. 21 5 Evaluation Board Bill of Materials ....................................................................................... 22 Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 3 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 6 Related Documents ............................................................................................................ 23 7 Definitions of Acronyms ...................................................................................................... 24 8 Document Revision History ................................................................................................ 24 Appendix A: ZSPM8010-KIT Physical Specifications and Layout............................................. 25 Appendix B: ZSPM8010-KIT Open-Loop Evaluation Board Schematic .................................... 29 List of Figures Figure 1.1 Figure 2.1 Figure 4.1 Figure 4.2 Figure 4.3 ZSPM8010-KIT Open-Loop Evaluation Board - Top View .................................................................. 5 Bottom View of the ZSPM8010-KIT Open-Loop Evaluation Board Showing Capacitor Footprints ..... 9 Circuit Diagram for Power Loss Measurement .................................................................................... 19 Efficiency and Power Loss vs. IOUT ...................................................................................................... 20 Switching Waveform ............................................................................................................................ 21 List of Tables Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.5 Table 3.1 Table 4.1 Table 5.1 ZSPM8010-KIT Open-Loop Evaluation Board Electrical Specifications ............................................... 7 ZSPM8010-KIT Open-Loop Evaluation Board Jumper Descriptions .................................................... 7 ZSPM8010-KIT Open-Loop Evaluation Board Test Point Descriptions ................................................ 8 J18 Efficiency Port Jumper Settings ...................................................................................................... 8 Key Component Values and Power Supply Configuration .................................................................. 10 Recommended Test Equipment .......................................................................................................... 12 Efficiency Test Conditions ................................................................................................................... 20 Bill of Materials..................................................................................................................................... 22 Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 4 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 1 Introduction 1.1. ZSPM8010-KIT Open-Loop Evaluation Board Overview The ZSPM8010-KIT single-phase open-loop evaluation board is a design platform providing the minimum circuitry needed to characterize critical performance of the ZSPM9010, a 6x6 mm DrMOS driver plus MOSFET multi-chip module. The scope of this user guide includes using the ZSPM8010-KIT Evaluation Board for internal testing as a reference and for customer support. See section 3.1 for the test equipment needed for the evaluation. Note: The ZSPM8000-KIT Evaluation Kit is an example of an application for the ZSPM9010. It can be used to evaluate the features of the ZSPM9010 in a closed loop configuration with the ZSPM1000 digital single-phase PWM controller. This document provides details of the construction of the ZSPM8010-KIT as a guide for modifying the Evaluation Board as needed for the user's specific application. ZSPM8010-KIT Open-Loop Evaluation Board - Top View Figure 1.1 VDRV Terminal J2 VCIN Terminal J1 Efficiency Port J18 SMOD# Jumper CON1 SMOD# Connector J7 DISB# Jumper SW1 PWM Connector J8 VIN Terminal J13 VOUT Terminal J14 Input Capacitors Output Capacitors GND Terminal J15 ZSPM9010 GND Terminal J16 Output Inductor L1 Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 5 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 The ZSPM9010 DrMOS device is a fully optimized integrated driver plus MOSFET power stage solution for high-current synchronous buck DC-DC applications. The device integrates a driver IC and two power MOSFETs in a space-saving, 6x6mm, 40-pin PQFN package. This integrated approach optimizes the complete switching power stage for the driver and MOSFET in terms of dynamic performance, system inductance and the power MOSFET's on-resistance. Package parasitic and layout issues associated with conventional fully discrete solutions are greatly reduced. This integrated approach results in a significant reduction of board space, maximizing footprint power density. The ZSPM9010 solution is based on the IntelTM DrMOS 4.0 specification. Key Features of the ZSPM9010 Ultra-compact 6x6 mm PQFN, 72% space saving compared to conventional full discrete solutions Fully optimized system efficiency: > 93 peak Clean switching waveforms with minimal ringing High current handling: up to 50A High performance PQFN copper clip package Tri-state 3.3V PWM input driver Skip Mode SMOD# (low side gate turn off) input Thermal warning flag for over-temperature conditions Driver output disable function (DISB# pin) Internal pull-up and pull-down for SMOD# and DISB# inputs, respectively Integrated Schottky diode technology in low side MOSFET Integrated bootstrap Schottky diode Adaptive gate drive timing for shoot-through protection Under voltage lockout (UVLO) Optimized for switching frequencies up to 1 MHz Based on the Intel(R) 4.0 DrMOS standard Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 6 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 2 Evaluation Board Description The ZSPM8010-KIT Open-Loop Evaluation Board is designed to demonstrate the optimized small size, high-efficiency performance of the ZSPM9010 DrMOS multi-chip module. The board is a high density, high-efficiency design, with a 1 MHz operating frequency and peak efficiency of over 92% with a 1.0V Vout condition. This board also demonstrates the ease of layout for printed circuit board artwork. The board was designed as an open-loop control to have only common passive components in a synchronous buck converter without a PWM controller. The open-loop control method is more reliable and flexible allowing performance testing with identical conditions. Since the ZSPM9010 pin map is industry standard, it is easy to compare its performance to other DrMOS devices without changing other components. See Appendix B for the schematic for the Evaluation Board. See Appendix A for the Evaluation Board's physical specifications and layouts for the individual layers of the circuit board. Table 2.1 ZSPM8010-KIT Open-Loop Evaluation Board Electrical Specifications Parameter Description Notes Switching Device ZSPM9010 PWM Control 0~100% duty by pulse generator Open-loop control VIN for Main DC/DC 12V DC typical Set by power supply 1 VDRV for MOSFET Driving 5V DC typical Set by power supply 2 VCIN for Gate Driver Vcc 5V DC typical Set by power supply 3 or power supply 2 depending on configuration (see section 2.2) VOUT PWM duty cycle Set by pulse generator fSW PWM switching frequency Set by pulse generator Max. Iout Maximum current handled by the ZSPM9010 (See ZSPM9010 for details) Set by electronic load Table 2.2 ZSPM8010-KIT Open-Loop Evaluation Board Jumper Descriptions Jumper Name Pin 1-2 Short Pin 2-3 Short Notes SW1 DISB# LO HI The ZSPM9010 is enabled when the SW1 DISB# jumper position = HI CON1 SMOD# LO HI SMOD is enabled when the SMOD# jumper position = LO Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 7 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 Table 2.3 ZSPM8010-KIT Open-Loop Evaluation Board Test Point Descriptions Test Point Test Point Name Notes TP5 VDRV VDRV test point (pin 3 on the ZSPM9010) TP6 VCIN VCIN test point (pin 2 on the ZSPM9010) TP9 DISB# DISB# test point (pin 39 on the ZSPM9010) TP14 THWN# TP12 GH GH test point (pin 6 on the ZSPM9010) TP1 PH2 PH2 net test point TP11 PHASE PHASE test point (pin 7 on the ZSPM9010) TP3 BOOT BOOT test point (pin 4 on the ZSPM9010) TP7 SMOD# SMOD# test point (pin 1 on the ZSPM9010) TP4 PWM PWM test point (pin 40 on the ZSPM9010) TP20 GL TP19 VSWH THWN# test point (pin 38 on the ZSPM9010) GL test point (pin 36 on the ZSPM9010) VSWH test point (pins 15, 29 to 35, and 43 on the ZSPM9010) Table 2.4 J18 Efficiency Port Jumper Settings Jumper Pin Jumper Name 2-1 VIN-GND 4-3 VDRV-GND Pin 4 and 3 are connected to C3 positive and negative pads by a differential pair. 6-5 VCIN-GND Pin 6 and 5 are connected to the C1 positive and negative pads by a differential pair. 8-7 VSW-GND Pin 8 is connected to the C42 positive pad. Pin 7 is connected to the R16 positive pad. 10-9 VOUT-GND Pin 10 and 9 are connected to the C24 positive and negative pads by a differential pair. Kit Description November 19, 2012 Notes Pin 2 and 1 are connected to the C41 positive and negative pads by a differential pair. (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 8 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 2.1. User-Selected Input and Output Capacitors The top side of the Evaluation Board has multiple unpopulated footprints for the user to add input and output capacitors as shown in Figure 1.1. For input capacitors, the board can accommodate up to six 1210-size ceramic capacitors or up to two 10x10 mm SMT-type OSCONTM*. C41 is a size 0603 ceramic capacitor used to reduce noise on VIN. For output capacitors, up to eight 1210-sized ceramic capacitors or up to two 10x10 mm SMTtype OS-CONTM can be placed on the top side. On the bottom side of the board, up to four 7x4 mm POSCAPTM* can be placed in each set of footprints for the input and output capacitors as shown in Figure 2.1. All three types of capacitors (ceramic, OS-CONTM and POSCAPTM) can be placed on the top side VIN-GND and VOUT-GND coppers to support various test requirements. Figure 2.1 Bottom View of the ZSPM8010-KIT Open-Loop Evaluation Board Showing Capacitor Footprints Filter Resistor R4 Output Capacitors POSCAPTM Input Capacitors POSCAPTM * OS-CONTM and POSCAPTM are trademarks of Sanyo, Inc. Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 9 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 2.2. Recommended Values for Key Passive Components Table 2.5 provides the recommended values for key passive components on the ZSPM8010KIT Open-Loop Evaluation Board for the ZSPM9010 for the two alternatives for the power supply setup: either using a shared power supply for VDRV and VCIN or using separate power supplies. The VDRV and VCIN columns give the voltage required from the supplies. See Table 3.1 regarding the effect of filter resistor R4, located on the bottom of the board as shown in Figure 2.1. The Evaluation Board is delivered with component values for the shared power supply. Table 2.5 Key Component Values and Power Supply Configuration Power Supply Setup Shared power supply for VDRV and VCIN Separate power supplies for VDRV and VCIN Kit Description November 19, 2012 R4 R7 C3 C1 VDRV VCIN 0 Open 1F N/A 5V NC Open Open 1F 1F 5V 5V (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 10 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 3 Test Setup and Procedure 3.1. Test Setup The following equipment is recommended for the using the Evaluation Board to test/evaluate the ZSPM9010. Efficiency Measurements: Power supply 1 for VIN and IIN rated for at least 20V / 10A. Power supply 2 for VDRV and IDRV; rated for at least 10V / 5A. Optional power supply 3 for VCIN and ICIN rated for at least 10V / 5A. Typically VCIN and ICIN can be shared with VDRV and IDRV from power supply 2 instead of using a third power supply. Pulse generator for PWM pulse signaling. Electronic load rated for 3V / 60A. Precise voltmeter to measure input and output voltage. Precise current sense resistors in series with each power rail to measure input and output currents. See Table 3.1 for recommended values. Recommendation: For efficiency measurements, use precise current sense resistors in series with the input and output power rails. Some vendors offer high-current, highprecision shunt resistors that perform well in this application. They are designed and calibrated at the factory to have a standard accuracy of 0.25 %. Waveform Measurements: Power supply 1 for VIN and IIN; rated for at least 20V / 10A. Power supply 2 for VDRV and IDRV; rated for at least 10V / 5A. Optional power supply 3 for VCIN and ICIN; rated for at least 10V / 5A. Typically VCIN and ICIN can be shared with VDRV and IDRV from power supply 2 instead of using a third power supply. Pulse generator for PWM pulse signaling. Electronic load; rated for 3 V / 60 A. Precise voltmeter to measure input and output voltage. Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 11 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 Four-channel oscilloscope; bandwidth (BW) of at least 1GHz. For measuring fast-switching waveforms such as VSWH, an active differential probe provides the best accuracy. It should be rated for at least 25V differential input and a BW of at least 500MHz. A standard single-ended probe with a BW of at least 500 MHz will also provide acceptable results. The output cables for the board must be made with large gauge wire to ensure that they do not cause excessive heating of the board by copper loss. In a normal test setup, use two parallel audio cables with 8 gauge thickness for the maximum 60A output current. Cables must be clamped to the board with large cross-section connectors. An alternative connector arrangement would be to use large ring or spade terminals attached to the ends of the cables. The cables should then be firmly bolted to the board. Table 3.1 Recommended Test Equipment Equipment Type Power Supply 1 Name Notes Agilent E3633A Power Supply 2 Agilent E3648A Power Supply 3 Power Supply 2 is connected to VDRV. The 0~10 R4 filter resistor can be placed between VDRV and VCIN to supply VCIN power so that Power Supply 3 is not needed. Pulse Generator Agilent 81101A Electronic Load Chroma 6312/63106 High-current electronic load Voltmeter Agilent 34970A Multi-channel DMM or data logger Current Sense Resistor Deltec 1m / 20A for IIN 50m / 5A for IDRV and ICIN 0.25m / 100A for IOUT Oscilloscope Tektronix DPO7104 Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 12 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 3.2. Evaluation Board Setup and Evaluation Procedures Use the following procedures when operating the ZSPM8010-KIT Open-Loop Evaluation Board. For this example setup, power supply 2 provides both VDRV and VCIN (see Table 2.5) and a PWM pulse generator is used to control VOUT. Operating Conditions VIN for main conversion: 12V typical VDRV for gate driving power and VCIN for gate driver logic: 5 V typical VOUT for output load: 1V typical (set by PWM duty cycle from pulse generator) PWM pulse: 5V high and 0V low, 300 kHz f SW, 10% duty cycle (depending on VOUT), 50 output impedance (R5 pull-down resistor on board should be the same value, 50 = typical value on delivery) Operating Procedures Important: During the following procedures, do not turn on the power supplies until indicated in the steps. 1. On the Evaluation Board, ensure that the DISB# jumper (SW1) is at the LO position (1-2 short). 2. Ensure that the SMOD# jumper (CON1) is at the HI position (2-3 short). 3. Ensure that the filter resistor (R4, 0~10 ) is connected on the bottom of the board between the VDRV and VCIN pins (see Figure 2.1). 4. Connect the electronic load to the J14 VOUT and J16 PGND terminals. 5. Connect power supply 1 to the J13 VIN and J15 PGND terminals. 6. Connect power supply 2 to the J2 VDRV (and GND) connector. 7. Connect the pulse generator to the J8 PWM connector. 8. Connect the data logger to the J18 Efficiency Port connector if needed. 9. Set the pulse generator for high and low levels (5V and 0V respectively), f SW (300 kHz), duty cycle (10%), output impedance (50), and other requirements. 10. Connect oscilloscope channels and probes to the desired voltage nodes; for example, CH1 PWM, CH2 GH, CH3 VSWH, and CH4 GL. See Table 2.3 for descriptions of the test points. Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 13 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 Important: Ensure that probes for voltage measurements are in place before powering up the board in step 18 and ensure that probes do not create any unwanted shorts since the board has very thin traces and sensitive noise immunity. If a short situation occurs, the board could malfunction or be damaged. 11. Set oscilloscope channels to appropriate voltage and time divisions. 12. Set the power supply 1 output voltage and current: 12V / 10A typical. 13. Set the power supply 2 output voltage and current: 5V / 1A typical. 14. Set the electronic load operating mode and current level: CC (Constant Current) / 1A typical. 15. Turn on the pulse generator to supply pulses into the PWM connector on board. 16. Turn on power supply 1. Check the 12V at the VIN terminal (across J13 and J15) and the VIN pins (2-1) on the J18 Efficiency Port. Check that no voltage is present on the VOUT terminal (across J14 and J16) or the VOUT pins 10-9 on the J18 Efficiency Port. 17. Turn on power supply 2. Check the 5V at the VDRV connector (J2) and across the VDRV pins (4-3) and VCIN pins (6-5) on the J18 Efficiency Port. Check that no voltage is present on the VSW pins (8-7) of the J18 Efficiency Port. Check that no voltage is present on the VOUT terminal (across J14 and J16) or the VOUT pins (10-9) on the J18 Efficiency Port. Check for 5V pulses at the PWM test point (TP4 PWM). 18. Turn on the Evaluation Board by setting the SW1 jumper on the HI (2-3) position. The board will turn on and all switching waveforms will appear on the oscilloscope. 19. Check that all input and output voltages and currents show proper values. 20. Apply the desired value for load current by setting the electronic load; for example, 1 to 10A for light loads, 10 to 20A for medium loads, or >30A for heavy loads. 21. Set all user-definable parameters such as VIN, VDRV/VCIN, fsw, VOUT, and IOUT as needed to test the board with various conditions. Since the ZSPM9010 does not have a specific power sequence for VIN, VDRV, VCIN, DISB#, and PWM, it is possible to turn on the board with any power-up sequence. However, to get proper operation and to avoid sudden extreme conditions caused by user errors, using the power up sequence mentioned above is recommended. Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 14 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 3.3. Evaluation Board Operation and Part Description This section describes the Evaluation Board operation and components. 3.3.1. SMOD# Operation When the SMOD# jumper (CON1) is set to the HI position, the board operates as a synchronous buck converter. In this mode, the internal low-side MOSFET of the ZSPM9010 is turning on and off according to the PWM signal. The power stage operates in Continuous Conduction Mode (CCM), allowing the inductor current to go negative if there are low output current values. When the SMOD# jumper (CON1) is set LOW, the Skip Mode is activated and the board operates as an asynchronous buck converter. In this operating mode, the low-side MOSFET of the ZSPM9010 is always off, so the low-side MOSFET free-wheeling current is flowing through the low-side MOSFET body diode when the inductor current is positive, but it is blocked when the inductor current would have gone negative. This prevents discharge of the output capacitors by preventing reversal of the current flow through the inductor. Diode emulation is performed via the SMOD# connector (J7 SMOD#): this connector is intended to supply a separate, dedicated, cycle-by-cycle-based SMOD signal to turn on the low-side MOSFET when the inductor current is positive, while turning off the low-side MOSFET when the inductor current would have gone negative. The SMOD signal input on the SMOD# connector should be synchronized with the PWM signal to guarantee precise gate signaling for the high-side and low-side MOSFETs. The SMOD# feature is designed for the ZSPM9010. 3.3.2. Filter Resistor R4 between VDRV and VCIN The R4 filter resistor is located on the bottom of the board across the VDRV and VCIN pins of the ZSPM9010. The VDRV pin is connected to an internal boot diode to supply the gate driving voltage. VCIN is connected to the supply voltage of the logic circuitry (VCC) of the gate driver. In normal applications, both power rails are connected together and can be powered by a single 5V power rail. Situations such as improper supply of VDRV and VCIN, defective/ incorrect decoupling capacitors placed on the VDRV and VCIN pins, or poor board layout design can result in higher noise on the VCIN pin, which could cause gate driver malfunction or damage. The resistor R4 placed between VDRV and VCIN is therefore intended to reduce the noise level on the VCIN pin. The typical value for normal applications is 0 . Recommended range of values is 0~10 . Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 15 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 3.3.3. Decoupling Capacitors C3 and C1 on VDRV and VCIN The C3 and C1 decoupling capacitors for VDRV and VCIN are located on the top side of the board. The typical value for the C3 ceramic decoupling capacitor on the VDRV pin is 1F / 10V / 0603 / X5R or better. Decoupling capacitors with a smaller size (e.g., 0402) or an inadequate temperature characteristic (e.g., Y5V) on the VDRV pin can degrade board dynamic performance. In general, the VCIN pin does not consume as much power as the VDRV pin. A decoupling capacitor with the same values as for the VDRV pin (1F / 10V / 0603 / X5R or better) or with a larger physical size and X5R or better temperature characteristic is recommended for the VCIN pin. When R4 is used, the decoupling capacitor on the VCIN pin can be removed; however, the user must select the correct values for R4 and for the decoupling capacitor C3 using the experimental results obtained for the testing conditions. 3.3.4. Bootstrap Capacitor C5 and Series Bootstrap Resistor R9 The C5 bootstrap capacitor and R9 series bootstrap resistor are located on the top side of the board. The typical value for the C5 ceramic bootstrap capacitor on the BOOT pin is 0.1F / 50V / 0603 / X5R or better in terms of physical size and temperature characteristic. The bootstrap resistor R9 is connected between the C5 bootstrap capacitor and the PHASE pin. Its value can be changed to reduce the high-side MOSFET switching speed. Due to EMI issues, many users use the bootstrap resistor to reduce VSWH spikes and ringing. However, the bootstrap resistor can decrease system efficiency while increasing high-side MOSFET switching loss. The value on delivery for R9 is 0 on the Evaluation Board. The typical range for normal applications is 0~5 . 3.3.5. Resistor R8 between the PHASE Pin and VSWH Node The R8 resistor is located on the bottom of the board between the PHASE pin (via R9) and the VSWH node (pins 15, 29 to 35, and 43 on the ZSPM9010). The PHASE pin and VSWH node of the ZSPM9010 are connected together via internal bonding wire. To increase noise immunity of the gate driver under extreme conditions, this 0 resistor is placed between the PHASE pin and VSWH copper trace. This resistor is in parallel with the internal bonding wire, so it helps reduce noise spikes on the VSWH node. The recommended value for R8 is 0. R8 values greater than 0 will lead to degradation of the noise immunity for the gate driver. This resistor can be removed if the board layout is well-designed so that parasitic noise from spikes on VSWH is minimal. Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 16 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 3.3.6. Resistor R7 Open Footprint (Not Applicable to the ZSPM9010) Important: Do not use R7 with the ZSPM9010 (unpopulated footprint for R7 is located on the top of the board between VIN and VDRV). It is only applicable to the ZSPM9000, which is a related product. 3.3.7. Pull-up Resistor R1 from SMOD# to VCIN The R1 pull-up resistor is located on the top side of the Evaluation Board between VCIN and the ZSPM9010's SMOD# pin via the SMOD# jumper CON1. This 10k pull-up resistor is used on the SMOD# pin to ensure the 5V HIGH level on the SMOD# pin. The value can be changed; however, a minimum of 10k is recommended. 3.3.8. Pull-up Resistor R6 from DISB# to VCIN The R6 pull-up resistor is located on the top side of the board from VCIN to the ZSPM9010's DISB# pin via the DISB# jumper SW1. This 10k pull-up resistor is used on the DISB# pin to ensure the 5V HIGH level on the DISB# pin. The value can be changed; however, a minimum of 10k is recommended. 3.3.9. Pull-up Resistor R12 from THWN# to VCIN The R12 pull-up resistor is located on the top side of the board from the ZSPM9010's THWN# pin to VCIN. The purpose of the THWN# pin is to go LOW indicating the over-temperature warning flag if the temperature of the gate driver is too high. The THWN# pin is an open-drain output. When the gate driver temperature is lower than 150C, the THWN# pin will remain HIGH via the R12 pull-up resistor. If the gate driver temperature rises to 150C or higher, the THWN# pin will be set LOW. A minimum value of 10k for R12 is recommended. 3.3.10. Resistor R11 between DISB# and THWN# The R11 resistor is located on the top side of the board between the ZSPM9010's DISB# and THWN# pins. This 0 resistor can be used to shut down the ZSPM9010 when the THWN# flag is set LOW due to an over-temperature condition. If THWN# is set LOW due to the gate driver temperature rising to 150C or higher, the DISB# pin will be set LOW via R11 and the ZSPM9010 will shut down. When the gate driver has cooled to 135C or lower, the THWN# pin will reset to HIGH so DISB# will also reset to HIGH. In this case, the ZSPM9010 will turn on again. The recommended value for R11 is 0. Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 17 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 3.3.11. R2 Pull-up and R5 Pull-down Resistors on PWM The R2 pull-up and R5 pull-down resistors are located on the top side of the board on the ZSPM9010's PWM pin (adjacent to the J8 PWM connector). The ZSPM9010's PWM pin supports three different logic levels: logic HIGH level, logic LOW level, and a tri-state open voltage window. The R2 pull-up and R5 pull-down resistors can be used to match the PWM open voltage from the pulse generator to the ZSPM9010 and to match the output impedance of the pulse generator to the impedance of the PWM pin. Default values: R2 = open and R5 = 50. 3.3.12. RC Snubber Components R13 and C34 The R13 resistor and C34 capacitor are located on the bottom of the board. The RC snubber for reducing VSWH spikes and ringing comprises R13 and C34. Their values can be calculated based on snubber theory for the operating conditions of the board. Typical values are R13=2.2 and C34=1nF. Recommended range of values are 0 to 3.3 for R13 and 0 to 2.2nF for C34. 3.3.13. RC Filter Components R14, C42, and C43 R14, C42, and C43 are located on the top side of the board. The default condition of the board is that R14=0 and C42 and C43 are not populated. In this condition, there is no RC filtering for the VSWH voltage. An RC filter can be added to change the VSWH AC voltage to a VSWH DC voltage by replacing R14 with a resistor value >0 and adding C42, and C43. Typical values are R14=10k, C42 =10nF, and C43 =10nF. The filtered VSWH DC voltage can be used to measure DC voltage on the VSWH node. This information can be used to calculate the power loss at the VSWH node. Note that some low-end voltmeters or digital multimeters cannot measure the correct DC value of the VSWH node, leading to an incorrect power loss computation and therefore an incorrect efficiency result. Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 18 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 4 Evaluation Board Performance 4.1. Efficiency and Power Loss Calculation For power loss and efficiency calculations, refer to the equations below and Figure 4.1. PIN _ TOT PIN PDRV VIN IIN VDRV IDRV (Watts) (1) POUT VOUT IOUT (Watts) (2) PLOSS PIN_TOT - POUT (Watts) (3) Efficiency POUT POUT x100% x100% PIN PDVR PIN _ TOT (4) Figure 4.1 Circuit Diagram for Power Loss Measurement SMOD# DISB# PWM Input IDRV VDRV PWM A DISB# VDRV CDRV A VIN CGND Analog GND November 19, 2012 CBOOT L PHASE CIN Kit Description BOOT ZSPM9010 IIN VIN SMOD# A VSWH PGND IOUT V VSW VOUT COUT Power GND (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 19 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 4.2. Efficiency and Power Loss Measurement Table 4.1 shows an example of test setup parameters for efficiency and power loss measurements. Table 4.1 Efficiency Test Conditions VIN VDRV / VCIN VOUT FSW Inductor IOUT Cooling 12V 5V 1V 300kHz 320nH 0~45A, 5A step, 3 minute soaking No Figure 4.2 shows the measured and calculated efficiency and power loss of the ZSPM8010KIT Open-Loop Evaluation Board with the test conditions above. Figure 4.2 Efficiency and Power Loss vs. IOUT Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 20 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 4.3. Switching Waveform Measurements Figure 4.3 illustrates a switching waveform example. Figure 4.3 Switching Waveform Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 21 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 5 Evaluation Board Bill of Materials Table 5.1 shows the complete bill of materials for the ZSPM8010-KIT Open-Loop Evaluation Board. Also see the schematic given in Appendix A. Table 5.1 Bill of Materials Qty Reference Value Size Remark 2 CON1, SW1 3P (1x3) header 1 J1 2P (1x2) header 1 J2 2P (1x2) header 1 J18 10P (2x5) header 2 J7, J8 4 J13, J14, J15, J16 1 U1 ZSPM9010 6 x 6 mm 1 L1 180 nH 10 x 12 mm Pulse PA2202.181NL 1 C1 1F / 10V 0603 MLCC, X5R. OPTION 1 C3 1F / 10V 0603 MLCC, X5R 1 C2 33F / 25V 7 x 4 mm POSCAPTMTM, OPTION 1 C35 33F / 25V 7 x 4 mm POSCAPTM 4 C6, C7, C8, C9 33F / 25V 7 x 4 mm POSCAPTM, OPTION 2 C4, C11 10nF / 50V 0603 MLCC, X5R, OPTION 10nF / 50V (Default is open.) 0603 MLCC, X5R, OPTION Note: If C42 and C43 are added to create an RC filter on VSWH, replace R14 with a value >0; typical = 10k. See section 3.3.13. Optional RF connector Mini BNC Terminal BR-113 DrMOS 2 C42, C43 1 C34 1nF/ 50V 0603 MLCC, X5R, OPTION 1 C5 0.1F / 50V 0603 MLCC, X5R 1 C41 0.1F / 50V 0603 MLCC, X5R. OPTION 2 C12, C13 330F / 16V 10 x 10 mm OS-CONTM, OPTION 2 C15, C16 22F / 25V 1210 MLCC, X5R, OPTION 4 C17, C18, C19, C20 22F / 25V 1210 MLCC, X5R 2 C21, C22 560F / 4V 10 x 10 mm Kit Description November 19, 2012 OS-CONTM, OPTION (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 22 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 Qty 6 Reference Value Size Remark 4 C24, C25, C26, C27 100F/ 6.3V 1206 MLCC, X5R 4 C28, C29, C39, C40 22 F / 6.3V 0805 MLCC, X5R 4 C30, C31, C32, C33 470F / 6.3V 7 x 4 mm 2 R1, R6 10k 0603 1 R12 10k 0603 OPTION Default value = 0 * 0603 * If adding an RC filter to the VSWH voltage, add C42 and C43 and replace R14 with >0; typical 10k. See section 3.3.13. Open 0603 OPTION POSCAPTM, OPTION 1 R14 3 R2, R7, R10 5 R3, R4, R8, R9, R16 0 0603 1 R11 0 0603 1 R5 49.9 0603 1 R13 2.2 0603 OPTION 1 R15 0 0603 OPTION OPTION Related Documents Note: X.xy represents the current version of the document. Documents Related to All Products File Name ZSPM9010 Data Sheet ZSPM9010_Data_Sheet_revX_xy.pdf ZSPM9010 Feature Sheet ZSPM9010_Feature_Sheet_revX_xy.pdf Visit ZMDI's website www.zmdi.com or contact your nearest sales office for the latest version of these documents. Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 23 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 7 Definitions of Acronyms Term Description DISB Driver Output Disable Function HS High Side LS Low Side NC No connection SMOD Skip Mode Input (low-side gate turn-off) 8 Document Revision History Revision Date Description 1.00 June 13, 2012 First release. 1.01 October 22, 2012 1.02 November 19, 2012 Revision of kit name and update of contact information. Identified default values for R14, C42, and C43 in Table 5.1 and clarified instructions for adding an RC filter to the output in section 3.3.13. Update of contact information. Sales and Further Information Zentrum Mikroelektronik Dresden AG Grenzstrasse 28 01109 Dresden Germany Phone +49.351.8822.7.776 Fax +49.351.8822.8.7776 ZMD America, Inc. 1525 McCarthy Blvd., #212 Milpitas, CA 95035-7453 USA Phone +855.275.9634 (USA) Phone +408.883.6310 Fax +408.883.6358 www.zmdi.com SPM@zmdi.com Zentrum Mikroelektronik Dresden AG, Japan Office 2nd Floor, Shinbashi Tokyu Bldg. 4-21-3, Shinbashi, Minato-ku Tokyo, 105-0004 Japan ZMD FAR EAST, Ltd. 3F, No. 51, Sec. 2, Keelung Road 11052 Taipei Taiwan Zentrum Mikroelektronik Dresden AG, Korea Office U-space 1 Building 11th Floor, Unit JA-1102 670 Sampyeong-dong Bundang-gu, Seongnam-si Gyeonggi-do, 463-400 Korea Phone +81.3.6895.7410 Fax +81.3.6895.7301 Phone +886.2.2377.8189 Fax +886.2.2377.8199 Phone +82.31.950.7679 Fax +82.504.841.3026 DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise. Kit Description November 19, 2012 (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 24 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 Appendix A: ZSPM8010-KIT Physical Specifications and Layout A.1 Evaluation Board Physical Specifications Figure A 1 shows the physical information for the individual layers of the board. The board's physical parameters are typical of values used for standard desktop and server motherboard design. Board size: 70 x 70 mm Copper layer count: 8 layer Board total thickness: 2.066mm Outer layer copper thickness: 1.5 oz (0.5 oz base + 1 oz plating) Inner layer copper thickness: 1 oz for IN1/IN2/IN5/IN6; 2 oz for IN3 and IN4 Via design rule: 0.25mm for drill hole, 0.4mm for pad diameter Figure A 1 ZSPM8010-KIT Open-Loop Evaluation Board Stack-up Structure 1 TOP (Sig/GND/PWR): 0.5oz base + 1oz plating, total 1.5oz, 0.053mm Prep 0.1mm IN1 (GND): 1oz , 0.035mm 2 Prep 0.2mm 3 IN2 (GND): 1oz, 0.035mm Prep 0.24mm IN3 (GND/PWR): 2oz, 0.07mm 4 Core 0.6mm 5 IN4 (GND/PWR): 2oz, 0.07mm Prep 0.24mm 6 IN5 (GND): 1oz, 0.035mm Prep 0.2mm IN6 (GND): 1oz, 0.035mm 7 Prep 0.1mm BOT (Sig/GND/PWR): 0.5oz base + 1oz plating, total 1.5oz, 0.053mm 8 Board total thickness: 2.066mm Kit Description November 19, 2012 Dielectric substance: prepreg / core (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 25 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 Figure A 2 Evaluation Board Layout Kit Description November 19, 2012 SST Layer SMT Layer TOP Layer IN1 Layer (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 26 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 Kit Description November 19, 2012 IN2 Layer IN3 Layer IN4 Layer IN5 Layer (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 27 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 Kit Description November 19, 2012 IN6 Layer BOT Layer SMB Layer SSB Layer (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 28 of 29 ZSPM8010-KIT Open-Loop Evaluation Board User Guide for Evaluating the ZSPM9010 Appendix B: ZSPM8010-KIT Open-Loop Evaluation Board Schematic 1 VCIN * * * * * * * * * * 0 Ohm Open NC 5V ZSPM9000 Open Open 5V 5V Open 0 Ohm NC NC TP19 VSWH Open Open NC 12V November 19, 2012 1 1 1 1 1 1 2 4 6 8 10 1 3 5 7 9 C24 VSW C43 VSW 10N/50V/0603/OPT C42 10N/50V/0603/OPT (c) 2012 Zentrum Mikroelektronik Dresden AG -- Rev. 1.02 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. + + C33 C28 C29 C39 BOTTOM PLACE C30 + 29 of 29 C32 C27 C31 + + + 1 2 3 4 5 C34 R14 10K/0603/OPT C26 100U/6.3V/1210 R13 C25 22U/6.3V/1206 C22 22U/6.3V/1206 C21 180nH/64A/0.48mO 100U/6.3V/1210 VSWH J16 PGND C40 22U/6.3V/1206 1 2 3 4 5 THWN# VOUT C5 and R9 are def ault Cboot and series Rboot R8 and R9 are placeholders f or Cboot negativ e pin connection to SW node To make thermal shutdown f unction by DISB# and THWN#, put a 0 Ohm on R11 J1,C1 and C2 are not needed when R4 is used ZSPM9000 has internal 5V LDO f or driv er VCC. LDO input is VDRV pin 3 and output is VCIN pin 2 R2 and R5 v alues depend on the pulse generator output impedance setting f or PWM/Tri-state lev el match R13 & C34 are optional R&C snubber R14 & C43 are optional R&C f ilter f or dif f erential v oltage measurement on Lout (L1) R14 & C42 are optional R&C f ilter f or VSWH DC measurement To measure VSWH AC v oltage at VSW on J18 EFFI PORT, put 0 Ohm at R14 & R16 Kit Description R16 J14 VOUT 470U/6.3V/OPT R4 R7 J1 VCIN J2 VDRV EFFI PORT TP14 THWN# 560U/4V/OPT 42 10 9 8 7 6 5 4 3 2 1 VIN42 VIN10 VIN9 NC PHASE GH CGND5 BOOT VDRV VCIN SMOD# 21 22 23 24 25 26 27 28 29 30 * Compatibility Table U1 ZSPM9010 VSWH R12 L1 1N/50V/0603/OPT J15 PGND 41 40 39 38 37 36 35 34 33 32 31 PGND21 PGND22 PGND23 PGND24 PGND25 PGND26 PGND27 PGND28 VSWH29 VSWH30 0.1U/25V/0603/OPT 22U/25V/1210 22U/25V/1210 22U/25V/1210 22U/25V/1210 CGND41 PWM DISB# THWN# CGND37 GL VSWH35 VSWH34 VSWH33 VSWH32 VSWH31 R11 470U/6.3V/OPT 33U/25V/OPT 33U/25V/OPT 33U/25V/OPT 33U/25V/OPT 22U/25V/1210/OPT 22U/25V/1210/OPT TP18 GND 1 2 3 4 5 330U/16V/OPT VSWH43 VIN11 VIN12 VIN13 VIN14 VSWH15 PGND16 PGND17 PGND18 PGND19 PGND20 0/0603/OPT VOUT 43 11 12 13 14 15 16 17 18 19 20 1/0603/OPT 330U/16V/OPT C41 R10 10K/0603/OPT C20 TP20 TP16 GL GND 0/0603/OPT C19 ZSPM9010 J18 10N/50V/0603/OPT OPEN/0603/OPT C18 U1 DISB# C17 VIN R15 0/0603 VIN GL C16 VCIN PWM 1 2 3 4 5 PHASE 10K/0603 SW1 DISB#/EN 3 2 1 C11 GND + C15 SMOD# + C13 VCIN C12 R8 GH + VDRV BOOT + TP11 TP12 PHASE GH 0/0603 R7 0/0603/OPT + R9 OPEN/0603/OPT + J13 VIN C9 R6 TP9 DISB# 470U/6.3V/OPT BOTTOM PLACE C8 1 49.9/0603 TP7 TP8 SMOD# GND 470U/6.3V/OPT TP5 TP6 VDRV VCIN C5 0.1U/50V/0603 C7 1 VCIN R5 22U/6.3V/1206 PH2 R3 R4 0/0603 0/0603 C6 J8 BNC FOR PWM 5 100U/6.3V/1210 VDRV OPEN/0603/OPT TP4 PWM 1 TP22 TP3 GND BOOT 1 TP2 GND VOUT VSW VCIN VDRV VIN TP1 PH2 2 3 4 33U/25V J6 SH2 J9 J10 J11 J12 FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL R2 1 + C35 1U/10V/0603 33U/25V J7 BNC FOR SMOD# 1 5 560U/4V/OPT + C2 1U/10V/0603 C4 10N/50V/0603/OPT J5 SH2 1 1 3 2 1 C3 2 3 4 C1 1 3 2 1 VCIN 1 2 1 2 R1 10K/0603 J4 SH2 1 J3 SH2 1 CON1 HEADER_3P VCIN 1 2 VDRV 1 2 VCIN J2 VDRV 100U/6.3V/1210 J1 VCIN Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: ZMDI: ZSPM8000KIT ZSPM8010KIT