LM49100
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SNAS392F –JUNE 2007–REVISED MAY 2013
LM49100 Mono Class AB Audio Sub-System with a True-
Ground Headphone Amplifier
Check for Samples: LM49100
1FEATURES APPLICATIONS
2• Mono and Stereo Inputs • Mobile Phones
• Thermal Overload Protection • PDAs
• True-Ground Headphone Drivers • Laptops
• I2C Control Interface • Portable Electronics
• Input Mute Attenuation DESCRIPTION
• 2nd Stage Headphone Attenuator The LM49100 is a fully integrated audio subsystem
• 32-Step Digital Volume Control capable of delivering 1.275W of continuous average
• 10 Operating Modes power into a mono 8Ωbridged-tied load (BTL) with
1% THD+N and with a 5V power supply. The
• Minimum External Components LM49100 also has a stereo true-ground headphone
• Click and Pop Suppression amplifier capable of 50mW per channel of continuous
• Micro-Power Shutdown average power into a 32Ωsingle-ended (SE) loads
with 1% THD+N.
• Available in Space-Saving 3mm x 3mm
25-Bump csBGA Package The LM49100 has three input channels. One pair of
• RF Suppression SE inputs can be used with a stereo signal. The other
input channel is fully differential and may be used
with a mono input signal. The LM49100 features a
KEY SPECIFICATIONS 32-step digital volume control and ten distinct output
• Power Output at VDD = 5V: modes. The mixer, volume control, and device mode
– Loudspeaker (LS): select are controlled through an I2C compatible
interface.
– RL = 8Ω, THD+N ≤: 1% 1.275W
– Headphone (VDDHP = 2.8V): Thermal overload protection prevent the device from
being damaged during fault conditions. Superior click
– RL = 32Ω, THD+N ≤1%: 50mW and pop suppression eliminates audible transients on
• Shutdown current 0.01μApower-up/down and during shutdown.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
0.1 PF
Mixer
and
Mode Select
Mono Input
-60 dB - +12 dB
Left Input
-54 dB - +18 dB
Right Input
-54 dB - +18 dB
I2C
Interface
Class AB
+6 dB
I2C
BUS
VIH
VIL
MIN+
MIN-
LIN
RIN
VDDI2C
SDA
SCL
ADDR GND
HPR
HPL
GND
LS
-
LS+
VDDLS
Audio
Input
Audio
Input
Audio
Input
VDDCP
Charge Pump
VSSHP VSSCP C1PC1N GNDCP
Bias
Click/Pop
Suppresion
BYPASS
0 dB
-12 dB
-18 dB
-24 dB
0 dB
-12 dB
-18 dB
-24 dB
CIN
CIN
CIN
CIN
+
AGND
VDDHP
VDDCP
4.7 PF
1 PF
1 PF
0.22 PF
0.22
PF
2.2 PF
C1
+
+
CAVSS
2.2 PF
VDDI2CCB
4.7 PF
CS1
4.7 PF
VDDLS
VDDLS
LM49100
SNAS392F –JUNE 2007–REVISED MAY 2013
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Typical Application
Figure 1. Typical Audio Amplifier Application Circuit
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VDDCP GNDCP MIN+BYPASS RIN
C1N C1P MIN-LIN LS-
VSSCP ADDRGND VDDLSVSSHP
HPL VDDHP VDDI2C SDA LS+
HPR VDDLS GNDAGND SCL
E
D
C
B
A
1 2 3 4 5
LM49100
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SNAS392F –JUNE 2007–REVISED MAY 2013
Connection Diagrams
Figure 2. Top View
25-Bump csBGA
3mm × 3mm × 1mm
See NYA0025A Package
BUMP DESCRIPTIONS
Bump Name Description
A1 VDDCP Positive Charge Pump Power Supply
A2 GNDCP Charge Pump Ground
A3 MIN+ Positive Mono Input
A4 BYPASS Half-Supply Bypass
A5 RIN Right Input
B1 C1N Negative Terminal – Charge Pump Flying
Capacitor
B2 C1P Positive Terminal – Charge Pump Flying
Capacitor
B3 MIN- Negative Mono Input
B4 LIN Left Input
B5 LS−Negative Loudspeaker Output
C1 VSSCP Negative Charge Pump Power Supply
C2 VSSHP Negative Headphone Power Supply
C3 GND Ground
C4 ADDR I2C Address Identification
C5 VDDLS Loudspeaker Power Supply
D1 HPL Left Headphone Output
D2 VDDHP Positive Headphone Power Supply
D3 VDDI2C I2C Power Supply
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BUMP DESCRIPTIONS (continued)
Bump Name Description
D4 SDA I2C Data
D5 LS+ Loudspeaker Output Positive
E1 HPR Right Headphone Output
E2 VDDLS Loudspeaker Power Supply
E3 AGND Headphone Signal Ground (See Application
Information section).
E4 GND Ground
E5 SCL I2C Clock
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)(3)
Supply Voltage (Loudspeaker) 6V
Supply Voltage (Headphone) 3V
Storage Temperature −65°C to +150°C
Input Voltage −0.3V to VDD + 0.3V
Power Dissipation (4) Internally Limited
ESD Susceptibility (5) 2000V
ESD Susceptibility (6) 200V
Junction Temperature 150°C
Thermal Resistance
θJA (GR) 50.2°C/W
(1) All voltages are measured with respect to the GND pin unless other wise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specify performance limits. This assumes that the device is within the Operating
Ratings. Specifications are not for parameters where no limit is given, however, the typical value is a good indication of device
performance.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA)/ θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM49100, see power derating currents for more information.
(5) Human body model, 100 pF discharged through a 1.5kΩresistor.
(6) Machine Model, 220pF - 240pF discharged through all pins.
Operating Ratings
Temperature Range
TMIN ≤TA≤TMAX −40°C ≤TA≤+85°C
Supply Voltage VDDLS 2.7V ≤VDDLS ≤5.5V
Supply Voltage VDDHP 2.4 V ≤VDDHP ≤2.9V
I2C Voltage (VDDI2C ) 1.7V ≤VDDI2C≤5.5V
VDDHP ≤VDDLS
VDDI2C≤VDDLS
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LM49100
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Electrical Characteristics VDDLS = 3.6V, VDDHP = 2.8V (1)(2)
The following specifications apply for all programmable gain set to 0 dB, CB= 4.7μF, RL (SP) = 8Ω, RL(HP) = 32Ω, f = 1 kHz
unless otherwise specified. Limits apply for TA= 25°C. LM49100 Units
Symbol Parameter Conditions Limit (Limits)
Typical (3) (4)
Modes 1, 3, 5 2.9 mA
VIN = 0V, No Load
VDDLS = 3.0V Modes 2, 4, 6 3.4 mA
VDDHP = 2.8V VIN = 0V, No Load
Modes 7, 10, 14 4.8 mA
VIN = 0V, No Load
Modes 1, 3, 5 2.9 4.3 mA (max)
VIN = 0V, No Load
VDDLS = 3.6V Modes 2, 4, 6
IDD Supply Current 3.5 5.4 mA (max)
VDDHP = 2.8V VIN = 0V, No Load
Modes 7, 10, 14 4.8 7.4 mA (max)
VIN = 0V, No Load
Modes 1, 3, 5 3.1 mA
VIN = 0V, No Load
VDDLS = 5.0V Modes 2, 4, 6 3.6 mA
VDDHP = 2.8V VIN = 0V, No Load
Modes 7, 10, 14 5.0 mA
VIN = 0V, No Load
ISD Shutdown Supply Current Mode 0 0.01 1 µA (max)
VIN = 0V, Mode 7, Mono 6.0 25 mV (max)
VIN = 0V, Mode 7, Headphone Gain = –24dB 2.2 5.5 mV
VOS Output Offset Voltage VIN = 0V, Mode 7, Headphone Gain = –18dB 2.4 mV (max)
VIN = 0V, Mode 7, Headphone Gain = –12dB 3.2 mV
VIN = 0V, Mode 7, Headphone Gain = 0dB 7 15 mV (max)
RL= 8Ω
LS 1% 425 mW
f = 1kHz 10% 525 mW
RL= 16Ω
POUT Output Power VDDLS = 3.0V 1% 49 mW
10% 69 mW
HP
f = 1kHz RL= 32Ω
1% 35 mW
10% 44 mW
RL= 8Ω
LS 1% 640 600 mW (min)
f = 1kHz 10% 790 mW
RL= 16Ω
POUT Output Power VDDLS = 3.6V 1% 49 mW
10% 72 mW
HP
f = 1kHz RL= 32Ω
1% 50 46 mW (min)
10% 62 mW
(1) All voltages are measured with respect to the GND pin unless other wise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specify performance limits. This assumes that the device is within the Operating
Ratings. Specifications are not for parameters where no limit is given, however, the typical value is a good indication of device
performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to AOQL (Average Outgoing Quality Level).
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Electrical Characteristics VDDLS = 3.6V, VDDHP = 2.8V (1)(2) (continued)
The following specifications apply for all programmable gain set to 0 dB, CB= 4.7μF, RL (SP) = 8Ω, RL(HP) = 32Ω, f = 1 kHz
unless otherwise specified. Limits apply for TA= 25°C. LM49100 Units
Symbol Parameter Conditions Limit (Limits)
Typical (3) (4)
RL= 8Ω
LS 1% 1275 mW
f = 1kHz 10% 1575 mW
RL= 16Ω
POUT Output Power VDDLS = 5.0V 1% 49 mW
10% 72 mW
HP
f = 1kHz RL= 32Ω
1% 53 mW
10% 62 mW
Loudspeaker;
Mode 1, 0.05 %
RL= 8Ω,
POUT = 215mW
Total Harmonic Distortion +
THD+N VDDLS = 3.0V f = 1kHz
Noise Headphone;
Mode 4, 0.02 %
RL= 32Ω,
POUT = 25mW
Loudspeaker;
Mode 1, 0.05 %
RL= 8Ω,
POUT = 320mW
Total Harmonic Distortion +
THD+N VDDLS = 3.6V f = 1kHz
Noise Headphone;
Mode 4, 0.02 %
RL= 32Ω,
POUT = 25mW
Loudspeaker;
Mode 1, 0.035 %
RL= 8Ω,
POUT = 630mW
Total Harmonic Distortion +
THD+N VDDLS = 5.0V f = 1kHz
Noise Headphone;
Mode 4, 0.02 %
RL= 32Ω,
POUT = 25mW Headphone
Mode 2, 10 12 µV
Mode 4, 7 13 µV
Mode 6, 14 16 µV
A-weighted, 0 dB, inputs
eNNoise terminated to GND, output Loudspeaker
referred Mode 1 14 µV
Mode 3, 7, 10, 23 µV
14
Mode 5 27 µV
TON Turn-on Time 26 ms
TOFF Turn-off Time 1 ms
10 kΩ(min)
Maximum gain setting 12.5 15 kΩ(max)
ZIN Input Impedance 90 kΩ(min)
Maximum attenuation setting 110 130 kΩ(max)
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Electrical Characteristics VDDLS = 3.6V, VDDHP = 2.8V (1)(2) (continued)
The following specifications apply for all programmable gain set to 0 dB, CB= 4.7μF, RL (SP) = 8Ω, RL(HP) = 32Ω, f = 1 kHz
unless otherwise specified. Limits apply for TA= 25°C. LM49100 Units
Symbol Parameter Conditions Limit (Limits)
Typical (3) (4)
Input referred maximum –52 dB (min)
−54
Stereo (Left attenuation –56 dB (max)
and Right 17.5 dB (min)
Channels) Input referred maximum gain 18 18.5 dB (max)
AVVolume Control Input referred maximum –58 dB (min)
−60
attenuation –62 dB (max)
Mono 11.5 dB (min)
Input referred maximum gain 12 12.5 dB (max)
Headphone Mode 2, f = 217 Hz, VCM = 1 VPP,64 dB
RL= 32Ω
CMRR Common Mode Rejection Ratio Loudspeaker Mode 1, f = 217 Hz, VCM = 1 VPP,58 dB
RL= 8Ω
VRIPPLE = 200mVpp on VDD LS, output referred, inputs terminated to GND, f = 217Hz
LS, Mode 1 90 dB
PSRR Power Supply Rejection Ratio LS, Mode 3, 7, 10, 14 78 dB
LS, Mode 5 77 dB
VRIPPLE = 200mVpp on VDD HP, output referred, inputs terminated to GND, f = 217Hz
PSRR Power Supply Rejection Ratio LS, Mode 7, 10, 14 83 dB
VRIPPLE = 200mVpp on VDD LS, output referred, inputs terminated to GND, f = 217Hz
HP, Mode 2, 10 90 dB
PSRR Power Supply Rejection Ratio HP, Mode 4, 7 88 dB
HP, Mode 6, 14 87 dB
VRIPPLE = 200mVpp on VDD HP, output referred, inputs terminated to GND, f = 217Hz
HP, Mode 2, 10 83 dB
PSRR Power Supply Rejection Ratio HP, Mode 4, 7 83 dB
HP, Mode 6, 14 80 dB
I2C(1)(2)
The following specifications apply for VDD = 5.0V and 3.3V, TA= 25°C, 2.2V ≤VDDI2C≤5.5V, unless otherwise specified.
Symbol Parameter Conditions (3) LM49100 Units
(Limits)
Typical Limits
(4) (2)
t1I2C Clock Period 2.5 µs (min)
t2I2C Data Setup Time 100 ns (min)
t3I2C Data Stable Time 0 ns (min)
t4Start Condition Time 100 ns (min)
t5Stop Condition Time 100 ns (min)
t6I2C Data Hold Time 100 ns (min)
VIH I2C Input Voltage High 0.7xVDDI2C V (min)
VIL I2C Input Voltage Low 0.3xVDDI2C V (max)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specify performance limits. This assumes that the device is within the Operating
Ratings. Specifications are not for parameters where no limit is given, however, the typical value is a good indication of device
performance.
(2) Limits are specified to AOQL (Average Outgoing Quality Level).
(3) Please refer to Figure 32 (I2C Timing Diagram).
(4) Typicals are measured at 25°C and represent the parametric norm.
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I2C(1)(2)
The following specifications apply for VDD = 5.0V and 3.3V, TA= 25°C, 1.7V ≤VDDI2C≤2.2V, unless otherwise specified.
Symbol Parameter Conditions (3) LM49100 Units
(Limits)
Typical Limits
(4) (2)
t1I2C Clock Period 2.5 µs (min)
t2I2C Data Setup Time 250 ns (min)
t3I2C Data Stable Time 0 ns (min)
t4Start Condition Time 250 ns (min)
t5Stop Condition Time 250 ns (min)
t6I2C Data Hold Time 250 ns (min)
VIH I2C Input Voltage High 0.7xVDDI2C V (min)
VIL I2C Input Voltage Low 0.3xVDDI2C V (max)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specify performance limits. This assumes that the device is within the Operating
Ratings. Specifications are not for parameters where no limit is given, however, the typical value is a good indication of device
performance.
(2) Limits are specified to AOQL (Average Outgoing Quality Level).
(3) Please refer to Figure 32 (I2C Timing Diagram).
(4) Typicals are measured at 25°C and represent the parametric norm.
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FREQUENCY (Hz)
THD+N (%)
10
1
0.1
0.01
0.001
20 200 2k 20k
FREQUENCY (Hz)
THD+N (%)
10
1
0.1
0.01
0.00120 200 2k 20k
FREQUENCY (Hz)
THD+N (%)
10
1
0.1
0.01
0.001
20 200 2k 20k
FREQUENCY (Hz)
THD+N (%)
10
1
0.1
0.00120 200 2k 20k
0.01
FREQUENCY (Hz)
THD+N (%)
10
1
0.1
0.01
0.001
20 200 2k 20k
FREQUENCY (Hz)
THD+N (%)
10
1
0.1
0.01
0.00120 200 2k 20k
LM49100
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Typical Performance Characteristics
THD+N vs Frequency THD+N vs Frequency
VDD = 3.6V, RL= 8Ω, PO= 320mW VDD = 3.6V, RL= 32Ω, PO= 25mW
BW = 22kHz, LS, Mode 1 HP, BW = 22kHz, Mode 4,7
Figure 3. Figure 4.
THD+N vs Frequency THD+N vs Frequency
VDD = 3V, RL= 8Ω, PO= 215mW VDD = 3V, RL= 32Ω, PO= 25mW
BW = 22kHz, LS, Mode 1 BW = 22kHz, HP, Mode 4, 7
Figure 5. Figure 6.
THD+N vs Frequency THD+N vs Frequency
VDD = 5V, RL= 8Ω, PO= 630mW VDD = 5V, RL= 32Ω, PO= 25mW
BW = 22kHz, Loudspeaker, Mode 1 BW = 22kHz, Headphone, Mode 4,7
Figure 7. Figure 8.
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OUTPUT POWER (mW)
POWER DISSIPATION (mW)
0
100
150
200
250
300
400
0 800
50
350
100 200 300 400 500 600 700
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
0
50
100
150
200
250
0 100 200 300 400 600
500
OUTPUT POWER (mW)
0
800
1000
1200
1400
1600
1800
2000
LOUDSPEAKER VOLTAGE SUPPLY (V)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
THD+N = 10%
THD+N = 1%
600
400
200
OUTPUT POWER (mW)
0
10
20
30
40
50
60
70
80
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
LOUDSPEAKER VOLTAGE SUPPLY (V)
THD+N = 1%
THD+N = 10%
10
THD+N (%)
OUTPUT POWER (mW)
1
0.01
0.1
1
5 10 20 50 1002
+3.6V
+3V
+5V
10
THD+N (%)
OUTPUT POWER (mW)
10 100 1000 10000
0.01
0.1
1
+5V
+3.6V
+3V
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Typical Performance Characteristics (continued)
THD+N vs Output Power THD+N vs Output Power
RL= 32Ω, f = 1kHz RL= 8Ω, f = 1kHz
BW = 22kHz, HP, Mode 4 BW = 22kHz, LS, Mode 1
Figure 9. Figure 10.
Output Power vs Supply Voltage Output Power vs Supply Voltage
VDDHP = 2.8V, RL= 8Ω, VDDHP = 2.8V, RL= 32Ω,
f = 1kHz, LS f = 1kHz, HP
Figure 11. Figure 12.
Power Dissipation vs Output Power Power Dissipation vs Output Power
VDD = 3.6V, RL= 8Ω, VDD = 3V, RL= 8Ω,
f = 1kHz, Mode 1 f = 1kHz, Mode 1
Figure 13. Figure 14.
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PSRR (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
FREQUENCY (Hz)
20k200 2k20
PSRR (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
FREQUENCY (Hz)
20k200 2k20
VDDLS (V)
SUPPLY CURRENT (mA)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDDLS ( V)
SUPPLY CURRENT (mA)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
0
700
0 1600
100
200
300
400
500
600
200 400 600 800 10001200 1400
VOLTAGE SUPPLY (V)
SUPPLY CURRENT (mA)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
LM49100
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Typical Performance Characteristics (continued)
Power Dissipation vs Output Power
VDD = 5V, RL= 8Ω, Supply Current vs VDDLS
f = 1kHz, Mode 1 VDDHP = 2.8V, Mode 1, 3, 5, No Load
Figure 15. Figure 16.
Supply Current vs VDDLS Supply Current vs VDDLS
VDDHP = 2.8V, Mode 2, 4, 6, No Load VDDHP = 2.8V, Mode 7,10, 14, No Load
Figure 17. Figure 18.
PSRR vs Frequency PSRR vs Frequency
RL= 32Ω, VRIPPLE = 200mVPP on VDDHP RL= 32Ω, VRIPPLE = 200mVPP on VDDHP
VDDHP = 2.8V, CB= 4.7μF, Mode 2, 10, HP VDDHP = 2.8V, CB= 4.7μF, Mode 4, 7, HP
Figure 19. Figure 20.
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PSRR (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
FREQUENCY (Hz)
20k200 2k20
PSRR (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
FREQUENCY (Hz)
20k200 2k20
PSRR (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
FREQUENCY (Hz)
20k200 2k20
PSRR (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
FREQUENCY (Hz)
20k200 2k20
PSRR (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
FREQUENCY (Hz)
20k200 2k20
PSRR (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
FREQUENCY (Hz)
20k200 2k20
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Typical Performance Characteristics (continued)
PSRR vs Frequency PSRR vs Frequency
RL= 32Ω, VRIPPLE = 200mVPP on VDDHP RL= 32Ω, VRIPPLE = 200mVPP on VDDLS
VDDHP = 2.8V, CB= 4.7μF, Mode 6, HP VDDLS = 3.6V, CB= 4.7μF, Mode 2, 10, HP
Figure 21. Figure 22.
PSRR vs Frequency PSRR vs Frequency
RL= 32Ω, VRIPPLE = 200mVPP on VDDLS RL= 32Ω, VRIPPLE = 200mVPP on VDDLS
VDDLS = 3.6V, CB= 4.7μF, Mode 4, 7, HP VDDLS = 3.6V, CB= 4.7μF, Mode 6, 14, HP
Figure 23. Figure 24.
PSRR vs Frequency PSRR vs Frequency
RL= 8Ω, VRIPPLE = 200mVPP on VDDHP RL= 8Ω, VRIPPLE = 200mVPP on VDDLS
VDDHP = 2.8V, CB= 4.7μF, Mode 7, 10, 14, LS+HP VDDLS = 3.6V, CB= 4.7μF, Mode 1, LS
Figure 25. Figure 26.
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PSRR (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
FREQUENCY (Hz)
20k200 2k20
FREQUENCY (Hz)
20k200 2k20
CROSSTALK (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
FREQUENCY (Hz)
20k200 2k20
PSRR (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
FREQUENCY (Hz)
20k200 2k20
LM49100
SNAS392F –JUNE 2007–REVISED MAY 2013
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Typical Performance Characteristics (continued)
PSRR vs Frequency PSRR vs Frequency
RL= 8Ω, VRIPPLE = 200mVPP on VDDLS RL= 8Ω, VRIPPLE = 200mVPP on VDDLS
VDDLS = 3.6V, CB= 4.7μF, Mode 7, 10, 14, LS+HP VDDLS = 3.6V, CB= 4.7μF, Mode 3, LS
Figure 27. Figure 28.
PSRR vs Frequency
RL= 8Ω, VRIPPLE = 200mVPP on VDDLS Crosstalk vs Frequency
VDDLS = 3.6V, CB= 4.7μF, Mode 5, LS PO= 12mW, f = 1kHz, Mode 4, HP
Figure 29. Figure 30.
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LM49100 Control Tables
Table 1. I2C Control Register Table(1)
D7 D6 D5 D4 D3 D2 D1 D0
Modes Control 0 0 1 1 MC3 MC2 MC1 MC0
HP Volume (Gain) INPUT_MU
0 1 0 0 HPR_SD HPVC1 HPVC0
Control TE
Mono Volume Control 1 0 0 MV4 MV3 MV2 MV1 MV0
Left Volume (Gain) 1 1 0 LV4 LV3 LV2 LV1 LV0
Control
Right Volume (Gain) 1 1 1 RV4 RV3 RV2 RV1 RV0
Control
(1) The LM49100 is controlled through an I2C compatible interface. The I2C chip address is 0xF8 (ADR pin = 0) or 0xFAh (ADDR pin = 1).
Table 2. Headphone Attenuation Control(1)
Gain Select HPVC1 HPVC0 Gain, dB
0 0 0 0
1 0 1 −12
2 1 0 −18
3 1 1 −24
(1) The following bits have added for extra headphone output attenuation:
Table 3. Output Mode Selection(1)
Output
Mode MC3 MC2 MC1 MC0 Handsfree Mono Output Right HP Output Left HP Output
Number
0 0 0 0 0 SD SD SD
1 0 0 0 1 2 × GM× M SD SD
2 0 0 1 0 SD GHP × (GM× M) GHP × (GM× M)
3 0 0 1 1 2 × (GL× L + GR× R) SD SD
4 0 1 0 0 SD GHP × (GR× R) GHP × (GL× L)
2 × (GL× L + GR× R + GM×
5 0 1 0 1 SD SD
M)
6 0 1 1 0 SD GHP × (GR× R + GM× M) GHP × (GL× L + GM× M)
7 0 1 1 1 2 × (GL× L + GR× R) GHP × (GR× R) GHP × (GL× L)
10 1 0 1 0 2 × (GL× L + GR× R) GHP × (GM× M) GHP × (GM× M)
14 1 1 1 0 2 × (GL× L + GR× R) GHP × (GR× R + GM× M) GHP × (GL× L + GM× M)
(1) GL— Left channel gain
GR— Right channel gain
GM— Mono channel gain
GHP — Headphone Amplifier gain
R — Right input signal
L — Left input signal
SD — Shutdown
M — Mono input signal
Table 4. Mono/Stereo Left/Stereo Right Input Gain Control
Volume Step MV4/LV4/RV4 MV3/LV3/RV3 MV2/LV2/RV2 MV1/LV1/RV1 MV0/LV0/RV0 R/L Gain, dB MonoGain, dB
1 0 0 0 0 0 −54 −60
2 0 0 0 0 1 −47 −53
3 0 0 0 1 0 −40.5 −46.5
4 0 0 0 1 1 −34.5 −40.5
5 0 0 1 0 0 −30.0 −36
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HPR
HPL
AGND
LM49100
SNAS392F –JUNE 2007–REVISED MAY 2013
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Table 4. Mono/Stereo Left/Stereo Right Input Gain Control (continued)
Volume Step MV4/LV4/RV4 MV3/LV3/RV3 MV2/LV2/RV2 MV1/LV1/RV1 MV0/LV0/RV0 R/L Gain, dB MonoGain, dB
6 0 0 1 0 1 −27 −33
7 0 0 1 1 0 −24 −30
8 0 0 1 1 1 −21 −27
9 0 1 0 0 0 −18 −24
10 0 1 0 0 1 −15 −21
11 0 1 0 1 0 −13.5 −19.5
12 0 1 0 1 1 −12 −18
13 0 1 1 0 0 −10.5 −16.5
14 0 1 1 0 1 −9−15
15 0 1 1 1 0 −7.5 −13.5
16 0 1 1 1 1 −6−12
17 1 0 0 0 0 −4.5 −10.5
18 1 0 0 0 1 −3−9
19 1 0 0 1 0 −1.5 −7.5
20 1 0 0 1 1 0 −6
21 1 0 1 0 0 1.5 −4.5
22 1 0 1 0 1 3 −3
23 1 0 1 1 0 4.5 −1.5
24 1 0 1 1 1 6 0
25 1 1 0 0 0 7.5 1.5
26 1 1 0 0 1 9 3
27 1 1 0 1 0 10.5 4.5
28 1 1 0 1 1 12 6
29 1 1 1 0 0 13.5 7.5
30 1 1 1 0 1 15 9
31 1 1 1 1 0 16.5 10.5
32 1 1 1 1 1 18 12
APPLICATION INFORMATION
MINIMIZING CLICK AND POP
To minimize the audible click and pop heard through a headphone, maximize the input signal through the
corresponding volume (gain) control registers and adjust the output amplifier gain accordingly to achieve the
user’s desired signal gain. For example, setting the output of the headphone amplifier to -24dB and setting the
input volume control gain to 24dB will reduce the output offset from 7mV (typical) to 2.2mV (typical). This will
reduce the audible click and pop noise significantly while maintaining a 0dB signal gain.
SIGNAL GROUND NOISE
The LM49100 has proprietary suppression circuitry, which provides an additional -50dB (typical) attenuation of
the headphone ground noise and its incursion into the headphone. For optimum utilization of this feature the
headphone jack ground should connect to the AGND (E3) bump.
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I2C PIN DESCRIPTION
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ADDR: This is the address select input pin.
I2C COMPATIBLE INTERFACE
The LM49100 uses a serial bus which conforms to the I2C protocol to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
LM49100's I2C compatible interface supports standard (100kHz) and fast (400kHz) I2C modes. In this discussion,
the master is the controlling microcontroller and the slave is the LM49100.
The I2C address for the LM49100 is determined using the ADDR pin. The LM49100's two possible I2C chip
addresses are of the form 111110X10 (binary), where X1= 0, if ADDR pin is logic LOW; and X1= 1, if ADDR pin
is logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM49100's chip address
can be changed to avoid any possible address conflicts.
The bus format for the I2C interface is shown in Figure 31. The bus format diagram is broken up into six major
sections:
The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will
alert all devices attached to the I2C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.
Each address bit must be stable while the clock level is HIGH.
After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the LM49100 has received the address correctly, then it
holds the data line LOW during the clock pulse. If the data line is not held LOW during the acknowledge clock
pulse, then the master should abort the rest of the data transfer to the LM49100.
The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable HIGH.
After the data byte is sent, the master must check for another acknowledge to see if the LM49100 received the
data.
If the master has more data bytes to send to the LM49100, then the master can repeat the previous two steps
until all data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is HIGH.
The data line should be held HIGH when not in use.
I2C INTERFACE POWER SUPPLY PIN (VDDI2C)
The LM49100's I2C interface is powered up through theVDD I2C pin. The LM49100's I2C interface operates at a
voltage level set by the VDD I2C pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
Figure 31. I2C Bus Format
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Figure 32. I2C Timing Diagram
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 8ΩLOAD
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by an 8Ωload from 158.3mW to 156.4mW. The problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
BRIDGE CONFIGURATION EXPLANATION
The LM49100 drives a load, such as a loudspeaker, connected between outputs, LS+ and LS-.
This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage
of this phase difference, a load is placed between LS- and LS+ and driven differentially (commonly referred to as
”bridge mode”).
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single
amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the single-
ended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces
four times the output power when compared to a single-ended amplifier under the same conditions. This increase
in attainable output power assumes that the amplifier is not current limited and that the output signal is not
clipped.
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by
biasing LS- and LS+ outputs at half-supply. This eliminates the coupling capacitor that single supply, single-
ended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration forces a
single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power dissipation
and may permanently damage loads such as loudspeakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power
dissipation. The LM49100 has a pair of bridged-tied amplifiers driving a handsfree loudspeaker, LS. The
maximum internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From
Equation 1, assuming a 5V power supply and an 8Ωload, the maximum MONO power dissipation is 634mW.
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PDMAX-LS = 4(VDD)2/(2π2RL): Bridge Mode (1)
The LM49100 also has a pair of single-ended amplifiers driving stereo headphones, HPR and HPL. The
maximum internal power dissipation for HPR and HPL is given by Equation 2. Assuming a 2.8V power supply
and a 32Ωload, the maximum power dissipation for LOUT and ROUT is 49mW, or 99mW total.
PDMAX-HPL = 4(VDDHP)2/ (2π2RL): Single-ended Mode (2)
The maximum internal power dissipation of the LM49100 occurs when all three amplifiers pairs are
simultaneously on; and is given by Equation 3.
PDMAX-TOTAL = PDMAX-LS + PDMAX-HPL + PDMAX-HPR (3)
The maximum power dissipation point given by Equation 3 must not exceed the power dissipation given by
Equation 4:
PDMAX = (TJMAX - TA) / θJA (4)
The LM49100's TJMAX = 150°C. In the csBGA package, the LM49100's θJA is 50.2°C/W. At any given ambient
temperature TA, use Equation 4 to find the maximum internal power dissipation supported by the IC packaging.
Rearranging Equation 4 and substituting PDMAX-TOTAL for PDMAX results in Equation 5. This equation gives the
maximum ambient temperature that still allows maximum stereo power dissipation without violating the
LM49100's maximum junction temperature.
TA= TJMAX - PDMAX-TOTAL θJA (5)
For a typical application with a 5V power supply and an 8Ωload, the maximum ambient temperature that allows
maximum mono power dissipation without exceeding the maximum junction temperature is approximately 114°C
for the csBGA package.
TJMAX = PDMAX-TOTAL θJA + TA(6)
Equation 6 gives the maximum junction temperature TJMAX. If the result violates the LM49100's 150°C, reduce
the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.
Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases. If the result of Equation 3 is greater than that of Equation 4,
then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these
measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional
copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 1µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 4.7µF tantalum bypass capacitor and a parallel
0.1µF ceramic capacitor connected between the LM49100's supply pin and ground. Keep the length of leads and
traces that connect capacitors between the LM49100's power supply pin and ground as short as possible.
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value input coupling capacitor (CIN in Figure 1). A high
value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases,
however, the loudspeakers used in portable systems, whether internal or external, have little ability to reproduce
signals below 150Hz. Applications using loudspeakers and headphones with this limited frequency response
reap little improvement by using large input capacitor.
The internal input resistor (Ri), typical 12.5kΩ, and the input capacitor (CIN) produce a high pass filter cutoff
frequency that is found using Equation 7.
fc= 1 / (2πRiCIN) (7)
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Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor
connected to the BYPASS pin. Since CBdetermines how fast the LM49100 settles to quiescent operation, its
value is critical when minimizing turn-on pops. Choosing CBequal to 2.2µF along with a small value of Ci(in the
range of 0.1µF to 0.33µF), produces a click-less and pop-less shutdown function. As discussed above, choosing
CIN no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value should be in
the range of 4 to 5 times the value of CIN . This ensures that output transients are eliminated when power is first
applied or the LM49100 resumes operation after shutdown.
Demo Board Schematic
Figure 33. Demo Board Schematic
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Figure 39. Bottom Overlay
REVISION HISTORY
Rev Date Description
1.0 06/21/07 Initial release.
1.1 06/28/07 Changed the mktg outline from TLA25XXX to GRA25A.
1.2 08/09/07 Replaced some curves.
1.3 08/13/07 Changed the f = 1kHz into f = 217Hz (PSRR) in the Electrical Characteristics
table.
1.4 08/14/07 Edited Table 1.
1.5 09/18/07 Edited the Schematic Diagram.
F 05/02/2013 Changed layout of National Data Sheet to TI format.
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PACKAGE OPTION ADDENDUM
www.ti.com 14-Aug-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM49100GR/NOPB ACTIVE csBGA NYA 25 1000 Green (RoHS
& no Sb/Br) CU SNAGCU Level-1-260C-UNLIM -40 to 85 GC9
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 14-Aug-2014
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM49100GR/NOPB csBGA NYA 25 1000 178.0 12.4 3.3 3.3 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM49100GR/NOPB csBGA NYA 25 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 2
MECHANICAL DATA
NYA0025A
www.ti.com
GRA25A (Rev A)
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