ADS8322Y/2KG4 - Texas Instruments

SAR

OutputLatches

and

3-State

Drivers

Comparator

ADS8322

S/HAmp

BYTE

Parallel

Data

Output

+IN

-IN

CDAC

REFIN

Conversion

andControl

Logic

Internal

+2.5VRef

CONVST

CLOCK

BUSY

REFOUT

ADS8322

www.ti.com

SBAS215A –JULY 2001–REVISED JANUARY 2010

16-Bit, 500kHz, MicroPower Sampling

ANALOG-TO-DIGITAL CONVERTER

Check for Samples: ADS8322

1FEATURES DESCRIPTION

2• HIGH-SPEED PARALLEL INTERFACE

• 500kHz SAMPLING RATE The ADS8322 is a 16-bit, 500kHz analog-to-digital

(A/D) converter with an internal 2.5V reference. The

• LOW POWER: 85mW at 500kHz device includes a 16-bit capacitor-based successive

• INTERNAL 2.5V REFERENCE approximation register (SAR) A/D converter with

• UNIPOLAR INPUT RANGE inherent sample-and-hold. The ADS8322 offers a full

16-bit interface, or an 8-bit option where data are

• TQFP-32 PACKAGE read using two read cycles and eight pins. The

ADS8322 is available in a TQFP-32 package and is

APPLICATIONS ensured over the industrial –40°C to +85°C

• CT SCANNERS temperature range.

• HIGH-SPEED DATA ACQUISITION white space here

• TEST AND INSTRUMENTATION white space here

• MEDICAL EQUIPMENT white space here

white space here

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS8322

SBAS215A –JULY 2001–REVISED JANUARY 2010

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION(1)

MAXIMUM NO

INTEGRAL MISSING SPECIFIED TRANSPORT

LINEARITY CODES PACKAGE- PACKAGE TEMPERATURE PACKAGE MEDIA,

PRODUCT ERROR (LSB) ERROR (LSB) LEAD DESIGNATOR RANGE MARKING QUANTITY

Tape and reel,

250

ADS8322Y ±8 14 TQFP-32 PBS –40°C to +85°C Tape and reel,

2000

Tape and reel,

250

ADS8322YB ±6 15 TQFP-32 PBS –40°C to +85°C Tape and reel,

2000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI

website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS(1)

Over operating free-air temperature range (unless otherwise noted). ADS8322 UNIT

+IN to GND VA+ 0.1 V

–IN to GND +0.5 V

VAto GND –0.3 to +7 V

Digital input voltage to GND –0.3 to (VA+ 0.3) V

VOUT to GND –0.3 to (VA+ 0.3) V

Operating temperature range –40 to +105 °C

Storage temperature range –65 to +150 °C

Junction temperature (TJmax) +150 °C

Power dissipation (TJmax – TA)/θJA

θJA thermal impedance 240 °C/W

(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

Product Folder Link(s): ADS8322

ADS8322

www.ti.com

SBAS215A –JULY 2001–REVISED JANUARY 2010

ELECTRICAL CHARACTERISTICS: +VA= +5V

At –40°C to +85°C, +VA= +5V, VREF = +2.5V, fSAMPLE = 500kHz, and fCLK = 20 • fSAMPLE, unless otherwise specified.

ADS8322Y ADS8322YB(1)

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT

RESOLUTION

Resolution 16 16 Bits

ANALOG INPUTS

Full-scale input span(2) +IN – (–IN) 0 +2VREF 0 +2VREF V

+IN –0.1 VA+ 0.1 –0.1 VA+ 0.1 V

Absolute input range –IN –0.1 +0.5 –0.1 +0.5 V

Capacitance 25 25 pF

Leakage current ±1 ±1 nA

SYSTEM PERFORMANCE

No missing codes 14 15 Bits

Integral linearity error ±4 ±8 ±3 ±6 LSBs(3)

Offset error ±1.0 ±2 ±0.5 ±1.0 mV

Gain error(4) ±0.25 ±0.50 ±0.22 ±0.25 %FSR

Common-mode rejection ratio At dc 70 70 dB

Noise 60 60 μVRMS

Power-supply rejection ratio At FFFFh output code ±3 ±3 LSBs

SAMPLING DYNAMICS

Conversion time 1.6 1.6 μs

Acquisition time 350 350 ns

Throughput rate 500 500 kHz

Aperture delay 50 50 ns

Aperture jitter 20 20 ps

Small-signal bandwidth 30 30 MHz

Step response 100 100 ns

DYNAMIC CHARACTERISTICS

Total harmonic distortion(5) VIN = 5VPP at 100kHz –90 –93 dB

SINAD VIN = 5VPP at 100kHz 81 83 dB

Spurious free dynamic range VIN = 5VPP at 100kHz 94 96 dB

REFERENCE OUTPUT

Voltage IOUT = 0 2.475 2.50 2.525 2.48 2.50 2.52 V

Source current Static load 10 10 μA

Drift IOUT = 0 20 20 ppm/°C

Line regulation 4.75V ≤VCC ≤5.25V 0.6 0.6 mV

REFERENCE INPUT

Range 1.5 2.55 1.5 2.55 V

Resistance(6) To internal reference voltage 10 10 kΩ

(1) Shaded cells indicate different specifications from ADS8322Y.

(2) Ideal input span; does not include gain or offset error.

(3) LSB means least significant bit, with VREF equal to +2.5V; 1LSB = 76μV.

(4) Measured relative to an ideal, full-scale input [+In – (–In)] of 4.9999V. Thus, gain error includes the error of the internal voltage

reference.

(5) Calculated on the first nine harmonics of the input frequency.

(6) Can vary ±30%.

Product Folder Link(s): ADS8322

+VA

AGND

+IN

-IN

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

BYTE

CONVST

CLOCK

DGND

+VD

BUSY

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

9 10 11 12 13 14 15 16

REFOUT

REFIN

32 31 30 29 28 27 26 25

ADS8322

SBAS215A –JULY 2001–REVISED JANUARY 2010

www.ti.com

ELECTRICAL CHARACTERISTICS: +VA= +5V (continued)

At –40°C to +85°C, +VA= +5V, VREF = +2.5V, fSAMPLE = 500kHz, and fCLK = 20 • fSAMPLE, unless otherwise specified.

ADS8322Y ADS8322YB(1)

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT

DIGITAL INPUT/OUTPUT

Logic family CMOS CMOS

Logic levels:

VIH IIH ≤+5μA 3.0 +VA3.0 +VAV

VIL IIL ≤+5μA –0.3 0.8 –0.3 0.8 V

VOH IOH = 2 TTL Loads 4.0 4.0 V

VOL IOH = 2 TTL Loads 0.4 0.4 V

Data format Straight binary Straight binary

POWER-SUPPLY REQUIREMENTS

Power-supply voltage

+VA4.75 5 5.25 4.75 5 5.25 V

+VD4.75 5 5.25 4.75 5 5.25 V

Supply current fSAMPLE = 500kHz 17 25 17 25 mA

Power dissipation fSAMPLE = 500kHz 85 125 85 125 mW

TEMPERATURE RANGE

Specified temperature range –40 +85 –40 +85 °C

DEVICE INFORMATION

PBS PACKAGE

TQFP-32

(TOP VIEW)

Product Folder Link(s): ADS8322

ADS8322

www.ti.com

SBAS215A –JULY 2001–REVISED JANUARY 2010

PIN ASSIGNMENTS

TERMINAL

NO NAME DESCRIPTION

1 DB15 Data Bit 15 (MSB)

2 DB14 Data Bit 14

3 DB13 Data Bit 13

4 DB12 Data Bit 12

5 DB11 Data Bit 11

6 DB10 Data Bit 10

7 DB9 Data Bit 9

8 DB8 Data Bit 8

9 DB7 Data Bit 7

10 DB6 Data Bit 6

11 DB5 Data Bit 5

12 DB4 Data Bit 4

13 DB3 Data Bit 3

14 DB2 Data Bit 2

15 DB1 Data Bit 1

16 DB0 Data Bit 0 (LSB)

17 BUSY High when a conversion is in progress.

18 VD+ Digital Power Supply, +5VDC.

19 DGND Digital Ground

An external CMOS-compatible clock can be applied to the CLOCK input to synchronize the conversion

20 CLOCK process to an external source.

21 CONVST Convert Start

22 RD Synchronization pulse for the parallel output.

23 BYTE Selects eight most significant bits (low) or eight least significant bits (high). Data valid on pins 9-16.

24 CS Chip Select

25 –IN Inverting Input Channel

26 +IN Noninverting Input Channel

27 AGND Analog Ground

28 +VAAnalog Power Supply, +5VDC.

29 NC No connection

30 NC No connection

31 REFIN Reference Input. When using the internal 2.5V reference, tie this pin directly to REFOUT.

Reference Output. A 0.1μF capacitor should be connected to this pin when the internal reference is

32 REFOUT used.

Product Folder Link(s): ADS8322

1CLOCK

Acquisition

CONVST

BUSY

BYTE

DB15-D8

DB7-D0

2 3 4 5 17 18 19 20 3 41 2 17 18 19 20

t6t9

AcquisitionConversion

tACQ

tCONV

t11

t10

t12

t13 t14

t16

t15

t17

Bits15-8 Bits15-8 FF

t18

t19

Bits7-0 Bits7-0 Bits15-8

ADS8322

SBAS215A –JULY 2001–REVISED JANUARY 2010

www.ti.com

TIMING INFORMATION

TIMING CHARACTERISTICS(1)(2)

All specifications typical at –40°C to +85°C, +VD= +5V. ADS8322

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tCONV Conversion Time 1.6 μs

tAQC Acquisition Time 350 ns

t1CLOCK Period 100 ns

t2CLOCK High Time 40 ns

t3CLOCK Low Time 40 ns

t4CONVST Low to Clock High 10 ns

t5CLOCK High to CONVST High 5 ns

t6CONVST Low Time 20 ns

t7CONVST Low to BUSY High 25 ns

t8CS Low to CONVST Low 0 ns

t9CONVST High 20 ns

t10 CLOCK Low to CONVST Low 0 ns

t11 CLOCK High to BUSY Low 25 ns

t12 CS High 0 ns

t13 CS Low to RD Low 0 ns

t14 RD High to CS High 0 ns

t15 RD Low Time 50 ns

t16 RD Low to Data Valid 40 ns

t17 Data Hold from RD High 5 ns

t18 BYTE Change to RD Low(3) 0 ns

t19 RD High Time 20 ns

(1) All input signals are specified with tR= tF= 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH) /2.

(2) See timing diagram, above.

(3) BYTE is asynchronous; when BYTE is 0, bits 15 through 0 appear at DB15-DB0. When BUSY is 1, bits 15 through 8 appear on

DB7-DB0. RD may remain low between changes in BYTE.

Product Folder Link(s): ADS8322

120

150

Amplitude(dB)

20 40 60 80 100 120 140 160 180 2000

Frequency(Hz)

SNR,SINAD(dB)

10 100 250

Frequency(kHz)

SINAD

SNR

100

-100

SFDR

THD(dB)

10 100 250

Frequency(kHz)

SFDR

THD

0.30

0.20

0.10

0.20

Deltas(LSB)

-40 -20 20 40 60 80 100

Temperature( C)°

1.0

0.5

1.0

1.5

Deltas(LSB)

Temperature( C)°

0-40 -20 20 40 60 80 100

0.2

0.4

0.6

Deltas(LSB)

Temperature( C)°

– 0

-40 -20 20 40 60 80 100

ADS8322

www.ti.com

SBAS215A –JULY 2001–REVISED JANUARY 2010

TYPICAL CHARACTERISTICS

At –40°C to +85°C, +VA= +5V, VREF = +2.5V, fSAMPLE = 500kHz, and fCLK = 20 • fSAMPLE, unless otherwise specified.

FREQUENCY SPECTRUM SIGNAL-TO-NOISE RATIO AND

(4096 Point FFT; fIN = 100.1kHz, –0.2dB) SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY

Figure 1. Figure 2.

SPURIOUS FREE DYNAMIC RANGE AND

TOTAL HARMONIC DISTORTIONvs INPUT FREQUENCY IL+ vs TEMPERATURE

Figure 3. Figure 4.

IL– vs TEMPERATURE DL+ vs TEMPERATURE

Figure 5. Figure 6.

Product Folder Link(s): ADS8322

0.05

0.10

0.15

0.20

0.05

0.25

Temperature( C)

0-40 -20 20 40 60 80 100

Deltas(LSB)

2.5

2.0

1.5

1.0

0.5

1.0

1.5

Deltas(LSB)

Temperature( C)°

-40 -20 20 40 60 80 100

Deltas(LSB)

Temperature( C)°

-40 -20 20 40 60 80 100

2.0

1.0

1.0-

2.0

3.0

4.0

5.0

6.0

7.0

8.0

Deltas(mV)

Temperature( C)°

-40 -20 20 40 60 80 100

2.5

2.0

1.5

1.0

0.5

1.0

1.5

INL(LSB)

DNL(LSB)

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

DecimalCode

1.2

0.8

0.4

0.8-

-0.4

Deltas(mA)

Temperature( C)°

-40 -20 20 40 60 80 100

ADS8322

SBAS215A –JULY 2001–REVISED JANUARY 2010

www.ti.com

TYPICAL CHARACTERISTICS (continued)

At –40°C to +85°C, +VA= +5V, VREF = +2.5V, fSAMPLE = 500kHz, and fCLK = 20 • fSAMPLE, unless otherwise specified.

DL– vs TEMPERATURE OFFSET ERROR vs TEMPERATURE

Figure 7. Figure 8.

GAIN ERROR vs TEMPERATURE VREF vs TEMPERATURE

Figure 9. Figure 10.

LINEARITY ERROR AND

IQvs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs CODE

Figure 11. Figure 12.

Product Folder Link(s): ADS8322

DB6

DB5

DB4

DB3

DB2

DB1

DB0

+VA

AGND

+IN

-IN

REFOUT

REFIN

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

BYTE

CONVST

CLOCK

DGND

+VD

BUSY

DB7

ChipSelect

ReadInput

ConversionStart

ClockInput

BusyOutput

AnalogInput

9 10 11 12 13 14 15 16

32 31 30 29 28

ADS8322

27 26 25

0.1mF

10mF

+5VAnalogSupply

0.1mF

ADS8322

www.ti.com

SBAS215A –JULY 2001–REVISED JANUARY 2010

THEORY OF OPERATION

The ADS8322 is a high-speed successive times are at least 40ns and the clock period is at

approximation register (SAR) A/D converter with an least 100ns. The minimum clock frequency is

internal 2.5V bandgap reference. The architecture is governed by the parasitic leakage of the capacitive

based on capacitive redistribution, which inherently digital-to-analog (CDAC) capacitors internal to the

includes a sample-and-hold function. The basic ADS8322.

operating circuit for the ADS8322 is shown in The analog input is provided to two input pins, +IN

Figure 13.and –IN. When a conversion is initiated, the

The ADS8322 requires an external clock to run the differential input on these pins is sampled on the

conversion process. The clock can be run internal capacitor array. While a conversion is in

continuously or it can be gated to conserve power progress, both inputs are disconnected from any

between conversions. This clock can vary between internal function.

25kHz (1.25kHz throughput) and 10MHz (500kHz

throughput). The duty cycle of the clock is

unimportant as long as the minimum HIGH and LOW

Figure 13. Typical Circuit Configuration

Product Folder Link(s): ADS8322

ADS8322

SBAS215A –JULY 2001–REVISED JANUARY 2010

www.ti.com

REFERENCE The ADS8322 uses an external clock (CLOCK) which

controls the conversion rate of the CDAC. With a

Under normal operation, the REFOUT pin should be 10MHz external clock, the A/D converter sampling

directly connected to the REFIN pin to provide an rate is 500kHz, which corresponds to a 2μs maximum

internal +2.5V reference to the ADS8322. The throughput time.

ADS8322 can operate, however, with an external

reference in the range of 1.5V to 2.6V for a Conversions are initiated by bringing the CONVST

corresponding full-scale range of 3.0V to 5.2V. pin low for a minimum of 20ns (after the 20ns

minimum requirement has been met, the CONVST

The internal reference of the ADS8322 is pin can be brought high), while CS is low. The

double-buffered. If the internal reference is used to ADS8322 switches from Sample-to-Hold mode on the

drive an external load, a buffer is provided between falling edge of the CONVST command. Following the

the reference and the load applied to the REFOUT pin first rising edge of the external clock after a CONVST

(the internal reference can typically source and sink low, the ADS8322 begins conversion (this first rising

10μA of current). If an external reference is used, the edge of the external clock represents the start of

second buffer provides isolation between the external clock cycle one; the ADS8322 requires 16 rising clock

reference and the CDAC. This buffer is also used to edges to complete a conversion). The BUSY output

recharge all of the CDAC capacitors during goes high immediately following CONVST going low.

conversion. BUSY stays high through the conversion process and

returns low when the conversion has ended.

ANALOG INPUT Both RD and CS can be high during and before a

When the converter enters the Hold mode, the conversion (although CS must be low when CONVST

voltage difference between the +IN and –IN inputs is goes low to initiate a conversion). Both the RD and

captured on the internal capacitor array. The voltage CS pins are brought low in order to enable the

on the –IN input is limited between –0.1V and 0.5V, parallel output bus with the conversion.

allowing the input to reject small signals which are

common to both the +IN and –IN inputs. The +IN READING DATA

input has a range of –0.1V to +VA+ 0.1V. The ADS8322 outputs full parallel data in Straight

The input current on the analog inputs depends upon Binary format, as shown in Table 1. The parallel

a number of factors: sample rate, input voltage, and output is active when CS and RD are both LOW. The

source impedance. Essentially, the current into the output data should not be read 125ns before the

ADS8322 charges the internal capacitor array during falling edge of CONVST and 10ns after the falling

the sample period. After this capacitance has been edge. Any other combination of CS and RD will

fully charged, there is no further input current. The 3-state the parallel output. Refer to Table 1 for ideal

source of the analog input voltage must be able to output codes.

charge the input capacitance (25pF) to a 16-bit

settling level within the acquisition time (400ns) of the Table 1. Ideal Input Voltages and Output Codes

device. When the converter goes into Hold mode, the ANALOG DIGITAL OUTPUT

input impedance is greater than 1GΩ.DESCRIPTION VALUE STRAIGHT BINARY

Care must be taken regarding the absolute analog Full-Scale 2 • VREF

input voltage. To maintain the linearity of the Range

converter, the –IN input should not drop below GND – Least Significant 2 • BINARY

100mV or exceed GND + 0.5V. The +IN input should Bit (LSB) VREF/65535 CODE HEX CODE

always remain within the range of GND – 100mV to 2VREF – 1 1111 1111

+Full Scale FFFF

VA+ 100mV. Outside of these ranges, the converter LSB 1111 1111

linearity may not meet specifications. To minimize 1000 0000

Midscale VREF 8000

noise, low-bandwidth input signals with low-pass 0000 0000

filters should be used. 0111 1111

Midscale – LSB VREF – 1 LSB 7FFF

1111 1111

DIGITAL INTERFACE 0000 0000

Zero 0 0000

0000 0000

TIMING AND CONTROL

See the timing diagram and the Timing

Characteristics section for detailed information on

timing signals and the respective requirements for

each.

Product Folder Link(s): ADS8322

54 300

5052

1968

818

0014 0015 0017 00180016

Code

ADS8322

www.ti.com

SBAS215A –JULY 2001–REVISED JANUARY 2010

BYTE AVERAGING

The output data appear as a full 16-bit word on The noise of the A/D converter can be compensated

DB15- DB0 (MSB-LSB), if BYTE is low. The result by averaging the digital codes. By averaging

may also be read on an 8-bit bus by using only conversion results, transition noise is reduced by a

DB7-DB0. In this case two reads are necessary. The factor of 1/√n, where nis the number of averages.

first read proceeds as before, leaving BYTE low and For example, averaging four conversion results

reading the eight least significant bits on DB7-DB0, reduces the transition noise by 1/2 to ±0.25 LSBs.

then bringing BYTE high. When BYTE is high, the Averaging should only be used for input signals with

upper eight bits (D15-D8) appear on DB7-DB0. frequencies near dc.

For ac signals, a digital filter can be used to low-pass

NOISE filter and decimate the output codes. This

configuration works in a similar manner to averaging:

Figure 14 shows the transition noise of the ADS8322. for every decimation by 2, the signal-to-noise ratio

A low-level dc input was applied to the analog input improves by 3dB.

pins and the converter was put through 8,192

conversions. The digital output of the A/D converter

varies in output code due to the internal noise of the LAYOUT

ADS8322. This characteristic is true for all 16-bit For optimum performance, care should be taken with

SAR-type A/D converters. Using a histogram to plot the physical layout of the ADS8322 circuitry. This

the output codes, the distribution should appear consideration is particularly true if the CLOCK input is

bell-shaped, with the peak of the bell curve approaching the maximum throughput rate.

representing the nominal code for the input value.

The ±1σ, ±2σ, and ±3σdistributions respectively As the ADS8322 offers single-supply operation, it is

represent the 68.3%, 95.5%, and 99.7% of all codes. often used in close proximity with digital logic,

The transition noise can be calculated by dividing the microcontrollers, microprocessors, and digital signal

number of codes measured by six; this yields the ±3σprocessors. The more digital logic present in the

distribution, or 99.7%, of all codes. Statistically, up to design and the higher the switching speed, the more

three codes could fall outside the distribution when difficult it is to achieve good performance from the

executing 1,000 conversions. The ADS8322, with five converter.

output codes for the ±3σdistribution, yields a < The basic SAR architecture is sensitive to glitches or

±0.8LSB transition noise at 5V operation. Remember sudden changes on the power supply, reference,

that to achieve this low-noise performance, the ground connections and digital inputs that occur just

peak-to-peak noise of the input signal and reference before latching the output of the analog comparator.

must be < 50μV. Thus, during any single conversion for an n-bit SAR

converter, there are n windows in which large

external transient voltages can affect the conversion

result. Such glitches might originate from switching

power supplies, or nearby digital logic or high-power

devices.

The degree of error in the digital output depends on

the reference voltage, layout, and the exact timing of

the external event. These errors can change if the

external event changes in time with respect to the

CLOCK input.

On average, the ADS8322 draws very little current

from an external reference, as the reference voltage

is internally buffered. If the reference voltage is

external and originates from an op amp, make sure

Figure 14. Histogram of 8,192 Conversions of a that it can drive the bypass capacitor or capacitors

Low-Level DC Input without oscillation.

Product Folder Link(s): ADS8322

ADS8322

SBAS215A –JULY 2001–REVISED JANUARY 2010

www.ti.com

The AGND and DGND pins should be connected to a As with the GND connections, VDD should be

clean ground point. In all cases, this point should be connected to a +5V power supply plane, or trace, that

the analog ground. Avoid connections which are too is separate from the connection for digital logic until

close to the grounding point of a microcontroller or they are connected at the power entry point. Power to

digital signal processor. If required, run a ground the ADS8322 should be clean and well-bypassed. A

trace directly from the converter to the power supply 0.1μF ceramic bypass capacitor should be placed as

entry point. The ideal layout will include an analog close to the device as possible. In addition, a 1μF to

ground plane dedicated to the converter and 10μF capacitor is recommended. If needed, an even

associated analog circuitry. larger capacitor and a 5Ωor 10Ωseries resistor may

be used to low-pass filter a noisy supply. In some

situations, additional bypassing may be required,

such as a 100μF electrolytic capacitor, or even a Pi

filter made up of inductors and capacitors—all

designed to essentially low-pass filter the +5V supply,

removing the high-frequency noise.

white space here REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (July, 2001) to Revision A Page

• Updated document format to current standards ................................................................................................................... 1

• Deleted lead temperature specifications from Absolute Maximum Ratings table ................................................................ 2

• Changed acquisition time specification from .4μs (max) to 350ns (min) .............................................................................. 3

• Changed acquisition time specification from .4μs (max) to 350ns (min) .............................................................................. 6

• Added Figure 12,Linearity Error and Differential Linearity Error vs Code ........................................................................... 8

Product Folder Link(s): ADS8322

PACKAGE OPTION ADDENDUM

www.ti.com 21-May-2010

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

ADS8322Y/250 ACTIVE TQFP PBS 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8322Y/250G4 ACTIVE TQFP PBS 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8322Y/2K ACTIVE TQFP PBS 32 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8322Y/2KG4 ACTIVE TQFP PBS 32 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8322YB/250 ACTIVE TQFP PBS 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8322YB/250G4 ACTIVE TQFP PBS 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 21-May-2010

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS8322Y/250 TQFP PBS 32 250 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2

ADS8322Y/2K TQFP PBS 32 2000 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2

ADS8322YB/250 TQFP PBS 32 250 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS8322Y/250 TQFP PBS 32 250 367.0 367.0 38.0

ADS8322Y/2K TQFP PBS 32 2000 367.0 367.0 38.0

ADS8322YB/250 TQFP PBS 32 250 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265