PRELIMINARY CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
PSoC® Programmable System-on-Chip
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document Number: 001-48111 Rev. *D Revised August 10, 2009
Features
■
Varied Resource Options Within One PSoC Device Group
■
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds up to 24 MHz
❐
8x8 Multiply, 32-Bit Accumu late
❐
Low Power at High Speed
❐
3.0V to 5.25V Operating Voltage
❐
Operating Voltages Down to 1.5V Using On-Chip Switched
Mode Pump (SMP)
❐
Industrial Temperature Range: -40°C to +85°C
■
Advanced Reconfigurable Peripherals (PSoC Blocks)
❐
Up to 12 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
• Multiple ADC configurations
• Dedicated SAR ADC, up to 192 ksps with Sample and Hold
• Up to 4 Synchronized or Independent Delta-Sigma ADCs
for Advanced Applications
❐
Up to 4 Limited Type E Analog Blocks Provide:
• Dual Channel Capacitive Sensing Capability
• Comparators with Programmable DAC Reference
• Up to 10-bit Single-Sl ope ADCs
❐
Up to 12 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• Shift Register, CRC, and PRS Modules
• Up to 3 Full-Duplex UARTs
• Up to 6 Half-Duplex UARTs
• Multiple Variable Data Length SPI™ Maste rs or Slaves
• Connectable to All GPIO
❐
Complex Peripherals by Combining Blocks
■
Precision, Programmable Clocking
❐
Internal ±2.5% 24/48 MHz Main Oscillator
❐
Optional 32.768 kHz Crystal for Precise On-Chip Clocks
❐
Optional External Oscillator, up to 24 MHz
❐
Internal Low Speed, Low Power Oscillator for Watchdog and
Sleep Functionality
■
Flexible On -C h ip Memory
❐
16K Bytes Flash Program Storage 50,0 00 Erase/Write Cy-
cles
❐
1K Bytes SRAM Data Storage
❐
In-System Serial Programming (ISSP™)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
■
Programmable Pi n Configurations
❐
25 mA Sink, 10 mA Drive on All GPIO
❐
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐
Analog Input on All GPIO
❐
30 mA Analog Outputs on GPIO
❐
Configurable Interrupt on all GPIO
■
Additional System Resources
❐
Up to 2 Hardware I
2
C Resources
• Each Resource Implements Slave, Master, or Multi-Master
Modes
• Operation Between 0 and 400 kHz
❐
Watchdog and Slee p Timers
❐
User-Configurable Low Vol tage Detection
❐
Flexible Inte rnal Voltage References
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
■
Complete Development Tools
❐
Free Development Software (PSoC
Designer™)
❐
Full Featured In-Circuit Emulator, and Programmer
❐
Full Speed Emulation
❐
Flexible and Functional Breakpoint Structure
❐
128K T race Memory
DIGITAL SYSTEM
SRAM
1K
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Global Digital Interconnect Global Analog Interconnect
PSoC
CORE
CPU Core (M8C)
SROM Flash 16K
Digital
Block
Array
2
MACs
Switch
Mode
Pump
Internal
Voltage
Ref.
Digital
Clocks
POR and LVD
System Resets
4 Type 2
Decimators
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref.
Analog
Input
Muxing
2 I
2
C
Blocks
Port 4 Port 3 Port 2 Port 1 Port 0 Analog
Drivers
System Bus
Analog
Block
Array
Port 5
System Block Diagram
[+] Feedback [+] Feedback
PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 2 of 65
PSoC Functional Overview
The PSoC family consists of many devices with On-Chip
Controllers. These devices are designed to replace multiple
traditional MCU based system components with one low cost
single chip programmable component. A PSo C device includes
configurable analog blocks, digital blocks, and interconnections.
This architecture enables the user to create customized
peripheral configurations to match the requirements of each
individual application. In addition, a fast CPU, Flash program
memory, SRAM data memory , and configurable I/O are included
in a range of convenient pinouts and packages.
The CY8C28xxx group of PSoC devices described in this data
sheet have multiple resource configuration options available.
Therefore, not every resource mentioned in this data sheet is
available for each CY8C28xxx subgroup. The CY8C28x45
subgroup has a full feature set of all resources described. There
are six more segmented subgroups that allow designers to use
a device with only the resources and functionality necessary for
a specific application. See Table 2 on page 6 to determine the
resources available for each CY8C28xxx subgroup. The same
information is also presented in more detail in the Ordering Infor-
mation section.
The architecture for this specific PSoC device family, as shown
in the System Block Diagram on page 1, consists of four main
areas: PSoC Core, Digital System, Analog System, and System
Resources. The configurable global bus system allows all the
device resources to be combined into a complete custom
system. PSoC CY8C28xxx family devices have up to six I/O
ports that connect to the global digital and analog interconnects,
providing access to up to 12 digital blocks and up to 16 analog
blocks.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
general Purpose I/O (GPIO). The M8C CPU core is a powerful
processor with speeds up to 24 MHz, providing a four MIPS 8-bit
Harvard architecture microcontroller.
Memory encompasses 16K bytes of Flash fo r program storag e,
1K bytes of SRAM for data storage. The PSoC device incorpo-
rates flexible internal clock generators, including a 24 MHz
internal main oscillator (IMO) accurate to 2.5% over temperature
and voltage. A low power 32 kHz internal low speed oscillator
(ILO) is provided for the sleep timer and watch dog timer (WDT).
The 32.768 kHz external crystal oscillator (ECO) is available for
use as a real time clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL.
PSoC GPIOs provide connections to the CPU, and digital and
analog resources. Each p in’s drive mode may be selected from
8 options, which allows great flexibility in external interfacing.
Every pin also has the capability to generate a system interrupt
on high level, low level, and change from last read.
The Digital System
The Digital System is composed of up to 12 con figurable d igital
PSoC blocks. Each bl ock is an 8-bit resource that can be used
alone or combined with other blocks to create 8, 16, 24, and
32-bit peripherals, which are called user modules. The digital
blocks can be connected to any GPIO through a series of global
buses that can route any signal to any pin.
Figure 1. Digital System Block Diagram
[1]
Digital peripheral configurations include:
■
PWMs (8 to 16 bit, One-shot and Multi-shot capability)
■
PWMs with Dead band/Kill (8 to 16 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
Full-duplex 8-bit UARTs (up to 3) with selectable parity
■
Half-duplex 8-bit UARTs (up to 6) w ith selectable parity
■
Variable length SPI slave and master
❐
Up to 6 total slaves and masters (8-bit)
❐
Supports 8 to 16 bit operation
■
I
2
C slave, master , or multi-master (up to 2 available as System
Resources)
■
IrDA (up to 3)
■
Pseudo Random Sequence Generators (8 to 32 bit)
■
Cyclical Redundancy Checker/Generator (16 bit)
■
Shift Register (2 to 32 bit)
DIGITAL SYSTEM
To System Bus
Digital Clocks
From Core
Digital PSoC Block Array
To Analog
System
8
88
8
GIE[7:0]
GIO[7:0] Gl obal Digital
Interconnect
Port 4 Port 3 Port 2
Port 1 Port 0
Port 5
GOO[7:0]
GOE[7:0]
Row Input
Configuration
Row 0
DBC00 DBC01 DCC02 DCC03
4
4
Row Output
Configuration
Row 1
DBC10 DBC11 DCC12 DCC13
Row Input
Configuration
4
4
Row Output
Configuration
Row 2
DBC20 DBC21 DCC22 DCC23
Row Input
Configuration
4
4
Row Output
Configuration
Note
1. CY8C28x52 devices do not have digital block row 2. They have two digital rows with eight total digital blocks.
[+] Feedback [+] Feedback
PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 3 of 65
The Analog System
The Analog System is composed of up to 16 configurable analog
blocks, each containing an op amp circuit that allows the creation
of complex analog signal flows. Some devices in this PSoC
family have an analog multiplex bus that can connect to every
GPIO pin. This bus can also connect to the analog system for
analysis with comparators and analog-to-digital converters. It
can be split into two sections for simultaneous dual-channel
processing.
Some of the more common PSoC analog functions (most
available as user modules) are:
■
Analog-to-digital converters (6 to 14-bit resolution, up to 4,
selectable as Incremental or Delta Sigma)
■
Dedicated 10-bit SAR ADC with sample rates up to 192 ksps
■
Synchronized, simultaneous Delta Sigma ADCs (up to 4)
■
Filters (2 to 8 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 4, with selectable gain to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
■
Comparators (up to 6, with 16 selectable thresholds)
■
DACs (up to 4, with 6 to 9-bit resolution)
■
Multiplying DACs (up to 4, with 6 to 9-bit resolution )
■
High current output drivers (up to 4 with 30 mA drive)
■
1.3V reference (as a System Resource)
■
DTMF Dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
Figure 2. Analog System Block Diagram for CY8C28x45 and
CY8C28x52 Devices
ACC00 ACC01
Block Array
Array Input Configuration
ACI1[1:0] ACI2[1:0]
ACC02 ACC03
ASC12 ASD13
ASD22 ASC23ASD20
ACI0[1:0] ACI3[1:0]
P0[6]
P0[4]
P0[2]
P0[0]
P2[2]
P2[0]
P2[6]
P2[4]
RefIn
AGNDIn
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Reference
Generators AGNDIn
RefIn
Bandgap
RefHi
RefLo
AGND
ASD11
ASC21
ASC10
Interface to
Digital System
M8C Interface (Address Bus, Data Bus, Etc.)
Analog Reference
ACE00 ACE01
ASE10 ASE11
Analog Mux
Bus
All GPIO
ACI4[1:0] ACI5[1:0]
[+] Feedback [+] Feedback
PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 4 of 65
Figure 3. Analog System Block Diagram for CY8C28x43
Devices Figure 4. Analog System Block Diagram for CY8C28x33
Devices
ACC00 ACC01
Block Array
Array Input Configuration
ACI1[1:0] ACI2[1:0]
ACC02 ACC03
ASC12 ASD13
ASD22 ASC23ASD20
ACI0[1:0] ACI3[1:0]
P0[6]
P0[4]
P0[2]
P0[0]
P2[2]
P2[0]
P2[6]
P2[4]
RefIn
AGNDIn
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Reference
Generators AGNDIn
RefIn
Bandgap
RefHi
RefLo
AGND
ASD11
ASC21
ASC10
Interface to
Digital Syst em
M8C Interface (Address Bus, Data Bus, Etc.)
Analog Refere nce
Analog Mux
Bus
All GPIO
ACC00 ACC01
Block Array
Array Input Configuration
ACI1[1:0]
ASD20
ACI0[1:0]
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[4]
RefIn
AGNDIn
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Reference
Generators AGNDIn
RefIn
Bandgap
RefHi
RefLo
AGND
ASD11
ASC21
ASC10
Interface to
Digital System
M8C Interface (Address Bus , Data Bus, Etc.)
Analog Reference
ACE00 ACE01
ASE10 ASE11
ACI4[1:0] ACI5[1:0]
Analog Mux
Bus
All GPIO
[+] Feedback [+] Feedback
PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 5 of 65
Figure 5. Analog System Block Diagram for CY8C28x23
Devices Figure 6. Analog System Block Diagram for CY8C28x13
Devices
ACC00 ACC01
Block Array
Array Input
Configuration
ACI1[1:0]
ASD20
ACI0[1:0]
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[4]
RefIn
AGNDIn
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Reference
Generators AGNDIn
RefIn
Bandgap
RefHi
RefLo
AGND
ASD11
ASC21
ASC10
Interface to
Digital System
M8C Interface (Address Bus , Data Bus, Etc.)
Analog Reference
Block Array
Array Input
Configuration
ACI1[1:0]ACI0[1:0]
P0[6]
P0[4]
P0[2]
P0[0]
P0[7]
P0[5]
P0[3]
P0[1]
Reference
Generators AGNDIn
RefIn
Bandgap
RefHi
RefLo
AGND
Interface to
Digital System
M8C Interface (Address Bus, Data Bus, Etc.)
Analog Reference
ACE00 ACE01
ASE10 ASE11
Analog Mux
Bus
All GPIO
[+] Feedback [+] Feedback
PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 6 of 65
System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a multiplier, multiple
decimators, switch mode pump, low voltage detection, and
power on reset. S tatements describing the merits of each system
resource follow:
■
Digital clock dividers provide three customizable clock
frequencies for use in appli cations. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
Multiply accumulate (MAC) provides fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
■
Up to four decimators provide custom hardware filters for digital
signal processing applications such as Delta-Sigma ADCs and
CapSense capacitive sensor measurement.
■
Up to two I
2
C resources provide 0 to 400 kHz communication
over two wires. Slave, master , and multi-master modes are all
supported. I
2
C resources have hardware address dete ction
capability.
■
Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.5V battery cell, providing a
low cost boost converter.
PSoC Device Characteristics
There are other PSoC device groups in addition to the one
described in this data sheet. These other PSoC device groups
offer even more resource options. The following table lists the
resources available for specific PSoC device groups. The PSoC
device group covered by this data sheet is highlighted.
The devices covered by this data sheet all have the same archi-
tecture, specifications, and ratings. However, the amount of
some hardware resources varies from device to device within the
group. The following table lists resources available for the
specific device subgroups covered by this data sheet.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
CY8C29x66 up to
64 416 12 4 4 12 2K 32K
CY8C28xxx up to
44 up to
3up to
12 up to
44 up to
4up to
6up to
12/4
[2]
1K 16K
CY8C27x43 up to
44 2 8 12 4 4 12 256
Bytes 16K
CY8C24x94 64 1 4 48 2 2 6 1K 16K
CY8C24x23A up to
24 1 4 12 2 2 6 256
Bytes 4K
CY8C23x33 up to 1 4 12 2 2 4 256
Bytes 8K
CY8C21x34 up to
28 1428024
[3]
512
Bytes 8K
CY8C21x23 16 1 4 8 0 2 4
[3]
256
Bytes 4K
CY8C20x34 up to
28 0 0 28 0 0 3
[4]
512
Bytes 8K
Table 2. CY8C28 xxx Device Characteristics
PSoC Part
Number
CapSense
Digital
Blocks
Regular
Analog Blocks
Limited
Analog Blocks
HW I
2
C
Decimators
Digital
I/O
Analog
Inputs
Analog
Outputs
CY8C28x03 N 12 0 0 2 0 up to
24 up to
80
CY8C28x13 Y 12 0 4 1 2 up to
40 up to
40 0
CY8C28x23 N 12 6 0 2 2 up to
44 up to
10 2
CY8C28x33 Y 12 6 4 1 4 up to
40 up to
40 2
CY8C28x43 N 12 12 0 2 4 up to
44 up to
44 4
CY8C28x45 Y 12 12 4 2 4 up to
44 up to
44 4
CY8C28x52 Y 8 12 4 1 4 up to
24 up to
24 4
Notes
2. Has 12 regular analog blocks and four limited Type-E analog blocks
3. Limited analog functionality
.
4. Two analog blocks and one CapSense.
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 7 of 65
Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming
details, see the PSoC® Programmable System-on-Chip
Technical Reference Manual for CY8C28xxx PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Libra ry
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various appli-
cation designs that include firmware and hardware design files
that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Development Tools
PSoC Designer is a Microsoft
®
Windows-based, integrated
development environment for the Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE run s
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system leve l view you create a
model of your system inputs, outputs, and communication inter-
faces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
On-Chip Controllers that match your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user module s, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Code Genera tion Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code ge neration tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embed ded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 8 of 65
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and ste p control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Designing with PSoC Designer
The development p rocess for the PSoC de vice differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I
2
C-bus, for example), and the logic to control how they interact
with one another (called valuators).
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application . Enter values directly or
by selecting values from drop-down menu s.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in the PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your desi gn.
Organize and Connect
You can build signal chain s at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan d river and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potenti ometer ’s output to
a digital signal, and a PWM to control the fan .
In the chip-level vi ew, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowin g you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and extern al signals.
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 9 of 65
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 8 on page 31 lists all the abbreviations used to
measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘0100001 1b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only
memory
FSR full scale range
GPIO general purpose I/O
GUI graphical user interface
HBM human body model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
I/O input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision power on reset
PSoC Programmable System-on-Chip
PWM pulse width modulator
SAR successive approximation register
SC switched capacitor
SLIMO slow IMO
SMP switch mode pump
SRAM static random access memory
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 10 of 65
Pinouts
This section describes, lists, and illustrates the CY8C28xxx PSoC device pins and pinout configurations.
The CY8C28xxx PSoC devices are available in a variety of packages which are listed and illustrated in the following tables. Every
port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, SMP, and XRES are not capable of Digital I/O.
20-Pin Part Pinout
Table 3. 20-Pin Part Pinout (SSOP)
Pin
No. Type Pin
Name Description CY8C28243 20-Pin PSoC Device
Digital Analog
1I/O I, M, S P0[7] Analog column mux and SAR ADC
input.
[6]
2I/O I/O, M, S P0[5] Analog column mux and SAR ADC
input. Analog column output.
[6, 7]
3I/O I/O, M, S P0[3] Analog column mux and SAR ADC
input. Analog column output.
[6, 7]
4I/O I, M, S P0[1] Analog column mux and SAR ADC
input.
[6]
5Output SMP Switch Mode Pump (SMP)
connection to external components.
6I/O M P1[7] I2C0 Serial Clock (SCL).
7I/O M P1[5] I2C0 Serial Data (SDA).
8I/O M P1[3]
9I/O M P1[1] Crystal Input (XTALin), I2C0 Serial
Clock (SCL), ISSP-SCLK
[5]
.
10 Power Vss Ground connection.
11 I/O M P1[0] Crystal Output (XTALout), I2C0
Serial Data (SDA), ISSP-SDATA
[5]
.
12 I/O M P1[2] I2C1 Serial Data (SDA).
[8]
13 I/O M P1[4] Optional External Clock Input
(EXTCLK).
14 I/O M P1[6] I2C1 Serial Clock (SCL).
[8]
15 Input XRES Active high external reset with
internal pull down.
16 I/O I, M, S P0[0] Analog column mux and SAR ADC
input.
[6]
17 I/O I/O, M, S P0[2] Analog column mux and SAR ADC
input.
Analog column output.
[6, 9]
18 I/O I/O, M, S P0[4] Analog column mux and SAR ADC
input. Analog column output.
[6, 9]
19 I/O I, M, S P0[6] Analog column mux and SAR ADC
input.
[6]
20 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input.
SSOP
2
1
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Vdd
P0[6], M, AI, S
P0[4], M, AIO, S
P0[2], M, AIO, S
P0[0], M, AI, S
XRES
P1[6], M, I2C1 SCL
P1[4], M, EXTCLK
P1[2], M, I2C1 SDA
P1[0], M, XTALout, I2C0 SDA
S, AI, M, P0[7]
S, AIO, M, P0[5]
S, AIO, M, P0[3]
S, AI, M, P0[1]
SMP
I2C0 SCL, M, P1[7]
I2C0 SDA, M, P1[5]
M, P1[3]
I2C0 SCL, XTALin, M, P1[1]
Vss
Notes
5. These are the IS SP pins, which ar e not High Z at PO R (Power On Reset). Se e the PSoC Programmable System-on-Chip T e chnical Reference Manual for CY8C28xxx
PSoC devices for details.
6. CY8C28x52 and CY8C28x23 devices do not have a SAR ADC. Therefore, this pin does not function as a SAR ADC input for these devices.
7. CY8C28x13 and CY8C28x03 devices do not have any analog output buffers. Therefore, this pin do es not function as an analog column output for these devices.
8. CY8C28x52, CY8C28x13, and CY8C28x33 devices only have one I2C block. Therefore, this GPIO does not function as an I2C pin for these devices.
9. CY8C28x33, CY8C28x23, CY8C28x13, and CY8C28x03 devices do not have an analog output buffer for this pin. Therefore, this pin does not function as an analog
column output for these devices.
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 11 of 65
28-Pin Part Pinout
Table 4. 28-Pin Part Pinout (SSOP)
Pin
No.
Type Pin
Name
Description
CY8C28403, CY8C28413, CY8C28433, CY8C28445, and
CY8C28452 28-Pin PSoC Devices
Digital Analog
1I/O I, M, S P0[7] Analog column mux and SAR ADC
input.
[6]
2I/O I/O, M, S P0[5] Analog column mux and SAR ADC input.
Analog column output.
[6, 7]
3I/O I/O, M, S P0[3] Analog column mux and SAR ADC input.
Analog column output.
[6, 7]
4I/O I, M, S P0[1] Analog column mux and SAR ADC
input.
[6]
5I/O M P2[7]
6I/O M P2[5]
7I/O I, M P2[3] Direct switched capacitor block input.
[10]
8I/O I, M P2[1] Direct switched capacitor block input.
[10]
9Output SMP Switch Mode Pump (SMP) connection to
external components.
10 I/O M P1[7] I2C0 Serial Clock (SCL).
11 I/O M P1[5] I2C0 Serial Data (SDA).
12 I/O M P1[3]
13 I/O M P1[1] Crystal Input (XT ALin), I2C0 Serial Clock
(SCL), ISSP-SCLK
[5]
.
14 Power Vss Ground connection.
15 I/O M P1[0] Crystal Output (XTALout), I2C0 Serial
Data (SDA), ISSP-SDATA
[5]
.
16 I/O M P1[2] I2C1 Serial Data (SDA).
[8]
17 I/O M P1[4] Optional External Clock Input (EXTCLK).
18 I/O M P1[6] I2C1 Serial Clock (SCL).
[8]
19 Input XRES Active high external reset with internal
pull down.
20 I/O I, M P2[0] Direct switched capacitor block input.
[11]
21 I/O I, M P2[2] Direct switched capacitor block input.
[11]
22 I/O M P2[4] External Analog Ground (AGND).
23 I/O M P2[6] External Voltage Reference (VRef).
24 I/O I, M, S P0[0] Analog column mux and SAR ADC
input.
[6]
25 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input.
Analog column output.
[6, 9]
26 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input.
Analog column output.
[6, 9]
27 I/O I, M, S P0[6] Analog column mux and SAR ADC
input.
[6]
28 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Vdd
P0[6], M, AI, S
P0[4], M, AIO, S
P0[2], M, AIO, S
P0[0], M, AI, S
P2[6], M, External VRef
P2[4], M, External AGND
P2[2], M, AI
P2[0], M, AI
XRES
P1[6], M, I2C1 SCL
P1[4], M, EXTCLK
P1[2], M, I2C1 SDA
P1[0], M, XTALout, I2C0 SDA
S, AI, M, P0[7]
S, AIO, M, P0[5]
S, AIO, M, P0[3]
S, AI, M, P0[1]
M, P2[7]
M, P2[5]
AI, M, P2[3]
AI, M, P2[1]
SMP
I2C0 SCL, M, P1[7]
I2C0 SDA, M, P1[5]
M, P1[3]
I2C0 SCL, XTALin, M, P1[ 1 ]
Vss
Notes
10.This pin is not a direct switched capacitor block analog input for CY8C28x03 and CY8C28x13 devices.
11. This pin is not a direct switched capacitor block analog input for CY8C28x03, CY8C28x13, CY8C2 8x23, and CY8C28x33 devices.
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 12 of 65
44-Pin Part Pinout
Table 5. 44-Pin Part Pinout (TQFP)
Pin
No. Type Pin
Name Description
CY8C28513, CY8C28533 , and CY8C28545
44-Pin PSoC Devices
Digital Analog
1I/O M P2[5]
2I/O I, M P2[3] Direct switched capacitor block input.
[10]
3I/O I, M P2[1] Direct switched capacitor block input.
[10]
4I/O M P4[7]
5I/O M P4[5]
6I/O M P4[3]
7I/O M P4[1]
8Output SMP Switch Mode Pump (SMP) connection to
external components.
9I/O M P3[7]
10 I/O M P3[5]
11 I/O M P3[3]
12 I/O M P3[1]
13 I/O M P1[7] I2C0 Serial Clock (SCL).
14 I/O M P1[5] I2C0 Serial Data (SDA).
15 I/O M P1[3]
16 I/O M P1[1] Crystal Input (XTALin), I2C0 Serial Clock
(SCL), ISSP-SCLK
[5]
.
17 Output Vss Ground connection.
18 I/O M P1[0] Crystal Output (XT ALout), I2C0 Serial Data
(SDA), ISSP-SDATA
[5]
.
19 I/O M P1[2] I2C1 Serial Data (SDA).
[8]
20 I/O M P1[4] Optional External Clock Input (EXTC L K).
21 I/O M P1[6] I2C1 Serial Clock (SCL).
[8]
22 I/O M P3[0] I2C1 Serial Data (SDA).
[8]
23 I/O M P3[2] I2C1 Serial Clock (SCL).
[8]
24 I/O M P3[4]
25 I/O M P3[6]
26 Input XRES Active high external reset with internal pull
down.
27 I/O M P4[0]
28 I/O M P4[2]
29 I/O M P4[4]
30 I/O M P4[6]
31 I/O I, M P2[0] Direct switched capacitor block input.
[11]
32 I/O I, M P2[2] Direct switched capacitor block input.
[11]
33 I/O M P2[4] External Analog Ground (AGND).
34 I/O M P2[6] External Voltage Reference (VRef).
35 I/O I, M, S P0[0] Analog column mux and SAR ADC input.
[6]
36 I/O I/O, M S P0[2] Analog column mux and SAR ADC input.
Analog column output.
[6, 9]
37 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input.
Analog column output.
[6, 9]
38 I/O I, M, S P0[6] Analog column mux and SAR ADC input.
[6]
39 Power Vdd Supply voltage.
40 I/O I, M, S P0[7] Analog column mux and SAR ADC input.
[6]
41 I/O I/O, M, S P0[5] Analog column mux and SAR ADC input.
Analog column output.
[6, 7]
42 I/O I/O, M, S P0[3] Analog column mux and SAR ADC input.
Analog column output.
[6, 7]
43 I/O I, M, S P0[1] Analog column mux and SAR ADC input.
[6]
44 I/O P2[7]
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input.
TQFP
44
43
42
41
40
39
38
37
36
35
34
13
14
15
16
17
18
19
20
21
22
12
1
2
3
4
5
6
7
8
9
10
11
M, P2[5]
AI, M, P2[3]
AI, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
SMP
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
I2C0 SCL, M, P1[7]
I2C0 SDA, M, P1[5]
M, P1[3]
I2C0 SCL, XTALin, M, P1[1]
Vss
I2C0 SDA, XTALo ut , M, P1[0]
I2C1 SDA, M, P1[2]
EXTCLK, M, P1[4]
I2C1 SCL, M, P1[6]
I2C1 SDA, M, P3[0]
P2[4], M, External AGND
P2[2], M, AI
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
P3[6], M
P3[4], M
P3[2], M, I2C1 SCL
P2[7], M
P0[1], M, AI, S
P0[3], M, AIO, S
P0[5], M, AIO, S
P0[7], M, AI, S
Vdd
P0[6], M, AI, S
P0[4], M, AIO, S
P0[2], M, AIO, S
P0[0], M, AI, S
P2[6], M, External VRef
33
32
31
30
29
28
27
26
25
24
23
[+] Feedback [+] Feedback
PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 13 of 65
48-Pin Part Pinout
Tab le 6. 48-Pin Part Pinout (QFN
[12]
)
Pin
No. Type Pin
Name Description
CY8C28623, CY8C28643, and CY8C28 645
48-Pin PSoC Devices
Digital Analog
1I/O I, M P2[3] Direct switched capacitor block input.
[10]
2I/O I, M P2[1] Direct switched capacitor block input.
[10]
3I/O M P4[7]
4I/O M P4[5]
5I/O M P4[3]
6I/O M P4[1]
7Output SMP Switch Mode Pump (SMP) connection to
external components.
8I/O M P3[7]
9I/O M P3[5]
10 I/O M P3[3]
11 I/O M P3[1]
12 I/O M P5[3]
13 I/O M P5[1]
14 I/O M P1[7] I2C0 Serial Clock (SCL).
15 I/O M P1[5] I2C0 Serial Data (SDA).
16 I/O M P1[3]
17 I/O M P1[1] Crystal Input (XTALin), I2C0 Serial Clock
(SCL), ISSP-SCLK
[5]
.
18 Power Vss Ground connection.
19 I/O M P1[0] Crystal Output (XTALout), I2C0 Serial
Data (SDA), ISSP-SDATA
[5]
.
20 I/O M P1[2] I2C1 Serial Data (SDA).
[8]
21 I/O M P1[4] Optional External Clock Input
(EXTCLK).
22 I/O M P1[6] I2C1 Serial Clock (SCL).
[8]
23 I/O M P5[0]
24 I/O M P5[2]
25 I/O M P3[0] I2C1 Serial Data (SDA).
[8]
26 I/O M P3[2] I2C1 Serial Clock (SCL).
[8]
27 I/O M P3[4]
28 I/O M P3[6]
29 Input XRES Active high external reset with internal
pull down.
30 I/O M P4[0]
31 I/O M P4[2] Pin
No. Type Pin
Name Description
32 I/O M P4[4] Digital Analog
33 I/O M P4[6] 41 I/O I, M, S P0[6] Analog column mux and SAR ADC
input.
[6]
34 I/O I, M P2[0] Direct switched capacitor block input.
[11]
42 Power Vdd Supply voltage.
35 I/O I, M P2[2] Direct switched capacitor block input.
[11]
43 I/O I, M, S P0[7] Analog column mux and SAR ADC
input.
[6]
36 I/O M P2[4] External Analog Ground (AGND). 44 I/O I/O, M,
SP0[5] Analog column mux and SAR ADC
input. Analog column output.
[6, 7]
37 I/O M P2[6] External Voltage Reference (VRef). 45 I/O I/O, M,
SP0[3] Analog column mux and SAR ADC
input. Analog column output.
[6, 7]
38 I/O I, M, S P0[0] Analog column mux and SAR ADC
input.
[6]
46 I/O I, M, S P0[1] Analog column mux and SAR ADC
input.
[6]
39 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input.
Analog column output.
[6, 9]
47 I/O M P2[7]
40 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input.
Analog column output.
[6, 9]
48 I/O M P2[5]
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input.
13
14
15
16
17
18
19
20
21
22
23
24
P2[5], M
P2[7], M
P0[1], M, AI, S
P0[3], M, AIO, S
P0[5], M, AIO, S
P0[7], M, AI, S
Vdd
P0[6], M, AI, S
P0[4], M, AIO, S
P0[2], M, AIO, S
P0[0], M, AI, S
P2[6], M, External VRef
M, P5[1]
I2C0 SCL, M, P1[7]
I2C0 SDA, M, P1[5]
M, P1[3]
I2C0 SCL, XTALin, M, P1[1]
Vss
I2C0 SDA, XTALout, M, P1[0]
I2C1 SDA, M, P1[2]
EXTCLK, M, P1[4]
I2C1 SCL, M, P1[6]
M, P5[0]
M, P5[2]
AI, M, P2[3]
AI, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
SMP
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[3]
35
34
33
32
31
30
29
28
27
26
25
36
48
47
46
45
44
43
42
41
40
39
38
37
10
11
12
1
2
3
4
5
6
7
8
9
QFN
(Top View)
P2[2], M, AI
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
P3[6], M
P3[4], M
P3[2], M, I2C1 SCL
P3[0], M, I2C1 SDA
P2[4], M, External AGND
Note
12.The QFN package has a center pad that must be connected to ground (Vss)
[+] Feedback [+] Feedback
PRELIMINARY CY8C28xxx
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56-Pin Part Pinout
The 56-pin SSOP part is for the CY8C28000 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 7. 56-Pin Part Pinout (SSOP)
Pin
No. Type Pin
Name Description
CY8C28000 56-Pin PSoC Device
Not for Production
Digital Analog
1NC No connection.
2I/O I, M, S P0[7] Analog column mux and SAR ADC input.
3I/O I/O, M, S P0[5] Analog column mux and SAR ADC input.
Analog column output.
4I/O I/O, M, S P0[3] Analog column mux and SAR ADC input.
Analog column output.
5I/O I, M, S P0[1] Analog column mux and SAR ADC input.
6I/O MP2[7]
7I/O MP2[5]
8I/O I P2[3] Direct switched capacitor block input.
9I/O I P2[1] Direct switched capacitor block input.
10 I/O MP4[7]
11 I/O MP4[5]
12 I/O I, M P4[3]
13 I/O I, M P4[1]
14 OCD M OCDE OCD even data I/O.
15 OCD M OCDO OCD odd data output.
16 Output SMP Switch Mode Pump (SMP) connection to
required external components.
17 I/O MP3[7]
18 I/O MP3[5]
19 I/O MP3[3]
20 I/O MP3[1]
21 I/O MP5[3]
22 I/O MP5[1]
23 I/O M P1[7] I2C0 Serial Clock (SCL).
24 I/O M P1[5] I2C0 Serial Da ta (SDA).
25 NC No connection.
26 I/O MP1[3]
27 I/O M P1[1] Crystal Input (XT ALin), I2C0 Serial Clock
(SCL), ISSP-SCLK
[5]
.
28 Power Vdd Ground conne ction.
29 NC No connection.
30 NC No connection.
31 I/O M P1[0] Crystal Output (XTALout), I2C0 Serial
Data (SDA), ISSP-SDATA
[5]
.
32 I/O M P1[2] I2C1 Seria l Data (SDA).
33 I/O M P1[4] Optional External Clock Input (EXTCLK).
34 I/O MP1[6]I2C1 Serial Clock (SCL).
35 I/O MP5[0]
36 I/O MP5[2]
37 I/O M P3[0] I2C1 Seria l Data (SDA).
38 I/O M P3[2] I2C1 Serial Clock (SCL).
39 I/O MP3[4]
40 I/O MP3[6]
SSOP
8
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
OCDE
OCDO
SMP
I2C0 SCL, M, P1[7]
NC
Vss
S, AI, M, P0[7]
S, AIO, M, P0[ 5]
S, AIO, M, P0[ 3]
AI, M, P2[3]
S, AI, M, P0[1]
M, P2[5]
M, P2[7]
AI, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
M, P3[7]
M, P5[1]
M, P5[3]
M, P3[1]
M, P3[3]
M, P3[5]
I2C0 SDA, M, P1[5]
M, P1[3]
SCLK, I2C0 SCL, XTALIn, M, P1[1]
Vdd
CCLK
HCLK
XRES
NC
NC
P1[6], M, I2C1 SCL
P1[2], M, I2C1 SDA
P0[6], M, AI, S
P0[4], M, AIO, S
P0[2], M, AIO, S
P2[2], M, AI
P0[0], M, AI, S
P2[4], M, External AGND
P2[6], M, External VRef
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
P3[6], M
P5[0], M
P5[2], M
P3[0], M, I2C1 SDA
P3[2], M, I2C1 SCL
P3[4], M
P1[4], M, EXTCLK
P1[0], M, XTALOut, I2C0 SDA, SDATA
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 15 of 65
Pin
No. Type Pin
Name Description
Digital Analog
41 Input XRES Active high external reset with internal
pull down.
42 OCD M HCLK OCD high-speed clock output.
43 OCD M CCLK OCD CPU clock output.
44 I/O MP4[0]
45 I/O MP4[2]
46 I/O MP4[4]
47 I/O MP4[6]
48 I/O I, M P2[0] Direct switched capacitor block input.
49 I/O I, M P2[2] Direct switched capacitor block input.
50 I/O M P2[4] External Analog Ground (AGND).
51 I/O M P2[6] External Voltage Reference (VRef).
52 I/O I, M, S P0[0] Analog column mux and SAR ADC input.
53 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input.
Analog column output.
54 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input.
Analog column output.
55 I/O I, M, S P0[6] Analog column mux and SAR ADC input.
56 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, M = Analog Mux Bus Input, and OCD = On-Chip Debug.
Table 7. 56-Pin Part Pinout (SSOP) (continued)
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 16 of 65
Register Reference
This section lists the registers of the CY8C28xxx PSoC devices. For detailed register information, reference the
PSoC Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices.
Register Conventions
The register conventions specific to this section are listed in the
following table.
Register Mapping Tables
CY8C28xxx PSoC devices have a total register address space
of 512 bytes. The register space is referred to as I/O space and
is divided into two banks. The XIO bit in the Flag register
(CPU_F) determines which bank of registers CPU instructions
access. When the XIO bit is set the registers in Bank 1 are
accessed by CPU instructions. When the XIO bit is cle ared the
registers in Bank 0 are accessed by CPU instructions.
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
Convention Description
R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 17 of 65
CY8C28x03 Register Map Bank 0 Table: User Space
Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW DBC20DR0 40 # 80 RDI2RI C0 RW
PRT0IE 01 RW DBC20DR1 41 W 81 RDI2SYN C1 RW
PRT0GS 02 RW DBC20DR2 42 RW 82 RDI2IS C2 RW
PRT0DM2 03 RW DBC20CR0 43 # 83 RDI2LT0 C3 RW
PRT1DR 04 RW DBC21DR0 44 # 84 RDI2LT1 C4 RW
PRT1IE 05 RW DBC21DR1 45 W 85 RDI2RO0 C5 RW
PRT1GS 06 RW DBC21DR2 46 RW 86 RDI2RO1 C6 RW
PRT1DM2 07 RW DBC21CR0 47 # 87 RDI2DSM C7 RW
PRT2DR 08 RW DCC22DR0 48 # 88 C8
PRT2IE 09 RW DCC22DR1 49 W 89 C9
PRT2GS 0A RW DCC22DR2 4A RW 8A CA
PRT2DM2 0B RW DCC22CR0 4B # 8B CB
PRT3DR 0C RW DCC23DR0 4C # 8C CC
PRT3IE 0D RW DCC23DR1 4D W 8D CD
PRT3GS 0E RW DCC23DR2 4E RW 8E CE
PRT3DM2 0F RW DCC23CR0 4F # 8F CF
PRT4DR 10 RW 50 90 CUR_PP D0 RW
PRT4IE 11 RW 51 91 STK_PP D1 RW
PRT4GS 12 RW 52 92 D2
PRT4DM2 13 RW 53 93 IDX_PP D3 RW
PRT5DR 14 RW 54 94 MVR_PP D4 RW
PRT5IE 15 RW 55 95 MVW_PP D5 RW
PRT5GS 16 RW 56 96 I2C0_CFG D6 RW
PRT5DM2 17 RW 57 97 I2C0_SCR D7 #
18 58 98 I2C0_DR D8 RW
19 59 99 I2C0_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C INT_CLR2 DC RW
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F INT_MSK2 DF RW
DBC00DR0 20 # 60 A0 INT_MSK0 E0 RW
DBC00DR1 21 W 61 A1 INT_MSK1 E1 RW
DBC00DR2 22 RW 62 A2 INT_VC E2 RC
DBC00CR0 23 # 63 A3 RES_WDT E3 W
DBC01DR0 24 # 64 A4 I2C1_SCR E4 #
DBC01DR1 25 W 65 A5 I2C1_MSCR E5 #
DBC01DR2 26 RW 66 A6 E6
DBC01CR0 27 # I2C1_DR 67 RW A7 E7
DCC02DR0 28 # 68 MUL1_X A8 WMUL0_X E8 W
DCC02DR1 29 W 69 MUL1_Y A9 WMUL0_Y E9 W
DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA RMUL0_DH EA R
DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB RMUL0_DL EB R
DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
DBC10DR0 30 # 70 RDI0RI B0 RW F0
DBC10DR1 31 W 71 RDI0SYN B1 RW F1
DBC10DR2 32 RW 72 RDI0IS B2 RW F2
DBC10CR0 33 # 73 RDI0LT0 B3 RW F3
DBC11DR0 34 # 74 RDI0LT1 B4 RW F4
DBC11DR1 35 W 75 RDI0RO0 B5 RW F5
DBC11DR2 36 RW 76 RDI0RO1 B6 RW F6
DBC11CR0 37 # 77 RDI0DSM B7 RW CPU_F F7 RL
DCC12DR0 38 # 78 RDI1RI B8 RW F8
DCC12DR1 39 W 79 RDI1SYN B9 RW F9
DCC12DR2 3A RW 7A RDI1IS BA RW FA
DCC12CR0 3B # 7B RDI1LT0 BB RW FB
DCC13DR0 3C # 7C RDI1LT1 BC RW FC
DCC13DR1 3D W 7D RDI1RO0 BD RW FD
DCC13DR2 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR0 3F # 7F RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 18 of 65
CY8C28x03
Register Map Bank 1 Table: Configuration Space
Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW DBC20FN 40 RW 80 RDI2RI C0 RW
PRT0DM1 01 RW DBC20IN 41 RW SADC_TSCMPL 81 RW RDI2SYN C1 RW
PRT0IC0 02 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RDI2IS C2 RW
PRT0IC1 03 RW DBC20CR1 43 RW 83 RDI2LT0 C3 RW
PRT1DM0 04 RW DBC21FN 44 RW 84 RDI2LT1 C4 RW
PRT1DM1 05 RW DBC21IN 45 RW 85 RDI2RO0 C5 RW
PRT1IC0 06 RW DBC21OU 46 RW 86 RDI2RO1 C6 RW
PRT1IC1 07 RW DBC21CR1 47 RW 87 RDI2DSM C7 RW
PRT2DM0 08 RW DCC22FN 48 RW 88 C8
PRT2DM1 09 RW DCC22IN 49 RW 89 C9
PRT2IC0 0A RW DCC22OU 4A RW 8A CA
PRT2IC1 0B RW DCC22CR1 4B RW 8B CB
PRT3DM0 0C RW DCC23FN 4C RW 8C CC
PRT3DM1 0D RW DCC23IN 4D RW 8D CD
PRT3IC0 0E RW DCC23OU 4E RW 8E CE
PRT3IC1 0F RW DCC23CR1 4F RW 8F CF
PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW
PRT4DM1 11 RW 51 91 GDI_E_IN D1 RW
PRT4IC0 12 RW 52 92 GDI_O_OU D2 RW
PRT4IC1 13 RW 53 93 GDI_E_OU D3 RW
PRT5DM0 14 RW 54 94 D4
PRT5DM1 15 RW 55 95 D5
PRT5IC0 16 RW 56 96 D6
PRT5IC1 17 RW 57 97 D7
18 58 98 D8
19 59 99 D9
1A 5A 9A DA
1B 5B 9B DB
1C 5C 9C DC
1D 5D 9D OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBC00FN 20 RW 60 GDI_O_IN_CR A0 RW OSC_CR0 E0 RW
DBC00IN 21 RW 61 GDI_E_IN_CR A1 RW OSC_CR1 E1 RW
DBC00OU 22 RW 62 GDI_O_OU_CR A2 RW OSC_CR2 E2 RW
DBC00CR1 23 RW 63 GDI_E_OU_CR A3 RW VLT_CR E3 RW
DBC01FN 24 RW 64 RTC_H A4 RW VLT_CMP E4 RW
DBC01IN 25 RW 65 RTC_M A5 RW E5
DBC01OU 26 RW 66 RTC_S A6 RW E6
DBC01CR1 27 RW 67 RTC_CR A7 RW E7
DCC02FN 28 RW 68 SADC_CR0 A8 RW IMO_TR E8 RW
DCC02IN 29 RW 69 SADC_CR1 A9 RW ILO_TR E9 RW
DCC02OU 2A RW 6A SADC_CR2 AA RW BDG_TR EA RW
DCC02CR1 2B RW I2C1_CFG 6B RW SADC_CR3 AB RW ECO_TR EB RW
DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW EC
DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW ED
DCC03OU 2E RW TMP_DR2 6E RW I2C1_ADDR AE RW EE
DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF
DBC10FN 30 RW 70 RDI0RI B0 RW F0
DBC10IN 31 RW SADC_TSCR0 71 RW RDI0SYN B1 RW F1
DBC10OU 32 RW SADC_TSCR1 72 RW RDI0IS B2 RW F2
DBC10CR1 33 RW 73 RDI0LT0 B3 RW F3
DBC11FN 34 RW 74 RDI0LT1 B4 RW F4
DBC11IN 35 RW 75 RDI0RO0 B5 RW F5
DBC11OU 36 RW 76 RDI0RO1 B6 RW F6
DBC11CR1 37 RW 77 RDIODSM B7 RW CPU_F F7 RL
DCC12FN 38 RW 78 RDI1RI B8 RW F8
DCC12IN 39 RW 79 RDI1SYN B9 RW F9
DCC12OU 3A RW 7A RDI1IS BA RW FLS_PR1 FA RW
DCC12CR1 3B RW 7B RDI1LT0 BB RW FB
DCC13FN 3C RW 7C RDI1LT1 BC RW FC
DCC13IN 3D RW 7D RDI1RO0 BD RW FD
DCC13OU 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR1 3F RW 7F RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be ac cessed. # Access is bit specific. *Addre ss has a dual purpose, se e “Mapping Exceptions” on page 251
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 19 of 65
CY8C28x13 Register Map Ba nk 0 Table: User Space
Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW DBC20DR0 40 # 80 RDI2RI C0 RW
PRT0IE 01 RW DBC20DR1 41 W 81 RDI2SYN C1 RW
PRT0GS 02 RW DBC20DR2 42 RW 82 RDI2IS C2 RW
PRT0DM2 03 RW DBC20CR0 43 # 83 RDI2LT0 C3 RW
PRT1DR 04 RW DBC21DR0 44 # 84 RDI2LT1 C4 RW
PRT1IE 05 RW DBC21DR1 45 W 85 RDI2RO0 C5 RW
PRT1GS 06 RW DBC21DR2 46 RW 86 RDI2RO1 C6 RW
PRT1DM2 07 RW DBC21CR0 47 # 87 RDI2DSM C7 RW
PRT2DR 08 RW DCC22DR0 48 # 88 C8
PRT2IE 09 RW DCC22DR1 49 W 89 C9
PRT2GS 0A RW DCC22DR2 4A RW 8A CA
PRT2DM2 0B RW DCC22CR0 4B # 8B CB
PRT3DR 0C RW DCC23DR0 4C # 8C CC
PRT3IE 0D RW DCC23DR1 4D W 8D CD
PRT3GS 0E RW DCC23DR2 4E RW 8E CE
PRT3DM2 0F RW DCC23CR0 4F # 8F CF
PRT4DR 10 RW 50 90 CUR_PP D0 RW
PRT4IE 11 RW 51 91 STK_PP D1 RW
PRT4GS 12 RW 52 92 D2
PRT4DM2 13 RW 53 93 IDX_PP D3 RW
PRT5DR 14 RW 54 94 MVR_PP D4 RW
PRT5IE 15 RW 55 95 MVW_PP D5 RW
PRT5GS 16 RW 56 96 I2C0_CFG D6 RW
PRT5DM2 17 RW 57 97 I2C0_SCR D7 #
18 58 98 I2C0_DR D8 RW
19 59 99 I2C0_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C INT_CLR2 DC RW
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F INT_MSK2 DF RW
DBC00DR0 20 # 60 DEC0_DH A0 RC INT_MSK0 E0 RW
DBC00DR1 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW
DBC00DR2 22 RW 62 DEC1_DH A2 RC INT_VC E2 RC
DBC00CR0 23 # 63 DEC1_DL A3 RC RES_WDT E3 W
DBC01DR0 24 # 64 A4 E4
DBC01DR1 25 W 65 A5 E5
DBC01DR2 26 RW 66 A6 DEC_CR0* E6 RW
DBC01CR0 27 # 67 A7 DEC_CR1* E7 RW
DCC02DR0 28 # 68 MUL1_X A8 WMUL0_X E8 W
DCC02DR1 29 W 69 MUL1_Y A9 WMUL0_Y E9 W
DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA RMUL0_DH EA R
DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB RMUL0_DL EB R
DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
DBC10DR0 30 # 70 RDI0RI B0 RW F0
DBC10DR1 31 W 71 RDI0SYN B1 RW F1
DBC10DR2 32 RW 72 RDI0IS B2 RW F2
DBC10CR0 33 # 73 RDI0LT0 B3 RW F3
DBC11DR0 34 # 74 RDI0LT1 B4 RW F4
DBC11DR1 35 W 75 RDI0RO0 B5 RW F5
DBC11DR2 36 RW 76 RDI0RO1 B6 RW F6
DBC11CR0 37 # 77 RDI0DSM B7 RW CPU_F F7 RL
DCC12DR0 38 # 78 RDI1RI B8 RW F8
DCC12DR1 39 W 79 RDI1SYN B9 RW F9
DCC12DR2 3A RW 7A RDI1IS BA RW FA
DCC12CR0 3B # 7B RDI1LT0 BB RW FB
DCC13DR0 3C # 7C RDI1LT1 BC RW DAC1_D FC RW
DCC13DR1 3D W 7D RDI1RO0 BD RW DAC0_D FD RW
DCC13DR2 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR0 3F # 7F RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 20 of 65
CY8C28x13 Register Map Bank 1 Table: Configuration Space
Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW DBC20FN 40 RW 80 RDI2RI C0 RW
PRT0DM1 01 RW DBC20IN 41 RW SADC_TSCMPL 81 RW RDI2SYN C1 RW
PRT0IC0 02 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RDI2IS C2 RW
PRT0IC1 03 RW DBC20CR1 43 RW ACE_AMD_CR1 83 RW RDI2LT0 C3 RW
PRT1DM0 04 RW DBC21FN 44 RW 84 RDI2LT1 C4 RW
PRT1DM1 05 RW DBC21IN 45 RW ACE_PWM_CR 85 RW RDI2RO0 C5 RW
PRT1IC0 06 RW DBC21OU 46 RW ACE_ADC0_CR 86 RW RDI2RO1 C6 RW
PRT1IC1 07 RW DBC21CR1 47 RW ACE_ADC1_CR 87 RW RDI2DSM C7 RW
PRT2DM0 08 RW DCC22FN 48 RW 88 C8
PRT2DM1 09 RW DCC22IN 49 RW ACE_CLK_CR0 89 RW C9
PRT2IC0 0A RW DCC22OU 4A RW ACE_CLK_CR1 8A RW CA
PRT2IC1 0B RW DCC22CR1 4B RW ACE_CLK_CR3 8B RW CB
PRT3DM0 0C RW DCC23FN 4C RW 8C RW CC
PRT3DM1 0D RW DCC23IN 4D RW ACE01CR1 8D RW CD
PRT3IC0 0E RW DCC23OU 4E RW ACE01CR2 8E RW CE
PRT3IC1 0F RW DCC23CR1 4F RW ASE11CR0 8F RW CF
PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW
PRT4DM1 11 RW 51 DEC0_CR0 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW 52 DEC_CR3 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW 53 93 GDI_E_OU D3 RW
PRT5DM0 14 RW 54 94 DEC0_CR D4 RW
PRT5DM1 15 RW 55 DEC1_CR0 95 RW DEC1_CR D5 RW
PRT5IC0 16 RW 56 96 D6
PRT5IC1 17 RW 57 97 D7
18 58 98 MUX_CR0 D8 RW
19 59 99 MUX_CR1 D9 RW
1A 5A DEC_CR5 9A RW MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW
1C 5C 9C IDAC_CR1 DC RW
1D 5D 9D OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBC00FN 20 RW 60 GDI_O_IN_CR A0 RW OSC_CR0 E0 RW
DBC00IN 21 RW 61 GDI_E_IN_CR A1 RW OSC_CR1 E1 RW
DBC00OU 22 RW 62 GDI_O_OU_CR A2 RW OSC_CR2 E2 RW
DBC00CR1 23 RW 63 GDI_E_OU_CR A3 RW VLT_CR E3 RW
DBC01FN 24 RW 64 RTC_H A4 RW VLT_CMP E4 RW
DBC01IN 25 RW 65 RTC_M A5 RW ADC0_TR E5 RW
DBC01OU 26 RW 66 RTC_S A6 RW ADC1_TR E6 RW
DBC01CR1 27 RW 67 RTC_CR A7 RW IDAC_CR2 E7 RW
DCC02FN 28 RW 68 SADC_CR0 A8 RW IMO_TR E8 RW
DCC02IN 29 RW 69 SADC_CR1 A9 RW ILO_TR E9 RW
DCC02OU 2A RW AMUX_CFG1 6A RW SADC_CR2 AA RW BDG_TR EA RW
DCC02CR1 2B RW 6B SADC_CR3 AB RW ECO_TR EB RW
DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW MUX_CR4 EC RW
DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW MUX_CR5 ED RW
DCC03OU 2E RW TMP_DR2 6E RW AE EE
DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF
DBC10FN 30 RW 70 RDI0RI B0 RW F0
DBC10IN 31 RW SADC_TSCR0 71 RW RDI0SYN B1 RW F1
DBC10OU 32 RW SADC_TSCR1 72 RW RDI0IS B2 RW F2
DBC10CR1 33 RW ACE_AMD_CR0 73 RW RDI0LT0 B3 RW F3
DBC11FN 34 RW 74 RW RDI0LT1 B4 RW F4
DBC11IN 35 RW ACE_AMX_IN 75 RW RDI0RO0 B5 RW F5
DBC11OU 36 RW ACE_CMP_CR0 76 RW RDI0RO1 B6 RW F6
DBC11CR1 37 RW ACE_CMP_CR1 77 RW RDIODSM B7 RW CPU_F F7 RL
DCC12FN 38 RW 78 RDI1RI B8 RW F8
DCC12IN 39 RW ACE_CMP_GI_EN 79 RW RDI1SYN B9 RW F9
DCC12OU 3A RW ACE_ALT_CR0 7A RW RDI1IS BA RW FLS_PR1 FA RW
DCC12CR1 3B RW ACE_ABF_CR0 7B RW RDI1LT0 BB RW FB
DCC13FN 3C RW 7C RDI1LT1 BC RW FC
DCC13IN 3D RW ACE0_CR1 7D RW RDI1RO0 BD RW IDAC_CR0 FD RW
DCC13OU 3E RW ACE0_CR2 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR1 3F RW ACE0_CR3 7F RW RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be ac cessed. # Access is bit specific. *Addre ss has a dual purpose, se e “Mapping Exceptions” on page 251
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 21 of 65
CY8C28x23 Register Map Ba nk 0 Table: User Space
Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW DBC20DR0 40 # ASC10CR0 80 RW RDI2RI C0 RW
PRT0IE 01 RW DBC20DR1 41 W ASC10CR1 81 RW RDI2SYN C1 RW
PRT0GS 02 RW DBC20DR2 42 RW ASC10CR2 82 RW RDI2IS C2 RW
PRT0DM2 03 RW DBC20CR0 43 # ASC10CR3 83 RW RDI2LT0 C3 RW
PRT1DR 04 RW DBC21DR0 44 # ASD11CR0 84 RW RDI2LT1 C4 RW
PRT1IE 05 RW DBC21DR1 45 W ASD11CR1 85 RW RDI2RO0 C5 RW
PRT1GS 06 RW DBC21DR2 46 RW ASD11CR2 86 RW RDI2RO1 C6 RW
PRT1DM2 07 RW DBC21CR0 47 # ASD11CR3 87 RW RDI2DSM C7 RW
PRT2DR 08 RW DCC22DR0 48 # 88 C8
PRT2IE 09 RW DCC22DR1 49 W 89 C9
PRT2GS 0A RW DCC22DR2 4A RW 8A CA
PRT2DM2 0B RW DCC22CR0 4B # 8B CB
PRT3DR 0C RW DCC23DR0 4C # 8C CC
PRT3IE 0D RW DCC23DR1 4D W 8D CD
PRT3GS 0E RW DCC23DR2 4E RW 8E CE
PRT3DM2 0F RW DCC23CR0 4F # 8F CF
PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW
PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW
PRT4GS 12 RW 52 ASD20CR2 92 RW D2
PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW
PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW
PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW
PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW
PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 #
18 58 98 I2C0_DR D8 RW
19 59 99 I2C0_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C INT_CLR2 DC RW
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F INT_MSK2 DF RW
DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW
DBC00DR1 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW
DBC00DR2 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC
DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W
DBC01DR0 24 # CMP_CR0 64 # A4 I2C1_SCR E4 #
DBC01DR1 25 W ASY_CR 65 # A5 I2C1_MSCR E5 #
DBC01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0* E6 RW
DBC01CR0 27 # I2C1_DR 67 RW A7 DEC_CR1* E7 RW
DCC02DR0 28 # 68 MUL1_X A8 WMUL0_X E8 W
DCC02DR1 29 W 69 MUL1_Y A9 WMUL0_Y E9 W
DCC02DR2 2A RW 6A MUL1_DH AA RMUL0_DH EA R
DCC02CR0 2B # 6B MUL1_DL AB RMUL0_DL EB R
DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0
DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1
DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2
DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3
DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4
DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5
DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6
DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW CPU_F F7 RL
DCC12DR0 38 # 78 RDI1RI B8 RW F8
DCC12DR1 39 W 79 RDI1SYN B9 RW F9
DCC12DR2 3A RW 7A RDI1IS BA RW FA
DCC12CR0 3B # 7B RDI1LT0 BB RW FB
DCC13DR0 3C # 7C RDI1LT1 BC RW FC
DCC13DR1 3D W 7D RDI1RO0 BD RW FD
DCC13DR2 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR0 3F # 7F RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 22 of 65
CY8C28x23 Register Map Bank 1 Table: Configuration Space
Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW DBC20FN 40 RW 80 RDI2RI C0 RW
PRT0DM1 01 RW DBC20IN 41 RW 81 RDI2SYN C1 RW
PRT0IC0 02 RW DBC20OU 42 RW 82 RDI2IS C2 RW
PRT0IC1 03 RW DBC20CR1 43 RW 83 RDI2LT0 C3 RW
PRT1DM0 04 RW DBC21FN 44 RW 84 RDI2LT1 C4 RW
PRT1DM1 05 RW DBC21IN 45 RW 85 RDI2RO0 C5 RW
PRT1IC0 06 RW DBC21OU 46 RW 86 RDI2RO1 C6 RW
PRT1IC1 07 RW DBC21CR1 47 RW 87 RDI2DSM C7 RW
PRT2DM0 08 RW DCC22FN 48 RW 88 C8
PRT2DM1 09 RW DCC22IN 49 RW 89 C9
PRT2IC0 0A RW DCC22OU 4A RW 8A CA
PRT2IC1 0B RW DCC22CR1 4B RW 8B CB
PRT3DM0 0C RW DCC23FN 4C RW 8C CC
PRT3DM1 0D RW DCC23IN 4D RW 8D CD
PRT3IC0 0E RW DCC23OU 4E RW 8E CE
PRT3IC1 0F RW DCC23CR1 4F RW 8F CF
PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW
PRT4DM1 11 RW 51 DEC0_CR0 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW 52 DEC_CR3 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW 53 93 RW GDI_E_OU D3 RW
PRT5DM0 14 RW 54 94 RW DEC0_CR D4 RW
PRT5DM1 15 RW 55 DEC1_CR0 95 RW DEC1_CR D5 RW
PRT5IC0 16 RW 56 96 D6
PRT5IC1 17 RW 57 97 D7
18 58 98 D8
19 59 99 D9
1A 5A DEC_CR5 9A RW DA
1B 5B 9B DB
1C 5C 9C DC
1D 5D 9D OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW
DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW
DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW
DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW
DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW
DBC01IN 25 RW 65 RTC_M A5 RW E5
DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW E6
DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW E7
DCC02FN 28 RW 68 A8 IMO_TR E8 RW
DCC02IN 29 RW CLK_CR2 69 RW A9 ILO_TR E9 RW
DCC02OU 2A RW 6A AA BDG_TR EA RW
DCC02CR1 2B RW I2C1_CFG 6B RW AB ECO_TR EB RW
DCC03FN 2C RW TMP_DR0 6C RW AC EC
DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW ED
DCC03OU 2E RW TMP_DR2 6E RW I2C1_ADDR AE RW EE
DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF
DBC10FN 30 RW 70 RDI0RI B0 RW F0
DBC10IN 31 RW 71 RDI0SYN B1 RW F1
DBC10OU 32 RW 72 RDI0IS B2 RW F2
DBC10CR1 33 RW 73 RDI0LT0 B3 RW F3
DBC11FN 34 RW 74 RDI0LT1 B4 RW F4
DBC11IN 35 RW 75 RDI0RO0 B5 RW F5
DBC11OU 36 RW 76 RDI0RO1 B6 RW F6
DBC11CR1 37 RW 77 RDIODSM B7 RW CPU_F F7 RL
DCC12FN 38 RW 78 RDI1RI B8 RW F8
DCC12IN 39 RW 79 RDI1SYN B9 RW F9
DCC12OU 3A RW 7A RDI1IS BA RW FLS_PR1 FA RW
DCC12CR1 3B RW 7B RDI1LT0 BB RW FB
DCC13FN 3C RW 7C RDI1LT1 BC RW FC
DCC13IN 3D RW 7D RDI1RO0 BD RW FD
DCC13OU 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR1 3F RW 7F RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be ac cessed. # Access is bit specific. *Addre ss has a dual purpose, se e “Mapping Exceptions” on page 251
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 23 of 65
CY8C28x33 Register Map Ba nk 0 Table: User Space
Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW DBC20DR0 40 # ASC10CR0 80 RW RDI2RI C0 RW
PRT0IE 01 RW DBC20DR1 41 W ASC10CR1 81 RW RDI2SYN C1 RW
PRT0GS 02 RW DBC20DR2 42 RW ASC10CR2 82 RW RDI2IS C2 RW
PRT0DM2 03 RW DBC20CR0 43 # ASC10CR3 83 RW RDI2LT0 C3 RW
PRT1DR 04 RW DBC21DR0 44 # ASD11CR0 84 RW RDI2LT1 C4 RW
PRT1IE 05 RW DBC21DR1 45 W ASD11CR1 85 RW RDI2RO0 C5 RW
PRT1GS 06 RW DBC21DR2 46 RW ASD11CR2 86 RW RDI2RO1 C6 RW
PRT1DM2 07 RW DBC21CR0 47 # ASD11CR3 87 RW RDI2DSM C7 RW
PRT2DR 08 RW DCC22DR0 48 # 88 C8
PRT2IE 09 RW DCC22DR1 49 W 89 C9
PRT2GS 0A RW DCC22DR2 4A RW 8A CA
PRT2DM2 0B RW DCC22CR0 4B # 8B CB
PRT3DR 0C RW DCC23DR0 4C # 8C CC
PRT3IE 0D RW DCC23DR1 4D W 8D CD
PRT3GS 0E RW DCC23DR2 4E RW 8E CE
PRT3DM2 0F RW DCC23CR0 4F # 8F CF
PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW
PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW
PRT4GS 12 RW 52 ASD20CR2 92 RW D2
PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW
PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW
PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW
PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW
PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 #
18 58 98 I2C0_DR D8 RW
19 59 99 I2C0_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C INT_CLR2 DC RW
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F INT_MSK2 DF RW
DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW
DBC00DR1 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW
DBC00DR2 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC
DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W
DBC01DR0 24 # CMP_CR0 64 # DEC2_DH A4 RC E4
DBC01DR1 25 W ASY_CR 65 # DEC2_DL A5 RC E5
DBC01DR2 26 RW CMP_CR1 66 RW DEC3_DH A6 RC DEC_CR0* E6 RW
DBC01CR0 27 # 67 DEC3_DL A7 RC DEC_CR1* E7 RW
DCC02DR0 28 # 68 MUL1_X A8 WMUL0_X E8 W
DCC02DR1 29 W 69 MUL1_Y A9 WMUL0_Y E9 W
DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA RMUL0_DH EA R
DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB RMUL0_DL EB R
DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0
DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1
DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2
DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3
DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4
DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5
DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6
DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW CPU_F F7 RL
DCC12DR0 38 # 78 RDI1RI B8 RW F8
DCC12DR1 39 W 79 RDI1SYN B9 RW F9
DCC12DR2 3A RW 7A RDI1IS BA RW FA
DCC12CR0 3B # 7B RDI1LT0 BB RW FB
DCC13DR0 3C # 7C RDI1LT1 BC RW DAC1_D FC RW
DCC13DR1 3D W 7D RDI1RO0 BD RW DAC0_D FD RW
DCC13DR2 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR0 3F # 7F RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 24 of 65
CY8C28x33 Register Map Bank 1 Table: Configuration Space
Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW DBC20FN 40 RW 80 RDI2RI C0 RW
PRT0DM1 01 RW DBC20IN 41 RW SADC_TSCMPL 81 RW RDI2SYN C1 RW
PRT0IC0 02 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RDI2IS C2 RW
PRT0IC1 03 RW DBC20CR1 43 RW ACE_AMD_CR1 83 RW RDI2LT0 C3 RW
PRT1DM0 04 RW DBC21FN 44 RW 84 RDI2LT1 C4 RW
PRT1DM1 05 RW DBC21IN 45 RW ACE_PWM_CR 85 RW RDI2RO0 C5 RW
PRT1IC0 06 RW DBC21OU 46 RW ACE_ADC0_CR 86 RW RDI2RO1 C6 RW
PRT1IC1 07 RW DBC21CR1 47 RW ACE_ADC1_CR 87 RW RDI2DSM C7 RW
PRT2DM0 08 RW DCC22FN 48 RW 88 RW C8
PRT2DM1 09 RW DCC22IN 49 RW ACE_CLK_CR0 89 RW C9
PRT2IC0 0A RW DCC22OU 4A RW ACE_CLK_CR1 8A RW CA
PRT2IC1 0B RW DCC22CR1 4B RW ACE_CLK_CR3 8B RW CB
PRT3DM0 0C RW DCC23FN 4C RW 8C CC
PRT3DM1 0D RW DCC23IN 4D RW ACE01CR1 8D RW CD
PRT3IC0 0E RW DCC23OU 4E RW ACE01CR2 8E RW CE
PRT3IC1 0F RW DCC23CR1 4F RW ASE11CR0 8F RW CF
PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW
PRT4DM1 11 RW 51 DEC0_CR0 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW 52 DEC_CR3 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW 53 93 GDI_E_OU D3 RW
PRT5DM0 14 RW 54 94 DEC0_CR D4 RW
PRT5DM1 15 RW 55 DEC1_CR0 95 RW DEC1_CR D5 RW
PRT5IC0 16 RW 56 DEC_CR4 96 RW DEC2_CR D6 RW
PRT5IC1 17 RW 57 97 DEC3_CR D7 RW
18 58 98 MUX_CR0 D8 RW
19 59 DEC2_CR0 99 RW MUX_CR1 D9 RW
1A 5A DEC_CR5 9A RW MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW
1C 5C 9C IDAC_CR1 DC RW
1D 5D DEC3_CR0 9D RW OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW
DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW
DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW
DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW
DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW
DBC01IN 25 RW 65 RTC_M A5 RW ADC0_TR E5 RW
DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW ADC1_TR E6 RW
DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW IDAC_CR2 E7 RW
DCC02FN 28 RW 68 SADC_CR0 A8 RW IMO_TR E8 RW
DCC02IN 29 RW CLK_CR2 69 RW SADC_CR1 A9 RW ILO_TR E9 RW
DCC02OU 2A RW AMUX_CFG1 6A RW SADC_CR2 AA RW BDG_TR EA RW
DCC02CR1 2B RW 6B SADC_CR3 AB RW ECO_TR EB RW
DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW MUX_CR4 EC RW
DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW MUX_CR5 ED RW
DCC03OU 2E RW TMP_DR2 6E RW AE EE
DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF
DBC10FN 30 RW 70 RDI0RI B0 RW F0
DBC10IN 31 RW SADC_TSCR0 71 RW RDI0SYN B1 RW F1
DBC10OU 32 RW SADC_TSCR1 72 RW RDI0IS B2 RW F2
DBC10CR1 33 RW ACE_AMD_CR0 73 RW RDI0LT0 B3 RW F3
DBC11FN 34 RW 74 RDI0LT1 B4 RW F4
DBC11IN 35 RW ACE_AMX_IN 75 RW RDI0RO0 B5 RW F5
DBC11OU 36 RW ACE_CMP_CR0 76 RW RDI0RO1 B6 RW F6
DBC11CR1 37 RW ACE_CMP_CR1 77 RW RDIODSM B7 RW CPU_F F7 RL
DCC12FN 38 RW 78 RDI1RI B8 RW F8
DCC12IN 39 RW ACE_CMP_GI_EN 79 RW RDI1SYN B9 RW F9
DCC12OU 3A RW ACE_ALT_CR0 7A RW RDI1IS BA RW FLS_PR1 FA RW
DCC12CR1 3B RW ACE_ABF_CR0 7B RW RDI1LT0 BB RW FB
DCC13FN 3C RW 7C RDI1LT1 BC RW FC
DCC13IN 3D RW ACE0_CR1 7D RW RDI1RO0 BD RW IDAC_CR0 FD RW
DCC13OU 3E RW ACE0_CR2 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR1 3F RW ACE0_CR3 7F RW RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be ac cessed. # Access is bit specific. *Addre ss has a dual purpose, se e “Mapping Exceptions” on page 251
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 25 of 65
CY8C28x43 Register Map Ba nk 0 Table: User Space
Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW DBC20DR0 40 # ASC10CR0 80 RW RDI2RI C0 RW
PRT0IE 01 RW DBC20DR1 41 W ASC10CR1 81 RW RDI2SYN C1 RW
PRT0GS 02 RW DBC20DR2 42 RW ASC10CR2 82 RW RDI2IS C2 RW
PRT0DM2 03 RW DBC20CR0 43 # ASC10CR3 83 RW RDI2LT0 C3 RW
PRT1DR 04 RW DBC21DR0 44 # ASD11CR0 84 RW RDI2LT1 C4 RW
PRT1IE 05 RW DBC21DR1 45 W ASD11CR1 85 RW RDI2RO0 C5 RW
PRT1GS 06 RW DBC21DR2 46 RW ASD11CR2 86 RW RDI2RO1 C6 RW
PRT1DM2 07 RW DBC21CR0 47 # ASD11CR3 87 RW RDI2DSM C7 RW
PRT2DR 08 RW DCC22DR0 48 # ASC12CR0 88 RW C8
PRT2IE 09 RW DCC22DR1 49 W ASC12CR1 89 RW C9
PRT2GS 0A RW DCC22DR2 4A RW ASC12CR2 8A RW CA
PRT2DM2 0B RW DCC22CR0 4B # ASC12CR3 8B RW CB
PRT3DR 0C RW DCC23DR0 4C # ASD13CR0 8C RW CC
PRT3IE 0D RW DCC23DR1 4D W ASD13CR1 8D RW CD
PRT3GS 0E RW DCC23DR2 4E RW ASD13CR2 8E RW CE
PRT3DM2 0F RW DCC23CR0 4F # ASD13CR3 8F RW CF
PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW
PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW
PRT4GS 12 RW 52 ASD20CR2 92 RW D2
PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW
PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW
PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW
PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW
PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 #
18 58 ASD22CR0 98 RW I2C0_DR D8 RW
19 59 ASD22CR1 99 RW I2C0_MSCR D9 #
1A 5A ASD22CR2 9A RW INT_CLR0 DA RW
1B 5B ASD22CR3 9B RW INT_CLR1 DB RW
1C 5C ASC23CR0 9C RW INT_CLR2 DC RW
1D 5D ASC23CR1 9D RW INT_CLR3 DD RW
1E 5E ASC23CR2 9E RW INT_MSK3 DE RW
1F 5F ASC23CR3 9F RW INT_MSK2 DF RW
DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW
DBC00DR1 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW
DBC00DR2 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC
DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W
DBC01DR0 24 # CMP_CR0 64 # DEC2_DH A4 RC I2C1_SCR E4 #
DBC01DR1 25 W ASY_CR 65 # DEC2_DL A5 RC I2C1_MSCR E5 #
DBC01DR2 26 RW CMP_CR1 66 RW DEC3_DH A6 RC DEC_CR0* E6 RW
DBC01CR0 27 # I2C1_DR 67 RW DEC3_DL A7 RC DEC_CR1* E7 RW
DCC02DR0 28 # 68 MUL1_X A8 WMUL0_X E8 W
DCC02DR1 29 W 69 MUL1_Y A9 WMUL0_Y E9 W
DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA RMUL0_DH EA R
DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB RMUL0_DL EB R
DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0
DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1
DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2
DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3
DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4
DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5
DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6
DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW CPU_F F7 RL
DCC12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F8
DCC12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9
DCC12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FA
DCC12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW FB
DCC13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW FC
DCC13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW FD
DCC13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR0 3F # ACB03CR2 7F RW RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 26 of 65
CY8C28x43 Register Map Bank 1 Table: Configuration Space
Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW DBC20FN 40 RW 80 RDI2RI C0 RW
PRT0DM1 01 RW DBC20IN 41 RW SADC_TSCMPL 81 RW RDI2SYN C1 RW
PRT0IC0 02 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RDI2IS C2 RW
PRT0IC1 03 RW DBC20CR1 43 RW 83 RDI2LT0 C3 RW
PRT1DM0 04 RW DBC21FN 44 RW 84 RDI2LT1 C4 RW
PRT1DM1 05 RW DBC21IN 45 RW 85 RDI2RO0 C5 RW
PRT1IC0 06 RW DBC21OU 46 RW 86 RDI2RO1 C6 RW
PRT1IC1 07 RW DBC21CR1 47 RW 87 RDI2DSM C7 RW
PRT2DM0 08 RW DCC22FN 48 RW 88 C8
PRT2DM1 09 RW DCC22IN 49 RW 89 C9
PRT2IC0 0A RW DCC22OU 4A RW 8A CA
PRT2IC1 0B RW DCC22CR1 4B RW 8B CB
PRT3DM0 0C RW DCC23FN 4C RW 8C CC
PRT3DM1 0D RW DCC23IN 4D RW 8D CD
PRT3IC0 0E RW DCC23OU 4E RW 8E CE
PRT3IC1 0F RW DCC23CR1 4F RW 8F CF
PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW
PRT4DM1 11 RW 51 DEC0_CR0 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW 52 DEC_CR3 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW 53 93 GDI_E_OU D3 RW
PRT5DM0 14 RW 54 94 DEC0_CR D4 RW
PRT5DM1 15 RW 55 DEC1_CR0 95 RW DEC1_CR D5 RW
PRT5IC0 16 RW 56 DEC_CR4 96 RW DEC2_CR D6 RW
PRT5IC1 17 RW 57 97 DEC3_CR D7 RW
18 58 98 MUX_CR0 D8 RW
19 59 DEC2_CR0 99 RW MUX_CR1 D9 RW
1A 5A DEC_CR5 9A RW MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW
1C 5C 9C DC
1D 5D DEC3_CR0 9D RW OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW
DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW
DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW
DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW
DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW
DBC01IN 25 RW CMP_GO_EN1 65 RW RTC_M A5 RW E5
DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW E6
DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW E7
DCC02FN 28 RW ALT_CR1 68 RW SADC_CR0 A8 RW IMO_TR E8 RW
DCC02IN 29 RW CLK_CR2 69 RW SADC_CR1 A9 RW ILO_TR E9 RW
DCC02OU 2A RW AMUX_CFG1 6A RW SADC_CR2 AA RW BDG_TR EA RW
DCC02CR1 2B RW I2C1_CFG 6B RW SADC_CR3 AB RW ECO_TR EB RW
DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW MUX_CR4 EC RW
DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW MUX_CR5 ED RW
DCC03OU 2E RW TMP_DR2 6E RW I2C1_ADDR AE RW EE
DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF
DBC10FN 30 RW 70 RDI0RI B0 RW F0
DBC10IN 31 RW SADC_TSCR0 71 RW RDI0SYN B1 RW F1
DBC10OU 32 RW SADC_TSCR1 72 RW RDI0IS B2 RW F2
DBC10CR1 33 RW 73 RDI0LT0 B3 RW F3
DBC11FN 34 RW 74 RDI0LT1 B4 RW F4
DBC11IN 35 RW 75 RDI0RO0 B5 RW F5
DBC11OU 36 RW 76 RDI0RO1 B6 RW F6
DBC11CR1 37 RW 77 RDIODSM B7 RW CPU_F F7 RL
DCC12FN 38 RW 78 RDI1RI B8 RW F8
DCC12IN 39 RW 79 RDI1SYN B9 RW F9
DCC12OU 3A RW 7A RDI1IS BA RW FLS_PR1 FA RW
DCC12CR1 3B RW 7B RDI1LT0 BB RW FB
DCC13FN 3C RW 7C RDI1LT1 BC RW FC
DCC13IN 3D RW 7D RDI1RO0 BD RW FD
DCC13OU 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR1 3F RW 7F RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be ac cessed. # Access is bit specific. *Addre ss has a dual purpose, se e “Mapping Exceptions” on page 251
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 27 of 65
CY8C28x45 Register Map Ba nk 0 Table: User Space
Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW DBC20DR0 40 # ASC10CR0 80 RW RDI2RI C0 RW
PRT0IE 01 RW DBC20DR1 41 W ASC10CR1 81 RW RDI2SYN C1 RW
PRT0GS 02 RW DBC20DR2 42 RW ASC10CR2 82 RW RDI2IS C2 RW
PRT0DM2 03 RW DBC20CR0 43 # ASC10CR3 83 RW RDI2LT0 C3 RW
PRT1DR 04 RW DBC21DR0 44 # ASD11CR0 84 RW RDI2LT1 C4 RW
PRT1IE 05 RW DBC21DR1 45 W ASD11CR1 85 RW RDI2RO0 C5 RW
PRT1GS 06 RW DBC21DR2 46 RW ASD11CR2 86 RW RDI2RO1 C6 RW
PRT1DM2 07 RW DBC21CR0 47 # ASD11CR3 87 RW RDI2DSM C7 RW
PRT2DR 08 RW DCC22DR0 48 # ASC12CR0 88 RW C8
PRT2IE 09 RW DCC22DR1 49 W ASC12CR1 89 RW C9
PRT2GS 0A RW DCC22DR2 4A RW ASC12CR2 8A RW CA
PRT2DM2 0B RW DCC22CR0 4B # ASC12CR3 8B RW CB
PRT3DR 0C RW DCC23DR0 4C # ASD13CR0 8C RW CC
PRT3IE 0D RW DCC23DR1 4D W ASD13CR1 8D RW CD
PRT3GS 0E RW DCC23DR2 4E RW ASD13CR2 8E RW CE
PRT3DM2 0F RW DCC23CR0 4F # ASD13CR3 8F RW CF
PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW
PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW
PRT4GS 12 RW 52 ASD20CR2 92 RW D2
PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW
PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW
PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW
PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW
PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 #
18 58 ASD22CR0 98 RW I2C0_DR D8 RW
19 59 ASD22CR1 99 RW I2C0_MSCR D9 #
1A 5A ASD22CR2 9A RW INT_CLR0 DA RW
1B 5B ASD22CR3 9B RW INT_CLR1 DB RW
1C 5C ASC23CR0 9C RW INT_CLR2 DC RW
1D 5D ASC23CR1 9D RW INT_CLR3 DD RW
1E 5E ASC23CR2 9E RW INT_MSK3 DE RW
1F 5F ASC23CR3 9F RW INT_MSK2 DF RW
DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW
DBC00DR1 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW
DBC00DR2 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC
DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W
DBC01DR0 24 # CMP_CR0 64 # DEC2_DH A4 RC I2C1_SCR E4 #
DBC01DR1 25 W ASY_CR 65 # DEC2_DL A5 RC I2C1_MSCR E5 #
DBC01DR2 26 RW CMP_CR1 66 RW DEC3_DH A6 RC DEC_CR0* E6 RW
DBC01CR0 27 # I2C1_DR 67 RW DEC3_DL A7 RC DEC_CR1* E7 RW
DCC02DR0 28 # 68 MUL1_X A8 WMUL0_X E8 W
DCC02DR1 29 W 69 MUL1_Y A9 WMUL0_Y E9 W
DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA RMUL0_DH EA R
DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB RMUL0_DL EB R
DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0
DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1
DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2
DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3
DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4
DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5
DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6
DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW CPU_F F7 RL
DCC12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F8
DCC12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9
DCC12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FA
DCC12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW FB
DCC13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW DAC1_D FC RW
DCC13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW DAC0_D FD RW
DCC13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR0 3F # ACB03CR2 7F RW RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 28 of 65
CY8C28x45 Register Map Bank 1 Table: Configuration Space
Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW DBC20FN 40 RW 80 RW RDI2RI C0 RW
PRT0DM1 01 RW DBC20IN 41 RW SADC_TSCMPL 81 RW RDI2SYN C1 RW
PRT0IC0 02 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RDI2IS C2 RW
PRT0IC1 03 RW DBC20CR1 43 RW ACE_AMD_CR1 83 RW RDI2LT0 C3 RW
PRT1DM0 04 RW DBC21FN 44 RW 84 RW RDI2LT1 C4 RW
PRT1DM1 05 RW DBC21IN 45 RW ACE_PWM_CR 85 RW RDI2RO0 C5 RW
PRT1IC0 06 RW DBC21OU 46 RW ACE_ADC0_CR 86 RW RDI2RO1 C6 RW
PRT1IC1 07 RW DBC21CR1 47 RW ACE_ADC1_CR 87 RW RDI2DSM C7 RW
PRT2DM0 08 RW DCC22FN 48 RW 88 RW C8
PRT2DM1 09 RW DCC22IN 49 RW ACE_CLK_CR0 89 RW C9
PRT2IC0 0A RW DCC22OU 4A RW ACE_CLK_CR1 8A RW CA
PRT2IC1 0B RW DCC22CR1 4B RW ACE_CLK_CR3 8B RW CB
PRT3DM0 0C RW DCC23FN 4C RW 8C RW CC
PRT3DM1 0D RW DCC23IN 4D RW ACE01CR1 8D RW CD
PRT3IC0 0E RW DCC23OU 4E RW ACE01CR2 8E RW CE
PRT3IC1 0F RW DCC23CR1 4F RW ASE11CR0 8F RW CF
PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW
PRT4DM1 11 RW 51 DEC0_CR0 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW 52 DEC_CR3 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW 53 93 GDI_E_OU D3 RW
PRT5DM0 14 RW 54 94 DEC0_CR D4 RW
PRT5DM1 15 RW 55 DEC1_CR0 95 RW DEC1_CR D5 RW
PRT5IC0 16 RW 56 DEC_CR4 96 RW DEC2_CR D6 RW
PRT5IC1 17 RW 57 97 DEC3_CR D7 RW
18 58 98 MUX_CR0 D8 RW
19 59 DEC2_CR0 99 RW MUX_CR1 D9 RW
1A 5A DEC_CR5 9A RW MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW
1C 5C 9C IDAC_CR1 DC RW
1D 5D DEC3_CR0 9D RW OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW
DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW
DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW
DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW
DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW
DBC01IN 25 RW CMP_GO_EN1 65 RW RTC_M A5 RW ADC0_TR E5 RW
DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW ADC1_TR E6 RW
DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW IDAC_CR2 E7 RW
DCC02FN 28 RW ALT_CR1 68 RW SADC_CR0 A8 RW IMO_TR E8 RW
DCC02IN 29 RW CLK_CR2 69 RW SADC_CR1 A9 RW ILO_TR E9 RW
DCC02OU 2A RW AMUX_CFG1 6A RW SADC_CR2 AA RW BDG_TR EA RW
DCC02CR1 2B RW I2C1_CFG 6B RW SADC_CR3 AB RW ECO_TR EB RW
DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW MUX_CR4 EC RW
DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW MUX_CR5 ED RW
DCC03OU 2E RW TMP_DR2 6E RW I2C1_ADDR AE RW EE
DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF
DBC10FN 30 RW 70 RDI0RI B0 RW F0
DBC10IN 31 RW SADC_TSCR0 71 RW RDI0SYN B1 RW F1
DBC10OU 32 RW SADC_TSCR1 72 RW RDI0IS B2 RW F2
DBC10CR1 33 RW ACE_AMD_CR0 73 RW RDI0LT0 B3 RW F3
DBC11FN 34 RW 74 RDI0LT1 B4 RW F4
DBC11IN 35 RW ACE_AMX_IN 75 RW RDI0RO0 B5 RW F5
DBC11OU 36 RW ACE_CMP_CR0 76 RW RDI0RO1 B6 RW F6
DBC11CR1 37 RW ACE_CMP_CR1 77 RW RDIODSM B7 RW CPU_F F7 RL
DCC12FN 38 RW 78 RDI1RI B8 RW F8
DCC12IN 39 RW ACE_CMP_GI_EN 79 RW RDI1SYN B9 RW F9
DCC12OU 3A RW ACE_ALT_CR0 7A RW RDI1IS BA RW FLS_PR1 FA RW
DCC12CR1 3B RW ACE_ABF_CR0 7B RW RDI1LT0 BB RW FB
DCC13FN 3C RW 7C RDI1LT1 BC RW FC
DCC13IN 3D RW ACE0_CR1 7D RW RDI1RO0 BD RW IDAC_CR0 FD RW
DCC13OU 3E RW ACE0_CR2 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR1 3F RW ACE0_CR3 7F RW RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be ac cessed. # Access is bit specific. *Addre ss has a dual purpose, se e “Mapping Exceptions” on page 251
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 29 of 65
CY8C28x52 Register Map Ba nk 0 Table: User Space
Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW 40 ASC10CR0 80 RW C0
PRT0IE 01 RW 41 ASC10CR1 81 RW C1
PRT0GS 02 RW 42 ASC10CR2 82 RW C2
PRT0DM2 03 RW 43 ASC10CR3 83 RW C3
PRT1DR 04 RW 44 ASD11CR0 84 RW C4
PRT1IE 05 RW 45 ASD11CR1 85 RW C5
PRT1GS 06 RW 46 ASD11CR2 86 RW C6
PRT1DM2 07 RW 47 ASD11CR3 87 RW C7
PRT2DR 08 RW 48 ASC12CR0 88 RW C8
PRT2IE 09 RW 49 ASC12CR1 89 RW C9
PRT2GS 0A RW 4A ASC12CR2 8A RW CA
PRT2DM2 0B RW 4B ASC12CR3 8B RW CB
PRT3DR 0C RW 4C ASD13CR0 8C RW CC
PRT3IE 0D RW 4D ASD13CR1 8D RW CD
PRT3GS 0E RW 4E ASD13CR2 8E RW CE
PRT3DM2 0F RW 4F ASD13CR3 8F RW CF
PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW
PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW
PRT4GS 12 RW 52 ASD20CR2 92 RW D2
PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW
PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW
PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW
PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW
PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 #
18 58 ASD22CR0 98 RW I2C0_DR D8 RW
19 59 ASD22CR1 99 RW I2C0_MSCR D9 #
1A 5A ASD22CR2 9A RW INT_CLR0 DA RW
1B 5B ASD22CR3 9B RW INT_CLR1 DB RW
1C 5C ASC23CR0 9C RW INT_CLR2 DC RW
1D 5D ASC23CR1 9D RW INT_CLR3 DD RW
1E 5E ASC23CR2 9E RW INT_MSK3 DE RW
1F 5F ASC23CR3 9F RW INT_MSK2 DF RW
DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW
DBC00DR1 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW
DBC00DR2 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC
DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W
DBC01DR0 24 # CMP_CR0 64 # DEC2_DH A4 RC E4
DBC01DR1 25 W ASY_CR 65 # DEC2_DL A5 RC E5
DBC01DR2 26 RW CMP_CR1 66 RW DEC3_DH A6 RC DEC_CR0* E6 RW
DBC01CR0 27 # 67 DEC3_DL A7 RC DEC_CR1* E7 RW
DCC02DR0 28 # 68 MUL1_X A8 WMUL0_X E8 W
DCC02DR1 29 W 69 MUL1_Y A9 WMUL0_Y E9 W
DCC02DR2 2A RW 6A MUL1_DH AA RMUL0_DH EA R
DCC02CR0 2B # 6B MUL1_DL AB RMUL0_DL EB R
DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0
DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1
DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2
DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3
DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4
DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5
DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6
DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW CPU_F F7 RL
DCC12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F8
DCC12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9
DCC12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FA
DCC12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW FB
DCC13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW DAC1_D FC RW
DCC13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW DAC0_D FD RW
DCC13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR0 3F # ACB03CR2 7F RW RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251
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PRELIMINARY CY8C28xxx
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CY8C28x52 Register Map Bank 1 Table: Configuration Space
Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW 40 80 C0
PRT0DM1 01 RW 41 81 C1
PRT0IC0 02 RW 42 82 C2
PRT0IC1 03 RW 43 ACE_AMD_CR1 83 RW C3
PRT1DM0 04 RW 44 84 C4
PRT1DM1 05 RW 45 ACE_PWM_CR 85 RW C5
PRT1IC0 06 RW 46 ACE_ADC0_CR 86 RW C6
PRT1IC1 07 RW 47 ACE_ADC1_CR 87 RW C7
PRT2DM0 08 RW 48 88 C8
PRT2DM1 09 RW 49 ACE_CLK_CR0 89 RW C9
PRT2IC0 0A RW 4A ACE_CLK_CR1 8A RW CA
PRT2IC1 0B RW 4B ACE_CLK_CR3 8B RW CB
PRT3DM0 0C RW 4C 8C CC
PRT3DM1 0D RW 4D ACE01CR1 8D RW CD
PRT3IC0 0E RW 4E ACE01CR2 8E RW CE
PRT3IC1 0F RW 4F ASE11CR0 8F RW CF
PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW
PRT4DM1 11 RW 51 DEC0_CR0 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW 52 DEC_CR3 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW 53 93 GDI_E_OU D3 RW
PRT5DM0 14 RW 54 94 DEC0_CR D4 RW
PRT5DM1 15 RW 55 DEC1_CR0 95 RW DEC1_CR D5 RW
PRT5IC0 16 RW 56 DEC_CR4 96 RW DEC2_CR D6 RW
PRT5IC1 17 RW 57 97 DEC3_CR D7 RW
18 58 98 MUX_CR0 D8 RW
19 59 DEC2_CR0 99 RW MUX_CR1 D9 RW
1A 5A DEC_CR5 9A RW MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW
1C 5C 9C IDAC_CR1 DC RW
1D 5D DEC3_CR0 9D RW OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW
DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW
DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW
DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW
DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW
DBC01IN 25 RW CMP_GO_EN1 65 RW RTC_M A5 RW ADC0_TR E5 RW
DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW ADC1_TR E6 RW
DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW IDAC_CR2 E7 RW
DCC02FN 28 RW ALT_CR1 68 RW A8 IMO_TR E8 RW
DCC02IN 29 RW CLK_CR2 69 RW A9 ILO_TR E9 RW
DCC02OU 2A RW AMUX_CFG1 6A RW AA BDG_TR EA RW
DCC02CR1 2B RW 6B AB ECO_TR EB RW
DCC03FN 2C RW TMP_DR0 6C RW AC MUX_CR4 EC RW
DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW MUX_CR5 ED RW
DCC03OU 2E RW TMP_DR2 6E RW AE EE
DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF
DBC10FN 30 RW 70 RDI0RI B0 RW F0
DBC10IN 31 RW 71 RDI0SYN B1 RW F1
DBC10OU 32 RW 72 RDI0IS B2 RW F2
DBC10CR1 33 RW ACE_AMD_CR0 73 RW RDI0LT0 B3 RW F3
DBC11FN 34 RW 74 RDI0LT1 B4 RW F4
DBC11IN 35 RW ACE_AMX_IN 75 RW RDI0RO0 B5 RW F5
DBC11OU 36 RW ACE_CMP_CR0 76 RW RDI0RO1 B6 RW F6
DBC11CR1 37 RW ACE_CMP_CR1 77 RW RDIODSM B7 RW CPU_F F7 RL
DCC12FN 38 RW 78 RDI1RI B8 RW F8
DCC12IN 39 RW ACE_CMP_GI_EN 79 RW RDI1SYN B9 RW F9
DCC12OU 3A RW ACE_ALT_CR0 7A RW RDI1IS BA RW FLS_PR1 FA RW
DCC12CR1 3B RW ACE_ABF_CR0 7B RW RDI1LT0 BB RW FB
DCC13FN 3C RW 7C RDI1LT1 BC RW FC
DCC13IN 3D RW ACE0_CR1 7D RW RDI1RO0 BD RW IDAC_CR0 FD RW
DCC13OU 3E RW ACE0_CR2 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR1 3F RW ACE0_CR3 7F RW RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be ac cessed. # Access is bit specific. *Addre ss has a dual purpose, se e “Mapping Exceptions” on page 251
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 31 of 65
Electrical Specifications
This section presents the DC and AC electrical spe cifications of the CY8C28xxx PSoC devices. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
S pecifications are valid for -40
o
C ≤ T
A
≤ 85
o
C and T
J
≤ 100
o
C, except where noted. S pecifications for devices running at greater than
12 MHz are valid for -40
o
C ≤ T
A
≤ 70
o
C and T
J
≤ 82
o
C.
Figure 7. Voltage versus CPU Frequency
The following table lists the units of measure that are used in this section.
Table 8. Units of Measure
Symbol Unit of Measure Symbol Unit of Measure
o
Cdegree Celsius μWmicrowatts
dB decibels mA milli-ampere
fF femto farad ms milli-second
Hz hertz mV milli-volts
KB 1024 bytes nA nanoampere
Kbit 1024 bits ns nanosecond
kHz kilohertz nV nanovolts
kΩkilohm Ωohm
MHz megahertz pA picoampere
MΩmegaohm pF picofarad
μAmicroampere pp peak-to-peak
μFmicrofarad ppm parts per million
μHmicrohenry ps picosecond
μsmicrosecond ksps kilo-samples per second
μVmicrovolts ∑sigma: one standard deviation
μVrms microvolts root-mean-square Vvolts
5.25
4.75
3.00
93 kHz 12 MHz 24 MHz
CPU Frequency
Vdd Voltage
Valid
Operating
Region
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 32 of 65
Absolute Maximum Ratings
Operating Temperature
Table 9. Absolute Maximum Ratings
Symbol Description Min Typ Max Units Notes
T
STG
Storage Temperature -55 25 +100
o
CHigher storage temperatures reduce
data retention time. Recommended
storage temperature is +25
o
C ±
25
o
C. Extended duration stor age
temperatures above 65
o
C degrade
reliability.
T
A
Ambient Temperatur e with Power Applied -40 –+85
o
C
Vdd Supply Voltage on Vdd Relative to Vss -0.5 –+6.0 V
V
IO
DC Input Voltage Vss-
0.5 –Vdd +
0.5 V
V
IOZ
DC Voltage Applied to Tri-state Vss -
0.5 –Vdd +
0.5 V
I
MIO
Maximum Current into any Port Pin -25 –+50 mA
I
MAIO
Maximum Current into any Port Pin
Configured as Analog Driver -50 –+50 mA
ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD.
LU Latch-up Current – – 200 mA
Tab le 10. Operating Temperature
Symbol Description Min Typ Max Units Notes
T
A
Ambient Temperature -40 –+85
o
C
T
J
Junction Temperature -40 –+100
o
CThe temperature rise from ambient to
junction is package specific. See
Thermal Impedances on page 60. The
user must limit the power
consumption to comply with this
requirement.
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PRELIMINARY CY8C28xxx
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DC Electrical Characteristics
DC Chip Level Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 11. DC Chip Level Specifications
Symbol Description Min Typ Max Units Notes
Vdd Supply Voltage 3.00 –5.25 V
I
DD
Supply Current – 8 14 mA Conditions are Vdd = 5.0V, T
A
= 25
o
C,
CPU = 3 MHz, SYSCLK doubler
disabled. VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 93.75 kHz.
I
DD3
Supply Current – 5 9 mA Conditions are Vdd = 3.3V , T
A
= 25
o
C,
CPU = 3 MHz, SYSCLK doubler
disabled. VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 93.75 kHz.
I
SB
Sleep (Mode) Current with POR, LVD, Sleep
Timer , and WDT.
[13]
– 3 10 μAConditions are with internal slow
speed oscillator , Vdd = 3.3V, -40
o
C ≤
T
A
≤ 55
o
C.
I
SBH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT at high temperature.
[13]
– 4 25 μAConditions are with internal slow
speed oscillator, Vdd = 3.3V, 55
o
C <
T
A
≤ 85
o
C.
I
SBXTL
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal.
[13]
– 4 11 μAConditions are with properly loaded, 1
μW max, 32.768 kHz crystal. Vdd =
3.3V, -40
o
C ≤ T
A
≤ 55
o
C.
I
SBXTLH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal at high
temperature.
[13]
– 5 26 μAConditions are with properly loaded, 1
μW max, 32.768 kHz crystal. Vdd =
3.3V, 55
o
C < T
A
≤ 85
o
C.
V
REF
Reference Voltage (Bandgap) 1.280 1.300 1.320 VTrimmed for appropriate Vdd.
I
XRES
1.00 –1.058 mA
Note
13.Standby (sleep) current includes all f uncti on
s
(POR, LVD, WDT, Sleep Timer) needed for reliable system op eration. This should be comp ar ed with d evice s t hat have
similar functions
enabled.
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 34 of 65
DC General Purpose I/O Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications fo r the voltage and temperature ra nges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only. The Operational Amplifiers covered by these specifications are components of both the Analog
Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog
Continuous Time PSoC block.
Table 12 . DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
R
PU
Pull Up Resistor 4 5.6 8 kΩ
R
PD
Pull Down Resistor 4 5.6 8 kΩ
V
OH
High Output Level Vdd -
1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
V
OL
Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
I
OH
High Level Source Current 10 – – mA V
OH
= Vdd-1.0V , see the limitations of
the tot al current in the note for V
OH.
I
OL
Low Level Sink Current 25 – – mA V
OL
= 0.75V , see the limitations of the
total current in the note for V
OL.
V
IL
Input Low Level – – 0.8 V Vdd = 3.0 to 5.25.
V
IH
Input High Level 2.1 – V Vdd = 3.0 to 5.25.
V
H
Input Hysteresis –60 –mV
I
IL
Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA.
C
IN
Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent. Temp =
25
o
C.
C
OUT
Capacitive Load on Pins as Output –3.5 10 pF Package and pin dependent. Temp =
25
o
C.
Tab le 13 . 5V DC Ope rational Amplifier Specification s
Symbol Description Min Typ Max Units Notes
V
OSOA
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
1.6
1.3
1.2
10
10
10
mV
mV
mV
TCV
OSOA
Average Input Offset Voltage Drift – 7.0 35.0 μV/
o
C
I
EBOA
Input Leakage Current (Port 0 Anal og Pins) – 200 – pA Gross tested to 1 μA.
C
INOA
Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp =
25
o
C.
V
CMOA
Common Mode Voltage Range
Common Mode V oltage Range (high power
or high opamp bias)
0.0 – Vdd
Vdd -
0.5
V The common-mode input voltage
range is measured through an analog
output buffer. The specification
includes the limitations imposed by
the characteristics of the analo g
output bu ffer.
0.5 –
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PRELIMINARY CY8C28xxx
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CMRR
OA
Common Mode Rejection Ratio
Power = Low
Power = Medium
Power = High
60
60
60
– – dB Specifica ti on is applicable at high
power. For all other bias modes
(except high power, high opamp
bias), minimum is 60 dB.
G
OLOA
Open Loop Gain
Power = Low
Power = Medium
Power = High
60
60
80
– – dB Specifica ti on is applicable at high
power. For all other bias modes
(except high power, high opamp
bias), minimum is 60 dB.
V
OHIGHOA
High Output V oltage Swing (internal signals)
Power = Low
Power = Medium
Power = High
Vdd -
0.2
Vdd -
0.2
Vdd -
0.5
–
–
–
–
–
–
V
V
V
V
OLOWOA
Low Output V oltage Swing (internal signals)
Power = Low
Power = Medium
Power = High
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
I
SOA
Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
μA
μA
μA
μA
μA
μA
PSRR
OA
Supply Voltage Rejection Ratio 60 – – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd -
1.25V) ≤ VIN ≤ Vdd.
Table 14. 3.3V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
V
OSOA
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5 Volts Only
–
–1.65
1.32 10
8 mV
mV
TCV
OSOA
Average Input Offset Voltage Drift – 7.0 35.0 μV/
o
C
I
EBOA
Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.
C
INOA
Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp =
25
o
C.
V
CMOA
Common Mode Voltage Range 0.2 – Vdd - 0.2 V The common-mode input voltage
range is measured through an
analog output buffer. The specifi-
cation includes the limitations
imposed by the characteristics of the
analog output buffer.
CMRR
OA
Common Mode Rejection Ratio
Power = Low
Power = Medium
Power = High
50
50
50
– – dB Specification is app licable at high
power. For all other bias modes
(except high power, high opamp
bias), minimum is 50 dB.
G
OLOA
Open Loop Gain
Power = Low
Power = Medium
Power = High
60
60
80
– – dB Specification is app licable at high
power. For all other bias modes
(except high power, high opamp
bias), minimum is 60 dB.
Tab le 13 . 5V DC Ope rational Amplifier Specification s (continued)
Symbol Description Min Typ Max Units Notes
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 36 of 65
DC Type-E Operationa l Amplifie r Specificat ions
The following tables list guaranteed maximum and minimum specifications fo r the voltage and temperature ra nges: 4.75V to 5.25V
and -40°C £ T
A
£ 85°C, or 3.0V to 3.6V and -40°C £ T
A
£ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only . The Operational Amplifiers covered by these specifications are components of the Limited Type E Analog
PSoC blocks.
V
OHIGHOA
High Output V oltage Swing (internal signals)
Power = Low
Power = Medium
Power = High is 5V only
Vdd -
0.2
Vdd -
0.2
Vdd -
0.2
–
–
–
–
–
–
V
V
V
V
OLOWOA
Low Output Voltage Swing (internal signals)
Power = Low
Power = Medium
Power = High
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
I
SOA
Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
μA
μA
μA
μA
μA
μA
PSRR
OA
Supply Voltage Rejection Ratio 50 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd -
1.25V) ≤ VIN ≤ Vdd.
Tab le 15. 5V DC Type-E Operational Amplifier Sp ecifications
Symbol Description Min Typ Max Units Notes
V
OSOA
Input Offset Voltage (absolute value) – 2.5 15 mV For 0.2V < Vin < Vdd - 1.2V.
– 2.5 20 mV For Vin = 0 to 0.2V and Vin > Vdd -
1.2V.
TCV
OSOA
Average Input Offset Voltage Drift – 10 – μV/
o
C
I
EBOA[14]
Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.
C
INOA
Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin depend ent. Temp
= 25
o
C.
V
CMOA
Common Mode Voltage Range 0.0 – Vdd - 1 V
I
SOA
Amplifier Supply Current – 10 30 μA
Table 14. 3.3V DC Operational Amplifier Specifications (continued)
Symbol Description Min Typ Max Units Notes
Table 16. 3.3V DC Type-E Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
V
OSOA
Input Offset Voltage (absolute value) – 2.5 15 mV For 0.2V < Vin < Vdd - 1.2V.
– 2.5 20 mV For Vin = 0 to 0.2V and Vin > Vdd -
1.2V.
TCV
OSOA
Average Input Offset Voltage Drift – 10 – μV/
o
C
I
EBOA[14]
Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.
C
INOA
Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. T emp =
25
o
C.
V
CMOA
Common Mode Voltage Range 0 – Vdd - 1 V
I
SOA
Amplifier Supply Current – 10 30 μA
Note
14.
Atypical behavior: I
EBOA
of Port 0 Pin 0 is below 1 nA at 25
°
C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leaka ge of 200 nA
.
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PRELIMINARY CY8C28xxx
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DC Low Power Comparator Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T
A
≤ 85°C, respectively. T ypical p arameters
apply to 5V at 25°C and are for design guidance only.
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications fo r the voltage and temperature ra nges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Tab le 17 . DC Low Power Comparator Specifications
Symbol Description Min Typ Max Units Notes
V
REFLPC
Low power comparator (LPC) reference
voltage range 0.2 – Vdd - 1 V
V
OSLPC
LPC voltage offset – 2.5 30 mV
I
SLPC
LPC supply current – 10 40 μA
Table 18. 5V DC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
V
OSOB
Input Offset Voltage (Ab solute Value) – 3 12 mV
TCV
OSOB
Average Input Offset Voltage Drift –+6 TBD μV/°C
V
CMOB
Common-Mode Input Voltage Range 0.5 –Vdd - 1.0 V
R
OUTOB
Output Resistance
Power = Low
Power = High –
–1
1–
–Ω
Ω
V
OHIGHOB
High Output Voltage Swing (Load = 32
ohms to Vdd/2)
Power = Low
Power = High
0.5 x Vdd
+ 1.3
0.5 x Vdd
+ 1.3
–
–
–
–
V
V
V
OLOWOB
Low Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x Vdd
- 1.3
0.5 x Vdd
- 1.3
V
V
I
SOB
Supply Current Including Bias Cell (No
Load)
Power = Low
Power = High –
–1.1
2.6 5.1
8.8 mA
mA
PSRR
OB
Supply Voltage Rejection Ratio 60 64 –dB
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Tab le 19 . 3.3V DC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
V
OSOB
Input Offset Voltage (Absolute Value) – 3 12 mV
TCV
OSOB
Average Input Offset Voltage Drift –+6 TBD μV/°C
V
CMOB
Common-Mode Input Voltage Range 0.5 -Vdd - 1.0 V
R
OUTOB
Output Resistance
Power = Low
Power = High –
–1
1–
–Ω
Ω
V
OHIGHOB
High Output Voltage Swing (Load = 1k ohms
to Vdd/2)
Power = Low
Power = High
0.5 x Vdd
+ 1.0
0.5 x Vdd
+ 1.0
–
–
–
–
V
V
V
OLOWOB
Low Output V oltage Swing (Load = 1k ohms
to Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x Vdd
- 1.0
0.5 x Vdd
- 1.0
V
V
I
SOB
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High –0.8
2.0 2.0
4.3 mA
mA
PSRR
OB
Supply Voltage Rejection Ratio 60 64 –dB
[+] Feedback [+] Feedback
PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 39 of 65
DC Switch Mode Pump Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 20. DC Switch Mode Pump (SMP) Specifications
Symbol Description Min Typ Max Units Notes
V
PUMP
5V 5V Output Voltage 4.75 5.0 5.25 V Configuration of footnote.
[15]
Average, neglecting ripple. SMP trip
voltage is set to 5.0V.
V
PUMP
3V 3V Output Voltage 3.00 3.25 3.60 V Configuration of footnote.
[15]
Average, neglecting ripple. SMP trip
voltage is set to 3.25V.
I
PUMP
Available Output Current
V
BAT
= 1.5V, V
PUMP
= 3.25V
V
BAT
= 1.8V, V
PUMP
= 5.0V 8
5–
––
–mA
mA
Configuration of footnote.
[15]
SMP trip voltage is set to 3.25V.
SMP trip voltage is set to 5.0V.
To get better performance, refer to
Cypress application note, AN2349.
V
BAT
5V Input Voltage Range from Battery 1.8 – 5.0 V Configuration of footnote.
[15]
SMP trip
voltage is set to 5.0V.
V
BAT
3V Input Voltage Range from Battery 1.5 – 3.3 V Configuration of footnote.
[15]
SMP trip
voltage is set to 3.25V.
V
BATSTART
Minimum Input Voltage from Battery to
St art Pump 1.1 – – V Configuration of footnote.
[15]
ΔV
PUMP_Line
Line Regulation (over V
BAT
range) – 5 – %V
O
Configuration of footnote.
[15]
V
O
is the
“Vdd Va lue for PUMP Trip” specified
by the VM[2:0] setting in the DC POR
and LVD Specification, Table 30 on
page 45.
ΔV
PUMP_Load
Load Regulation – 5 – %V
O
Configuration of footnote.
[15]
V
O
is the
“Vdd Va lue for PUMP Trip” specified
by the VM[2:0] setting in the DC POR
and LVD Specification, Table 30 on
page 45.
ΔV
PUMP_Ripple
Output Voltage Ripple (depends on
capacitor/load) – 100 – mVp p Configuration of footnote.
[15]
Load is
5mA.
E
3
Efficiency 35 50 – % Configuration of footnote.
[15]
Load is
5 mA. SMP trip voltage is set to 3.25V .
F
PUMP
Switching Frequency – 1.3 – MHz
DC
PUMP
Switching Duty Cycle – 50 – %
Note
15.L
1
= 2 uH inductor, C
1
= 10 uF capacitor, D
1
= Schottky diode. See
Figure 8.
[+] Feedback [+] Feedback
PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 40 of 65
Figure 8. Basic Swit ch Mode Pump Circuit
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications fo r the voltage and temperature ra nges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous T ime PSoC blocks. The power levels for AGND refer to
the power of the Analog C ontinuous Ti me PSoC block. The power levels fo r RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Battery
C1
D1
+PSoC
TM
Vdd
Vss
SMP
V
BAT
V
PUMP
L
1
Note
16.AGND tolerance includes the offsets of the local buffer in the PSoC block.
Tab le 21 . 5V DC Analog Reference Specifications for High Power
Symbol Description Min Typ Max Units
V
BG5
Bandgap Voltage Reference 5V 1.28 1.30 1.32 V
–AGND = Vdd/2
[16]
Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V
–AGND = 2 x BandGap
[16]
2.52 2.60 2.72 V
–AGND = P2[4] (P2[4] = Vdd/2)
[16]
P2[4] - 0.013 P2[4] P2[4] + 0.013 V
–AGND = BandGap
[16]
1.27 1.3 1.34 V
–AGND = 1.6 x BandGap
[16]
2.03 2.08 2.13 V
–AGND Block to Block Variation (AGND = Vdd/2)
[16]
-0.034 0.000 0.034 V
–RefHi = Vdd/2 + BandGap
Vdd
/2 + 1.21
Vdd
/2 + 1.3
Vdd
/2 + 1.382 V
–RefHi = 3 x BandGap 3.75 3.9 4.05 V
–RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) P2[6] + 2.478 P2[6] + 2.6 P2[6] + 2.722 V
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + 1.218 P2[4] + 1.3 P2[4] + 1.382 V
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] -
0.058 P2[4] + P2[6] P2[4] + P2[6] +
0.058 V
–RefHi = 2 x BandGap 2.50 2.60 2.70 V
–RefHi = 3.2 x BandGap 4.02 4.16 4.29 V
–RefLo = Vdd/2 – BandGap
Vdd
/2 - 1.369
Vdd
/2 - 1.30
Vdd
/2 - 1.231 V
–RefLo = BandGap 1.20 1.30 1.40 V
–RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2.489 - P2[6] 2.6 - P2[6] 2.711 - P2[6] V
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - 1.368 P2[4] - 1.30 P2[4] - 1.232 V
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] -
0.042 P2[4] - P2[6] P2[4] - P2[6] +
0.042 V
[+] Feedback [+] Feedback
PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 41 of 65
Tab le 22 . 5V D C Analo g Reference Specifications for Medium Powe r
Symbol Description Min Typ Max Units
V
BG5
Bandgap Voltage Reference 5V 1.28 1.30 1.32 V
–AGND = Vdd/2
[16]
Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V
–AGND = 2 x BandGap
[16]
2.52 2.60 2.72 V
–AGND = P2[4] (P2[4] = Vdd/2)
[16]
P2[4] - 0.013 P2[4] P2[4] + 0.013 V
–AGND = BandGap
[16]
1.27 1.3 1.34 V
–AGND = 1.6 x BandGap
[16]
2.03 2.08 2.13 V
–AGND Block to Block Variation (AGND = Vdd/2)
[16]
-0.034 0.000 0.034 V
–RefHi = Vdd/2 + BandGap
Vdd
/2 + 1.21
Vdd
/2 + 1.3
Vdd
/2 + 1.382 V
–RefHi = 3 x BandGap 3.75 3.9 4.05 V
–RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) P2[6] + 2.478 P2[6] + 2.6 P2[6] + 2.722 V
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + 1.218 P2[4] + 1.3 P2[4] + 1.382 V
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] -
0.058 P2[4] + P2[6] P2[4] + P2[6] +
0.058 V
–RefHi = 2 x BandGap 2.50 2.60 2.70 V
–RefHi = 3.2 x BandGap 4.02 4.16 4.29 V
–RefLo = Vdd/2 – BandGap
Vdd
/2 - 1.369
Vdd
/2 - 1.30
Vdd
/2 - 1.231 V
–RefLo = BandGap 1.20 1.30 1.40 V
–RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2.489 - P2[6] 2.6 - P2[6] 2.711 - P2[6] V
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - 1.368 P2[4] - 1.30 P2[4] - 1.232 V
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] -
0.042 P2[4] - P2[6] P2[4] - P2[6] +
0.042 V
Tab le 23 . 5V D C Analo g Reference Specifications for Low Power
Symbol Description Min Typ Max Units
V
BG5
Bandgap Voltage Reference 5V 1.28 1.30 1.32 V
–AGND = Vdd/2
[16]
Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V
–AGND = 2 x BandGap
[16]
2.52 2.60 2.72 V
–AGND = P2[4] (P2[4] = Vdd/2)
[16]
P2[4] - 0.013 P2[4] P2[4] + 0.013 V
–AGND = BandGap
[16]
1.27 1.3 1.34 V
–AGND = 1.6 x BandGap
[16]
2.03 2.08 2.13 V
–AGND Block to Block Variation (AGND = Vdd/2)
[16]
-0.034 0.000 0.034 V
–RefHi = Vdd/2 + BandGap
Vdd
/2 + 1.21
Vdd
/2 + 1.3
Vdd
/2 + 1.382 V
–RefHi = 3 x BandGap 3.75 3.9 4.05 V
–RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) P2[6] + 2.478 P2[6] + 2.6 P2[6] + 2.722 V
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + 1.218 P2[4] + 1.3 P2[4] + 1.382 V
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] -
0.058 P2[4] + P2[6] P2[4] + P2[6] +
0.058 V
–RefHi = 2 x BandGap 2.50 2.60 2.70 V
–RefHi = 3.2 x BandGap 4.02 4.16 4.29 V
–RefLo = Vdd/2 – BandGap
Vdd
/2 - 1.369
Vdd
/2 - 1.30
Vdd
/2 - 1.231 V
–RefLo = BandGap 1.20 1.30 1.40 V
–RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2.489 - P2[6] 2.6 - P2[6] 2.711 - P2[6] V
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - 1.368 P2[4] - 1.30 P2[4] - 1.232 V
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] -
0.042 P2[4] - P2[6] P2[4] - P2[6] +
0.042 V
[+] Feedback [+] Feedback
PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 42 of 65
Tab le 24 . 3.3V DC Analog Reference Specifications for High Power
Symbol Description Min Typ Max Units
V
BG33
Bandgap Voltage Reference 3.3V 1.28 1.30 1.32 V
–AGND = Vdd/2
[16]
Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V
–AGND = 2 x BandGap
[16]
Not Allowed
–AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.009 P2[4] P2[4] + 0. 009 V
–AGND = BandGap
[16]
1.27 1.30 1.34 V
–AGND = 1.6 x BandGap
[16]
2.03 2.08 2.13 V
–AGND Block to Block Variation (AGND = Vdd/2)
[16]
-0.034 0.000 0.034 mV
–RefHi = Vdd/2 + BandGap Not Allowed
–RefHi = 3 x BandGap Not Allowed
–RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] -
0.042 P2[4] + P2[6] P2[4] + P2[6] +
0.042 V
–RefHi = 2 x BandGap 2.50 2.60 2.70 V
–RefHi = 3.2 x BandGap Not Allowed
–RefLo = Vdd/2 - BandGap Not Allowed
–RefLo = BandGap Not Allowed
–RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) No t Allowed
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allo wed
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] -
0.036 P2[4] - P2[6] P2[4] - P2[6] +
0.036 V
Tab le 25. 3.3V DC Analog Reference Specifications for Medium Power
Symbol Description Min Typ Max Units
V
BG33
Bandgap Voltage Reference 3.3V 1.28 1.30 1.32 V
–AGND = Vdd/2
[16]
Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V
–AGND = 2 x BandGap
[16]
Not Allowed
–AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.009 P2[4] P2[4] + 0. 009 V
–AGND = BandGap
[16]
1.27 1.30 1.34 V
–AGND = 1.6 x BandGap
[16]
2.03 2.08 2.13 V
–AGND Block to Block Variation (AGND = Vdd/2)
[16]
-0.034 0.000 0.034 mV
–RefHi = Vdd/2 + BandGap Not Allowed
–RefHi = 3 x BandGap Not Allowed
–RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] -
0.042 P2[4] + P2[6] P2[4] + P2[6] +
0.042 V
–RefHi = 2 x BandGap 2.50 2.60 2.70 V
–RefHi = 3.2 x BandGap Not Allowed
–RefLo = Vdd/2 - BandGap Not Allowed
–RefLo = BandGap Not Allowed
–RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) No t Allowed
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allo wed
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] -
0.036 P2[4] - P2[6] P2[4] - P2[6] +
0.036 V
[+] Feedback [+] Feedback
PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 43 of 65
Note See Application Note AN2012 “Adjusting PSo C Microcon tro ller Trims for Dual Voltage-Range Ope ration” for information on
trimming for operation at 3.3V.
DC Analog PSoC Block Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
DC Analog Mux Bus Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Tab le 26. 3.3V DC Analog Reference Specifications for Lo w Power
Symbol Description Min Typ Max Units
V
BG33
Bandgap Voltage Reference 3.3V 1.28 1.30 1.32 V
–AGND = Vdd/2
[16]
Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V
–AGND = 2 x BandGap
[16]
Not Allowed
–AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.009 P2[4] P2[4] + 0. 009 V
–AGND = BandGap
[16]
1.27 1.30 1.34 V
–AGND = 1.6 x BandGap
[16]
2.03 2.08 2.13 V
–AGND Block to Block Variation (AGND = Vdd/2)
[16]
-0.034 0.000 0.034 mV
–RefHi = Vdd/2 + BandGap Not Allowed
–RefHi = 3 x BandGap Not Allowed
–RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] -
0.042 P2[4] + P2[6] P2[4] + P2[6] +
0.042 V
–RefHi = 2 x BandGap 2.50 2.60 2.70 V
–RefHi = 3.2 x BandGap Not Allowed
–RefLo = Vdd/2 - BandGap Not Allowed
–RefLo = BandGap Not Allowed
–RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) No t Allowed
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allo wed
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] -
0.036 P2[4] - P2[6] P2[4] - P2[6] +
0.036 V
Table 27 . DC Analog PSoC Block Specifications
Symbol Description Min Typ Max Units Notes
R
CT
Resistor Unit Value (Continuous Time) –12.24 – kΩ
C
SC
Capacitor Unit Value (Switch Cap) –80 –fF
Tab le 28 . DC Analog Mux Bus Specifications
Symbol Description Min Typ Max Units Notes
R
SW
Switch Resistance to Common Analog Bus – – 400 ΩVdd ≥ 3.0V
R
VSS
Resistance of Initialization Switch to VSS – – 800 Ω
[+] Feedback [+] Feedback
PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 44 of 65
DC SAR10 ADC Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 29 . DC SAR10 ADC Specifications
Symbol Description Min Typ Max Units Notes
INL
SAR10
Integral nonlinearity -2.5 -2.5 LSB 10-bit resolution
DNL
SAR10
Differential nonlinearity -1.5 -1.5 LSB 10-bit resolution
I
SAR10
Active current consumption 0.08 TBD 0.497 mA
I
VREFSAR10
Input current into P2[5] when configured as
the SAR10 ADC's VREF input. - - 0.5 mA The inte rnal voltage reference buffer is
disabled in this configuration.
V
VREFSAR10
Input reference voltage at P2[5] when
configured as the SAR10 ADC's external
voltage reference.
3.0 -4.95 VWhen VREF is buffered inside the SAR10
ADC, the voltage level at P2[5] (when
configured as the external reference
voltage) must always be at least 300 mV
less than the chip supply voltage level on
the Vdd pin.
(V
VREFSAR10
< (Vdd - 300 mV) ).
V
OSSAR10
Offset voltage 5TBD 9mV
[+] Feedback [+] Feedback
PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 45 of 65
DC POR and LVD Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VL T_CR register . See the PSoC Programmable System-on-Chip
Technical Reference Manual for CY8C28xxx PSoC devices, for more information on the VLT_CR register.
Tab le 30 . DC POR and LVD Specifications
Symbol Description Min Typ Max Units Notes
V
PPOR0R
V
PPOR1R
V
PPOR2R
Vdd Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b –2.91
4.39
4.55 –V
V
V
Vdd must be greater than or equal
to 2.5V during startup, reset from
the XRES pin, or reset from
Watchdog.
V
PPOR0
V
PPOR1
V
PPOR2
Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b –2.82
4.39
4.55 –V
V
V
V
PH0
V
PH1
V
PH2
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
–
–
92
0
0
–
–
–
mV
mV
mV
V
LVD0
V
LVD1
V
LVD2
V
LVD3
V
LVD4
V
LVD5
V
LVD6
V
LVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
2.98
[17]
3.08
3.20
4.08
4.57
4.74
[18]
4.82
4.91
V
V
V
V
V
V
V
V
V
PUMP0
V
PUMP1
V
PUMP2
V
PUMP3
V
PUMP4
V
PUMP5
V
PUMP6
V
PUMP7
Vdd Value for PUMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.96
3.03
3.18
4.11
4.55
4.63
4.72
4.90
3.02
3.10
3.25
4.19
4.64
4.73
4.82
5.00
3.08
3.16
3.32
4.28
4.74
4.82
4.91
5.10
V
V
V
V
V
V
V
V
Notes
17.Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
18.Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
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DC Programming Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Tab le 31 . DC Programming Specifications
Symbol Description Min Typ Max Units Notes
I
DDP
Supply Current During Progra mming or Verify – 5 25 mA
V
ILP
Input Low Voltage During Programming or
Verify – – 0.8 V
V
IHP
Input High Voltage During Programming or
Verify 2.2 – – V
I
ILP
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify – – 0.2 mA Driving inte rnal pull-down
resistor.
I
IHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify – – 1.5 mA Driving inte rnal pull-down
resistor.
V
OLV
Output Low Voltage During Programming or
Verify – – Vss + 0.75 V
V
OHV
Output High Voltage During Programming or
Verify Vdd
- 1.0 –Vdd V
Flash
ENPB
Flash Endurance (per block) 50,000 –––Erase/write cycles per block.
Flash
ENT
Flash Endurance (total)
[19]
1,800,000 –––Erase/write cycl e s .
Flash
DR
Flash Da ta Retentio n 10 – – Years
Note
19.A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operat ions on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit th e total number of cycles to 36x50,000 an d that no single block e ver
sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
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AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 32. AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
F
IMO
Internal Main Oscillator Frequency
23.4 24 24.6
[20]
MHz
T rimmed. Utilizing factory trim values.
F
IMO6
Internal Main Oscillator Frequency for
6MHz
5.5 66.5
[20]
MHz
Trimmed for 5V or 3.3V operation
using factory trim values. SLIMO
Mode = 1.
F
CPU1
CPU Frequency (5V Nominal)
0.091 24 24.6
[20, 21]
MHz
T rimmed. Utilizing factory trim values.
F
CPU2
CPU Frequency (3.3V Nominal)
0.091 12 12.3
[21,22]
MHz
T rimmed. Utilizing factory trim values.
F
BLK5
Digital PSoC Block Frequency
0 - 49.2
[20,21,23]
MHz 4.75V< Vdd <5.25V
F
BLK33
Digital PSoC Block Frequency
024 24.6
[21, 23]
MHz
3.0V<Vdd<3.6V
F
32K1
Internal Low Speed Oscillator
Frequency
15 32 64 kHz
T rimmed. Utilizing factory trim values.
F
32K2
External Crystal Oscillator
–32.768 –kHz
Accuracy is capacitor and crystal
dependent. 50% duty cycle.
F
32K_U
Internal Low Speed Oscillator
Untrimmed Frequency
5 – – kHz
After a reset and before the m8c starts
to run, the ILO is not trimmed. See the
System Resets section of the PSoC
Technica l R eference manual for
details on timing this.
F
PLL
PLL Frequency
–23.986 –MHz
Multiple (x732) of crystal frequency.
Jitter24M2 24 MHz RMS Period Jitter (PLL)
– – 600 ps
T
PLLSLEW
PLL Lock Time
0.5 –10 ms
T
PLLSLEWS
LOW
PLL Lock Time for Low Gain Setting
0.5 –50 ms
T
OS
External Crystal Oscillator Startup to
1%
–1700 2620 ms
T
OSACC
External Crystal Oscillator Startup to
100 ppm
–2800 3800 ms
The crystal oscillator frequency is
within 100 ppm of its final value by the
end of the T
osacc
period. Correct
operation assumes a properly loaded
1 uW maximum drive level 32.768 kHz
crystal. 3.0V £ Vdd £ 5.5V , -40
o
C £ T
A
£ 85
o
C.
Jitter32k 32 kHz RMS Period Jitter
–100 ns
T
XRST
External Reset Pulse Width
10 – – μs
DC24M 24 MHz Duty Cycle
40 50 60 %
DC
ILO
Internal Low Speed Oscillator Duty
Cycle
20 50 80 %
Fout48M 48 MHz Output Frequency
46.8 48.0 49.2
[20,22]
MHz
T rimmed. Utilizing factory trim values.
Jitter24M1 24 MHz RMS Period Jitter (IMO)
–600 ps
F
MAX
Maximum Frequency of Signal on Row
Input or Row Output.
– – 12.3 MHz
T
RAMP
Supply Ramp Time
0 – – μs
Notes
20.4.75V < Vdd < 5.25V.
21.Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
22.3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjust ing PSoC Microcontrolle r T rims for Dual V olt age-Range Opera tion” for information on t rimming for operation
at 3.3V.
23.See the individual user module data sheets for information on maximum frequencies for user modules.
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Figure 9. PLL Lock Timing Diagram
Figure 10. PLL Lock for Low Gain Setting Timing Diagram
Figure 11. External Crystal Oscillator Startup Timing Diagram
Figure 12. 24 MHz Period Jitter (IMO ) Timing Diagram
Figure 13. 32 kHz Period Jitter (ECO) Timing Diagram
24 MHz
F
PLL
PLL
Enable
T
PLLSLEW
PLL
Gain
0
24 MHz
F
PLL
PLL
Enable
T
PLLSLEWLOW
PLL
Gain
1
32 kHz
F
32K2
32K
Select T
OS
Jitter24M1
F
24M
Jitter32k
F
32K2
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AC General Purpose I/O Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Figure 14. GPIO Timing Diagram
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications fo r the voltage and temperature ra nges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only. The Operational Amplifiers covered by these specifications are components of both the Analog
Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. Settling times, slew rates, and gain bandwidth are based
on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 33 . AC GPIO Specifications
Symbol Description Min Typ Max Units Notes
F
GPIO
GPIO Operating Frequency 0 – 12.3 MHz Normal Strong Mode
TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.5 to 5.25V , 10% - 90%
TFallF Fall Time, Normal S trong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25V , 10% - 90%
TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10% - 90%
TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 2 2 – ns Vdd = 3 to 5.25V, 10% - 90 %
Tab le 34 . 5V AC Ope rational Amplifier Specification s
Symbol Description Min Typ Max Units Notes
T
ROA
Rising Settling Time from 80% of ΔV to 0.1% of
ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
T
SOA
Falling Settling Time from 20% of ΔV to 0.1%
of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
SR
ROA
Rising Slew Rate (20% to 80%)(10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
TFallF
TFallS
TRiseF
TRiseS
90%
10%
GPIO
Pin
Output
Voltage
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SR
FOA
Falling Slew Rate (20% to 80%)(10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
BW
OA
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
E
NOA
Noise at 1 kHz
Power = Medium, Opamp Bias = High – 100 – nV/rt-Hz
Tab le 34 . 5V A C Ope rational Amplifier Sp eci f ications (continued)
Symbol Description Min Typ Max Units Notes
Table 35. 3.3V AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
T
ROA
Rising Settling Time from 80% of ΔV to 0.1% of
ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High –
––
–3.92
0.72 μs
μs
T
SOA
Falling Settling Time from 20% of ΔV to 0.1%
of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High –
––
–5.41
0.72 μs
μs
SR
ROA
Rising Slew Rate (20% to 80%)(10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
0.31
2.7 –
––
–V/μs
V/μs
SR
FOA
Falling Slew Rate (80% to 20%)(10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
0.24
1.8 –
––
–V/μs
V/μs
BW
OA
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High 0.67
2.8 –
––
–MHz
MHz
E
NOA
Noise at 1 kHz
Power = Medium, Opamp Bias = High – 100 – nV/rt-Hz
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When bypassed by a capacitor on P2[4], the noise of the anal og ground signal distributed to e ach block is reduced by a factor of up
to TBD (TBD dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor .
Figure 15. Typical AGND Noise with P2[4] Bypass
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level redu ces the noise spectrum level.
Figure 16. Typical Opamp Noise
TBD
TBD
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AC Type-E Operationa l Amplifie r Specificat ions
Table 36 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T
A
≤ 85°C, 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to
5V , 3.3V , or 2.7V at 25°C and are for design guidance only . The Operational Amplifiers covered by these specifications are components
of the Limited Type E Analog PSoC blocks.
AC Low Power Comparator Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T
A
≤ 85°C, respectively. T ypical p arameters
apply to 5V at 25°C and are for design guidance only.
AC Analog Mux Bus Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
AC Digital Block Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 36 . AC Type-E Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
T
COMP
Comparator Mode Response Time, 50 mV
Overdrive – 100 ns
Tab le 37 . AC Low Power Comparator Specifications
Symbol Description Min Typ Max Units Notes
T
RLPC
LPC Response Time – – 50 μs≥ 50 mV overd riv e comparator
reference set within V
REFLPC
.
Tab le 38 . AC Analog Mux Bus Specifications
Symbol Description Min Typ Max Units Notes
F
SW
Switch Rate – – 3.17 MHz
Table 39 . AC Digital Block Specifications
Function Description Min Typ Max Units Notes
All
Functions Maximum Block Clocking Frequency (> 4.75V) – – 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Block Clocking Frequency (< 4.75V) – – 24.6 MHz 3.0V < Vdd < 4.75V.
Timer Capture Pulse Width 50
[24]
– – ns
Maximum Frequency, No Capture – – 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, With Captur e – – 24.6 MHz
Counter Enable Pulse Width 50
[24]
– – ns
Maximum Frequency, No Enable Input – – 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Freque ncy, Enable Input – – 24.6 MHz
Dead
Band Kill Pulse Width:
Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 50
[24]
– – ns
Disable Mode 50
[24]
– – ns
Maximum Freque ncy – – 49.2 MHz 4.75V < Vdd < 5.25V.
CRCPRS
(PRS
Mode)
Maximum Input Clock Frequency – – 49.2 MHz 4.75V < Vdd < 5. 25V.
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AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications fo r the voltage and temperature ra nges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
CRCPRS
(CRC
Mode)
Maximum Input Clock Frequency – – 24.6 MHz
SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz
due to 2 x over clocking.
SPIS Maximum Input Clock Frequency – – 4.1 MHz
Width of SS_ Negated Between Transmissions 50
[24]
– – ns
Trans-
mitter Full Vdd Range
Vdd ≥ 4.75V, 2 Stop Bits
–
–
–
–
24.6
49.2
MHz
MHz
Maximum data rate at 3.16 MHz
due to 8 x over clocking.
Maximum data rate at 6.30 MHz
due to 8 x over clocking.
Receiver Full Vdd Range
Vdd ≥ 4.75V, 2 Stop Bits
–
–
–
–
24.6
49.2
MHz
MHz
Maximum data rate at 3.16 MHz
due to 8 x over clocking.
Maximum data rate at 6.30 MHz
due to 8 x over clocking.
Table 39 . AC Digital Block Specifications (continued)
Function Description Min Typ Max Units Notes
Note
24.50 ns minimum input pulse width i s based on the input synchronizers running at 24 MHz (42 ns nominal period).
Table 40. 5V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
T
ROB
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High –
––
–2.5
2.5 μs
μs
T
SOB
Falling Settling Time to 0.1%, 1V Step, 100 pF
Load
Power = Low
Power = High
–
––
–2.2
2.2 μs
μs
SR
ROB
Rising Slew Rate (20% to 80%), 1V S t ep, 100 pF
Load
Power = Low
Power = High
0.65
0.65 –
––
–V/μs
V/μs
SR
FOB
Falling Slew Rate (80% to 20%), 1V S tep, 100 pF
Load
Power = Low
Power = High
0.65
0.65 –
––
–V/μs
V/μs
BW
OB
Small Signal Bandwidth, 20mV
pp
, 3dB BW, 100 pF
Load
Power = Low
Power = High
0.8
0.8 –
––
–MHz
MHz
BW
OB
Large Signal Bandwidth, 1V
pp
, 3dB BW, 100 pF
Load
Power = Low
Power = High
300
300 –
––
–kHz
kHz
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AC SAR10 ADC Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
AC External Cloc k Specific at ion s
The following tables list guaranteed maximum and minimum specifications fo r the voltage and temperature ra nges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Tab le 41 . 3.3V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
T
ROB
Rising Settling Time to 0.1%, 1V S tep, 100 pF Load
Power = Low
Power = High –
––
–3.8
3.8 μs
μs
T
SOB
Falling Settling T ime to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High –
––
–2.6
2.6 μs
μs
SR
ROB
Rising Slew Rate (20% to 80%), 1V Step, 100 pF
Load
Power = Low
Power = High
0.5
0.5 –
––
–V/μs
V/μs
SR
FOB
Falling Slew Rate (80% to 20%), 1V Step, 100 pF
Load
Power = Low
Power = High
0.5
0.5 –
––
–V/μs
V/μs
BW
OB
Small Signal Bandwidth, 20mV
pp
, 3dB BW, 100 pF
Load
Power = Low
Power = High
0.7
0.7 –
––
–MHz
MHz
BW
OB
Large Signal Bandwidth, 1V
pp
, 3dB BW, 100 pF
Load
Power = Low
Power = High
200
200 –
––
–kHz
kHz
Table 42 . AC SAR10 ADC Specifications
Symbol Description Min Typ Max Units Notes
F
INSAR10
Input clock frequency for SAR10 ADC – – 2.7 MHz
F
SSAR10
Sample rate for SAR10 ADC
SAR10 ADC Resolution = 10 bits – – 192.6 ksps For 10-bit resolution, the
sample rate is the ADC's input
clock divided by 14.
Tab le 43. 5V AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
F
OSCEXT
Frequency 0.093 – 24.6 MHz
– High Period 20.6 –5300 ns
– Low Period 20.6 ––ns
– Power Up IMO to Switch 150 – – μs
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AC Programming Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Tab le 44 . 3.3V A C External Clock Specifications
Symbol Description Min Typ Max Units Notes
F
OSCEXT
Frequency with CPU Clock divide by 1
[25]
0.093 – 12.3 MHz
F
OSCEXT
Frequency with CPU Clock divide by 2 or
greater
[26]
0.186 – 24.6 MHz
– High Period with CPU Clock divide by 1 41.7 –5300 ns
– Low Period with CPU Clock divide by 1 41.7 ––ns
– Power Up IMO to Switch 150 – – μs
Tab le 45 . AC Programming Specifications
Symbol Description Min Typ Max Units Notes
T
RSCLK
Rise Time of SCLK 1 – 20 ns
T
FSCLK
Fall Time of SCLK 1 – 20 ns
T
SSCLK
Data Setup Time to Falling Edge of SCLK 40 – – ns
T
HSCLK
Data Hold Time from Falling Edge of SCLK 40 – – ns
F
SCLK
Frequency of SCLK 0 – 8 MHz
T
ERASEB
Flash Erase Time (Block) –40 –ms
T
WRITE
Flash Block Write Time –40 –ms
T
DSCLK
Data Out Delay from Falling Edge of SCLK – – 55 ns Vdd > 3.6
T
DSCLK3
Data Out Delay from Falling Edge of SCLK – – 70 ns 3.0 ≤ Vdd ≤ 3.6
T
ERASEALL
Flash Erase Time (Bulk) –80 –ms Erase all blocks and protection
fields at once.
T
PROGRAM_HOT
Flash Block Erase + Fl a s h Bl ock Write Time – – 100
[27]
ms 0°C ≤ Tj ≤ 100°C
T
PROGRAM_COLD
Flash Block Erase + Fl a s h Bl ock Write Time – – 200
[27]
ms -40°C ≤ Tj ≤ 0°C
Notes
25.Maximum CPU frequency is 12 MHz at 3.3V . With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
26.
If the frequency of the ext ernal cloc k is great er than 12 MHz, the CPU clock divider must be s et to 2 o r great er. In this case, the CPU c lock divide r en sures tha t the f ift y perce nt
duty cycle requirement is met
.
27.For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note, AN2015 at http://ww.cypress.com under App lication Notes for more information.
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AC I2C Specifications
The following table lists guaranteed ma ximum and minimum spe cificati ons for the voltage and temperature ranges: 4.75 V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Figure 17. Definition for Timing for Fast/Standard Mod e on the I
2
C Bus
Tab le 46. AC Characteristic s of the I
2
C SDA and SCL Pins
Symbol Description Standard Mode Fa st Mode Units Notes
Min Max Min Max
F
SCLI2C
SCL Clock Frequency 0 100 0 400 kHz
T
HDSTAI2C
Hold Time (repeated ) START Condition. After
this period, the first clock pulse is generated. 4.0 –0.6–μs
T
LOWI2C
LOW Period of the SCL Clock 4.7 –1.3–μs
T
HIGHI2C
HIGH Period of the SCL Clock 4.0 –0.6–μs
T
SUSTAI2C
Setup T ime for a Repeated START Condition 4.7 –0.6–μs
T
HDDATI2C
Data Hold Time 0 –0–μs
T
SUDATI2C
Data Setup Time 250 –100
[28]
–ns
T
SUSTOI2C
Setup Time for STOP Condition 4.0 –0.6–μs
T
BUFI2C
Bus Free Time Between a STOP and START
Condition 4.7 –1.3–μs
T
SPI2C
Pulse Width of spikes are suppressed by the
input filter. ––050ns
SDA
SCL
SSr SP
T
BUFI2C
T
SPI2C
T
HDSTAI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
Note
28.A Fast-Mode I2C-bus device can be used in a Standard -Mode I2C-bus system, but the requirement t
SU;DAT
Š 250 ns must t hen be met. This is a utomatically t he case
if the device does not stretch the L OW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line t
rmax
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 57 of 65
Packaging Information
This section illustrates the packaging specifications for the CY8C28xxx PSoC devices, along with the thermal impe dances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area o n the target PCB th an th e chip’s footprint. For a detailed descri ption of
the emulation tools’ dimensions, refer to the drawings at http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 18. 20-Pin (210-Mil) SSOP
51-85077 *C
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 59 of 65
Figure 21. 48-Pin (7x7 mm) QFN
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Figure 22. 56-Pin SSOP Package
001-13191 *C
51-85062 *C
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 60 of 65
Thermal Impedances
Capacitance on Crystal Pins
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Tab le 47. Thermal Impedance s per Package
Package Typical θ
JA [29]
20 SSOP 80.8 °C/W
28 SSOP 45.4 °C/W
44 TQFP 24.0 °C/W
48 QFN 16.7 °C/W
56 SSOP 67.5 °C/W
Tab le 48 . Typical Package Capacitance on Crystal Pins
Package Package Capacitance
20 SSOP Pin9 = 0.0056 pF
Pin11 = 0.006048 pF
28 SSOP Pin13 = 0.006796 pF
Pin15 = 0.006755 pF
44 TQFP Pin16 = 0.009428 pF
Pin18 = 0.008635 pF
48 QFN Pin17 = 0.008493 pF
Pin19 = 0.008742 pF
56 SSOP Pin27 = 0.007916 pF
Pin31 = 0.007132 pF
Tab le 49 . Solder Reflow Peak Temperature
Package Minimum Peak Temperature
[30]
Maximum Peak Temperature
20 SSOP 245 °C260 °C
28 SSOP 245 °C260 °C
44 TQFP 245 °C260 °C
48 QFN 245 °C260 °C
56 SSOP 245 °C260 °C
Notes
29.T
J
= T
A
+ POWER x θ
JA
30.Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5
o
C with Sn-Pb or 245 ± 5
o
C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 61 of 65
Development Tool Selection
This section presents the development tools available for all current PSoC device families including the CY8C28xxx family.
Software
PSoC Designer
At the core of the PSoC development software suite is PSoC
Designer . Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for over half a
decade. PSoC Designer is available free of charge at
http://www.cypress.com/psocdesigner.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC Programmer is available free of charge
at http://www.cypress.com/psocprogrammer.
PSoC C Compilers
CY3202 is the optio nal upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It can be purchased from the
Cypress Online Store. At http://www.cypress.com, click the
Online Store shoppin g cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a
current list of available items.
Development Kits
All development kits can be purchased from the Cypress Online
Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyp ing and deve lopment with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the content of specific memory locations. Advanced
emulation features are supported in PSoC Designer. The kit
includes:
■
PSoC Designer Software CD
■
ICE-Cube In-Circuit Emulator
■
Pod kit for CY8C29x66 PSoC Family
■
Cat-5 Adapter
■
Mini-Eval Programming Board
■
110 ~ 240V Po wer Supply, Euro-Plug Adapter
■
ISSP Cable
■
USB 2.0 Cable and Blue Cat-5 Cable
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
CY3210-ExpressDK PSoC Express Development Kit
The CY3210-ExpressDK is for advanced prototyping and devel-
opment with PSoC Express (may be used with ICE-Cube
In-Circuit Emulator). It provides access to I
2
C buses, voltage
reference, switches, upgradeable modules and more. The kit
includes:
■
PSoC Express Software CD
■
Express Development Board
■
4 Fan Modules
■
2 Proto Modules
■
MiniProg In-System Serial Programmer
■
MiniEval PCB Evaluation Board
■
Jumper Wire Kit
■
USB 2.0 Cable
■
Serial Cable (DB9)
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
2 CY8C24423A-24PXI 28-PDIP Chip Sa mples
■
2 CY8C27443-24PXI 28-PDIP Chip Samples
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
Evaluation Tools
All evaluation tools can be pu rchased from the Cypress Online
Store.
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Samp le
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Samp le
■
PSoC Designer Software CD
■
Getting S tarted Guide
■
USB 2.0 Cable
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 62 of 65
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
Device Programmer s
All device programmers can be purchased from the Cypress
Online Sto r e.
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note: The CY3207ISSP programmer needs the PSoC ISSP
software. It is not compatible with the PSoC Programmer
software. The latest PSoC ISSP software for this kit can be
downloaded from http://www.cypress.com. The kit includes:
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
Accessories (Emulation and Programming)
3rd-Party Tools
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during devel-
opment and producti on. Specifi c details for each of these tools
can be found at http://www.cypress.com under DESIGN
RESOURCES >> Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note “Debugging - Build a PSoC
Emulator into Your Board - AN2323” at
http://www.cypress.com/an2323.
Table 50 . Emulation and Programming Accessories
Part # Pin Package Pod Kit
[31]
Foot Kit
[32]
Adapter
[33]
CY8C28243-24PVXI 20 SSOP CY3250-28XXX CY3250-20SSOP-FK
Adapters can be found at
http://www.emulation.com.
CY8C28403-24PVXI
CY8C28413-24PVXI
CY8C28433-24PVXI
CY8C28445-24PVXI
CY8C28452-24PVXI
28 SSOP CY3250-28XXX CY3250-28SSOP-FK
CY8C28513-24AXI
CY8C28533-24AXI
CY8C28545-24AXI
44 TQFP CY3250-28XXX CY3250-44TQFP-FK
CY8C28623-24LTXI
CY8C28643-24LTXI
CY8C28645-24LTXI
48 QFN CY3250-28XXXQFN CY3250-48QFN-FK
Notes
31.Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.
32.Foot kit includes surface mount feet that can be soldered to the target PCB.
33.Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 63 of 65
Ordering Information
The following table lists the CY8C28xxx PSoC devices key package features and ordering codes.
Package
Ordering Code
Temperature Range
CapSense
Digital Blocks
Regular Analog Blocks
Limited Analog Blo cks
HW I
2
C
Decimators
10-bit SAR ADC
Digital I/O Pins
Analog Inputs
Analog Outputs
Flash (KBytes)
RAM (KBytes)
XRES Pin
28-Pin (210 Mil) SSOP CY8C28403-24PVXI -40 to 85 N 12 0 0 2 0 Y 24 8 0 16 1 Y
28-Pin (210 Mil) SSOP
(Tape and Reel) CY8C28403-24PVXIT -40 to 85 N 12 0 0 2 0 Y 24 8 0 16 1 Y
28-Pin (210 Mil) SSOP CY8C28413-24PVXI -40 to 85 Y 12 0 4 1 2 Y 24 24 0 16 1 Y
28-Pin (210 Mil) SSOP
(Tape and Reel) CY8C28413-24PVXIT -40 to 85 Y 12 0 4 1 2 Y 24 24 0 16 1 Y
44-Pin TQFP CY8C28513-24AXI -40 to 85 Y 12 0 4 1 2 Y 40 40 0 16 1 Y
44-Pin TQFP (Tape
and Reel) CY8C28513-24AXIT -40 to 85 Y 12 0 4 1 2 Y 40 40 0 16 1 Y
48-Pin Sawn QFN CY8C28623-24LTXI -40 to 85 N 12 6 0 2 2 N 44 10 2 16 1 Y
48-Pin Sawn QFN
(Tape and Reel) CY8C28623-24L TXIT -40 to 85 N 12 6 0 2 2 N 44 10 2 16 1 Y
28-Pin (210 Mil) SSOP CY8C28433-24PVXI -40 to 85 Y 12 6 4 1 4 Y 24 24 2 16 1 Y
28-Pin (210 Mil) SSOP
(Tape and Reel) CY8C28433-24PVXIT -40 to 85 Y 12 6 4 1 4 Y 24 24 2 16 1 Y
44-Pin TQFP CY8C28533-24AXI -40 to 85 Y 12 6 4 1 4 Y 40 40 2 16 1 Y
44-Pin TQFP (Tape
and Reel) CY8C28533-24AXIT -40 to 85 Y 12 6 4 1 4 Y 40 40 2 16 1 Y
20-Pin (210 Mil) SSOP CY8C28243-24PVXI -40 to 85 N 12 12 0 2 4 Y 16 16 4 16 1 Y
20-Pin (210 Mil) SSOP
(Tape and Reel) CY8C28243-24PVXIT -40 to 85 N 12 12 0 2 4 Y 16 16 4 16 1 Y
48-Pin Sawn QFN CY8C28643-24LTXI -40 to 85 N 12 12 0 2 4 Y 44 44 4 16 1 Y
48-Pin Sawn QFN
(Tape and Reel) CY8C28643-24L TXIT -40 to 85 N 12 12 0 2 4 Y 44 44 4 16 1 Y
28-Pin (210 Mil) SSOP CY8C28445-24PVXI -40 to 85 Y 12 12 4 2 4 Y 24 24 4 16 1 Y
28-Pin (210 Mil) SSOP
(Tape and Reel) CY8C28445-24PVXIT -40 to 85 Y 12 12 4 2 4 Y 24 24 4 16 1 Y
44-Pin TQFP CY8C28545-24AXI -40 to 85 Y 12 12 4 2 4 Y 40 40 4 16 1 Y
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PRELIMINARY CY8C28xxx
Document Number: 001-48111 Rev. *D Page 64 of 65
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (F AE).
Ordering Code Definitions
44-Pin TQFP (Tape
and Reel) CY8C28545-24AXIT -40 to 85 Y 12 12 4 2 4 Y 40 40 4 16 1 Y
48-Pin Sawn QFN CY8C28645-24LTXI -40 to 85 Y 12 12 4 2 4 Y 44 44 4 16 1 Y
48-Pin Sawn QFN
(Tape and Reel) CY8C28645-24L TXIT -40 to 85 Y 12 12 4 2 4 Y 44 44 4 16 1 Y
28-Pin (210 Mil) SSOP CY8C28452 -24PVXI -40 to 85 Y 8 12 4 1 4 N 24 24 4 16 1 Y
28-Pin (210 Mil) SSOP
(Tape and Reel) CY8C28452-24PVXIT -40 to 85 Y 8 12 4 1 4 N 24 24 4 16 1 Y
56-Pin SSOP OCD CY8C28000-24PVXI -40 to 85 Y 12 12 4 2 4 Y 44 44 4 16 1 Y
Package
Ordering Code
Temperature Range
CapSense
Digita l Blocks
Regular Analog Blocks
Limited Analog Blo cks
HW I
2
C
Decimators
10-bit SAR ADC
Digital I/O Pins
Analog Inputs
Analog Outputs
Flash (KBytes)
RAM (KBytes)
XRES Pin
CY 8 C 28 xxx - SP xxxx
Package Type: Thermal Rating:
PX = PDIP Pb-free C = Commercial
SX = SOIC Pb-free I = Industrial
PVX = SSOP Pb-free E = Extended
LTX/LFX/LKX = QFN Pb-free
AX = TQFP Pb-free
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Co de : 8 = Cypress PSoC
Company ID: CY = Cypress
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Document Number: 001-48111 Rev. *D Revise d August 10, 2009 Page 65 of 65
PSoC Design er™ is a tradem ark and PS oC® i s a reg istered tr ademark of Cypress Semico nductor Corp. Al l oth er tradema rks or registe red trademarks refer enced herein are pr operty of the respec tive
corporation s. Pu rchas e of I 2C comp one nts from C ypres s or on e of its sublice nsed A sso ciate d Companies conv eys a licens e unde r th e Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their
respective holders.
PRELIMINARY CY8C28xxx
© Cypress Semicondu ctor Corpor ation, 2008-200 9. The informati on cont ained herein is subject to change witho ut notice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress prod ucts a re n ot war ran t ed no r int end ed to be us ed fo r
medical, life supp or t, l if e savi n g, cr it ical control or safety applicatio ns, unless pursuant to an express writte n ag reement with Cypress. Furthermor e, Cyp ress doe s not auth or iz e its products for use as
critical components in life-support systems where a malfunction or failur e may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and interna tional trea ty provisi ons. Cyp ress he reby gra nt s to l icense e a per sonal , non-excl usive , no n-tran sferab le lic ense to copy, use, modify, create derivative works of ,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of lice nsee product to be used on ly in conjunction wit h a Cypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, m odification, transl ation, compilatio n, or represent ation of this S ource Code exce pt as specified above is prohib ited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNE SS FOR A PARTICULAR PURPOSE. Cypre ss reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liabil ity ar ising ou t of t he app licati on or us e of an y product or circ uit de scrib ed herei n. Cypr ess does n ot auth orize it s product s for use a s critical componen ts in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at www.cypress.com/sales.
Products
PSoC psoc.cypress.com
Clocks & Buffers clocks.cypress.com
Wireless wireless.cypress.com
Memories memory.cypress.com
Image Sensors image.cypress.com
Document Title: CY8C28243, CY8C28403, CY8C2841 3, CY8C28433, CY8C28445, CY8C28452, CY8C28513, CY8C28533,
CY8C28545, CY8C28623, CY8C28643, CY8C28645 PSoC® Program mable System-on-Chip
Document Number: 001-48111
Revision ECN No. Origin of
Change Submission
Date Description of Cha ng e
** 2593460 BTK/PYRS 10/20/08 New document (Revision **).
*A 2652217 BTK/PYRS 02/02/09 Extensive updates to content.
Added registers maps.
Updated Getting Started section
Updated Development Tools section
Added some SAR10 ADC specifications.
Added more analog system figures
*B 2675937 BTK 03/18/09 Updated DC Analog Reference Specifications tables
Minor content updates
*C 2679015 HMI 03/26/2009 Post to external web.
*D 2750217 TDU 08/10/09 Updates to Electrica l Specificatons section
Minor content updates
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