CY8C28243, CY8C28403, CY8C28413 PRELIMINARY CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 (R) PSoC Programmable System-on-Chip Features Varied Resource Options Within One PSoC Device Group Powerful Harvard Architecture Processor M8C Processor Speeds up to 24 MHz 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed 3.0V to 5.25V Operating Voltage Operating Voltages Down to 1.5V Using On-Chip Switched Mode Pump (SMP) Industrial Temperature Range: -40C to +85C Advanced Reconfigurable Peripherals (PSoC Blocks) Up to 12 Rail-to-Rail Analog PSoC Blocks Provide: * Up to 14-Bit ADCs * Up to 9-Bit DACs * Programmable Gain Amplifiers * Programmable Filters and Comparators * Multiple ADC configurations * Dedicated SAR ADC, up to 192 ksps with Sample and Hold * Up to 4 Synchronized or Independent Delta-Sigma ADCs for Advanced Applications Up to 4 Limited Type E Analog Blocks Provide: * Dual Channel Capacitive Sensing Capability * Comparators with Programmable DAC Reference * Up to 10-bit Single-Slope ADCs Up to 12 Digital PSoC Blocks Provide: * 8 to 32-Bit Timers, Counters, and PWMs * Shift Register, CRC, and PRS Modules * Up to 3 Full-Duplex UARTs * Up to 6 Half-Duplex UARTs * Multiple Variable Data Length SPITM Masters or Slaves * Connectable to All GPIO Complex Peripherals by Combining Blocks Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO Analog Input on All GPIO 30 mA Analog Outputs on GPIO Configurable Interrupt on all GPIO Additional System Resources 2 Up to 2 Hardware I C Resources * Each Resource Implements Slave, Master, or Multi-Master Modes * Operation Between 0 and 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Flexible Internal Voltage References Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoC DesignerTM) Full Featured In-Circuit Emulator, and Programmer Full Speed Emulation Flexible and Functional Breakpoint Structure 128K Trace Memory System Block Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 PSoC CORE System Bus Global Digital Interconnect SRAM 1K Global Analog Interconnect Flash 16K CPU Core (M8C) Sleep and Watchdog Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Clocks 2 MACs ANALOG SYSTEM Analog Block Array Digital Block Array Programmable Pin Configurations 25 mA Sink, 10 mA Drive on All GPIO Cypress Semiconductor Corporation Document Number: 001-48111 Rev. *D SROM Interrupt Controller Precision, Programmable Clocking Internal 2.5% 24/48 MHz Main Oscillator Optional 32.768 kHz Crystal for Precise On-Chip Clocks Optional External Oscillator, up to 24 MHz Internal Low Speed, Low Power Oscillator for Watchdog and Sleep Functionality Flexible On-Chip Memory 16K Bytes Flash Program Storage 50,000 Erase/Write Cycles 1K Bytes SRAM Data Storage In-System Serial Programming (ISSPTM) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Analog Drivers 4 Type 2 2 I2C Decimators Blocks POR and LVD System Resets Analog Ref. Analog Input Muxing Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised August 10, 2009 [+] Feedback PRELIMINARY CY8C28xxx PSoC Functional Overview The PSoC family consists of many devices with On-Chip Controllers. These devices are designed to replace multiple traditional MCU based system components with one low cost single chip programmable component. A PSoC device includes configurable analog blocks, digital blocks, and interconnections. This architecture enables the user to create customized peripheral configurations to match the requirements of each individual application. In addition, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. alone or combined with other blocks to create 8, 16, 24, and 32-bit peripherals, which are called user modules. The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. Figure 1. Digital System Block Diagram[1] Port 5 Port 0 Port 2 Digital Clocks From Core To Analog System To System Bus DIGITAL SYSTEM The CY8C28xxx group of PSoC devices described in this data sheet have multiple resource configuration options available. Therefore, not every resource mentioned in this data sheet is available for each CY8C28xxx subgroup. The CY8C28x45 subgroup has a full feature set of all resources described. There are six more segmented subgroups that allow designers to use a device with only the resources and functionality necessary for a specific application. See Table 2 on page 6 to determine the resources available for each CY8C28xxx subgroup. The same information is also presented in more detail in the Ordering Information section. Row 0 DBC00 DBC01 4 DCC02 DCC03 4 Row Output Configuration Row Input Configuration Digital PSoC Block Array 8 8 DBC10 DBC11 DCC12 DCC13 4 Row 2 DBC20 DBC21 DCC22 4 DCC23 4 GIE[7:0] GIO[7:0] The PSoC Core 4 Global Digital Interconnect 8 Row Output Configuration Row Input Configuration Row 1 Row Output Configuration Row Input Configuration 8 The architecture for this specific PSoC device family, as shown in the System Block Diagram on page 1, consists of four main areas: PSoC Core, Digital System, Analog System, and System Resources. The configurable global bus system allows all the device resources to be combined into a complete custom system. PSoC CY8C28xxx family devices have up to six I/O ports that connect to the global digital and analog interconnects, providing access to up to 12 digital blocks and up to 16 analog blocks. The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable general Purpose I/O (GPIO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microcontroller. Port 1 Port 3 Port 4 GOE[7:0] GOO[7:0] Digital peripheral configurations include: PWMs (8 to 16 bit, One-shot and Multi-shot capability) PWMs with Dead band/Kill (8 to 16 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) Full-duplex 8-bit UARTs (up to 3) with selectable parity Half-duplex 8-bit UARTs (up to 6) with selectable parity Variable length SPI slave and master Up to 6 total slaves and masters (8-bit) Supports 8 to 16 bit operation I2C slave, master, or multi-master (up to 2 available as System Resources) IrDA (up to 3) The Digital System Pseudo Random Sequence Generators (8 to 32 bit) The Digital System is composed of up to 12 configurable digital PSoC blocks. Each block is an 8-bit resource that can be used Cyclical Redundancy Checker/Generator (16 bit) Shift Register (2 to 32 bit) Memory encompasses 16K bytes of Flash for program storage, 1K bytes of SRAM for data storage. The PSoC device incorporates flexible internal clock generators, including a 24 MHz internal main oscillator (IMO) accurate to 2.5% over temperature and voltage. A low power 32 kHz internal low speed oscillator (ILO) is provided for the sleep timer and watch dog timer (WDT). The 32.768 kHz external crystal oscillator (ECO) is available for use as a real time clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. PSoC GPIOs provide connections to the CPU, and digital and analog resources. Each pin's drive mode may be selected from 8 options, which allows great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. Note 1. CY8C28x52 devices do not have digital block row 2. They have two digital rows with eight total digital blocks. Document Number: 001-48111 Rev. *D Page 2 of 65 [+] Feedback PRELIMINARY CY8C28xxx Some of the more common PSoC analog functions (most available as user modules) are: Analog-to-digital converters (6 to 14-bit resolution, up to 4, selectable as Incremental or Delta Sigma) All GPIO P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] AGNDIn RefIn The Analog System is composed of up to 16 configurable analog blocks, each containing an opamp circuit that allows the creation of complex analog signal flows. Some devices in this PSoC family have an analog multiplex bus that can connect to every GPIO pin. This bus can also connect to the analog system for analysis with comparators and analog-to-digital converters. It can be split into two sections for simultaneous dual-channel processing. Figure 2. Analog System Block Diagram for CY8C28x45 and CY8C28x52 Devices P2[3] Analog Mux Bus The Analog System P2[1] P2[6] P2[4] P2[2] P2[0] Dedicated 10-bit SAR ADC with sample rates up to 192 ksps Synchronized, simultaneous Delta Sigma ADCs (up to 4) Filters (2 to 8 pole band-pass, low-pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 6, with 16 selectable thresholds) DACs (up to 4, with 6 to 9-bit resolution) Multiplying DACs (up to 4, with 6 to 9-bit resolution) ACC00 ACC01 ACC02 ACC03 High current output drivers (up to 4 with 30 mA drive) ASC10 ASD11 ASC12 ASD13 1.3V reference (as a System Resource) ASD20 ASC21 ASD22 ASC23 DTMF Dialer Modulators Correlators Peak detectors Many other topologies possible Array Input Configuration ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] ACI4[1:0] ACI5[1:0] Block Array ACE00 ACE01 ASE10 ASE11 Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-48111 Rev. *D Page 3 of 65 [+] Feedback PRELIMINARY CY8C28xxx Figure 3. Analog System Block Diagram for CY8C28x43 Devices Figure 4. Analog System Block Diagram for CY8C28x33 Devices All GPIO All GPIO P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] P0[7] P0[5] P0[6] P0[3] P0[4] P2[1] P2[6] P2[4] P0[2] P2[3] P2[1] P2[2] P0[0] AGNDIn RefIn Analog Mux Bus P2[3] Analog Mux Bus AGNDIn RefIn P0[1] P2[0] P2[6] P2[4] Array Input Configuration Array Input Configuration ACI0[1:0] ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI1[1:0] ACI4[1:0] ACI5[1:0] ACI3[1:0] Block Array Block Array ACC00 ACC01 ACC00 ACC01 ACC02 ACC03 ASC10 ASD11 ASC10 ASD11 ASC12 ASD13 ASD20 ASC21 ASD20 ASC21 ASD22 ASC23 ACE00 ACE01 ASE10 ASE11 Analog Reference Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators Interface to Digital System AGNDIn RefIn Bandgap RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-48111 Rev. *D Page 4 of 65 [+] Feedback PRELIMINARY CY8C28xxx Figure 5. Analog System Block Diagram for CY8C28x23 Devices Figure 6. Analog System Block Diagram for CY8C28x13 Devices P0[7] All GPIO P0[5] Analog Mux Bus P0[6] P0[7] P0[3] P0[4] P0[1] P0[5] P0[6] P0[4] P0[2] P2[3] P0[0] AGNDIn RefIn P2[1] P0[3] P0[2] P0[1] P0[0] P2[6] Array Input Configuration P2[4] ACI0[1:0] ACI1[1:0] Array Input Configuration ACI0[1:0] Block Array ACI1[1:0] Block Array ACC00 ACC01 ASC10 ASD11 ASD20 ASC21 ACE00 ACE01 ASE10 ASE11 Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap Analog Reference M8C Interface (Address Bus, Data Bus, Etc.) Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-48111 Rev. *D Page 5 of 65 [+] Feedback PRELIMINARY CY8C28xxx 2K 32K up to up to up to 3 12 44 up to 4 up to 6 up to 1K 12/4[2] 16K 2 4 4 12 256 Bytes 16K 6 1K 16K 6 256 Bytes 4K 4 256 Bytes 8K 2 4[3] 512 Bytes 8K 0 2 4[3] 256 Bytes 4K 0 0 3[4] 512 Bytes 8K 4 16 Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. CY8C28xxx up to 44 CY8C27x43 up to 44 CY8C24x94 64 1 4 48 2 2 Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. CY8C24x23A up to 24 1 4 12 2 2 Up to four decimators provide custom hardware filters for digital signal processing applications such as Delta-Sigma ADCs and CapSense capacitive sensor measurement. CY8C23x33 up to 1 4 12 2 2 CY8C21x34 up to 28 1 4 28 0 CY8C21x23 16 1 4 8 CY8C20x34 up to 28 0 0 28 An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.5V battery cell, providing a low cost boost converter. PSoC Device Characteristics There are other PSoC device groups in addition to the one described in this data sheet. These other PSoC device groups offer even more resource options. The following table lists the resources available for specific PSoC device groups. The PSoC device group covered by this data sheet is highlighted. Table 2. CY8C28xxx Device Characteristics CY8C28x03 N 12 0 0 2 0 up to up to 24 8 0 CY8C28x13 Y 12 0 4 1 2 up to up to 40 40 0 CY8C28x23 N 12 6 0 2 2 up to up to 44 10 2 CY8C28x33 Y 12 6 4 1 4 up to up to 40 40 2 CY8C28x43 N 12 12 0 2 4 up to up to 44 44 4 CY8C28x45 Y 12 12 4 2 4 up to up to 44 44 4 CY8C28x52 Y 8 12 4 1 4 up to up to 24 24 4 PSoC Part Number Analog Outputs An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. Analog Inputs The devices covered by this data sheet all have the same architecture, specifications, and ratings. However, the amount of some hardware resources varies from device to device within the group. The following table lists resources available for the specific device subgroups covered by this data sheet. Digital I/O Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. Decimators 12 HW I2C Up to two I2C resources provide 0 to 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. I2C resources have hardware address detection capability. 8 Digital Blocks Regular Analog Blocks Limited Analog Blocks CapSense Flash Size 12 up to 64 SRAM Size 4 CY8C29x66 PSoC Part Number Analog Blocks Analog Columns 4 Digital Blocks 12 Digital Rows Analog Outputs Table 1. PSoC Device Characteristics Digital I/O System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a multiplier, multiple decimators, switch mode pump, low voltage detection, and power on reset. Statements describing the merits of each system resource follow: Analog Inputs System Resources Notes 2. Has 12 regular analog blocks and four limited Type-E analog blocks 3. Limited analog functionality. 4. Two analog blocks and one CapSense. Document Number: 001-48111 Rev. *D Page 6 of 65 [+] Feedback PRELIMINARY CY8C28xxx Getting Started The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming details, see the PSoC(R) Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at www.cypress.com/psoc. Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here: www.cypress.com/psoc. Select Application Notes under the Documentation tab. Development Kits PSoC Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Training Free PSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family. PSoC Designer Software Subsystems System-Level View A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC On-Chip Controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. Chip-Level View The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.4. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools. Solutions Library Code Generation Tools Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Development Tools PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. Document Number: 001-48111 Rev. *D Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Page 7 of 65 [+] Feedback PRELIMINARY CY8C28xxx Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in the PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. In-Circuit Emulator Organize and Connect A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. You can build signal chains at the chip level by interconnecting user modules to each other and the I/O pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select components 2. Configure components 3. Organize and Connect 4. Generate, Verify, and Debug Select Components Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called "drivers" and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2C-bus, for example), and the logic to control how they interact with one another (called valuators). In the chip-level view, the components are called "user modules". User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. Configure Components Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Document Number: 001-48111 Rev. *D In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer's output to a digital signal, and a PWM to control the fan. In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Page 8 of 65 [+] Feedback PRELIMINARY CY8C28xxx Document Conventions Acronyms Used Units of Measure The following table lists the acronyms that are used in this document. A units of measure table is located in the Electrical Specifications section. Table 8 on page 31 lists all the abbreviations used to measure the PSoC devices. Acronym Description AC alternating current ADC analog-to-digital converter API application programming interface CPU central processing unit CT continuous time DAC digital-to-analog converter DC direct current ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory FSR full scale range GPIO general purpose I/O GUI graphical user interface HBM human body model ICE in-circuit emulator ILO internal low speed oscillator IMO internal main oscillator I/O input/output IPOR imprecise power on reset LSb least-significant bit LVD low voltage detect MSb most-significant bit PC program counter PLL phase-locked loop POR power on reset PPOR precision power on reset PSoC Programmable System-on-Chip PWM pulse width modulator SAR successive approximation register SC switched capacitor SLIMO slow IMO SMP switch mode pump SRAM static random access memory Document Number: 001-48111 Rev. *D Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h' or `b' are decimal. Page 9 of 65 [+] Feedback PRELIMINARY CY8C28xxx Pinouts This section describes, lists, and illustrates the CY8C28xxx PSoC device pins and pinout configurations. The CY8C28xxx PSoC devices are available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital I/O. However, Vss, Vdd, SMP, and XRES are not capable of Digital I/O. 20-Pin Part Pinout Table 3. 20-Pin Part Pinout (SSOP) Type Pin No. Digital Analog 1 I/O I, M, S Pin Name Description CY8C28243 20-Pin PSoC Device S, AI, M, P0[7] 1 P0[7] Analog column mux and SAR ADC input.[6] 2 S, AIO, M, P0[5] S, AIO, M, P0[3] 3 2 I/O I/O, M, S P0[5] Analog column mux and SAR ADC S, AI, M, P0[1] 4 input. Analog column output.[6, 7] SMP 5 SSOP 3 I/O I/O, M, S P0[3] Analog column mux and SAR ADC I2C0 SCL, M, P1[7] 6 input. Analog column output.[6, 7] I2C0 SDA, M, P1[5] 7 4 I/O I, M, S P0[1] Analog column mux and SAR ADC M, P1[3] 8 [6] input. I2C0 SCL, XTALin, M, P1[1] 9 Vss 5 Output SMP Switch Mode Pump (SMP) 10 connection to external components. 6 I/O M P1[7] I2C0 Serial Clock (SCL). 7 I/O M P1[5] I2C0 Serial Data (SDA). 8 I/O M P1[3] 9 I/O M P1[1] Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. 10 Power Vss Ground connection. 11 I/O M P1[0] Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. 12 I/O M P1[2] I2C1 Serial Data (SDA).[8] 13 I/O M P1[4] Optional External Clock Input (EXTCLK). 14 I/O M P1[6] I2C1 Serial Clock (SCL).[8] 15 Input XRES Active high external reset with internal pull down. 16 I/O I, M, S P0[0] Analog column mux and SAR ADC input.[6] 17 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input. Analog column output.[6, 9] 18 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input. Analog column output.[6, 9] 19 I/O I, M, S P0[6] Analog column mux and SAR ADC input.[6] 20 Power Vdd Supply voltage. LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input. 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S XRES P1[6], M, I2C1 SCL P1[4], M, EXTCLK P1[2], M, I2C1 SDA P1[0], M, XTALout, I2C0 SDA Notes 5. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices for details. 6. CY8C28x52 and CY8C28x23 devices do not have a SAR ADC. Therefore, this pin does not function as a SAR ADC input for these devices. 7. CY8C28x13 and CY8C28x03 devices do not have any analog output buffers. Therefore, this pin does not function as an analog column output for these devices. 8. CY8C28x52, CY8C28x13, and CY8C28x33 devices only have one I2C block. Therefore, this GPIO does not function as an I2C pin for these devices. 9. CY8C28x33, CY8C28x23, CY8C28x13, and CY8C28x03 devices do not have an analog output buffer for this pin. Therefore, this pin does not function as an analog column output for these devices. Document Number: 001-48111 Rev. *D Page 10 of 65 [+] Feedback PRELIMINARY CY8C28xxx 28-Pin Part Pinout Table 4. 28-Pin Part Pinout (SSOP) Type Description Pin No. Digital Analog Pin Name 1 I/O I, M, S P0[7] Analog column mux and SAR ADC input.[6] 2 I/O I/O, M, S P0[5] Analog column mux and SAR ADC input. Analog column output.[6, 7] 3 I/O I/O, M, S P0[3] Analog column mux and SAR ADC input. Analog column output.[6, 7] 4 I/O I, M, S P0[1] Analog column mux and SAR ADC input.[6] 5 I/O M P2[7] 6 I/O M P2[5] 7 I/O I, M P2[3] Direct switched capacitor block input.[10] 8 I/O I, M P2[1] Direct switched capacitor block input.[10] SMP Switch Mode Pump (SMP) connection to external components. 9 Output 10 I/O M P1[7] I2C0 Serial Clock (SCL). 11 I/O M P1[5] I2C0 Serial Data (SDA). 12 I/O M P1[3] 13 I/O M P1[1] 14 Power Vss M P1[0] Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. 16 I/O M P1[2] I2C1 Serial Data (SDA).[8] 17 I/O M P1[4] Optional External Clock Input (EXTCLK). 18 I/O M P1[6] I2C1 Serial Clock (SCL).[8] I/O I, M P2[0] Direct switched capacitor block input.[11] 21 I/O I, M P2[2] Direct switched capacitor block input.[11] 22 I/O M P2[4] External Analog Ground (AGND). 23 I/O M P2[6] External Voltage Reference (VRef). 24 I/O I, M, S P0[0] Analog column mux and SAR ADC input.[6] 25 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input. Analog column output.[6, 9] 26 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input. Analog column output.[6, 9] 27 I/O I, M, S P0[6] Analog column mux and SAR ADC input.[6] Vdd Supply voltage. Power SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef P2[4], M, External AGND P2[2], M, AI P2[0], M, AI XRES P1[6], M, I2C1 SCL P1[4], M, EXTCLK P1[2], M, I2C1 SDA P1[0], M, XTALout, I2C0 SDA XRES Active high external reset with internal pull down. 20 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Ground connection. I/O Input S, AI, M, P0[7] S, AIO, M, P0[5] S, AIO, M, P0[3] S, AI, M, P0[1] M, P2[7] M, P2[5] AI, M, P2[3] AI, M, P2[1] SMP I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] M, P1[3] I2C0 SCL, XTALin, M, P1[1] Vss Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. 15 19 CY8C28403, CY8C28413, CY8C28433, CY8C28445, and CY8C28452 28-Pin PSoC Devices LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input Notes 10. This pin is not a direct switched capacitor block analog input for CY8C28x03 and CY8C28x13 devices. 11. This pin is not a direct switched capacitor block analog input for CY8C28x03, CY8C28x13, CY8C28x23, and CY8C28x33 devices. Document Number: 001-48111 Rev. *D Page 11 of 65 [+] Feedback PRELIMINARY CY8C28xxx 44-Pin Part Pinout Table 5. 44-Pin Part Pinout (TQFP) 9 10 11 12 13 14 15 16 I/O I/O I/O I/O I/O I/O I/O I/O 17 18 Pin Name M M M M M M M M P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] I/O M Vss P1[0] 19 20 21 22 23 24 25 26 I/O I/O I/O I/O I/O I/O I/O M M M M M M M 27 28 29 30 31 32 33 34 35 36 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M M M M I, M I, M M M I, M, S I/O, M S P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] 37 I/O I/O, M, S P0[4] 38 39 40 41 I/O I, M, S Power I/O I, M, S I/O I/O, M, S P0[6] Vdd P0[7] P0[5] 42 I/O P0[3] Output Input I/O, M, S P1[2] P1[4] P1[6] P3[0] P3[2] P3[4] P3[6] XRES P2[7], M P0[1], M, AI, S P0[3], M, AIO, S P0[5], M, AIO, S P0[7], M, AI, S Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef Direct switched capacitor block input.[10] Direct switched capacitor block input.[10] Switch Mode Pump (SMP) connection to external components. I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. Ground connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. I2C1 Serial Data (SDA).[8] Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL).[8] I2C1 Serial Data (SDA).[8] I2C1 Serial Clock (SCL).[8] Active high external reset with internal pull down. 44 43 42 41 40 39 38 37 36 35 34 P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP CY8C28513, CY8C28533, and CY8C28545 44-Pin PSoC Devices Description M, P2[5] AI, M, P2[3] AI, M, P2[1] M, P4[7] M, P4[5] M, P4[3] M, P4[1] SMP M, P3[7] M, P3[5] M, P3[3] 1 2 3 4 5 6 7 8 9 10 11 TQFP 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 Type Digital Analog I/O M I/O I, M I/O I, M I/O M I/O M I/O M I/O M Output P2[4], M, External AGND P2[2], M, AI P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M XRES P3[6], M P3[4], M P3[2], M, I2C1 SCL M, P3[1] I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] M, P1[3] I2C0 SCL, XTALin, M, P1[1] Vss I2C0 SDA, XTALout, M, P1[0] I2C1 SDA, M, P1[2] EXTCLK, M, P1[4] I2C1 SCL, M, P1[6] I2C1 SDA, M, P3[0] Pin No. Direct switched capacitor block input.[11] Direct switched capacitor block input.[11] External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux and SAR ADC input.[6] Analog column mux and SAR ADC input. Analog column output.[6, 9] Analog column mux and SAR ADC input. Analog column output.[6, 9] Analog column mux and SAR ADC input.[6] Supply voltage. Analog column mux and SAR ADC input.[6] Analog column mux and SAR ADC input. Analog column output.[6, 7] Analog column mux and SAR ADC input. Analog column output.[6, 7] Analog column mux and SAR ADC input.[6] 43 I/O I, M, S P0[1] 44 I/O P2[7] LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input. Document Number: 001-48111 Rev. *D Page 12 of 65 [+] Feedback PRELIMINARY CY8C28xxx 48-Pin Part Pinout Table 6. 48-Pin Part Pinout (QFN[12]) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 18 19 P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP Direct switched capacitor block input.[10] Direct switched capacitor block input.[10] Switch Mode Pump (SMP) connection to external components. CY8C28623, CY8C28643, and CY8C28645 48-Pin PSoC Devices P2[5], M P2[7], M P0[1], M, AI, S P0[3], M, AIO, S P0[5], M, AIO, S P0[7], M, AI, S Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef Description AI, M, P2[3] AI, M, P2[1] M, P4[7] M, P4[5] M, P4[3] M, P4[1] SMP M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[3] 1 2 3 4 5 6 7 8 9 10 11 12 M M M M M M M M M M P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] I/O M Vss P1[0] 20 21 I/O I/O M M P1[2] P1[4] 22 23 24 25 26 27 28 29 I/O I/O I/O I/O I/O I/O I/O M M M M M M M 30 31 32 33 I/O I/O I/O I/O M M M M P1[6] P5[0] P5[2] P3[0] I2C1 Serial Data (SDA).[8] P3[2] I2C1 Serial Clock (SCL).[8] P3[4] P3[6] XRES Active high external reset with internal pull down. P4[0] P4[2] P4[4] P4[6] 34 35 I/O I/O I, M I, M P2[0] P2[2] Direct switched capacitor block input.[11] Direct switched capacitor block input.[11] 42 43 I/O 36 I/O M P2[4] External Analog Ground (AGND). 44 I/O 37 I/O M P2[6] External Voltage Reference (VRef). 45 I/O 38 I/O I, M, S P0[0] Power Input I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. Ground connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. I2C1 Serial Data (SDA).[8] Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL).[8] QFN (Top View) 36 35 34 33 32 31 30 29 28 27 26 25 P2[4], M, External AGND P2[2], M, AI P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M XRES P3[6], M P3[4], M P3[2], M, I2C1 SCL P3[0], M, I2C1 SDA M, P5[1] I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] M, P1[3] I2C0 SCL, XTALin, M, P1[1] Vss I2C0 SDA, XTALout, M, P1[0] I2C1 SDA, M, P1[2] EXTCLK, M, P1[4] I2C1 SCL, M, P1[6] M, P5[0] M, P5[2] 8 9 10 11 12 13 14 15 16 17 Pin Name 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 Type Digital Analog I/O I, M I/O I, M I/O M I/O M I/O M I/O M Output 13 14 15 16 17 18 19 20 21 22 23 24 Pin No. Pin No. 41 Type Digital Analog I/O I, M, S Pin Name Power I, M, S Vdd P0[7] I/O, M, S I/O, M, S I, M, S P0[5] Analog column mux and SAR ADC 46 I/O input.[6] 39 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input. 47 I/O M Analog column output.[6, 9] 40 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input. 48 I/O M Analog column output.[6, 9] LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input. P0[6] P0[3] P0[1] Description Analog column mux and SAR ADC input.[6] Supply voltage. Analog column mux and SAR ADC input.[6] Analog column mux and SAR ADC input. Analog column output.[6, 7] Analog column mux and SAR ADC input. Analog column output.[6, 7] Analog column mux and SAR ADC input.[6] P2[7] P2[5] Note 12. The QFN package has a center pad that must be connected to ground (Vss) Document Number: 001-48111 Rev. *D Page 13 of 65 [+] Feedback PRELIMINARY CY8C28xxx 56-Pin Part Pinout The 56-pin SSOP part is for the CY8C28000 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 7. 56-Pin Part Pinout (SSOP) Pin No. Type Digital Analog Pin Name 2 I/O I, M, S P0[7] Analog column mux and SAR ADC input. 3 I/O I/O, M, S P0[5] Analog column mux and SAR ADC input. Analog column output. 4 I/O I/O, M, S P0[3] Analog column mux and SAR ADC input. Analog column output. 5 I/O I, M, S P0[1] Analog column mux and SAR ADC input. 6 I/O M P2[7] 7 I/O M P2[5] 8 I/O I P2[3] Direct switched capacitor block input. Direct switched capacitor block input. 1 NC 9 I/O I P2[1] 10 I/O M P4[7] Description No connection. 11 I/O M P4[5] 12 I/O I, M P4[3] 13 I/O I, M 14 OCD M OCDE OCD even data I/O. 15 OCD M OCDO OCD odd data output. 16 Output P4[1] SMP Switch Mode Pump (SMP) connection to required external components. 17 I/O M P3[7] 18 I/O M P3[5] 19 I/O M P3[3] 20 I/O M P3[1] 21 I/O M P5[3] 22 I/O M P5[1] 23 I/O M P1[7] I2C0 Serial Clock (SCL). 24 I/O M P1[5] I2C0 Serial Data (SDA). 25 NC I/O M P1[3] 27 I/O M P1[1] Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. Power NC S, AI, M, P0[7] S, AIO, M, P0[5] S, AIO, M, P0[3] S, AI, M, P0[1] M, P2[7] M, P2[5] AI, M, P2[3] AI, M, P2[1] M, P4[7] M, P4[5] M, P4[3] M, P4[1] OCDE OCDO SMP M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[3] M, P5[1] I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] NC M, P1[3] SCLK, I2C0 SCL, XTALIn, M, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SSOP 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef P2[4], M, External AGND P2[2], M, AI P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M CCLK HCLK XRES P3[6], M P3[4], M P3[2], M, I2C1 SCL P3[0], M, I2C1 SDA P5[2], M P5[0], M P1[6], M, I2C1 SCL P1[4], M, EXTCLK P1[2], M, I2C1 SDA P1[0], M, XTALOut, I2C0 SDA, SDATA NC NC Not for Production No connection. 26 28 CY8C28000 56-Pin PSoC Device Vdd Ground connection. 29 NC No connection. 30 NC No connection. 31 I/O M P1[0] Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. 32 I/O M P1[2] I2C1 Serial Data (SDA). 33 I/O M P1[4] Optional External Clock Input (EXTCLK). 34 I/O M P1[6] I2C1 Serial Clock (SCL). 35 I/O M P5[0] 36 I/O M P5[2] 37 I/O M P3[0] I2C1 Serial Data (SDA). 38 I/O M P3[2] I2C1 Serial Clock (SCL). 39 I/O M P3[4] 40 I/O M P3[6] Document Number: 001-48111 Rev. *D Page 14 of 65 [+] Feedback PRELIMINARY CY8C28xxx Table 7. 56-Pin Part Pinout (SSOP) (continued) Pin No. Type Digital 41 Analog Input Pin Name Description XRES Active high external reset with internal pull down. 42 OCD M HCLK OCD high-speed clock output. 43 OCD M CCLK OCD CPU clock output. 44 I/O M P4[0] 45 I/O M P4[2] 46 I/O M P4[4] 47 I/O M P4[6] 48 I/O I, M P2[0] Direct switched capacitor block input. 49 I/O I, M P2[2] Direct switched capacitor block input. 50 I/O M P2[4] External Analog Ground (AGND). 51 I/O M P2[6] External Voltage Reference (VRef). 52 I/O I, M, S P0[0] Analog column mux and SAR ADC input. 53 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input. Analog column output. 54 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input. Analog column output. 55 I/O I, M, S P0[6] Analog column mux and SAR ADC input. Vdd Supply voltage. 56 Power LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, M = Analog Mux Bus Input, and OCD = On-Chip Debug. Document Number: 001-48111 Rev. *D Page 15 of 65 [+] Feedback PRELIMINARY CY8C28xxx Register Reference This section lists the registers of the CY8C28xxx PSoC devices. For detailed register information, reference the PSoC Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices. Register Conventions Register Mapping Tables The register conventions specific to this section are listed in the following table. CY8C28xxx PSoC devices have a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XIO bit in the Flag register (CPU_F) determines which bank of registers CPU instructions access. When the XIO bit is set the registers in Bank 1 are accessed by CPU instructions. When the XIO bit is cleared the registers in Bank 0 are accessed by CPU instructions. Convention R Description Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific Document Number: 001-48111 Rev. *D Note In the following register mapping tables, blank fields are reserved and should not be accessed. Page 16 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY8C28x03 Register Map Bank 0 Table: User Space Name PRT0DR Addr (0,Hex) 00 Access RW Name DBC20DR0 Addr (0,Hex) 40 Access # Name Addr (0,Hex) 80 PRT0IE 01 RW DBC20DR1 41 W 81 PRT0GS 02 RW DBC20DR2 42 RW 82 PRT0DM2 03 RW DBC20CR0 43 # PRT1DR 04 RW DBC21DR0 44 PRT1IE 05 RW DBC21DR1 PRT1GS 06 RW PRT1DM2 07 PRT2DR Access Name RDI2RI Addr (0,Hex) C0 Access RW RDI2SYN C1 RW RDI2IS C2 RW 83 RDI2LT0 C3 RW # 84 RDI2LT1 C4 RW 45 W 85 RDI2RO0 C5 RW DBC21DR2 46 RW 86 RDI2RO1 C6 RW RW DBC21CR0 47 # 87 RDI2DSM C7 RW 08 RW DCC22DR0 48 # 88 PRT2IE 09 RW DCC22DR1 49 W 89 C9 PRT2GS 0A RW DCC22DR2 4A RW 8A CA C8 PRT2DM2 0B RW DCC22CR0 4B # 8B CB PRT3DR 0C RW DCC23DR0 4C # 8C CC PRT3IE 0D RW DCC23DR1 4D W 8D CD PRT3GS 0E RW DCC23DR2 4E RW 8E CE PRT3DM2 0F RW DCC23CR0 4F # 8F PRT4DR 10 RW 50 90 CUR_PP D0 RW PRT4IE 11 RW 51 91 STK_PP D1 RW PRT4GS 12 RW 52 92 PRT4DM2 13 RW 53 93 IDX_PP D3 RW PRT5DR 14 RW 54 94 MVR_PP D4 RW PRT5IE 15 RW 55 95 MVW_PP D5 RW PRT5GS 16 RW 56 96 I2C0_CFG D6 RW PRT5DM2 17 RW 57 97 I2C0_SCR D7 # 58 98 I2C0_DR D8 RW 18 CF D2 19 59 99 I2C0_MSCR D9 # 1A 5A 9A INT_CLR0 DA RW 1B 5B 9B INT_CLR1 DB RW 1C 5C 9C INT_CLR2 DC RW 1D 5D 9D INT_CLR3 DD RW 1E 5E 9E INT_MSK3 DE RW 1F 5F 9F INT_MSK2 DF RW # 60 A0 INT_MSK0 E0 RW DBC00DR0 20 DBC00DR1 21 W 61 A1 INT_MSK1 E1 RW DBC00DR2 22 RW 62 A2 INT_VC E2 RC DBC00CR0 23 # 63 A3 RES_WDT E3 W DBC01DR0 24 # 64 A4 I2C1_SCR E4 # DBC01DR1 25 W 65 A5 I2C1_MSCR E5 # DBC01DR2 26 RW 66 A6 DBC01CR0 27 # DCC02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W DCC02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA R MUL0_DH EA R DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB R MUL0_DL EB R DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW DBC10DR0 30 # 70 RDI0RI B0 RW F0 DBC10DR1 31 W 71 RDI0SYN B1 RW F1 DBC10DR2 32 RW 72 RDI0IS B2 RW F2 DBC10CR0 33 # 73 RDI0LT0 B3 RW F3 DBC11DR0 34 # 74 RDI0LT1 B4 RW F4 DBC11DR1 35 W 75 RDI0RO0 B5 RW F5 DBC11DR2 36 RW 76 RDI0RO1 B6 RW DBC11CR0 37 # 77 RDI0DSM B7 RW DCC12DR0 38 # 78 RDI1RI B8 RW I2C1_DR 67 RW E6 A7 E7 F6 CPU_F F7 DCC12DR1 39 W 79 RDI1SYN B9 RW F9 DCC12DR2 3A RW 7A RDI1IS BA RW FA DCC12CR0 3B # 7B RDI1LT0 BB RW FB DCC13DR0 3C # 7C RDI1LT1 BC RW FC DCC13DR1 3D W 7D RDI1RO0 BD RW DCC13DR2 3E RW 7E RDI1RO1 BE RW DCC13CR0 3F # Blank fields are Reserved and should not be accessed. Document Number: 001-48111 Rev. *D 7F # Access is bit specific. RL F8 FD CPU_SCR1 RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see "Mapping Exceptions" on page 251 FE # FF # Page 17 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY8C28x03 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 Addr (1,Hex) 00 Access RW PRT0DM1 01 RW PRT0IC0 02 RW PRT0IC1 03 PRT1DM0 Name DBC20FN Addr (1,Hex) 40 Access RW Name Addr (1,Hex) 80 Access DBC20IN 41 RW SADC_TSCMPL 81 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RW DBC20CR1 43 RW 04 RW DBC21FN 44 PRT1DM1 05 RW DBC21IN PRT1IC0 06 RW PRT1IC1 07 PRT2DM0 Name RDI2RI Addr (1,Hex) C0 Access RW RDI2SYN C1 RW RDI2IS C2 RW 83 RDI2LT0 C3 RW RW 84 RDI2LT1 C4 RW 45 RW 85 RDI2RO0 C5 RW DBC21OU 46 RW 86 RDI2RO1 C6 RW RW DBC21CR1 47 RW 87 RDI2DSM C7 RW 08 RW DCC22FN 48 RW 88 PRT2DM1 09 RW DCC22IN 49 RW 89 C9 PRT2IC0 0A RW DCC22OU 4A RW 8A CA C8 PRT2IC1 0B RW DCC22CR1 4B RW 8B CB PRT3DM0 0C RW DCC23FN 4C RW 8C CC PRT3DM1 0D RW DCC23IN 4D RW 8D CD PRT3IC0 0E RW DCC23OU 4E RW 8E CE PRT3IC1 0F RW DCC23CR1 4F RW 8F PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW PRT4DM1 11 RW 51 91 GDI_E_IN D1 RW PRT4IC0 12 RW 52 92 GDI_O_OU D2 RW PRT4IC1 13 RW 53 93 GDI_E_OU D3 RW PRT5DM0 14 RW 54 94 D4 CF PRT5DM1 15 RW 55 95 D5 PRT5IC0 16 RW 56 96 D6 PRT5IC1 17 RW 57 97 D7 18 58 98 D8 19 59 99 D9 1A 5A 9A DA 1B 5B 9B DB 1C 5C 9C DC 1D 5D 9D OSC_GO_EN DD RW 1E 5E 9E OSC_CR4 DE RW 1F 5F 9F OSC_CR3 DF RW DBC00FN 20 RW 60 GDI_O_IN_CR A0 RW OSC_CR0 E0 RW DBC00IN 21 RW 61 GDI_E_IN_CR A1 RW OSC_CR1 E1 RW DBC00OU 22 RW 62 GDI_O_OU_CR A2 RW OSC_CR2 E2 RW DBC00CR1 23 RW 63 GDI_E_OU_CR A3 RW VLT_CR E3 RW DBC01FN 24 RW 64 RTC_H A4 RW VLT_CMP E4 RW DBC01IN 25 RW 65 RTC_M A5 RW E5 DBC01OU 26 RW 66 RTC_S A6 RW E6 DBC01CR1 27 RW 67 RTC_CR A7 RW DCC02FN 28 RW 68 SADC_CR0 A8 RW IMO_TR E8 RW DCC02IN 29 RW 69 SADC_CR1 A9 RW ILO_TR E9 RW DCC02OU 2A RW SADC_CR2 AA RW BDG_TR EA RW DCC02CR1 2B RW I2C1_CFG 6B RW SADC_CR3 AB RW ECO_TR EB RW DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW EC DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW ED DCC03OU 2E RW TMP_DR2 6E RW I2C1_ADDR AE RW EE DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF DBC10FN 30 RW RDI0RI B0 RW F0 DBC10IN 31 RW SADC_TSCR0 71 RW RDI0SYN B1 RW F1 DBC10OU 32 RW SADC_TSCR1 72 RW RDI0IS B2 RW F2 DBC10CR1 33 RW 73 RDI0LT0 B3 RW F3 DBC11FN 34 RW 74 RDI0LT1 B4 RW F4 DBC11IN 35 RW 75 RDI0RO0 B5 RW F5 DBC11OU 36 RW 76 RDI0RO1 B6 RW DBC11CR1 37 RW 77 RDIODSM B7 RW DCC12FN 38 RW 78 RDI1RI B8 RW DCC12IN 39 RW 79 RDI1SYN B9 RW DCC12OU 3A RW 7A RDI1IS BA RW DCC12CR1 3B RW 7B RDI1LT0 BB RW FB DCC13FN 3C RW 7C RDI1LT1 BC RW FC DCC13IN 3D RW 7D RDI1RO0 BD RW DCC13OU 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE # DCC13CR1 3F RW 7F RDI1DSM BF RW CPU_SCR0 FF # 6A 70 Blank fields are Reserved and should not be accessed. Document Number: 001-48111 Rev. *D # Access is bit specific. E7 F6 CPU_F F7 RL F8 F9 FLS_PR1 FA RW FD *Address has a dual purpose, see "Mapping Exceptions" on page 251 Page 18 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY8C28x13 Register Map Bank 0 Table: User Space Name PRT0DR Addr (0,Hex) 00 Access RW Name DBC20DR0 Addr (0,Hex) 40 Access # Name Addr (0,Hex) 80 PRT0IE 01 RW DBC20DR1 41 W 81 PRT0GS 02 RW DBC20DR2 42 RW 82 PRT0DM2 03 RW DBC20CR0 43 # PRT1DR 04 RW DBC21DR0 44 PRT1IE 05 RW DBC21DR1 PRT1GS 06 RW PRT1DM2 07 PRT2DR Access Name RDI2RI Addr (0,Hex) C0 Access RW RDI2SYN C1 RW RDI2IS C2 RW 83 RDI2LT0 C3 RW # 84 RDI2LT1 C4 RW 45 W 85 RDI2RO0 C5 RW DBC21DR2 46 RW 86 RDI2RO1 C6 RW RW DBC21CR0 47 # 87 RDI2DSM C7 RW 08 RW DCC22DR0 48 # 88 PRT2IE 09 RW DCC22DR1 49 W 89 C9 PRT2GS 0A RW DCC22DR2 4A RW 8A CA C8 PRT2DM2 0B RW DCC22CR0 4B # 8B CB PRT3DR 0C RW DCC23DR0 4C # 8C CC PRT3IE 0D RW DCC23DR1 4D W 8D CD PRT3GS 0E RW DCC23DR2 4E RW 8E CE PRT3DM2 0F RW DCC23CR0 4F # 8F PRT4DR 10 RW 50 90 CUR_PP D0 RW PRT4IE 11 RW 51 91 STK_PP D1 RW PRT4GS 12 RW 52 92 PRT4DM2 13 RW 53 93 IDX_PP D3 RW PRT5DR 14 RW 54 94 MVR_PP D4 RW PRT5IE 15 RW 55 95 MVW_PP D5 RW PRT5GS 16 RW 56 96 I2C0_CFG D6 RW PRT5DM2 17 RW 57 97 I2C0_SCR D7 # 58 98 I2C0_DR D8 RW 18 CF D2 19 59 99 I2C0_MSCR D9 # 1A 5A 9A INT_CLR0 DA RW 1B 5B 9B INT_CLR1 DB RW 1C 5C 9C INT_CLR2 DC RW 1D 5D 9D INT_CLR3 DD RW 1E 5E 9E INT_MSK3 DE RW 1F 5F 9F INT_MSK2 DF RW DBC00DR0 20 # 60 DBC00DR1 21 W DBC00DR2 22 RW 62 DBC00CR0 23 # 63 DBC01DR0 24 # 64 A4 DBC01DR1 25 W 65 A5 DBC01DR2 26 RW 66 A6 DEC_CR0* E6 RW DBC01CR0 27 # 67 A7 DEC_CR1* E7 RW DCC02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W DCC02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA R MUL0_DH EA R DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB R MUL0_DL EB R DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW DBC10DR0 30 # 70 RDI0RI B0 RW F0 DBC10DR1 31 W 71 RDI0SYN B1 RW F1 DBC10DR2 32 RW 72 RDI0IS B2 RW F2 DBC10CR0 33 # 73 RDI0LT0 B3 RW F3 DBC11DR0 34 # 74 RDI0LT1 B4 RW F4 DBC11DR1 35 W 75 RDI0RO0 B5 RW F5 DBC11DR2 36 RW 76 RDI0RO1 B6 RW DBC11CR0 37 # 77 RDI0DSM B7 RW DCC12DR0 38 # 78 RDI1RI B8 RW AMUX_CFG 61 RW DEC0_DH A0 RC INT_MSK0 E0 RW DEC0_DL A1 RC INT_MSK1 E1 RW DEC1_DH A2 RC INT_VC E2 RC DEC1_DL A3 RC RES_WDT E3 W E4 E5 F6 CPU_F F7 RL F8 DCC12DR1 39 W 79 RDI1SYN B9 RW F9 DCC12DR2 3A RW 7A RDI1IS BA RW FA DCC12CR0 3B # 7B RDI1LT0 BB RW DCC13DR0 3C # 7C RDI1LT1 BC RW DAC1_D FC RW DCC13DR1 3D W 7D RDI1RO0 BD RW DAC0_D FD RW DCC13DR2 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE # FF # DCC13CR0 3F # Blank fields are Reserved and should not be accessed. Document Number: 001-48111 Rev. *D 7F # Access is bit specific. FB RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see "Mapping Exceptions" on page 251 Page 19 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY8C28x13 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 Addr (1,Hex) 00 Access RW PRT0DM1 01 RW PRT0IC0 02 RW PRT0IC1 03 PRT1DM0 Name DBC20FN Addr (1,Hex) 40 Access RW Name Addr (1,Hex) 80 Access Addr (1,Hex) C0 Access RW DBC20IN 41 RW SADC_TSCMPL 81 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RDI2SYN C1 RW RDI2IS C2 RW DBC20CR1 43 RW ACE_AMD_CR1 83 RW RW RDI2LT0 C3 04 RW DBC21FN 44 RW RW RDI2LT1 C4 PRT1DM1 05 RW DBC21IN 45 RW ACE_PWM_CR 85 RW RW RDI2RO0 C5 PRT1IC0 06 RW DBC21OU 46 RW ACE_ADC0_CR RW 86 RW RDI2RO1 C6 PRT1IC1 07 RW DBC21CR1 47 RW ACE_ADC1_CR RW 87 RW RDI2DSM C7 PRT2DM0 08 RW DCC22FN 48 RW RW PRT2DM1 09 RW DCC22IN 49 RW ACE_CLK_CR0 89 RW C9 PRT2IC0 0A RW DCC22OU 4A RW ACE_CLK_CR1 8A RW CA ACE_CLK_CR3 84 Name RDI2RI 88 PRT2IC1 0B RW DCC22CR1 4B RW PRT3DM0 0C RW DCC23FN 4C RW PRT3DM1 0D RW DCC23IN 4D RW PRT3IC0 0E RW DCC23OU 4E RW PRT3IC1 0F RW DCC23CR1 4F RW PRT4DM0 10 RW 50 PRT4DM1 11 RW 51 DEC0_CR0 91 PRT4IC0 12 RW 52 DEC_CR3 92 PRT4IC1 13 RW 53 PRT5DM0 14 RW 54 PRT5DM1 15 RW 55 PRT5IC0 16 RW 56 96 PRT5IC1 17 RW C8 8B RW CB 8C RW CC ACE01CR1 8D RW CD ACE01CR2 8E RW CE ASE11CR0 8F RW 90 DEC1_CR0 CF GDI_O_IN D0 RW RW GDI_E_IN D1 RW RW GDI_O_OU D2 RW 93 GDI_E_OU D3 RW 94 DEC0_CR D4 RW DEC1_CR D5 RW 95 RW D6 57 97 18 58 98 MUX_CR0 D8 RW 19 59 99 MUX_CR1 D9 RW 1A 5A MUX_CR2 DA RW 1B 5B 9B MUX_CR3 DB RW 1C 5C 9C IDAC_CR1 DC RW 1D 5D 9D OSC_GO_EN DD RW 1E 5E 9E OSC_CR4 DE RW 1F 5F 9F OSC_CR3 DF RW DEC_CR5 9A D7 RW DBC00FN 20 RW 60 GDI_O_IN_CR A0 RW OSC_CR0 E0 RW DBC00IN 21 RW 61 GDI_E_IN_CR A1 RW OSC_CR1 E1 RW DBC00OU 22 RW 62 GDI_O_OU_CR A2 RW OSC_CR2 E2 RW DBC00CR1 23 RW 63 GDI_E_OU_CR A3 RW VLT_CR E3 RW DBC01FN 24 RW 64 RTC_H A4 RW VLT_CMP E4 RW DBC01IN 25 RW 65 RTC_M A5 RW ADC0_TR E5 RW DBC01OU 26 RW 66 RTC_S A6 RW ADC1_TR E6 RW DBC01CR1 27 RW 67 RTC_CR A7 RW IDAC_CR2 E7 RW DCC02FN 28 RW 68 SADC_CR0 A8 RW IMO_TR E8 RW DCC02IN 29 RW SADC_CR1 A9 RW ILO_TR E9 RW DCC02OU 2A RW SADC_CR2 AA RW BDG_TR EA RW DCC02CR1 2B RW SADC_CR3 AB RW ECO_TR EB RW DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW MUX_CR4 EC RW DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW MUX_CR5 ED RW DCC03OU 2E RW TMP_DR2 6E RW DCC03CR1 2F RW TMP_DR3 6F RW DBC10FN 30 RW DBC10IN 31 RW SADC_TSCR0 71 DBC10OU 32 RW SADC_TSCR1 DBC10CR1 33 RW ACE_AMD_CR0 DBC11FN 34 RW DBC11IN 35 RW DBC11OU 36 DBC11CR1 DCC12FN 69 AMUX_CFG1 6A RW 6B AE EE AMUX_CLK AF RW EF RDI0RI B0 RW F0 RW RDI0SYN B1 RW F1 72 RW RDI0IS B2 RW F2 73 RW RDI0LT0 B3 RW F3 74 RW RDI0LT1 B4 RW F4 ACE_AMX_IN 75 RW RDI0RO0 B5 RW F5 RW ACE_CMP_CR0 76 RW RDI0RO1 B6 RW 37 RW ACE_CMP_CR1 77 RW RDIODSM B7 RW 38 RW RDI1RI B8 RW DCC12IN 39 RW ACE_CMP_GI_EN 79 RW RDI1SYN B9 RW DCC12OU 3A RW ACE_ALT_CR0 7A RW RDI1IS BA RW DCC12CR1 3B RW ACE_ABF_CR0 7B RW RDI1LT0 BB RW DCC13FN 3C RW RDI1LT1 BC RW DCC13IN 3D RW ACE0_CR1 7D RW RDI1RO0 BD RW IDAC_CR0 FD RW DCC13OU 3E RW ACE0_CR2 7E RW RDI1RO1 BE RW CPU_SCR1 FE # DCC13CR1 3F RW ACE0_CR3 7F RW RDI1DSM BF RW CPU_SCR0 FF # 70 78 7C Blank fields are Reserved and should not be accessed. Document Number: 001-48111 Rev. *D # Access is bit specific. F6 CPU_F F7 RL F8 F9 FLS_PR1 FA RW FB FC *Address has a dual purpose, see "Mapping Exceptions" on page 251 Page 20 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY8C28x23 Register Map Bank 0 Table: User Space Name PRT0DR Addr (0,Hex) 00 Access RW Name DBC20DR0 Addr (0,Hex) 40 Access # Name ASC10CR0 Addr (0,Hex) 80 Access RW PRT0IE 01 RW DBC20DR1 PRT0GS 02 RW DBC20DR2 PRT0DM2 03 RW PRT1DR 04 PRT1IE Name RDI2RI Addr (0,Hex) C0 Access RW 41 W ASC10CR1 81 RW 42 RW ASC10CR2 82 RW RDI2SYN C1 RW RDI2IS C2 DBC20CR0 43 # ASC10CR3 83 RW RW RDI2LT0 C3 RW DBC21DR0 44 # ASD11CR0 RW 84 RW RDI2LT1 C4 05 RW DBC21DR1 45 W RW ASD11CR1 85 RW RDI2RO0 C5 PRT1GS 06 RW DBC21DR2 46 RW RW ASD11CR2 86 RW RDI2RO1 C6 PRT1DM2 07 RW DBC21CR0 RW 47 # ASD11CR3 87 RW RDI2DSM C7 PRT2DR 08 RW DCC22DR0 RW 48 # PRT2IE 09 RW DCC22DR1 49 W 89 C9 PRT2GS 0A RW DCC22DR2 4A RW 8A CA 88 C8 PRT2DM2 0B RW DCC22CR0 4B # 8B CB PRT3DR 0C RW DCC23DR0 4C # 8C CC PRT3IE 0D RW DCC23DR1 4D W 8D CD PRT3GS 0E RW DCC23DR2 4E RW 8E CE PRT3DM2 0F RW DCC23CR0 4F # 8F PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW PRT4GS 12 RW 52 ASD20CR2 92 RW PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 # 98 I2C0_DR D8 RW 18 58 CF D2 19 59 99 I2C0_MSCR D9 # 1A 5A 9A INT_CLR0 DA RW 1B 5B 9B INT_CLR1 DB RW 1C 5C 9C INT_CLR2 DC RW 1D 5D 9D INT_CLR3 DD RW 1E 5E 9E INT_MSK3 DE RW 1F 5F 9F INT_MSK2 DF RW DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW DBC00DR1 DBC00DR2 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W DBC01DR0 24 # CMP_CR0 64 # A4 I2C1_SCR E4 # DBC01DR1 25 W ASY_CR 65 # A5 I2C1_MSCR E5 # DBC01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0* E6 RW DBC01CR0 27 # I2C1_DR 67 RW DEC_CR1* E7 RW DCC02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W DCC02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W DCC02DR2 2A RW 6A MUL1_DH AA R MUL0_DH EA R DCC02CR0 2B # 6B MUL1_DL AB R MUL0_DL EB R DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0 DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1 DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2 DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3 DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4 DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5 DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW DCC12DR0 38 # 78 RDI1RI B8 RW A7 F6 CPU_F F7 DCC12DR1 39 W 79 RDI1SYN B9 RW F9 DCC12DR2 3A RW 7A RDI1IS BA RW FA DCC12CR0 3B # 7B RDI1LT0 BB RW FB DCC13DR0 3C # 7C RDI1LT1 BC RW FC DCC13DR1 3D W 7D RDI1RO0 BD RW DCC13DR2 3E RW 7E RDI1RO1 BE RW DCC13CR0 3F # Blank fields are Reserved and should not be accessed. Document Number: 001-48111 Rev. *D 7F # Access is bit specific. RL F8 FD CPU_SCR1 RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see "Mapping Exceptions" on page 251 FE # FF # Page 21 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY8C28x23 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 Addr (1,Hex) 00 Access RW PRT0DM1 01 RW PRT0IC0 02 RW PRT0IC1 03 PRT1DM0 Name DBC20FN Addr (1,Hex) 40 Access RW Name Addr (1,Hex) 80 DBC20IN 41 RW 81 DBC20OU 42 RW 82 RW DBC20CR1 43 RW 04 RW DBC21FN 44 PRT1DM1 05 RW DBC21IN PRT1IC0 06 RW PRT1IC1 07 PRT2DM0 Access Name RDI2RI Addr (1,Hex) C0 Access RW RDI2SYN C1 RW RDI2IS C2 RW 83 RDI2LT0 C3 RW RW 84 RDI2LT1 C4 RW 45 RW 85 RDI2RO0 C5 RW DBC21OU 46 RW 86 RDI2RO1 C6 RW RW DBC21CR1 47 RW 87 RDI2DSM C7 RW 08 RW DCC22FN 48 RW 88 PRT2DM1 09 RW DCC22IN 49 RW 89 C9 PRT2IC0 0A RW DCC22OU 4A RW 8A CA C8 PRT2IC1 0B RW DCC22CR1 4B RW 8B CB PRT3DM0 0C RW DCC23FN 4C RW 8C CC PRT3DM1 0D RW DCC23IN 4D RW 8D CD PRT3IC0 0E RW DCC23OU 4E RW 8E CE PRT3IC1 0F RW DCC23CR1 4F RW 8F PRT4DM0 10 RW 50 PRT4DM1 11 RW 51 DEC0_CR0 91 PRT4IC0 12 RW 52 DEC_CR3 PRT4IC1 13 RW PRT5DM0 14 PRT5DM1 CF 90 GDI_O_IN D0 RW RW GDI_E_IN D1 RW 92 RW GDI_O_OU D2 RW 53 93 RW GDI_E_OU D3 RW RW 54 94 RW DEC0_CR D4 RW 15 RW 55 95 RW DEC1_CR D5 RW PRT5IC0 16 RW 56 96 D6 PRT5IC1 17 RW DEC1_CR0 57 97 D7 18 58 98 D8 19 59 99 1A 5A DEC_CR5 9A D9 RW DA 1B 5B 9B DB 1C 5C 9C DC 1D 5D 9D OSC_GO_EN DD RW 1E 5E 9E OSC_CR4 DE RW 1F 5F 9F OSC_CR3 DF RW DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW DBC01IN 25 RW RTC_M A5 RW E5 DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW E6 DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW DCC02FN 28 RW DCC02IN 29 RW DCC02OU 2A RW DCC02CR1 2B RW I2C1_CFG 6B RW DCC03FN 2C RW TMP_DR0 6C RW AC DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW ED DCC03OU 2E RW TMP_DR2 6E RW I2C1_ADDR AE RW EE DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF DBC10FN 30 RW 70 RDI0RI B0 RW F0 DBC10IN 31 RW 71 RDI0SYN B1 RW F1 DBC10OU 32 RW 72 RDI0IS B2 RW F2 DBC10CR1 33 RW 73 RDI0LT0 B3 RW F3 DBC11FN 34 RW 74 RDI0LT1 B4 RW F4 DBC11IN 35 RW 75 RDI0RO0 B5 RW F5 DBC11OU 36 RW 76 RDI0RO1 B6 RW DBC11CR1 37 RW 77 RDIODSM B7 RW DCC12FN 38 RW 78 RDI1RI B8 RW DCC12IN 39 RW 79 RDI1SYN B9 RW DCC12OU 3A RW 7A RDI1IS BA RW DCC12CR1 3B RW 7B RDI1LT0 BB RW FB DCC13FN 3C RW 7C RDI1LT1 BC RW FC DCC13IN 3D RW 7D RDI1RO0 BD RW DCC13OU 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE # DCC13CR1 3F RW 7F RDI1DSM BF RW CPU_SCR0 FF # 65 68 CLK_CR2 69 RW 6A Blank fields are Reserved and should not be accessed. Document Number: 001-48111 Rev. *D # Access is bit specific. E7 A8 IMO_TR E8 RW A9 ILO_TR E9 RW AA BDG_TR EA RW AB ECO_TR EB RW EC F6 CPU_F F7 RL F8 F9 FLS_PR1 FA RW FD *Address has a dual purpose, see "Mapping Exceptions" on page 251 Page 22 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY8C28x33 Register Map Bank 0 Table: User Space Name PRT0DR Addr (0,Hex) 00 Access RW Name DBC20DR0 Addr (0,Hex) 40 Access # Name ASC10CR0 Addr (0,Hex) 80 Access RW PRT0IE 01 RW DBC20DR1 PRT0GS 02 RW DBC20DR2 PRT0DM2 03 RW PRT1DR 04 PRT1IE Name RDI2RI Addr (0,Hex) C0 Access RW 41 W ASC10CR1 81 RW 42 RW ASC10CR2 82 RW RDI2SYN C1 RW RDI2IS C2 DBC20CR0 43 # ASC10CR3 83 RW RW RDI2LT0 C3 RW DBC21DR0 44 # ASD11CR0 RW 84 RW RDI2LT1 C4 05 RW DBC21DR1 45 W RW ASD11CR1 85 RW RDI2RO0 C5 PRT1GS 06 RW DBC21DR2 46 RW RW ASD11CR2 86 RW RDI2RO1 C6 PRT1DM2 07 RW DBC21CR0 RW 47 # ASD11CR3 87 RW RDI2DSM C7 PRT2DR 08 RW DCC22DR0 RW 48 # PRT2IE 09 RW DCC22DR1 49 W 89 C9 PRT2GS 0A RW DCC22DR2 4A RW 8A CA 88 C8 PRT2DM2 0B RW DCC22CR0 4B # 8B CB PRT3DR 0C RW DCC23DR0 4C # 8C CC PRT3IE 0D RW DCC23DR1 4D W 8D CD PRT3GS 0E RW DCC23DR2 4E RW 8E CE PRT3DM2 0F RW DCC23CR0 4F # 8F PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW PRT4GS 12 RW 52 ASD20CR2 92 RW PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 # 98 I2C0_DR D8 RW 18 58 CF D2 19 59 99 I2C0_MSCR D9 # 1A 5A 9A INT_CLR0 DA RW 1B 5B 9B INT_CLR1 DB RW 1C 5C 9C INT_CLR2 DC RW 1D 5D 9D INT_CLR3 DD RW 1E 5E 9E INT_MSK3 DE RW 1F 5F 9F INT_MSK2 DF RW DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW DBC00DR1 DBC00DR2 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W DBC01DR0 24 # CMP_CR0 64 # DEC2_DH A4 RC DBC01DR1 25 W ASY_CR 65 # DEC2_DL A5 RC DBC01DR2 26 RW CMP_CR1 66 RW DEC3_DH A6 RC DEC_CR0* E6 RW DBC01CR0 27 # 67 DEC3_DL A7 RC DEC_CR1* E7 RW DCC02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W DCC02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA R MUL0_DH EA R DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB R MUL0_DL EB R DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0 DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1 DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2 DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3 DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4 DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5 DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW DCC12DR0 38 # 78 RDI1RI B8 RW E4 E5 F6 CPU_F F7 RL F8 DCC12DR1 39 W 79 RDI1SYN B9 RW F9 DCC12DR2 3A RW 7A RDI1IS BA RW FA DCC12CR0 3B # 7B RDI1LT0 BB RW DCC13DR0 3C # 7C RDI1LT1 BC RW DAC1_D FC RW DCC13DR1 3D W 7D RDI1RO0 BD RW DAC0_D FD RW DCC13DR2 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE # FF # DCC13CR0 3F # Blank fields are Reserved and should not be accessed. Document Number: 001-48111 Rev. *D 7F # Access is bit specific. FB RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see "Mapping Exceptions" on page 251 Page 23 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY8C28x33 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 Addr (1,Hex) 00 Access RW PRT0DM1 01 RW PRT0IC0 02 RW PRT0IC1 03 PRT1DM0 Name DBC20FN Addr (1,Hex) 40 Access RW Name Addr (1,Hex) 80 Access DBC20IN 41 RW SADC_TSCMPL 81 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RW DBC20CR1 43 RW ACE_AMD_CR1 83 RW 04 RW DBC21FN 44 RW Addr (1,Hex) C0 Access RW RDI2SYN C1 RW RDI2IS C2 RW RDI2LT0 C3 RW RDI2LT1 C4 PRT1DM1 05 RW DBC21IN 45 RW ACE_PWM_CR 85 RW RW RDI2RO0 C5 PRT1IC0 06 RW DBC21OU 46 RW ACE_ADC0_CR RW 86 RW RDI2RO1 C6 PRT1IC1 07 RW DBC21CR1 47 RW ACE_ADC1_CR RW 87 RW RDI2DSM C7 PRT2DM0 08 RW DCC22FN 48 RW RW 88 RW PRT2DM1 09 RW DCC22IN 49 RW PRT2IC0 0A RW DCC22OU 4A RW ACE_CLK_CR0 89 RW C9 ACE_CLK_CR1 8A RW CA ACE_CLK_CR3 8B RW 84 Name RDI2RI C8 PRT2IC1 0B RW DCC22CR1 4B RW PRT3DM0 0C RW DCC23FN 4C RW CB PRT3DM1 0D RW DCC23IN 4D RW ACE01CR1 8D RW CD PRT3IC0 0E RW DCC23OU 4E RW ACE01CR2 8E RW CE PRT3IC1 0F RW DCC23CR1 4F RW ASE11CR0 8F RW PRT4DM0 10 RW 50 PRT4DM1 11 RW 51 DEC0_CR0 91 PRT4IC0 12 RW 52 DEC_CR3 92 PRT4IC1 13 RW 53 PRT5DM0 14 RW 54 PRT5DM1 15 RW 55 DEC1_CR0 95 PRT5IC0 16 RW 56 DEC_CR4 96 PRT5IC1 17 RW 57 18 58 19 59 DEC2_CR0 99 1A 5A DEC_CR5 9A 1B 5B 1C 5C 1D 5D 1E 5E 9E 1F 5F 9F 8C CC 90 DEC3_CR0 CF GDI_O_IN D0 RW RW GDI_E_IN D1 RW RW GDI_O_OU D2 RW 93 GDI_E_OU D3 RW 94 DEC0_CR D4 RW RW DEC1_CR D5 RW RW DEC2_CR D6 RW 97 DEC3_CR D7 RW 98 MUX_CR0 D8 RW RW MUX_CR1 D9 RW RW MUX_CR2 DA RW 9B MUX_CR3 DB RW 9C IDAC_CR1 DC RW OSC_GO_EN DD RW OSC_CR4 DE RW OSC_CR3 DF RW 9D RW DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW DBC01IN 25 RW RTC_M A5 RW ADC0_TR E5 RW DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW ADC1_TR E6 RW DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW IDAC_CR2 E7 RW DCC02FN 28 RW SADC_CR0 A8 RW IMO_TR E8 RW DCC02IN 29 RW CLK_CR2 69 RW SADC_CR1 A9 RW ILO_TR E9 RW DCC02OU 2A RW AMUX_CFG1 6A RW SADC_CR2 AA RW BDG_TR EA RW DCC02CR1 2B RW SADC_CR3 AB RW ECO_TR EB RW DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW MUX_CR4 EC RW DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW MUX_CR5 ED RW DCC03OU 2E RW TMP_DR2 6E RW DCC03CR1 2F RW TMP_DR3 6F RW DBC10FN 30 RW DBC10IN 31 RW SADC_TSCR0 71 DBC10OU 32 RW SADC_TSCR1 DBC10CR1 33 RW ACE_AMD_CR0 DBC11FN 34 RW DBC11IN 35 RW ACE_AMX_IN 75 DBC11OU 36 RW ACE_CMP_CR0 DBC11CR1 37 RW ACE_CMP_CR1 DCC12FN 38 RW DCC12IN 39 RW ACE_CMP_GI_EN 79 RW DCC12OU 3A RW ACE_ALT_CR0 7A RW DCC12CR1 3B RW ACE_ABF_CR0 7B RW DCC13FN 3C RW DCC13IN 3D RW ACE0_CR1 7D RW DCC13OU 3E RW ACE0_CR2 7E DCC13CR1 3F RW ACE0_CR3 7F 65 68 6B AF RW EF RDI0RI B0 RW F0 RW RDI0SYN B1 RW F1 72 RW RDI0IS B2 RW F2 73 RW RDI0LT0 B3 RW F3 RDI0LT1 B4 RW F4 RW RDI0RO0 B5 RW F5 76 RW RDI0RO1 B6 RW 77 RW RDIODSM B7 RW RDI1RI B8 RW RDI1SYN B9 RW RDI1IS BA RW RDI1LT0 BB RW RDI1LT1 BC RW RDI1RO0 BD RW IDAC_CR0 FD RW RW RDI1RO1 BE RW CPU_SCR1 FE # RW RDI1DSM BF RW CPU_SCR0 FF # 74 78 7C Document Number: 001-48111 Rev. *D EE AMUX_CLK 70 Blank fields are Reserved and should not be accessed. AE # Access is bit specific. F6 CPU_F F7 RL F8 F9 FLS_PR1 FA RW FB FC *Address has a dual purpose, see "Mapping Exceptions" on page 251 Page 24 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY8C28x43 Register Map Bank 0 Table: User Space Name PRT0DR Addr (0,Hex) 00 Access RW Name DBC20DR0 Addr (0,Hex) 40 Access # Name ASC10CR0 Addr (0,Hex) 80 Access RW PRT0IE 01 RW DBC20DR1 PRT0GS 02 RW DBC20DR2 41 W ASC10CR1 81 RW 42 RW ASC10CR2 82 RW PRT0DM2 03 RW DBC20CR0 43 # ASC10CR3 83 PRT1DR 04 RW DBC21DR0 44 # ASD11CR0 PRT1IE 05 RW DBC21DR1 45 W PRT1GS 06 RW DBC21DR2 46 PRT1DM2 07 RW DBC21CR0 PRT2DR 08 RW DCC22DR0 PRT2IE 09 RW DCC22DR1 PRT2GS 0A RW DCC22DR2 Name RDI2RI Addr (0,Hex) C0 Access RW RDI2SYN C1 RW RDI2IS C2 RW RW RDI2LT0 C3 RW 84 RW RDI2LT1 C4 RW ASD11CR1 85 RW RDI2RO0 C5 RW RW ASD11CR2 86 RW RDI2RO1 C6 RW 47 # ASD11CR3 87 RW RDI2DSM C7 RW 48 # ASC12CR0 88 RW 49 W ASC12CR1 89 RW C9 4A RW ASC12CR2 8A RW CA C8 PRT2DM2 0B RW DCC22CR0 4B # ASC12CR3 8B RW CB PRT3DR 0C RW DCC23DR0 4C # ASD13CR0 8C RW CC PRT3IE 0D RW DCC23DR1 4D W ASD13CR1 8D RW CD PRT3GS 0E RW DCC23DR2 4E RW ASD13CR2 8E RW CE PRT3DM2 0F RW DCC23CR0 4F # ASD13CR3 8F RW PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW PRT4GS 12 RW 52 ASD20CR2 92 RW PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 # 58 ASD22CR0 98 RW I2C0_DR D8 RW 19 59 ASD22CR1 99 RW I2C0_MSCR D9 # 1A 5A ASD22CR2 9A RW INT_CLR0 DA RW 18 CF D2 1B 5B ASD22CR3 9B RW INT_CLR1 DB RW 1C 5C ASC23CR0 9C RW INT_CLR2 DC RW 1D 5D ASC23CR1 9D RW INT_CLR3 DD RW 1E 5E ASC23CR2 9E RW INT_MSK3 DE RW 1F 5F ASC23CR3 9F RW INT_MSK2 DF RW DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW DBC00DR1 DBC00DR2 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W DBC01DR0 24 # CMP_CR0 64 # DEC2_DH A4 RC I2C1_SCR E4 # DBC01DR1 25 W ASY_CR 65 # DEC2_DL A5 RC I2C1_MSCR E5 # DBC01DR2 26 RW CMP_CR1 66 RW DEC3_DH A6 RC DEC_CR0* E6 RW DBC01CR0 27 # I2C1_DR 67 RW DEC3_DL A7 RC DEC_CR1* E7 RW DCC02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W DCC02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA R MUL0_DH EA R DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB R MUL0_DL EB R DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0 DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1 DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2 DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3 DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4 DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5 DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW DCC12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F6 CPU_F F7 DCC12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9 DCC12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FA DCC12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW FB DCC13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW FC DCC13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW DCC13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW DCC13CR0 3F # ACB03CR2 Blank fields are Reserved and should not be accessed. Document Number: 001-48111 Rev. *D 7F RW # Access is bit specific. RL F8 FD CPU_SCR1 RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see "Mapping Exceptions" on page 251 FE # FF # Page 25 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY8C28x43 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 Addr (1,Hex) 00 Access RW PRT0DM1 01 RW PRT0IC0 02 RW PRT0IC1 03 PRT1DM0 Name DBC20FN Addr (1,Hex) 40 Access RW Name Addr (1,Hex) 80 Access DBC20IN 41 RW SADC_TSCMPL 81 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RW DBC20CR1 43 RW 04 RW DBC21FN 44 PRT1DM1 05 RW DBC21IN PRT1IC0 06 RW PRT1IC1 07 PRT2DM0 Name RDI2RI Addr (1,Hex) C0 Access RW RDI2SYN C1 RW RDI2IS C2 RW 83 RDI2LT0 C3 RW RW 84 RDI2LT1 C4 RW 45 RW 85 RDI2RO0 C5 RW DBC21OU 46 RW 86 RDI2RO1 C6 RW RW DBC21CR1 47 RW 87 RDI2DSM C7 RW 08 RW DCC22FN 48 RW 88 PRT2DM1 09 RW DCC22IN 49 RW 89 C9 PRT2IC0 0A RW DCC22OU 4A RW 8A CA C8 PRT2IC1 0B RW DCC22CR1 4B RW 8B CB PRT3DM0 0C RW DCC23FN 4C RW 8C CC PRT3DM1 0D RW DCC23IN 4D RW 8D CD PRT3IC0 0E RW DCC23OU 4E RW 8E CE PRT3IC1 0F RW DCC23CR1 4F RW 8F PRT4DM0 10 RW 50 PRT4DM1 11 RW 51 DEC0_CR0 91 PRT4IC0 12 RW 52 DEC_CR3 92 PRT4IC1 13 RW 53 PRT5DM0 14 RW 54 PRT5DM1 15 RW 55 DEC1_CR0 95 PRT5IC0 16 RW 56 DEC_CR4 96 PRT5IC1 17 RW 57 18 58 19 59 DEC2_CR0 99 1A 5A DEC_CR5 9A 1B 5B 9B 1C 5C 9C 1D 5D OSC_GO_EN DD RW 1E 5E 9E OSC_CR4 DE RW 1F 5F 9F OSC_CR3 DF RW CF 90 DEC3_CR0 GDI_O_IN D0 RW RW GDI_E_IN D1 RW RW GDI_O_OU D2 RW 93 GDI_E_OU D3 RW 94 DEC0_CR D4 RW RW DEC1_CR D5 RW RW DEC2_CR D6 RW 97 DEC3_CR D7 RW 98 MUX_CR0 D8 RW RW MUX_CR1 D9 RW RW MUX_CR2 DA RW MUX_CR3 DB RW 9D DC RW DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW DBC01IN 25 RW CMP_GO_EN1 65 RW RTC_M A5 RW E5 DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW E6 DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW DCC02FN 28 RW ALT_CR1 68 RW SADC_CR0 A8 RW IMO_TR E8 RW DCC02IN 29 RW CLK_CR2 69 RW SADC_CR1 A9 RW ILO_TR E9 RW DCC02OU 2A RW AMUX_CFG1 6A RW SADC_CR2 AA RW BDG_TR EA RW DCC02CR1 2B RW I2C1_CFG 6B RW SADC_CR3 AB RW ECO_TR EB RW DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW MUX_CR4 EC RW DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW MUX_CR5 ED RW DCC03OU 2E RW TMP_DR2 6E RW I2C1_ADDR AE RW EE DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF DBC10FN 30 RW RDI0RI B0 RW F0 DBC10IN 31 RW SADC_TSCR0 71 RW RDI0SYN B1 RW F1 DBC10OU 32 RW SADC_TSCR1 72 RW RDI0IS B2 RW F2 DBC10CR1 33 RW 73 RDI0LT0 B3 RW F3 DBC11FN 34 RW 74 RDI0LT1 B4 RW F4 DBC11IN 35 RW 75 RDI0RO0 B5 RW F5 DBC11OU 36 RW 76 RDI0RO1 B6 RW DBC11CR1 37 RW 77 RDIODSM B7 RW DCC12FN 38 RW 78 RDI1RI B8 RW DCC12IN 39 RW 79 RDI1SYN B9 RW DCC12OU 3A RW 7A RDI1IS BA RW DCC12CR1 3B RW 7B RDI1LT0 BB RW FB DCC13FN 3C RW 7C RDI1LT1 BC RW FC DCC13IN 3D RW 7D RDI1RO0 BD RW DCC13OU 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE # DCC13CR1 3F RW 7F RDI1DSM BF RW CPU_SCR0 FF # 70 Blank fields are Reserved and should not be accessed. Document Number: 001-48111 Rev. *D # Access is bit specific. E7 F6 CPU_F F7 RL F8 F9 FLS_PR1 FA RW FD *Address has a dual purpose, see "Mapping Exceptions" on page 251 Page 26 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY8C28x45 Register Map Bank 0 Table: User Space Name PRT0DR Addr (0,Hex) 00 Access RW Name DBC20DR0 Addr (0,Hex) 40 Access # Name ASC10CR0 Addr (0,Hex) 80 Access RW PRT0IE 01 RW DBC20DR1 PRT0GS 02 RW DBC20DR2 41 W ASC10CR1 81 RW 42 RW ASC10CR2 82 RW PRT0DM2 03 RW DBC20CR0 43 # ASC10CR3 83 PRT1DR 04 RW DBC21DR0 44 # ASD11CR0 PRT1IE 05 RW DBC21DR1 45 W PRT1GS 06 RW DBC21DR2 46 PRT1DM2 07 RW DBC21CR0 PRT2DR 08 RW DCC22DR0 PRT2IE 09 RW DCC22DR1 PRT2GS 0A RW DCC22DR2 Name RDI2RI Addr (0,Hex) C0 Access RW RDI2SYN C1 RW RDI2IS C2 RW RW RDI2LT0 C3 RW 84 RW RDI2LT1 C4 RW ASD11CR1 85 RW RDI2RO0 C5 RW RW ASD11CR2 86 RW RDI2RO1 C6 RW 47 # ASD11CR3 87 RW RDI2DSM C7 RW 48 # ASC12CR0 88 RW 49 W ASC12CR1 89 RW C9 4A RW ASC12CR2 8A RW CA C8 PRT2DM2 0B RW DCC22CR0 4B # ASC12CR3 8B RW CB PRT3DR 0C RW DCC23DR0 4C # ASD13CR0 8C RW CC PRT3IE 0D RW DCC23DR1 4D W ASD13CR1 8D RW CD PRT3GS 0E RW DCC23DR2 4E RW ASD13CR2 8E RW CE PRT3DM2 0F RW DCC23CR0 4F # ASD13CR3 8F RW PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW PRT4GS 12 RW 52 ASD20CR2 92 RW PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 # 58 ASD22CR0 98 RW I2C0_DR D8 RW 19 59 ASD22CR1 99 RW I2C0_MSCR D9 # 1A 5A ASD22CR2 9A RW INT_CLR0 DA RW 18 CF D2 1B 5B ASD22CR3 9B RW INT_CLR1 DB RW 1C 5C ASC23CR0 9C RW INT_CLR2 DC RW 1D 5D ASC23CR1 9D RW INT_CLR3 DD RW 1E 5E ASC23CR2 9E RW INT_MSK3 DE RW 1F 5F ASC23CR3 9F RW INT_MSK2 DF RW DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW DBC00DR1 DBC00DR2 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W DBC01DR0 24 # CMP_CR0 64 # DEC2_DH A4 RC I2C1_SCR E4 # DBC01DR1 25 W ASY_CR 65 # DEC2_DL A5 RC I2C1_MSCR E5 # DBC01DR2 26 RW CMP_CR1 66 RW DEC3_DH A6 RC DEC_CR0* E6 RW DBC01CR0 27 # I2C1_DR 67 RW DEC3_DL A7 RC DEC_CR1* E7 RW DCC02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W DCC02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA R MUL0_DH EA R DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB R MUL0_DL EB R DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0 DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1 DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2 DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3 DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4 DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5 DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW DCC12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F6 CPU_F F7 RL F8 DCC12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9 DCC12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FA DCC12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW DCC13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW DAC1_D FC RW DCC13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW DAC0_D FD RW DCC13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE # FF # DCC13CR0 3F # ACB03CR2 Blank fields are Reserved and should not be accessed. Document Number: 001-48111 Rev. *D 7F RW # Access is bit specific. FB RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see "Mapping Exceptions" on page 251 Page 27 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY8C28x45 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 Addr (1,Hex) 00 Access RW PRT0DM1 01 RW PRT0IC0 02 RW PRT0IC1 03 PRT1DM0 Name DBC20FN Addr (1,Hex) 40 Access RW Name Addr (1,Hex) 80 Addr (1,Hex) C0 Access RW DBC20IN 41 RW SADC_TSCMPL 81 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RDI2SYN C1 RW RDI2IS C2 RW DBC20CR1 43 RW ACE_AMD_CR1 83 RW RW RDI2LT0 C3 04 RW DBC21FN 44 RW RW 84 RW RDI2LT1 C4 PRT1DM1 05 RW DBC21IN 45 RW RW ACE_PWM_CR 85 RW RDI2RO0 C5 PRT1IC0 06 RW DBC21OU 46 RW RW ACE_ADC0_CR 86 RW RDI2RO1 C6 PRT1IC1 07 RW DBC21CR1 RW 47 RW ACE_ADC1_CR 87 RW RDI2DSM C7 PRT2DM0 08 RW DCC22FN RW 48 RW 88 RW PRT2DM1 09 RW PRT2IC0 0A RW DCC22IN 49 RW ACE_CLK_CR0 89 RW C9 DCC22OU 4A RW ACE_CLK_CR1 8A RW CA ACE_CLK_CR3 PRT2IC1 0B RW DCC22CR1 4B RW PRT3DM0 0C RW DCC23FN 4C RW PRT3DM1 0D RW DCC23IN 4D RW PRT3IC0 0E RW DCC23OU 4E RW PRT3IC1 0F RW DCC23CR1 4F RW PRT4DM0 10 RW 50 PRT4DM1 11 RW 51 DEC0_CR0 91 PRT4IC0 12 RW 52 DEC_CR3 92 PRT4IC1 13 RW 53 PRT5DM0 14 RW 54 PRT5DM1 15 RW 55 DEC1_CR0 95 PRT5IC0 16 RW 56 DEC_CR4 96 PRT5IC1 17 RW 57 18 58 19 59 DEC2_CR0 99 1A 5A DEC_CR5 9A 1B 5B 1C 5C 1D 5D 1E 5E 9E 1F 5F 9F Access RW Name RDI2RI C8 8B RW CB 8C RW CC ACE01CR1 8D RW CD ACE01CR2 8E RW CE ASE11CR0 8F RW 90 DEC3_CR0 CF GDI_O_IN D0 RW RW GDI_E_IN D1 RW RW GDI_O_OU D2 RW 93 GDI_E_OU D3 RW 94 DEC0_CR D4 RW RW DEC1_CR D5 RW RW DEC2_CR D6 RW 97 DEC3_CR D7 RW 98 MUX_CR0 D8 RW RW MUX_CR1 D9 RW RW MUX_CR2 DA RW 9B MUX_CR3 DB RW 9C IDAC_CR1 DC RW OSC_GO_EN DD RW OSC_CR4 DE RW OSC_CR3 DF RW 9D RW DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW DBC01IN 25 RW CMP_GO_EN1 65 RW RTC_M A5 RW ADC0_TR E5 RW DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW ADC1_TR E6 RW DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW IDAC_CR2 E7 RW DCC02FN 28 RW ALT_CR1 68 RW SADC_CR0 A8 RW IMO_TR E8 RW DCC02IN 29 RW CLK_CR2 69 RW SADC_CR1 A9 RW ILO_TR E9 RW DCC02OU 2A RW AMUX_CFG1 6A RW SADC_CR2 AA RW BDG_TR EA RW DCC02CR1 2B RW I2C1_CFG 6B RW SADC_CR3 AB RW ECO_TR EB RW DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW MUX_CR4 EC RW DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW MUX_CR5 ED RW DCC03OU 2E RW TMP_DR2 6E RW I2C1_ADDR AE RW EE DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF DBC10FN 30 RW RDI0RI B0 RW F0 DBC10IN 31 RW SADC_TSCR0 71 RW RDI0SYN B1 RW F1 DBC10OU 32 RW SADC_TSCR1 72 RW RDI0IS B2 RW F2 DBC10CR1 33 RW ACE_AMD_CR0 73 RW RDI0LT0 B3 RW F3 DBC11FN 34 RW RDI0LT1 B4 RW F4 DBC11IN 35 RW ACE_AMX_IN 75 RW RDI0RO0 B5 RW F5 DBC11OU 36 RW ACE_CMP_CR0 76 RW RDI0RO1 B6 RW DBC11CR1 37 RW ACE_CMP_CR1 77 RW RDIODSM B7 RW DCC12FN 38 RW RDI1RI B8 RW DCC12IN 39 RW ACE_CMP_GI_EN 79 RW RDI1SYN B9 RW DCC12OU 3A RW ACE_ALT_CR0 7A RW RDI1IS BA RW DCC12CR1 3B RW ACE_ABF_CR0 7B RW RDI1LT0 BB RW DCC13FN 3C RW RDI1LT1 BC RW DCC13IN 3D RW ACE0_CR1 7D RW RDI1RO0 BD RW IDAC_CR0 FD RW DCC13OU 3E RW ACE0_CR2 7E RW RDI1RO1 BE RW CPU_SCR1 FE # DCC13CR1 3F RW ACE0_CR3 7F RW RDI1DSM BF RW CPU_SCR0 FF # 70 74 78 7C Blank fields are Reserved and should not be accessed. Document Number: 001-48111 Rev. *D # Access is bit specific. F6 CPU_F F7 RL F8 F9 FLS_PR1 FA RW FB FC *Address has a dual purpose, see "Mapping Exceptions" on page 251 Page 28 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY8C28x52 Register Map Bank 0 Table: User Space Name PRT0DR Addr (0,Hex) 00 Access RW PRT0IE 01 RW PRT0GS 02 RW PRT0DM2 03 PRT1DR Name Addr (0,Hex) 40 Access Name ASC10CR0 Addr (0,Hex) 80 Access RW Name Addr (0,Hex) C0 41 ASC10CR1 81 RW C1 42 ASC10CR2 82 RW C2 RW 43 ASC10CR3 83 RW C3 04 RW 44 ASD11CR0 84 RW C4 PRT1IE 05 RW 45 ASD11CR1 85 RW C5 PRT1GS 06 RW 46 ASD11CR2 86 RW C6 PRT1DM2 07 RW 47 ASD11CR3 87 RW C7 PRT2DR 08 RW 48 ASC12CR0 88 RW C8 PRT2IE 09 RW 49 ASC12CR1 89 RW C9 PRT2GS 0A RW 4A ASC12CR2 8A RW CA Access PRT2DM2 0B RW 4B ASC12CR3 8B RW CB PRT3DR 0C RW 4C ASD13CR0 8C RW CC PRT3IE 0D RW 4D ASD13CR1 8D RW CD PRT3GS 0E RW 4E ASD13CR2 8E RW CE PRT3DM2 0F RW 4F ASD13CR3 8F RW PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW PRT4GS 12 RW 52 ASD20CR2 92 RW PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 # 58 ASD22CR0 98 RW I2C0_DR D8 RW 19 59 ASD22CR1 99 RW I2C0_MSCR D9 # 1A 5A ASD22CR2 9A RW INT_CLR0 DA RW 18 CF D2 1B 5B ASD22CR3 9B RW INT_CLR1 DB RW 1C 5C ASC23CR0 9C RW INT_CLR2 DC RW 1D 5D ASC23CR1 9D RW INT_CLR3 DD RW 1E 5E ASC23CR2 9E RW INT_MSK3 DE RW 1F 5F ASC23CR3 9F RW INT_MSK2 DF RW DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW DBC00DR1 DBC00DR2 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W DBC01DR0 24 # CMP_CR0 64 # DEC2_DH A4 RC DBC01DR1 25 W ASY_CR 65 # DEC2_DL A5 RC DBC01DR2 26 RW CMP_CR1 66 RW DEC3_DH A6 RC DEC_CR0* E6 RW DBC01CR0 27 # 67 DEC3_DL A7 RC DEC_CR1* E7 RW DCC02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W DCC02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W DCC02DR2 2A RW 6A MUL1_DH AA R MUL0_DH EA R DCC02CR0 2B # 6B MUL1_DL AB R MUL0_DL EB R DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0 DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1 DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2 DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3 DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4 DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5 DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW DCC12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW E4 E5 F6 CPU_F F7 RL F8 DCC12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9 DCC12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FA DCC12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW DCC13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW DAC1_D FC RW DCC13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW DAC0_D FD RW DCC13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE # FF # DCC13CR0 3F # ACB03CR2 Blank fields are Reserved and should not be accessed. Document Number: 001-48111 Rev. *D 7F RW # Access is bit specific. FB RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see "Mapping Exceptions" on page 251 Page 29 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY8C28x52 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 Addr (1,Hex) 00 Access RW Name Addr (1,Hex) 40 Access Name PRT0DM1 01 RW 41 81 PRT0IC0 02 RW 42 82 PRT0IC1 03 RW 43 PRT1DM0 04 RW 44 PRT1DM1 05 RW 45 ACE_PWM_CR 85 RW C5 PRT1IC0 06 RW 46 ACE_ADC0_CR 86 RW C6 PRT1IC1 07 RW 47 ACE_ADC1_CR 87 RW C7 PRT2DM0 08 RW 48 PRT2DM1 09 RW 49 ACE_CLK_CR0 89 RW C9 PRT2IC0 0A RW 4A ACE_CLK_CR1 8A RW CA ACE_CLK_CR3 8B RW ACE_AMD_CR1 Addr (1,Hex) 80 83 Access Name Addr (1,Hex) C0 C1 C2 RW C3 84 C4 88 C8 PRT2IC1 0B RW 4B PRT3DM0 0C RW 4C CB PRT3DM1 0D RW 4D ACE01CR1 8D RW CD PRT3IC0 0E RW 4E ACE01CR2 8E RW CE PRT3IC1 0F RW 4F ASE11CR0 8F RW PRT4DM0 10 RW 50 PRT4DM1 11 RW 51 DEC0_CR0 91 PRT4IC0 12 RW 52 DEC_CR3 92 PRT4IC1 13 RW 53 PRT5DM0 14 RW 54 PRT5DM1 15 RW 55 DEC1_CR0 95 PRT5IC0 16 RW 56 DEC_CR4 96 PRT5IC1 17 RW 57 18 58 19 59 DEC2_CR0 99 1A 5A DEC_CR5 9A 1B 5B 1C 5C 1D 5D 1E 5E 9E 1F 5F 9F 8C CC 90 DEC3_CR0 Access CF GDI_O_IN D0 RW RW GDI_E_IN D1 RW RW GDI_O_OU D2 RW 93 GDI_E_OU D3 RW 94 DEC0_CR D4 RW RW DEC1_CR D5 RW RW DEC2_CR D6 RW 97 DEC3_CR D7 RW 98 MUX_CR0 D8 RW RW MUX_CR1 D9 RW RW MUX_CR2 DA RW 9B MUX_CR3 DB RW 9C IDAC_CR1 DC RW OSC_GO_EN DD RW OSC_CR4 DE RW OSC_CR3 DF RW 9D RW DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW DBC01IN 25 RW CMP_GO_EN1 65 RW RTC_M A5 RW ADC0_TR E5 RW DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW ADC1_TR E6 RW DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW IDAC_CR2 E7 RW DCC02FN 28 RW ALT_CR1 68 RW A8 IMO_TR E8 RW DCC02IN 29 RW CLK_CR2 69 RW A9 ILO_TR E9 RW DCC02OU 2A RW AMUX_CFG1 6A RW AA BDG_TR EA RW DCC02CR1 2B RW AB ECO_TR EB RW DCC03FN 2C RW TMP_DR0 6C RW AC MUX_CR4 EC RW DCC03IN 2D RW TMP_DR1 6D RW MUX_CR5 ED RW DCC03OU 2E RW TMP_DR2 6E RW DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF DBC10FN 30 RW 70 RDI0RI B0 RW F0 DBC10IN 31 RW 71 RDI0SYN B1 RW F1 DBC10OU 32 RW 72 RDI0IS B2 RW F2 DBC10CR1 33 RW RDI0LT0 B3 RW F3 DBC11FN 34 RW RDI0LT1 B4 RW F4 DBC11IN 35 RW ACE_AMX_IN 75 RW RDI0RO0 B5 RW F5 DBC11OU 36 RW ACE_CMP_CR0 76 RW RDI0RO1 B6 RW DBC11CR1 37 RW ACE_CMP_CR1 77 RW RDIODSM B7 RW DCC12FN 38 RW RDI1RI B8 RW DCC12IN 39 RW ACE_CMP_GI_EN 79 RW RDI1SYN B9 RW DCC12OU 3A RW ACE_ALT_CR0 7A RW RDI1IS BA RW DCC12CR1 3B RW ACE_ABF_CR0 7B RW RDI1LT0 BB RW DCC13FN 3C RW RDI1LT1 BC RW DCC13IN 3D RW ACE0_CR1 7D RW RDI1RO0 BD RW IDAC_CR0 FD RW DCC13OU 3E RW ACE0_CR2 7E RW RDI1RO1 BE RW CPU_SCR1 FE # DCC13CR1 3F RW ACE0_CR3 7F RW RDI1DSM BF RW CPU_SCR0 FF # 6B ACE_AMD_CR0 73 RW 74 78 7C Blank fields are Reserved and should not be accessed. Document Number: 001-48111 Rev. *D # Access is bit specific. I2C0_ADDR AD RW AE EE F6 CPU_F F7 RL F8 F9 FLS_PR1 FA RW FB FC *Address has a dual purpose, see "Mapping Exceptions" on page 251 Page 30 of 65 [+] Feedback PRELIMINARY CY8C28xxx Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C28xxx PSoC devices. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. Specifications are valid for -40oC TA 85oC and TJ 100oC, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40oC TA 70oC and TJ 82oC. Figure 7. Voltage versus CPU Frequency 5.25 lid ing Va rat on pe i O R eg 4.75 Vdd Voltage 3.00 93 kHz 12 MHz 24 MHz CPU Frequency The following table lists the units of measure that are used in this section. Table 8. Units of Measure Symbol C dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms o Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Document Number: 001-48111 Rev. *D Symbol W mA ms mV nA ns nV pA pF pp ppm ps ksps V Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond kilo-samples per second sigma: one standard deviation volts Page 31 of 65 [+] Feedback PRELIMINARY CY8C28xxx Absolute Maximum Ratings Table 9. Absolute Maximum Ratings Symbol Description TSTG Storage Temperature Min -55 Typ 25 Max +100 TA Vdd VIO Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage - - - VIOZ DC Voltage Applied to Tri-state IMIO IMAIO Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch-up Current -40 -0.5 Vss0.5 Vss 0.5 -25 -50 - - +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 +50 mA mA 2000 - - - - 200 V mA Min -40 -40 Typ - - Max +85 +100 Units oC oC ESD LU - Units o C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25oC 25oC. Extended duration storage temperatures above 65oC degrade reliability. o C V V V Human Body Model ESD. Operating Temperature Table 10. Operating Temperature Symbol Description TA Ambient Temperature TJ Junction Temperature Document Number: 001-48111 Rev. *D Notes The temperature rise from ambient to junction is package specific. See Thermal Impedances on page 60. The user must limit the power consumption to comply with this requirement. Page 32 of 65 [+] Feedback PRELIMINARY CY8C28xxx DC Electrical Characteristics DC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 11. DC Chip Level Specifications Symbol Description Vdd Supply Voltage IDD Supply Current Min 3.00 - Typ - 8 Max 5.25 14 Units V mA IDD3 Supply Current - 5 9 mA ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.[13] - 3 10 A ISBH Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.[13] - 4 25 A ISBXTL Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal.[13] - 4 11 A ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature.[13] Reference Voltage (Bandgap) - 5 26 A 1.280 1.00 1.300 - 1.320 1.058 V mA VREF IXRES Notes Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC TA 55 oC. Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA 85 oC. Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, -40 oC TA 55 oC. Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, 55 oC < TA 85 oC. Trimmed for appropriate Vdd. Note 13. Standby (sleep) current includes all functions (POR, LVD, WDT, Sleep Timer) needed for reliable system operation. This should be compared with devices that have similar functions enabled. Document Number: 001-48111 Rev. *D Page 33 of 65 [+] Feedback PRELIMINARY CY8C28xxx DC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 12. DC GPIO Specifications Symbol Description Pull Up Resistor RPU Pull Down Resistor RPD VOH High Output Level Min 4 4 Vdd 1.0 Typ 5.6 5.6 - Max 8 8 - Units k k V VOL Low Output Level - - 0.75 V IOH High Level Source Current 10 - - mA IOL Low Level Sink Current 25 - - mA VIL VIH VH IIL CIN Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input - 2.1 - - - - - 60 1 3.5 0.8 - - 10 V V mV nA pF COUT Capacitive Load on Pins as Output - 3.5 10 pF Notes IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). VOH = Vdd-1.0V, see the limitations of the total current in the note for VOH. VOL = 0.75V, see the limitations of the total current in the note for VOL. Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The Operational Amplifiers covered by these specifications are components of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Table 13. 5V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High TCVOSOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) IEBOA Input Capacitance (Port 0 Analog Pins) CINOA Min Typ Max Units - - - - - - 1.6 1.3 1.2 7.0 200 4.5 10 10 10 35.0 - 9.5 mV mV mV V/oC pA pF Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias) 0.0 0.5 - - Vdd Vdd 0.5 V VCMOA Document Number: 001-48111 Rev. *D Notes Gross tested to 1 A. Package and pin dependent. Temp = 25oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Page 34 of 65 [+] Feedback PRELIMINARY CY8C28xxx Table 13. 5V DC Operational Amplifier Specifications (continued) Symbol Description CMRROA Common Mode Rejection Ratio Power = Low Power = Medium Power = High GOLOA Open Loop Gain Power = Low Power = Medium Power = High VOHIGHOA High Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High Min Typ - Max - Units dB - - dB Vdd 0.2 Vdd 0.2 Vdd 0.5 - - - - - - V V V - - - - - - 0.2 0.2 0.5 V V V - - - - - - 60 150 300 600 1200 2400 4600 - 200 400 800 1600 3200 6400 - A A A A A A dB Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only TCVOSOA Average Input Offset Voltage Drift IEBOA Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) CINOA Min Typ Max Units - - 1.65 1.32 10 8 mV mV - - - 7.0 200 4.5 Common Mode Voltage Range 0.2 - 60 60 60 60 60 80 VOLOWOA Low Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio Notes Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. Vss VIN (Vdd - 2.25) or (Vdd 1.25V) VIN Vdd. Table 14. 3.3V DC Operational Amplifier Specifications Symbol VOSOA VCMOA CMRROA Common Mode Rejection Ratio Power = Low Power = Medium Power = High GOLOA Open Loop Gain Power = Low Power = Medium Power = High Document Number: 001-48111 Rev. *D - 50 50 50 - 60 60 80 Notes V/oC pA Gross tested to 1 A. pF Package and pin dependent. Temp = 25oC. Vdd - 0.2 V The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. - dB Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 50 dB. - dB Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. 35.0 - 9.5 Page 35 of 65 [+] Feedback PRELIMINARY CY8C28xxx Table 14. 3.3V DC Operational Amplifier Specifications (continued) Symbol Description VOHIGHOA High Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High is 5V only VOLOWOA Low Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio Min Typ Max Units Vdd 0.2 Vdd 0.2 Vdd 0.2 - - - - - - V V V - - - - - - 0.2 0.2 0.2 V V V - - - - - - 150 300 600 1200 2400 4600 200 400 800 1600 3200 6400 A A A A A A 50 80 - dB Notes Vss VIN (Vdd - 2.25) or (Vdd 1.25V) VIN Vdd. DC Type-E Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The Operational Amplifiers covered by these specifications are components of the Limited Type E Analog PSoC blocks. Table 15. 5V DC Type-E Operational Amplifier Specifications Symbol Description VOSOA Input Offset Voltage (absolute value) Min - - Typ 2.5 2.5 Max 15 20 Units mV mV - - - 10 200 4.5 - - 9.5 0.0 - - 10 Vdd - 1 30 V/oC pA Gross tested to 1 A. pF Package and pin dependent. Temp = 25oC. V A Min - - Typ 2.5 2.5 Max 15 20 TCVOSOA Average Input Offset Voltage Drift IEBOA[14] Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) CINOA - - - 10 200 4.5 - - 9.5 VCMOA ISOA 0 - - 10 Vdd - 1 30 TCVOSOA Average Input Offset Voltage Drift IEBOA[14] Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) CINOA VCMOA ISOA Common Mode Voltage Range Amplifier Supply Current Notes For 0.2V < Vin < Vdd - 1.2V. For Vin = 0 to 0.2V and Vin > Vdd 1.2V. Table 16. 3.3V DC Type-E Operational Amplifier Specifications Symbol Description Input Offset Voltage (absolute value) VOSOA Common Mode Voltage Range Amplifier Supply Current Units Notes mV For 0.2V < Vin < Vdd - 1.2V. mV For Vin = 0 to 0.2V and Vin > Vdd 1.2V. V/oC pA Gross tested to 1 A. pF Package and pin dependent. Temp = 25oC. V A Note 14. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA. Document Number: 001-48111 Rev. *D Page 36 of 65 [+] Feedback PRELIMINARY CY8C28xxx DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 17. DC Low Power Comparator Specifications Symbol VREFLPC VOSLPC ISLPC Description Low power comparator (LPC) reference voltage range LPC voltage offset LPC supply current Min 0.2 Typ - Max Vdd - 1 Units V - - 2.5 10 30 40 mV A Notes DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 18. 5V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Min - - 0.5 Typ 3 +6 - Max 12 TBD Vdd - 1.0 Units mV V/C V - - 1 1 - - 0.5 x Vdd + 1.3 0.5 x Vdd + 1.3 - - V - - V Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low - - V Power = High - - 0.5 x Vdd - 1.3 0.5 x Vdd - 1.3 Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio - - 60 1.1 2.6 64 5.1 8.8 - mA mA dB Power = High VOLOWOB ISOB PSRROB Document Number: 001-48111 Rev. *D Notes V Page 37 of 65 [+] Feedback PRELIMINARY CY8C28xxx Table 19. 3.3V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Min - - 0.5 Typ 3 +6 - Max 12 TBD Vdd - 1.0 Units mV V/C V - - 1 1 - - 0.5 x Vdd + 1.0 0.5 x Vdd + 1.0 - - V - - V Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low - - V Power = High - - 0.5 x Vdd - 1.0 0.5 x Vdd - 1.0 Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio - 60 0.8 2.0 64 2.0 4.3 - mA mA dB Power = High VOLOWOB ISOB PSRROB Document Number: 001-48111 Rev. *D Notes V Page 38 of 65 [+] Feedback PRELIMINARY CY8C28xxx DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 20. DC Switch Mode Pump (SMP) Specifications Symbol Description Min Typ Max Units Notes VPUMP 5V 5V Output Voltage 4.75 5.0 5.25 V Configuration of footnote.[15] Average, neglecting ripple. SMP trip voltage is set to 5.0V. VPUMP 3V 3V Output Voltage 3.00 3.25 3.60 V Configuration of footnote.[15] Average, neglecting ripple. SMP trip voltage is set to 3.25V. IPUMP Available Output Current VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.8V, VPUMP = 5.0V 8 5 - - - - mA mA VBAT5V Input Voltage Range from Battery 1.8 - 5.0 V Configuration of footnote.[15] SMP trip voltage is set to 5.0V. VBAT3V Input Voltage Range from Battery 1.5 - 3.3 V Configuration of footnote.[15] SMP trip voltage is set to 3.25V. VBATSTART Minimum Input Voltage from Battery to Start Pump 1.1 - - V Configuration of footnote.[15] VPUMP_Line Line Regulation (over VBAT range) - 5 - %VO Configuration of footnote.[15] VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 30 on page 45. VPUMP_Load Load Regulation - 5 - %VO Configuration of footnote.[15] VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 30 on page 45. VPUMP_Ripple Output Voltage Ripple (depends on capacitor/load) - 100 - mVpp Configuration of footnote.[15] Load is 5mA. E3 Efficiency 35 50 - % Configuration of footnote.[15] Load is 5 mA. SMP trip voltage is set to 3.25V. FPUMP Switching Frequency - 1.3 - MHz DCPUMP Switching Duty Cycle - 50 - % Configuration of footnote.[15] SMP trip voltage is set to 3.25V. SMP trip voltage is set to 5.0V. To get better performance, refer to Cypress application note, AN2349. Note 15. L1 = 2 uH inductor, C1 = 10 uF capacitor, D1 = Schottky diode. See Figure 8. Document Number: 001-48111 Rev. *D Page 39 of 65 [+] Feedback PRELIMINARY CY8C28xxx Figure 8. Basic Switch Mode Pump Circuit D1 Vdd L1 V BAT + V PUMP C1 SMP Battery PSoC TM Vss DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 21. 5V DC Analog Reference Specifications for High Power Symbol VBG5 - - - - - - - - - - - Description Bandgap Voltage Reference 5V AGND = Vdd/2[16] AGND = 2 x BandGap[16] AGND = P2[4] (P2[4] = Vdd/2)[16] AGND = BandGap[16] AGND = 1.6 x BandGap[16] AGND Block to Block Variation (AGND = Vdd/2)[16] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) - - - - - - - RefHi = 2 x BandGap RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Min 1.28 Vdd/2 - 0.02 2.52 P2[4] - 0.013 1.27 2.03 -0.034 Vdd/2 + 1.21 3.75 P2[6] + 2.478 P2[4] + 1.218 P2[4] + P2[6] 0.058 2.50 4.02 Vdd/2 - 1.369 1.20 2.489 - P2[6] P2[4] - 1.368 P2[4] - P2[6] 0.042 Typ 1.30 Vdd/2 2.60 P2[4] 1.3 2.08 0.000 Vdd/2 + 1.3 3.9 P2[6] + 2.6 P2[4] + 1.3 P2[4] + P2[6] 2.60 4.16 Vdd/2 - 1.30 1.30 2.6 - P2[6] P2[4] - 1.30 P2[4] - P2[6] Max 1.32 Vdd/2 + 0.02 2.72 P2[4] + 0.013 1.34 2.13 0.034 Vdd/2 + 1.382 4.05 P2[6] + 2.722 P2[4] + 1.382 P2[4] + P2[6] + 0.058 2.70 4.29 Vdd/2 - 1.231 1.40 2.711 - P2[6] P2[4] - 1.232 P2[4] - P2[6] + 0.042 Units V V V V V V V V V V V V V V V V V V V Note 16. AGND tolerance includes the offsets of the local buffer in the PSoC block. Document Number: 001-48111 Rev. *D Page 40 of 65 [+] Feedback PRELIMINARY CY8C28xxx Table 22. 5V DC Analog Reference Specifications for Medium Power Symbol VBG5 - - - - - - - - - - - Description Bandgap Voltage Reference 5V AGND = Vdd/2[16] AGND = 2 x BandGap[16] AGND = P2[4] (P2[4] = Vdd/2)[16] AGND = BandGap[16] AGND = 1.6 x BandGap[16] AGND Block to Block Variation (AGND = Vdd/2)[16] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) - - - - - - - RefHi = 2 x BandGap RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Min 1.28 Vdd/2 - 0.02 2.52 P2[4] - 0.013 1.27 2.03 -0.034 Vdd/2 + 1.21 3.75 P2[6] + 2.478 P2[4] + 1.218 P2[4] + P2[6] 0.058 2.50 4.02 Vdd/2 - 1.369 1.20 2.489 - P2[6] P2[4] - 1.368 P2[4] - P2[6] 0.042 Typ 1.30 Vdd/2 2.60 P2[4] 1.3 2.08 0.000 Vdd/2 + 1.3 3.9 P2[6] + 2.6 P2[4] + 1.3 P2[4] + P2[6] 2.60 4.16 Vdd/2 - 1.30 1.30 2.6 - P2[6] P2[4] - 1.30 P2[4] - P2[6] Max 1.32 Vdd/2 + 0.02 2.72 P2[4] + 0.013 1.34 2.13 0.034 Vdd/2 + 1.382 4.05 P2[6] + 2.722 P2[4] + 1.382 P2[4] + P2[6] + 0.058 2.70 4.29 Vdd/2 - 1.231 1.40 2.711 - P2[6] P2[4] - 1.232 P2[4] - P2[6] + 0.042 Units V V V V V V V V V V V V V V V V V V V Table 23. 5V DC Analog Reference Specifications for Low Power Symbol VBG5 - - - - - - - - - - - Description Bandgap Voltage Reference 5V AGND = Vdd/2[16] AGND = 2 x BandGap[16] AGND = P2[4] (P2[4] = Vdd/2)[16] AGND = BandGap[16] AGND = 1.6 x BandGap[16] AGND Block to Block Variation (AGND = Vdd/2)[16] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) - - - - - - - RefHi = 2 x BandGap RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Document Number: 001-48111 Rev. *D Min 1.28 Vdd/2 - 0.02 2.52 P2[4] - 0.013 1.27 2.03 -0.034 Vdd/2 + 1.21 3.75 P2[6] + 2.478 P2[4] + 1.218 P2[4] + P2[6] 0.058 2.50 4.02 Vdd/2 - 1.369 1.20 2.489 - P2[6] P2[4] - 1.368 P2[4] - P2[6] 0.042 Typ 1.30 Vdd/2 2.60 P2[4] 1.3 2.08 0.000 Vdd/2 + 1.3 3.9 P2[6] + 2.6 P2[4] + 1.3 P2[4] + P2[6] 2.60 4.16 Vdd/2 - 1.30 1.30 2.6 - P2[6] P2[4] - 1.30 P2[4] - P2[6] Max 1.32 Vdd/2 + 0.02 2.72 P2[4] + 0.013 1.34 2.13 0.034 Vdd/2 + 1.382 4.05 P2[6] + 2.722 P2[4] + 1.382 P2[4] + P2[6] + 0.058 2.70 4.29 Vdd/2 - 1.231 1.40 2.711 - P2[6] P2[4] - 1.232 P2[4] - P2[6] + 0.042 Units V V V V V V V V V V V V V V V V V V V Page 41 of 65 [+] Feedback PRELIMINARY CY8C28xxx Table 24. 3.3V DC Analog Reference Specifications for High Power Symbol VBG33 - - - - - - - - - - - - - - - - - - Description Bandgap Voltage Reference 3.3V AGND = Vdd/2[16] AGND = 2 x BandGap[16] AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap[16] AGND = 1.6 x BandGap[16] AGND Block to Block Variation (AGND = Vdd/2)[16] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Min 1.28 Vdd/2 - 0.02 Not Allowed P2[4] - 0.009 1.27 2.03 -0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] 0.042 RefHi = 2 x BandGap 2.50 RefHi = 3.2 x BandGap Not Allowed RefLo = Vdd/2 - BandGap Not Allowed RefLo = BandGap Not Allowed RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed RefLo = P2[4] - BandGap (P2[4] = Vdd/2) Not Allowed RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] 0.036 1.30 Vdd/2 Typ Max 1.32 Vdd/2 + 0.02 Units V V P2[4] 1.30 2.08 0.000 P2[4] + 0.009 1.34 2.13 0.034 V V V mV P2[4] + P2[6] P2[4] + P2[6] + 0.042 2.70 V P2[4] - P2[6] + 0.036 V 1.30 Vdd/2 Max 1.32 Vdd/2 + 0.02 Units V V P2[4] 1.30 2.08 0.000 P2[4] + 0.009 1.34 2.13 0.034 V V V mV P2[4] + P2[6] P2[4] + P2[6] + 0.042 2.70 V P2[4] - P2[6] + 0.036 V 2.60 P2[4] - P2[6] V Table 25. 3.3V DC Analog Reference Specifications for Medium Power Symbol VBG33 - - - - - - - - - - - - - - - - - - Description Bandgap Voltage Reference 3.3V AGND = Vdd/2[16] AGND = 2 x BandGap[16] AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap[16] AGND = 1.6 x BandGap[16] AGND Block to Block Variation (AGND = Vdd/2)[16] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Min 1.28 Vdd/2 - 0.02 Not Allowed P2[4] - 0.009 1.27 2.03 -0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] 0.042 RefHi = 2 x BandGap 2.50 RefHi = 3.2 x BandGap Not Allowed RefLo = Vdd/2 - BandGap Not Allowed RefLo = BandGap Not Allowed RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed RefLo = P2[4] - BandGap (P2[4] = Vdd/2) Not Allowed RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] 0.036 Document Number: 001-48111 Rev. *D Typ 2.60 P2[4] - P2[6] V Page 42 of 65 [+] Feedback PRELIMINARY CY8C28xxx Table 26. 3.3V DC Analog Reference Specifications for Low Power Symbol VBG33 - - - - - - - - - - - - - - - - - - Description Bandgap Voltage Reference 3.3V AGND = Vdd/2[16] AGND = 2 x BandGap[16] AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap[16] AGND = 1.6 x BandGap[16] AGND Block to Block Variation (AGND = Vdd/2)[16] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Min 1.28 Vdd/2 - 0.02 Not Allowed P2[4] - 0.009 1.27 2.03 -0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] 0.042 RefHi = 2 x BandGap 2.50 RefHi = 3.2 x BandGap Not Allowed RefLo = Vdd/2 - BandGap Not Allowed RefLo = BandGap Not Allowed RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed RefLo = P2[4] - BandGap (P2[4] = Vdd/2) Not Allowed RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] 0.036 Typ 1.30 Vdd/2 1.32 Vdd/2 + 0.02 Units V V P2[4] 1.30 2.08 0.000 P2[4] + 0.009 1.34 2.13 0.034 V V V mV P2[4] + P2[6] P2[4] + P2[6] + 0.042 2.70 V P2[4] - P2[6] + 0.036 V 2.60 P2[4] - P2[6] Max V Note See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 27. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) Min - - Typ 12.24 80 Max - - Units k fF Notes DC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 28. DC Analog Mux Bus Specifications Symbol RSW RVSS Description Switch Resistance to Common Analog Bus Resistance of Initialization Switch to VSS Document Number: 001-48111 Rev. *D Min - - Typ - - Max 400 800 Units Notes Vdd 3.0V Page 43 of 65 [+] Feedback PRELIMINARY CY8C28xxx DC SAR10 ADC Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 29. DC SAR10 ADC Specifications Symbol INLSAR10 DNLSAR10 ISAR10 IVREFSAR10 Description Integral nonlinearity Differential nonlinearity Active current consumption Input current into P2[5] when configured as the SAR10 ADC's VREF input. VVREFSAR10 Input reference voltage at P2[5] when configured as the SAR10 ADC's external voltage reference. VOSSAR10 Offset voltage Document Number: 001-48111 Rev. *D Min -2.5 -1.5 0.08 - Typ TBD - 3.0 - 5 TBD Max Units Notes 2.5 LSB 10-bit resolution 1.5 LSB 10-bit resolution 0.497 mA 0.5 mA The internal voltage reference buffer is disabled in this configuration. 4.95 V When VREF is buffered inside the SAR10 ADC, the voltage level at P2[5] (when configured as the external reference voltage) must always be at least 300 mV less than the chip supply voltage level on the Vdd pin. (VVREFSAR10 < (Vdd - 300 mV) ). 9 mV Page 44 of 65 [+] Feedback PRELIMINARY CY8C28xxx DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices, for more information on the VLT_CR register. Table 30. DC POR and LVD Specifications Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description Vdd Value for PPOR Trip (positive ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for PUMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ Max Units - 2.91 4.39 4.55 - V V V - 2.82 4.39 4.55 - V V V - - - 92 0 0 - - - mV mV mV 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98[17] 3.08 3.20 4.08 4.57 4.74[18] 4.82 4.91 V V V V V V V V 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 V V V V V V V V Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog. Notes 17. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 18. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. Document Number: 001-48111 Rev. *D Page 45 of 65 [+] Feedback PRELIMINARY CY8C28xxx DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 31. DC Programming Specifications Symbol IDDP VILP Description Supply Current During Programming or Verify Input Low Voltage During Programming or Verify VIHP Input High Voltage During Programming or Verify IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify VOLV Output Low Voltage During Programming or Verify VOHV Output High Voltage During Programming or Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total)[19] FlashDR Flash Data Retention Min - - Typ 5 - Max 25 0.8 Units mA V 2.2 - - V - - 0.2 mA - - 1.5 mA - - Vss + 0.75 V Vdd - 1.0 - Vdd V 50,000 1,800,000 10 - - - - - - Notes Driving internal pull-down resistor. Driving internal pull-down resistor. - Erase/write cycles per block. - Erase/write cycles. Years Note 19. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 001-48111 Rev. *D Page 46 of 65 [+] Feedback PRELIMINARY CY8C28xxx AC Electrical Characteristics AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 32. AC Chip-Level Specifications Symbol FIMO FIMO6 Description Internal Main Oscillator Frequency Internal Main Oscillator Frequency for 6 MHz Min 23.4 5.5 Typ 24 6 Max 24.6[20] 6.5[20] Units MHz MHz FCPU1 FCPU2 FBLK5 FBLK33 F32K1 CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator 0.091 0.091 0 0 15 24 12 24 32 24.6[20, 21] 12.3[21,22] 49.2[20,21,23] 24.6[21, 23] 64 MHz MHz MHz MHz kHz - 32.768 - kHz 5 - - kHz F32K2 F32K_U Internal Low Speed Oscillator Untrimmed Frequency FPLL Jitter24M2 TPLLSLEW TPLLSLEWS PLL Frequency 24 MHz RMS Period Jitter (PLL) PLL Lock Time PLL Lock Time for Low Gain Setting - - 0.5 0.5 23.986 - - - - 600 10 50 MHz ps ms ms External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm - 1700 2620 ms - 2800 3800 ms 32 kHz RMS Period Jitter External Reset Pulse Width 24 MHz Duty Cycle Internal Low Speed Oscillator Duty Cycle 48 MHz Output Frequency 24 MHz RMS Period Jitter (IMO) Maximum Frequency of Signal on Row Input or Row Output. Supply Ramp Time - 10 40 20 100 - 50 50 - 60 80 ns s % % 46.8 - - 48.0 600 - 49.2[20,22] 12.3 MHz ps MHz 0 - - s Notes Trimmed. Utilizing factory trim values. Trimmed for 5V or 3.3V operation using factory trim values. SLIMO Mode = 1. Trimmed. Utilizing factory trim values. Trimmed. Utilizing factory trim values. 4.75V< Vdd <5.25V 3.0V<Vdd<3.6V Trimmed. Utilizing factory trim values. Accuracy is capacitor and crystal dependent. 50% duty cycle. After a reset and before the m8c starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference manual for details on timing this. Multiple (x732) of crystal frequency. LOW TOS TOSACC Jitter32k TXRST DC24M DCILO Fout48M Jitter24M1 FMAX TRAMP The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. 3.0V Vdd 5.5V, -40 oC TA 85 oC. Trimmed. Utilizing factory trim values. Notes 20. 4.75V < Vdd < 5.25V. 21. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 22. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. 23. See the individual user module data sheets for information on maximum frequencies for user modules. Document Number: 001-48111 Rev. *D Page 47 of 65 [+] Feedback PRELIMINARY CY8C28xxx Figure 9. PLL Lock Timing Diagram PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 10. PLL Lock for Low Gain Setting Timing Diagram PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 11. External Crystal Oscillator Startup Timing Diagram 32K Select 32 kHz TOS F32K2 Figure 12. 24 MHz Period Jitter (IMO) Timing Diagram Jitter24M1 F 24M Figure 13. 32 kHz Period Jitter (ECO) Timing Diagram Jitter32k F 32K2 Document Number: 001-48111 Rev. *D Page 48 of 65 [+] Feedback PRELIMINARY CY8C28xxx AC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 33. AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 3 2 10 10 Typ - - - 27 22 Max 12.3 18 18 - - Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Figure 14. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The Operational Amplifiers covered by these specifications are components of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V. Table 34. 5V AC Operational Amplifier Specifications Symbol TROA TSOA SRROA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Document Number: 001-48111 Rev. *D Min Typ Max Units - - - - - - 3.9 0.72 0.62 s s s - - - - - - 5.9 0.92 0.72 s s s 0.15 1.7 6.5 - - - - - - V/s V/s V/s Notes Page 49 of 65 [+] Feedback PRELIMINARY CY8C28xxx Table 34. 5V AC Operational Amplifier Specifications (continued) Symbol SRFOA BWOA ENOA Description Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Noise at 1 kHz Power = Medium, Opamp Bias = High Min Typ Max Units 0.01 0.5 4.0 - - - - - - V/s V/s V/s 0.75 3.1 5.4 - - - - 100 - - - - MHz MHz MHz nV/rt-Hz Min Typ Max Units - - - - 3.92 0.72 s s - - - - 5.41 0.72 s s 0.31 2.7 - - - - V/s V/s 0.24 1.8 - - - - V/s V/s 0.67 2.8 - - - 100 - - - MHz MHz nV/rt-Hz Notes Table 35. 3.3V AC Operational Amplifier Specifications Symbol TROA TSOA SRROA SRFOA BWOA ENOA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Slew Rate (80% to 20%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Noise at 1 kHz Power = Medium, Opamp Bias = High Document Number: 001-48111 Rev. *D Notes Page 50 of 65 [+] Feedback PRELIMINARY CY8C28xxx When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to TBD (TBD dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 15. Typical AGND Noise with P2[4] Bypass TBD At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 16. Typical Opamp Noise TBD Document Number: 001-48111 Rev. *D Page 51 of 65 [+] Feedback PRELIMINARY CY8C28xxx AC Type-E Operational Amplifier Specifications Table 36 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. The Operational Amplifiers covered by these specifications are components of the Limited Type E Analog PSoC blocks. Table 36. AC Type-E Operational Amplifier Specifications Symbol TCOMP Description Comparator Mode Response Time, 50 mV Overdrive Min - Typ Max 100 Units ns Notes AC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 37. AC Low Power Comparator Specifications Symbol TRLPC Description LPC Response Time Min - Typ - Max 50 Units s Notes 50 mV overdrive comparator reference set within VREFLPC. AC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 38. AC Analog Mux Bus Specifications Symbol FSW Description Switch Rate Min - Typ - Max 3.17 Units MHz Notes AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 39. AC Digital Block Specifications Function Description All Maximum Block Clocking Frequency (> 4.75V) Functions Maximum Block Clocking Frequency (< 4.75V) Timer Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Kill Pulse Width: Band Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) Document Number: 001-48111 Rev. *D Min - - 50[24] - - 50[24] - - Typ - - - - - - - - Max 49.2 24.6 - 49.2 24.6 - 49.2 24.6 Units MHz MHz ns MHz MHz ns MHz MHz 20 50[24] 50[24] - - - - - - - - - - 49.2 49.2 ns ns ns MHz MHz Notes 4.75V < Vdd < 5.25V. 3.0V < Vdd < 4.75V. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. Page 52 of 65 [+] Feedback PRELIMINARY CY8C28xxx Table 39. AC Digital Block Specifications (continued) Function Description CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM Maximum Input Clock Frequency SPIS Transmitter Receiver Min - Typ - Max 24.6 Units MHz - - 8.2 MHz - 50[24] - - - - 4.1 - 24.6 MHz ns MHz Vdd 4.75V, 2 Stop Bits - - 49.2 MHz Full Vdd Range - - 24.6 MHz Vdd 4.75V, 2 Stop Bits - - 49.2 MHz Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Full Vdd Range Notes Maximum data rate at 4.1 MHz due to 2 x over clocking. Maximum data rate at 3.16 MHz due to 8 x over clocking. Maximum data rate at 6.30 MHz due to 8 x over clocking. Maximum data rate at 3.16 MHz due to 8 x over clocking. Maximum data rate at 6.30 MHz due to 8 x over clocking. AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 40. 5V AC Analog Output Buffer Specifications Symbol Description TROB Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High Min Typ Max Units - - - - 2.5 2.5 s s - - - - 2.2 2.2 s s 0.65 0.65 - - - - V/s V/s 0.65 0.65 - - - - V/s V/s 0.8 0.8 - - - - MHz MHz 300 300 - - - - kHz kHz Notes Note 24. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-48111 Rev. *D Page 53 of 65 [+] Feedback PRELIMINARY CY8C28xxx Table 41. 3.3V AC Analog Output Buffer Specifications Symbol TROB TSOB SRROB SRFOB BWOB BWOB Description Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High Min Typ Max Units - - - - 3.8 3.8 s s - - - - 2.6 2.6 s s 0.5 0.5 - - - - V/s V/s 0.5 0.5 - - - - V/s V/s 0.7 0.7 - - - - MHz MHz 200 200 - - - - kHz kHz Notes AC SAR10 ADC Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 42. AC SAR10 ADC Specifications Symbol FINSAR10 FSSAR10 Description Input clock frequency for SAR10 ADC Sample rate for SAR10 ADC SAR10 ADC Resolution = 10 bits Min - - Typ - - Max 2.7 192.6 Units MHz ksps Notes For 10-bit resolution, the sample rate is the ADC's input clock divided by 14. AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 43. 5V AC External Clock Specifications Symbol Description Min Typ Max Units FOSCEXT Frequency 0.093 - 24.6 MHz - High Period 20.6 - 5300 ns - Low Period 20.6 - - ns - Power Up IMO to Switch 150 - - s Document Number: 001-48111 Rev. *D Notes Page 54 of 65 [+] Feedback PRELIMINARY CY8C28xxx Table 44. 3.3V AC External Clock Specifications Min Typ Max Units FOSCEXT Symbol Frequency with CPU Clock divide by 1[25] Description 0.093 - 12.3 MHz FOSCEXT Frequency with CPU Clock divide by 2 or greater[26] 0.186 - 24.6 MHz - High Period with CPU Clock divide by 1 41.7 - 5300 ns - Low Period with CPU Clock divide by 1 41.7 - - ns - Power Up IMO to Switch 150 - - s Notes AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 45. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TERASEALL Description Rise Time of SCLK Fall Time of SCLK Data Setup Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Flash Erase Time (Bulk) TPROGRAM_HOT Flash Block Erase + Flash Block Write Time TPROGRAM_COLD Flash Block Erase + Flash Block Write Time Min 1 1 40 40 0 - - - - - Typ - - - - - 40 40 - - 80 - - - - Max 20 20 - - 8 - - 55 70 - Units Notes ns ns ns ns MHz ms ms ns Vdd > 3.6 ns 3.0 Vdd 3.6 ms Erase all blocks and protection fields at once. 100[27] ms 0C Tj 100C 200[27] ms -40C Tj 0C Notes 25. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 26. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. 27. For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note, AN2015 at http://ww.cypress.com under Application Notes for more information. Document Number: 001-48111 Rev. *D Page 55 of 65 [+] Feedback PRELIMINARY CY8C28xxx AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 46. AC Characteristics of the I2C SDA and SCL Pins Symbol Description SCL Clock Frequency FSCLI2C THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. TLOWI2C LOW Period of the SCL Clock HIGH Period of the SCL Clock THIGHI2C TSUSTAI2C Setup Time for a Repeated START Condition THDDATI2C Data Hold Time TSUDATI2C Data Setup Time TSUSTOI2C Setup Time for STOP Condition Bus Free Time Between a STOP and START TBUFI2C Condition TSPI2C Pulse Width of spikes are suppressed by the input filter. Standard Mode Min Max 0 100 4.0 - Fast Mode Min Max 0 400 0.6 - Units Notes kHz s 4.7 4.0 4.7 0 250 4.0 4.7 - - - - - - - 1.3 0.6 0.6 0 100[28] 0.6 1.3 - - - - - - - s s s s ns s s - - 0 50 ns Figure 17. Definition for Timing for Fast/Standard Mode on the I2C Bus SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S Note 28. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT S 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-48111 Rev. *D Page 56 of 65 [+] Feedback PRELIMINARY CY8C28xxx Packaging Information This section illustrates the packaging specifications for the CY8C28xxx PSoC devices, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the drawings at http://www.cypress.com/design/MR10161. Packaging Dimensions Figure 18. 20-Pin (210-Mil) SSOP 51-85077 *C Document Number: 001-48111 Rev. *D Page 57 of 65 [+] Feedback PRELIMINARY CY8C28xxx Figure 19. 28-Pin (210-Mil) SSOP 51-85079*C Figure 20. 44-Pin TQFP 51-85064 *C Document Number: 001-48111 Rev. *D Page 58 of 65 [+] Feedback PRELIMINARY CY8C28xxx Figure 21. 48-Pin (7x7 mm) QFN 001-13191 *C Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Figure 22. 56-Pin SSOP Package 51-85062 *C Document Number: 001-48111 Rev. *D Page 59 of 65 [+] Feedback PRELIMINARY CY8C28xxx Thermal Impedances Table 47. Thermal Impedances per Package Package 20 SSOP 28 SSOP 44 TQFP 48 QFN 56 SSOP Typical JA [29] 80.8 C/W 45.4 C/W 24.0 C/W 16.7 C/W 67.5 C/W Capacitance on Crystal Pins Table 48. Typical Package Capacitance on Crystal Pins Package 20 SSOP 28 SSOP 44 TQFP 48 QFN 56 SSOP Package Capacitance Pin9 = 0.0056 pF Pin11 = 0.006048 pF Pin13 = 0.006796 pF Pin15 = 0.006755 pF Pin16 = 0.009428 pF Pin18 = 0.008635 pF Pin17 = 0.008493 pF Pin19 = 0.008742 pF Pin27 = 0.007916 pF Pin31 = 0.007132 pF Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 49. Solder Reflow Peak Temperature Package Minimum Peak Temperature[30] Maximum Peak Temperature 20 SSOP 245 C 260 C 28 SSOP 245 C 260 C 44 TQFP 245 C 260 C 48 QFN 245 C 260 C 56 SSOP 245 C 260 C Notes 29. TJ = TA + POWER x JA 30. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5oC with Sn-Pb or 245 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-48111 Rev. *D Page 60 of 65 [+] Feedback PRELIMINARY CY8C28xxx Development Tool Selection This section presents the development tools available for all current PSoC device families including the CY8C28xxx family. Software PSoC Designer CY3210-ExpressDK PSoC Express Development Kit At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for over half a decade. PSoC Designer is available free of charge at http://www.cypress.com/psocdesigner. The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (may be used with ICE-Cube In-Circuit Emulator). It provides access to I2C buses, voltage reference, switches, upgradeable modules and more. The kit includes: PSoC Programmer PSoC Express Software CD Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC Programmer is available free of charge at http://www.cypress.com/psocprogrammer. Express Development Board 4 Fan Modules 2 Proto Modules MiniProg In-System Serial Programmer MiniEval PCB Evaluation Board PSoC C Compilers Jumper Wire Kit USB 2.0 Cable Serial Cable (DB9) 110 ~ 240V Power Supply, Euro-Plug Adapter 2 CY8C24423A-24PXI 28-PDIP Chip Samples Development Kits 2 CY8C27443-24PXI 28-PDIP Chip Samples All development kits can be purchased from the Cypress Online Store. 2 CY8C29466-24PXI 28-PDIP Chip Samples CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. Advanced emulation features are supported in PSoC Designer. The kit includes: Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store. CY3210-MiniProg1 PSoC Designer Software CD The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: ICE-Cube In-Circuit Emulator MiniProg Programming Unit Pod kit for CY8C29x66 PSoC Family MiniEval Socket Programming and Evaluation Board Cat-5 Adapter 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample Mini-Eval Programming Board 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample 110 ~ 240V Power Supply, Euro-Plug Adapter PSoC Designer Software CD ISSP Cable Getting Started Guide USB 2.0 Cable and Blue Cat-5 Cable USB 2.0 Cable 2 CY8C29466-24PXI 28-PDIP Chip Samples Document Number: 001-48111 Rev. *D Page 61 of 65 [+] Feedback PRELIMINARY CY8C28xxx CY3210-PSoCEval1 Device Programmers The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: All device programmers can be purchased from the Cypress Online Store. CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide CY3207 Programmer Unit USB 2.0 Cable PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable Note: The CY3207ISSP programmer needs the PSoC ISSP software. It is not compatible with the PSoC Programmer software. The latest PSoC ISSP software for this kit can be downloaded from http://www.cypress.com. The kit includes: Accessories (Emulation and Programming) Table 50. Emulation and Programming Accessories Part # Pin Package Pod Kit[31] Foot Kit[32] CY8C28243-24PVXI 20 SSOP CY3250-28XXX CY3250-20SSOP-FK CY8C28403-24PVXI CY8C28413-24PVXI CY8C28433-24PVXI CY8C28445-24PVXI CY8C28452-24PVXI 28 SSOP CY3250-28XXX CY3250-28SSOP-FK CY8C28513-24AXI CY8C28533-24AXI CY8C28545-24AXI 44 TQFP CY3250-28XXX CY8C28623-24LTXI CY8C28643-24LTXI CY8C28645-24LTXI 48 QFN CY3250-28XXXQFN CY3250-48QFN-FK CY3250-44TQFP-FK Adapter[33] Adapters can be found at http://www.emulation.com. 3rd-Party Tools Build a PSoC Emulator into Your Board Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards. For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note "Debugging - Build a PSoC Emulator into Your Board AN2323" at http://www.cypress.com/an2323. Notes 31. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples. 32. Foot kit includes surface mount feet that can be soldered to the target PCB. 33. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. Document Number: 001-48111 Rev. *D Page 62 of 65 [+] Feedback PRELIMINARY CY8C28xxx Ordering Information CapSense Digital Blocks Regular Analog Blocks Limited Analog Blocks HW I2C Decimators 10-bit SAR ADC Digital I/O Pins Analog Inputs Analog Outputs Flash (KBytes) RAM (KBytes) XRES Pin CY8C28403-24PVXI -40 to 85 N 12 0 0 2 0 Y 24 8 0 16 1 Y 28-Pin (210 Mil) SSOP (Tape and Reel) CY8C28403-24PVXIT -40 to 85 N 12 0 0 2 0 Y 24 8 0 16 1 Y 28-Pin (210 Mil) SSOP CY8C28413-24PVXI -40 to 85 Y 12 0 4 1 2 Y 24 24 0 16 1 Y 28-Pin (210 Mil) SSOP (Tape and Reel) CY8C28413-24PVXIT -40 to 85 Y 12 0 4 1 2 Y 24 24 0 16 1 Y 44-Pin TQFP CY8C28513-24AXI -40 to 85 Y 12 0 4 1 2 Y 40 40 0 16 1 Y 44-Pin TQFP (Tape and Reel) CY8C28513-24AXIT -40 to 85 Y 12 0 4 1 2 Y 40 40 0 16 1 Y 48-Pin Sawn QFN CY8C28623-24LTXI -40 to 85 N 12 6 0 2 2 N 44 10 2 16 1 Y 48-Pin Sawn QFN (Tape and Reel) CY8C28623-24LTXIT -40 to 85 N 12 6 0 2 2 N 44 10 2 16 1 Y 28-Pin (210 Mil) SSOP CY8C28433-24PVXI -40 to 85 Y 12 6 4 1 4 Y 24 24 2 16 1 Y 28-Pin (210 Mil) SSOP (Tape and Reel) CY8C28433-24PVXIT -40 to 85 Y 12 6 4 1 4 Y 24 24 2 16 1 Y 44-Pin TQFP CY8C28533-24AXI -40 to 85 Y 12 6 4 1 4 Y 40 40 2 16 1 Y 44-Pin TQFP (Tape and Reel) CY8C28533-24AXIT -40 to 85 Y 12 6 4 1 4 Y 40 40 2 16 1 Y 20-Pin (210 Mil) SSOP CY8C28243-24PVXI -40 to 85 N 12 12 0 2 4 Y 16 16 4 16 1 Y 20-Pin (210 Mil) SSOP (Tape and Reel) CY8C28243-24PVXIT -40 to 85 N 12 12 0 2 4 Y 16 16 4 16 1 Y 48-Pin Sawn QFN CY8C28643-24LTXI -40 to 85 N 12 12 0 2 4 Y 44 44 4 16 1 Y 48-Pin Sawn QFN (Tape and Reel) CY8C28643-24LTXIT -40 to 85 N 12 12 0 2 4 Y 44 44 4 16 1 Y 28-Pin (210 Mil) SSOP CY8C28445-24PVXI -40 to 85 Y 12 12 4 2 4 Y 24 24 4 16 1 Y 28-Pin (210 Mil) SSOP (Tape and Reel) CY8C28445-24PVXIT -40 to 85 Y 12 12 4 2 4 Y 24 24 4 16 1 Y 44-Pin TQFP CY8C28545-24AXI -40 to 85 Y 12 12 4 2 4 Y 40 40 4 16 1 Y Ordering Code 28-Pin (210 Mil) SSOP Package Temperature Range The following table lists the CY8C28xxx PSoC devices key package features and ordering codes. Document Number: 001-48111 Rev. *D Page 63 of 65 [+] Feedback PRELIMINARY CapSense Digital Blocks Regular Analog Blocks Limited Analog Blocks HW I2C Decimators 10-bit SAR ADC Digital I/O Pins Analog Inputs Analog Outputs Flash (KBytes) RAM (KBytes) XRES Pin 44-Pin TQFP (Tape and Reel) CY8C28545-24AXIT -40 to 85 Y 12 12 4 2 4 Y 40 40 4 16 1 Y 48-Pin Sawn QFN CY8C28645-24LTXI -40 to 85 Y 12 12 4 2 4 Y 44 44 4 16 1 Y 48-Pin Sawn QFN (Tape and Reel) CY8C28645-24LTXIT -40 to 85 Y 12 12 4 2 4 Y 44 44 4 16 1 Y 28-Pin (210 Mil) SSOP CY8C28452-24PVXI -40 to 85 Y 8 12 4 1 4 N 24 24 4 16 1 Y 28-Pin (210 Mil) SSOP (Tape and Reel) CY8C28452-24PVXIT -40 to 85 Y 8 12 4 1 4 N 24 24 4 16 1 Y 56-Pin SSOP OCD CY8C28000-24PVXI -40 to 85 Y 12 12 4 2 4 Y 44 44 4 16 1 Y Package Ordering Code Temperature Range CY8C28xxx Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE). Ordering Code Definitions CY 8 C 28 xxx - SP xxxx Package Type: PX = PDIP Pb-free SX = SOIC Pb-free PVX = SSOP Pb-free LTX/LFX/LKX = QFN Pb-free AX = TQFP Pb-free Thermal Rating: C = Commercial I = Industrial E = Extended Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Document Number: 001-48111 Rev. *D Page 64 of 65 [+] Feedback PRELIMINARY CY8C28xxx Document History Page Document Title: CY8C28243, CY8C28403, CY8C28413, CY8C28433, CY8C28445, CY8C28452, CY8C28513, CY8C28533, CY8C28545, CY8C28623, CY8C28643, CY8C28645 PSoC(R) Programmable System-on-Chip Document Number: 001-48111 Origin of Submission Revision ECN No. Description of Change Change Date ** 2593460 BTK/PYRS 10/20/08 New document (Revision **). *A 2652217 BTK/PYRS 02/02/09 Extensive updates to content. Added registers maps. Updated Getting Started section Updated Development Tools section Added some SAR10 ADC specifications. Added more analog system figures *B 2675937 BTK 03/18/09 Updated DC Analog Reference Specifications tables Minor content updates *C 2679015 HMI 03/26/2009 Post to external web. *D 2750217 TDU 08/10/09 Updates to Electrical Specificatons section Minor content updates Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at www.cypress.com/sales. Products PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com (c) Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-48111 Rev. *D Revised August 10, 2009 Page 65 of 65 PSoC DesignerTM is a trademark and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback