ICS2694
Motherboard Clock Generator
Integrated
Circuit
Systems, Inc.
Description
The ICS2694 Motherboard Clock Generator is an integrat ed
circuit using P LL and VCO technology to generate virtually all
the clock signals required in a PC. The use of the device can be
generalized to satisfy the timing needs of most digital systems
by reprogramming the VCO or reconfiguring the counter stages
which derive the output frequencies from the VCO’ s.
The primary VCO is customarily used to generate the CPU
clock and is so labeled on the ICS2694. Pre-programmed
frequency sets are listed on page 6. These choices were made
to match the major microprocessor families. CPUSEL (0-3)
allow the user to select the appropriate frequency for the
application.
Due to the filter in the phase-locked loop, the CPUCLK will
move in a linear fashion from one frequency to a newly-
sele cte d frequ ency wit hout gl itch es. If a fixe d CPUCLK v alue
is desired, CPUSEL (0-3) may be hard wired to the desired
address with STROBE tied high. (I t has a pull-up.) For board
test and debug, pulling OUTPUTE to Ground will tristat e al l
th e outputs.
Features
•• Low cost - eliminates multiple oscillators and Count
Down Logic
•• Primary VCO has 16 Mask Programmable frequencies
(normally CPU cloc k)
•• Secondary VCO has 1 Mask Programmable frequency
(usually 96 MHz)
•• Pre -pr ogra m med versions for typi c al PC appli cat io ns
•• 10 Outputs in addition to the primary CPU clock
•• Capability to reconfigure counter stages to change the
frequencies of the outputs via mask options
•• Adva nc ed PL L desig n
•• On-c hip PL L filte rs
•• Ve ry Flexible Ar c hitec tu re
OUT2 1 24 OUT3
OUT1 2 23 OUT4
OUT0 3 22 OUT5
OUT9 4 21 OUT6
CPUCLK 5 20 OUT 7 (CPUCLK/2)
VSS 6 19 OUT8
DVDD 7 18 AVDD
STROBE 8 17 XTAL2
CPUSEL0 9 16 XTAL1
CPUSEL1 10 15 AVSS
CPUSEL2 11 14 OUTPUTE
CPUSEL3 12 13 CLKIN
24-Pin DIP or SOIC
ICS2694
Pin Configuration
ICS2694RevA1094
Applications
•• CPU clock and Co -pro cessor c lock
•• Ha rd Disk and Fl oppy Di sk cl ock
•• Keyboard clock
•• Serial Port clock
•• Bus c lock
•• Syste m co unt ing or timing fu ncti ons
Pin Description
PIN NUMBER NAME DESCRIPTION
1 OUT2 4mA Output .
2 OUT1 4mA Output .
3 OUT0 4mA Output
4 OUT9 4mA Output .
5 CPUCL K 4mA Ou tput d riven by Vo lt age Control led Osci llator 1 (VC01). VC 01 i s cont rolle d
by a 1 6 word ROM.
6 V SS Groun d for digi tal po rtion of chip.
7 DVDD Plus supply for digital por tion of chip .
8 STR OBE Input cont rol for t ransparent latc hes a ssoci at ed wit h CPU (0-3) whic h se lec t one of
16 values for CPUCLK. Holding STROBE high causes the latches to be transpa rent.
9 CPUSEL0 LSB CPUCLK address bit.
10 CPUSEL1 CPUCLK ad dres s bi t.
1 1 CPUSEL2 CPUCLK ad dres s bi t.
12 CPUSEL3 MSB CPUCLK ad dres s bi t.
13 CLKIN An alternative input for the reference clock. The crystal oscillator output and CLKIN
are ga ted toge the r to genera t e the ref eren ce cl oc k for the VCO’s. If CL KIN is used,
XTAL1 shoul d be held high and XTAL 2 lef t open. If the int er nal oscil lat or is used,
hol d CLKIN hig h.
14 OUTPUT E Pullin g this lin e low trista tes al l outpu ts.
15 AVS S Groun d for ana lo g port io n of chip .
16 XTAL 1 Inpu t of internal cr ysta l oscil lat or sta ge .
17 XTAL2 Output of in te rnal crystal oscilla tor stage. This pin should have nothing connected
to it but one of th e quar tz crystal t er mi na ls.
18 AVDD Positive supply for a na log por tion of chip.
19 OUT8 4mA Output.
20 OUT7 4mA Output . (Usually assi gne d as CPUCLK/ 2 for c o- proc e ssor use. )
21 OUT6 4mA Output.
22 OUT5 4mA Output.
23 OUT4 4mA Output.
24 OUT3 4mA Output.
ICS2694
2
Frequency Reference
The internal reference oscillator contains all of the passive
components required. An appropriate series-resonant crystal
should be connected between XTAL1 (1) and XTAL2 (2). In
IBM-compatible applications, this will typically be a
14.31818 MHz crystal, but fundamental mode crystals be-
tween 10 MHz and 25 MHz have been tested. Maintain short
lead lengths between the crystal and the ICS2694. In ord er to
optimize the quality of the quartz crystal oscillator, the input
switchi ng threshold of XTAL1 is VDD/2 rather than the con-
ventional 1.4V of TTL. Therefore, XTAL1 may not respond
properly to a legal TTL signal since TTL is not required to
exceed VDD/2. Therefore, another clock input CLKIN (pin 13)
has been added to the chip which is sized to have an input
switching point of 1.4V. Inside the chip, these two inputs are
ANDED. Therefore, when using the XTAL1 and XTAL2,
CLKIN should be held high. (It has a pull-up.) When using
CLKIN, XTAL1 should be held high. (It does not have a
pull-up because a pull-up would interfere with the oscillator
bias.)
It is anticipated that some applications will use both clock
inputs , properly gated, for eith er board test or unique system
fun ctio ns. By ge nerat ing all the sy st em clocks from one refer-
ence input, the phase and delay relationships between the
vari ous o utp uts wil l rem a in re lat iv el y fixed, t he re by e lim ina t -
ing prob le ms arising from totally unsynchro niz ed clocks inter-
acting in a system.
Power Supply Conditioning
The ICS2694 is a member of the second generation of dot clock
pro duc ts. By inc orp ora ti ng the lo op filt er on chi p and upgr ad -
ing the VCO, the ease of application has been substantially
improved over earlier products. If a stable and noise-free power
supply is available, no external components are required. How-
eve r, in some appl ica ti ons it may be jud icio us to de c oupl e t he
power supply as shown in Figures 1 or 2. Figure 1 is the normal
configuration for 5 volt only appl ications . Which of the two
pro vides sup erior performance d epen ds on the noise co ntent of
the p ower supplie s. In gene ral , the configur atio n of Figure 1 is
satisfactory. Figure 2 is the more conventional if a 12 volt
analog supply is available, although the improved performance
comes at a cost of an extra component; however , the cost of t he
discre t es used in Fig ure 1’s are less tha n the co st of Figure 1’s
di screte c om po n ents.
Since the ICS2694 outputs a large nu mber of high-frequency
clocks, conservative design practices are recommended. Care
should be exercised in the board layout of supply and ground
trac es, and a dequate powe r supply de c oupl in g capa c itors c on -
siste nt wit h the applic a tion should be used .
R1
33
+5
+5
DVDD
VSS, AVSS
AVDD
C2
22µV
C1
C3
.µ1F
.µ1F
Fi gu re 1
D1R1
470
+120
+50 DVDD
VSS, AVSS
AVDD
4.7V
C1
C2
.µ1F
.µ1F
Fi gu re 2
ICS2694
3
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . VDD. . . . . . . . . . . . -0.5V to + 7V
I nput Voltage. . . . . . . . . . . . . . . . . . VIN . . . . . . . . . . . . -0.5V to VDD +0. 5V
Outpu t Voltag e . . . . . . . . . . . . . . . . VOUT. . . . . . . . . . -0.5V to VDD +0.5V
C lam p Diode Cu rre nt . . . . . . . . . . . V IK & IOK. . . . . . . ±30mA
Output Current per Pin . . . . . . . . . . IOUT . . . . . . . . . . . ±50mA
Operating Temperature . . . . . . . . . . TO. . . . . . . . . . . . . 0°C to + 150°C
Storage Temperature. . . . . . . . . . . . TS. . . . . . . . . . . . . -85°C to + 150°C
Power Di ssipation. . . . . . . . . . . . . . PD. . . . . . . . . . . . . 500mW
Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is adv ised that normal precautions be taken to avoid applications
of any voltage higher than the maximum rated voltages. For proper operation, it is recommended that VIN and VOUT be constrained
to > = VSS and < = VDD.
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
Operating Voltage Range VDD 4.0 5.5 V
Input Low Volta ge VIL VDD = 5V VSS 0.8 V
Input Hi gh Vol tage VIH VDD = 5V 2. 0 VDD V
Input Leaka ge Curre nt IIH VIN = Vcc -10uA
Output Low Voltag e VOL IOL = 4.0 m A - 0 .4 V
Output Hi gh Vo ltag e VOH IOH = 4. 0 m A 2 .4 - V
Supply Cur re nt I DD VDD = 5V, CPUCLK = 80 MHz - 55 mA
Int erna l Pul l-u p Resistor s RUP *V
DD = 5V, Vin = 0V 50 - k ohm
Input Pin C ap aci tanc e Cin Fc = 1 MHz - 8 pF
Output Pi n Capaci tanc e C out Fc = 1 MHz - 12 pF
* The following inputs have pull-ups: OUTPUTE, STROBE, CPUSEL (0-3), CLKIN.
DC Characteristics (0°C to 70°C)
ICS2694
4
AC Timing Characteristics
The foll owing note s appl y to all pa ra m et e rs pre se nt e d in this sec t ion :
1. Xtal Frequency = 14.31818 MHz
2. All units a re in nanose c onds (ns).
3. Rise and fall time is betwee n 0.8 a nd 2.0 VDC.
4. Output pin loading = 15pF
5. Duty cycle is measure d at 1.4V.
6. Supply Voltage Range = 4.5 to 5.5 volts
7. Temperature Range = 0°C to 70°C
SYMBOL PARAMETER MIN MAX NOTES
STROBE TIMING
Tpw
Tsu
Thd
Strobe Pulse Width
Se tup Time Data to Strobe
Hold Time Data to Strobe
20
10
10
-
-
-
FOUT TIMIN G
Tr
Tf
-
-
Ri se T im e
Fall Time
Frequency Erro r
Maximum Frequency
-
-3
3
0.5
135
Duty Cycle 40% min. to 60% m ax.
at 80 MHz
%
MHz
Note:
Patt er n -004 has rising edge s of CPUCL K a nd CPUCLK/2 ma tch ed t o ± 2 ns.
STROBE
CPUSEL (0-3)
Tpw
Tsu Thd
ICS2694
5
24-Pin DIP Package
Ordering Information
ICS2694N-XXX
Example:
ICS XXX X M -XXX
Pattern Number ( 2 or 3 digit number for parts with ROM code patterns)
Package Type
N=DIP ( Plastic)
Devic e Type (cons i sts of 3 or 4 digit numbe rs )
Prefix
ICS, AV=Stan dard Device; GSP=Genlock Device
ICS2694
6
LE AD COUNT 14L 16L 18L 20L 24 L 28L 32 L
DIMENSION L 0.35 4 0.404 0. 454 0.5 04 0.6 04 0.7 04 0.8 04
SOIC Packag es
Ordering Information
ICS2694M-XXX
Example:
ICS XXX X M -XXX
Pattern Number ( 2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC
Devic e Type (cons i sts of 3 or 4 digit numbe rs )
Prefix
ICS, AV=Stan dard Device; GSP=Genlock Device
ICS2694
7
ICS2694 Standard P atterns
CPUSEL0-3
(Hex) CPUCLK OUT PUT (Pi n 5)
(MHz)
02
110
220
324
425
532
6 33.33
740
848
950
10 54
11 66.67
12 68
13 80
14 100
15 16
Note: Pattern -004 has rising edges of CPUCLK and
CPUCLK/ 2 mat ch ed to ± 2 ns.
Another alternative for CPU CLOCK generation is the
ICS2494-244 if the additional functions of the ICS2694 are
not ne ed ed in the appl ic a ti on.
ICS
Part Num ber ICS2494-
244
Addre ss FS3-0
(Hex) Frequency
(MHz)
020
124
232
340
450
566.6
680
7 100
854
970
090
B110
C25
D33.3
E40
F50
Address MS1-0
(Hex) Frequency
(MHz)
016
124
250
366.6
32 MHz 1 24 16 M Hz
1
.846 M Hz 2 23 8 M Hz
24 M H z 3 22 9. 6 M Hz
6 MHz 4 21 14.318 MHz
CPUCLK 5 20 CPUCLK/2
VSS 6 1 9 1.19 MH z
DVDD 7 18 AVDD
STROBE 8 17 XTAL2
C
PUSEL0 9 16 XTAL1
C
PUSEL1 10 15 AVSS
C
PUSEL2 11 14 OUTPUTE
C
PUSEL3 12 13 CLKIN
ICS2694-004
ICS2694
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