User's Guide SLVUAF3A - March 2015 - Revised March 2015 UCD90240EVM-704 24-Rail Sequencer Development Board The UCD90240 is a 24-rail PMBus power sequencer and system manager. This UCD90240EVM-704 user's guide describes features, typical applications, electrical specifications, and an overview of the EVM board. Also included are test setup and procedures, software setup, printed-circuit board layouts, a bill of materials (BOM), and the EVM schematics. 1 2 3 4 5 6 7 8 9 10 Contents Introduction ................................................................................................................... 2 Description .................................................................................................................... 2 2.1 Typical Applications ................................................................................................ 2 2.2 Features .............................................................................................................. 2 Electrical Performance Specifications ..................................................................................... 3 Board Overview .............................................................................................................. 4 Test Setup .................................................................................................................... 5 5.1 Test Equipment ..................................................................................................... 5 5.2 Recommended Test Setup ........................................................................................ 5 5.3 List of Connectors and Functions ................................................................................. 6 5.4 Test Points ......................................................................................................... 13 Software Setup ............................................................................................................. 13 6.1 Fusion Digital Power Designer Software (Fusion GUI) Installation ......................................... 13 Test Procedure ............................................................................................................. 14 7.1 Voltage Monitoring Example ..................................................................................... 14 7.2 Rail Enable Example .............................................................................................. 14 7.3 Fault Log Example (Including Blackbox Log) .................................................................. 14 7.4 Command GPO Example ........................................................................................ 14 7.5 Configurable Pullup/Pulldown Signals .......................................................................... 14 7.6 GPI and Logic GPO Example ................................................................................... 14 7.7 Margin Example ................................................................................................... 15 7.8 Cascading Example ............................................................................................... 15 EVM Assembly Drawing and PCB Layout .............................................................................. 16 Bill of Materials (BOM) ..................................................................................................... 24 UCD90240EVM-704 Schematics ........................................................................................ 26 List of Figures 1 UCD90240EVM-704 Board Overview ..................................................................................... 4 2 UCD90240EVM-704 Recommended Test Setup ........................................................................ 5 3 UCD90240EVM-704 Top Assembly Drawing........................................................................... 16 4 UCD90240EVM-704 Bottom Assembly Drawing ....................................................................... 16 5 UCD90240EVM-704 Fabrication Drawing .............................................................................. 17 6 UCD90240EVM-704 Top Overlay ........................................................................................ 18 7 UCD90240EVM-704 Top Solder Mask .................................................................................. 18 8 UCD90240EVM-704 Top Layer .......................................................................................... 19 9 UCD90240EVM-704 Midlayer 1 .......................................................................................... 19 10 UCD90240EVM-704 Midlayer 2 .......................................................................................... 20 11 UCD90240EVM-704 Midlayer 3 .......................................................................................... 20 SWIFT is a trademark of Texas Instruments. Microsoft, Windows are registered trademarks of Microsoft Corporation. SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 1 Introduction www.ti.com 12 UCD90240EVM-704 Midlayer 4 .......................................................................................... 21 13 UCD90240EVM-704 Bottom Layer ...................................................................................... 21 14 UCD90240EVM-704 Bottom Solder Mask .............................................................................. 22 15 UCD90240EVM-704 Bottom Overlay .................................................................................... 22 16 UCD90240EVM-704 Drill Drawing ....................................................................................... 23 17 UCD90240EVM-704 Board Dimensions ................................................................................ 23 18 UCD90240EVM Schematic (1 of 6) ...................................................................................... 26 19 UCD90240EVM Schematic (2 of 6) ...................................................................................... 27 20 UCD90240EVM Schematic (3 of 6) ...................................................................................... 28 21 UCD90240EVM Schematic (4 of 6) ...................................................................................... 29 22 UCD90240EVM Schematic (5 of 6) ...................................................................................... 30 23 UCD90240EVM Schematic (6 of 6) ...................................................................................... 31 List of Tables 1 1 UCD90240EVM-704 Electrical Performance Specifications ........................................................... 3 2 Connector Definition ......................................................................................................... 6 3 Test Point Functions ....................................................................................................... 13 4 UCD90240EVM-704 Bill of Materials .................................................................................... 24 Introduction This user's guide describes the UCD90240 Sequencer Development Board (UCD90240EVM-704). The UCD90240 is a 24-rail PMBus power sequencer and system manager. The UCD90240 can sequence, monitor and margin 24 voltage rails, monitor and respond to user-defined faults such as OV, UV, OC, UC, temperature, time-out, and GPI-triggered faults; provide flexible configurations such as sequence-on/off dependencies, delay time, and Boolean logic; store fault logs into nonvolatile memory; and integrate value-added features such as watchdog, system reset, cascading and sync clock. 2 Description The UCD90240EVM-704 contains a UCD90240 sequencer device and a step-down power stage using the TPS54678 synchronous step-down switcher with integrated FET (SWIFTTM). Access to all of the I/O pins is provided via strip connectors for integration into complex systems using clip-type jumper wires. The UCD90240EVM provides a PMBus (power management bus) communication port. Microsoft(R) Windows(R) based host computers can monitor, control and configure the UCD90240 device using a USB interface adapter EVM (HPA172) and TI fusion digital power designer graphical user interface (GUI). The power stage using the TPS54678 synchronous step-down switcher (5-V input, 1.2-V output) is provided to assist evaluation of the UCD90240's margining function. 2.1 Typical Applications * * * * 2.2 Features * * * * * 2 Industrial / ATE Telecom / Networking equipment Servers and storage systems Any system requiring sequencing and monitoring of multiple power rails Powered by single 5-V supply Status LEDs on all digital I/O pins Strip connector I/O access Headers with pullup/pulldown configurability PMBus interface for configuration and monitoring UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback Electrical Performance Specifications www.ti.com 3 Electrical Performance Specifications Table 1. UCD90240EVM-704 Electrical Performance Specifications Parameter Test Conditions MIN TYP MAX 4.5 5 5.5 UNIT Input Power Input voltage range Input current V All LEDs on, no external load current on I/O pins or step-down converter 135 mA Normal operation, not in margin mode 1.2 V Step-Down Converter Output voltage Output current 6 A Analog Input Analog input voltage range Use internal reference 0 - 3.3 V Analog input voltage range Use external reference 0 - 3 V 2.15 - 5.5 V Digital Inputs and Outputs I/O high-level input voltage (1) I/O low-level input voltage I/O input hysteresis I/O high-level output voltage Load current (source) = -4 mA I/O low-level output voltage Load current (sink) = 4 mA (1) 0 - 1.15 V 0.2 - - V 2.4 - - V - - 0.4 V Maximum input voltage for PMBUS_CNTRL, PMBALERT#, MARGIN19 and MARGIN20 pins are V33D +0.3 V SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 3 Board Overview 4 www.ti.com Board Overview Figure 1 illustrates the UCD90240EVM-704 board. Figure 1. UCD90240EVM-704 Board Overview 4 UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback Test Setup www.ti.com 5 Test Setup 5.1 Test Equipment Voltage Source: One 5-volt power supply with at least 0.5-A sourcing capability. (Optional) One DC power supply with adjustable voltage from 0 V to 3.3 V. Multimeters: One voltmeter Output Load: Optional Oscilloscope: Optional Fan: None Recommended Wire Gauge:AWG 24, or thicker To Test Configuration, Monitoring and Control Functionality Recommended PC platform: Windows 7, 64-bit with 8-GB RAM USB Interface Adapter EVM (USB-to-GPIO): HPA172 The latest version Fusion Digital Power Designer software can be downloaded at the following link to the Texas Instruments website: http://focus.ti.com/docs/toolsw/folders/print/fusion_digital_power_designer.html 5.2 Recommended Test Setup Figure 2 illustrates the recommended test setup. Figure 2. UCD90240EVM-704 Recommended Test Setup SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 5 Test Setup 5.3 www.ti.com List of Connectors and Functions Table 2 lists the EVM connectors and functions. Table 2. Connector Definition Connectors Pins Name Description J1 1 MARGIN1 Margin PWM output 2 MARGIN2 Margin PWM output 3 MARGIN3 Margin PWM output 4 MARGIN4 Margin PWM output 5 MARGIN5 Margin PWM output 6 MARGIN6 Margin PWM output 7 MARGIN7 Margin PWM output 8 MARGIN8 Margin PWM output 1 MARGIN9 Margin PWM output 2 MARGIN10 Margin PWM output 3 MARGIN11 Margin PWM output 4 MARGIN12 Margin PWM output 5 MARGIN13 Margin PWM output 6 MARGIN14 Margin PWM output 7 MARGIN15 Margin PWM output 8 MARGIN16 Margin PWM output 1 MARGIN17 Margin PWM output 2 MARGIN18 Margin PWM output 3 MARGIN19 Margin PWM output 4 MARGIN20 Margin PWM output 5 MARGIN21 Margin PWM output 6 MARGIN22 Margin PWM output 7 MARGIN23 Margin PWM output 8 MARGIN24 Margin PWM output 1 EN1 Rail enable output 2 EN2 Rail enable output 3 EN3 Rail enable output 4 EN4 Rail enable output 5 EN5 Rail enable output 6 EN6 Rail enable output 7 EN7 Rail enable output 8 EN8 Rail enable output 1 EN9 Rail enable output 2 EN10 Rail enable output 3 EN11 Rail enable output 4 EN12 Rail enable output 5 EN13 Rail enable output 6 EN14 Rail enable output 7 EN15 Rail enable output 8 EN16 Rail enable output J2 J3 J4 J5 6 UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback Test Setup www.ti.com Table 2. Connector Definition (continued) Connectors Pins Name Description J6 1 EN17 Rail enable output 2 EN18 Rail enable output 3 EN19 Rail enable output 4 EN20 Rail enable output 5 EN21 Rail enable output 6 EN22 Rail enable output 7 EN23 Rail enable output 8 EN24 Rail enable output 1 LGPO1 Logic GPO output 2 LGPO2 Logic GPO output 3 LGPO3 Logic GPO output 4 LGPO4 Logic GPO output 5 LGPO5 Logic GPO output 6 LGPO6 Logic GPO output 7 LGPO7 Logic GPO output 8 LGPO8 Logic GPO output 1 LGPO9 Logic GPO output 2 LGPO10 Logic GPO output 3 LGPO11 Logic GPO output 4 LGPO12 Logic GPO output 5 GPIO1 General Purpose I/O 6 GPIO2 General Purpose I/O 7 GPIO3 General Purpose I/O 8 GPIO4 General Purpose I/O 1 PMBUS_ADDR0 PMBus address pin 2 PMBUS_ADDR1 PMBus address pin 3 PMBUS_ADDR2 PMBus address pin 4 SYNC_CLOCK Sync Clock pin 5 GPIO21 General Purpose I/O 6 GPIO22 General Purpose I/O 7 GPIO23 General Purpose I/O 8 GPIO24 General Purpose I/O 1 GPIO13 General Purpose I/O 2 GPIO14 General Purpose I/O 3 GPIO15 General Purpose I/O 4 GPIO16 General Purpose I/O 5 GPIO17 General Purpose I/O 6 GPIO18 General Purpose I/O 7 GPIO19 General Purpose I/O 8 GPIO20 General Purpose I/O J7 J8 J9 J10 SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 7 Test Setup www.ti.com Table 2. Connector Definition (continued) Connectors Pins Name Description J11 1 GPIO5 General Purpose I/O 2 GPIO6 General Purpose I/O 3 GPIO7 General Purpose I/O 4 GPIO8 General Purpose I/O 5 GPIO9 General Purpose I/O 6 GPIO10 General Purpose I/O 7 GPIO11 General Purpose I/O 8 GPIO12 General Purpose I/O J12 1 No connection 2 No connection 3 No connection 4 5 J13 No connection +3V3_USB 3.3-V power provided by USB Interface Adapter EVM 6 GND PMBus GND 7 PMB_CTRL PMBus CONTROL line 8 PMB_ALERT PMBus ALERT# line 9 PMB_SCL PMBus Clock 10 PMB_SDA PMBus Data 1 JTAG_TMS 2 3 JTAG_TDI JTAG TDIS (unused) 5 JTAG VTRef (unused) JTAG KEY 7 JTAG_TDO 8 GND 9 JTAG TDO JTAG GND JTAG RTCK (unused) 10 GND 11 JTAG_TCK JTAG TCK 12 GND JTAG GND 13 JTAG GND JTAG EMU0 (unused) 14 8 JTAG TDI 4 6 J14 JTAG TMS JTAG nTRST (unused) JTAG EMU1 (unused) 1 MON1 Analog monitor input 2 MON2 Analog monitor input 3 MON3 Analog monitor input 4 MON4 Analog monitor input 5 MON5 Analog monitor input 6 MON6 Analog monitor input 7 MON7 Analog monitor input 8 MON8 Analog monitor input UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback Test Setup www.ti.com Table 2. Connector Definition (continued) Connectors Pins Name Description J15 1 MON9 Analog monitor input 2 MON10 Analog monitor input 3 MON11 Analog monitor input 4 MON12 Analog monitor input 5 MON13 Analog monitor input 6 MON14 Analog monitor input 7 MON15 Analog monitor input 8 MON16 Analog monitor input 1 MON17 Analog monitor input 2 MON18 Analog monitor input 3 MON19 Analog monitor input 4 MON20 Analog monitor input 5 MON21 Analog monitor input 6 MON22 Analog monitor input 7 MON23 Analog monitor input 8 MON24 J16 J17 J18 J19 Analog monitor input 1 Pullup/pulldown signal (can be used as GPI input) 2 Pullup/pulldown signal (can be used as GPI input) 3 Pullup/pulldown signal (can be used as GPI input) 4 Pullup/pulldown signal (can be used as GPI input) 5 Pullup/pulldown signal (can be used as GPI input) 6 Pullup/pulldown signal (can be used as GPI input) 7 Pullup/pulldown signal (can be used as GPI input) 8 Pullup/pulldown signal (can be used as GPI input) 1 Pullup/pulldown signal (can be used as GPI input) 2 Pullup/pulldown signal (can be used as GPI input) 3 Pullup/pulldown signal (can be used as GPI input) 4 Pullup/pulldown signal (can be used as GPI input) 5 Pullup/pulldown signal (can be used as GPI input) 6 Pullup/pulldown signal (can be used as GPI input) 7 Pullup/pulldown signal (can be used as GPI input) 8 Pullup/pulldown signal (can be used as GPI input) 1 Pullup/pulldown signal (can be used as GPI input) 2 Pullup/pulldown signal (can be used as GPI input) 3 Pullup/pulldown signal (can be used as GPI input) 4 Pullup/pulldown signal (can be used as GPI input) 5 Pullup/pulldown signal (can be used as GPI input) 6 Pullup/pulldown signal (can be used as GPI input) 7 Pullup/pulldown signal (can be used as GPI input) 8 Pullup/pulldown signal (can be used as GPI input) SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 9 Test Setup www.ti.com Table 2. Connector Definition (continued) Connectors Pins J20 1 Pullup/pulldown signal (can be used as GPI input) 2 Pullup/pulldown signal (can be used as GPI input) 3 Pullup/pulldown signal (can be used as GPI input) 4 Pullup/pulldown signal (can be used as GPI input) 5 Pullup/pulldown signal (can be used as GPI input) 6 Pullup/pulldown signal (can be used as GPI input) 7 Pullup/pulldown signal (can be used as GPI input) 8 Pullup/pulldown signal (can be used as GPI input) J21 1 Name VDD 2 J22 3 GND 1 VDD VDD (connect to Pin2 to pullup) 3 GND GND (connect to Pin2 to pulldown) 1 VDD VDD (connect to Pin2 to pullup) Floating pin connected to PMBUS_ADDR2 through 1-k resistor 3 GND GND (connect to Pin2 to pulldown) 1 +3V3_USB 3.3-V power provided by USB Interface Adapter EVM 2 +3V3 3.3V rail to power VDD 1 5V_VIN 5-V input power positive terminal 2 GND 5-V input power negative terminal 1 5V_VIN 5-V input power positive terminal 2 GND 5-V input power negative terminal J27 1 POL_Margin Connect this pin to a MARGIN pin to test margining function. J28 1 +3V3 +3V3 rail (connect to Pin2 to pullup) 2 POL_EN J25 J26 POL enable 3 Input from J29 (connect to Pin2 to control POL enable) J29 1 Connect this pin to an EN pin to test enable function. J30 1 POL_VOUT J31 1 +3V3 Connect to Pin2 to pullup 2 DIO_01 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_02 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown J32 J33 J34 J35 10 GND (connect to Pin2 to pulldown) Floating pin connected to PMBUS_ADDR1 through 1-k resistor 2 J24 VDD (connect to Pin2 to pullup) Floating pin connected to PMBUS_ADDR0 through 1-k resistor 2 J23 Description Connect this pin to a MON pin to test margining function. 1 +3V3 Connect to Pin2 to pullup 2 DIO_03 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_04 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_05 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback Test Setup www.ti.com Table 2. Connector Definition (continued) Connectors Pins Name Description J36 1 +3V3 Connect to Pin2 to pullup 2 DIO_06 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_07 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_08 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_09 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_10 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown J37 J38 J39 J40 J41 J42 J43 J44 J45 J46 J47 J48 J49 J50 1 +3V3 Connect to Pin2 to pullup 2 DIO_11 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_12 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_13 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_14 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_15 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_16 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_17 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_18 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_19 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_20 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 11 Test Setup www.ti.com Table 2. Connector Definition (continued) Connectors Pins Name Description J51 1 +3V3 Connect to Pin2 to pullup 2 DIO_21 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_22 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_23 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_24 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_25 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown J52 J53 J54 J55 J56 J57 J58 J59 J60 J61 J62 12 1 +3V3 Connect to Pin2 to pullup 2 DIO_26 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_27 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_28 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_29 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_30 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_31 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown 1 +3V3 Connect to Pin2 to pullup 2 DIO_32 Floating pin to create a digital signal (high or low) 3 GND Connect to Pin2 to pulldown UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback Test Setup www.ti.com 5.4 Test Points Table 3. Test Point Functions 6 Test Points Name Description TP1 GND Ground TP2 GND Ground TP3 GND Ground TP4 GND Ground TP5 GND Ground TP6 GND Ground TP7 GND Ground TP8 POL_VOUT POL output voltage TP9 GND Ground TP10 PMB_SDA PMBus Data TP11 PMB_CTRL PMBus CONTROL line TP12 PMB_SCL PMBus Clock TP13 PMB_ALERT PMBus ALERT# line TP14 RESET UCD90240 reset pin signal Software Setup Accessing the UCD90240EVM-704's configuration, control, and monitoring capabilities with the Fusion Digital Power Designer software tool requires a onetime software setup per host system. 6.1 Fusion Digital Power Designer Software (Fusion GUI) Installation Place the Fusion Digital Power Designer Software (Fusion GUI) Installer executable file in a known location on the host computer to be used for EVM configuration/test. Double click the TI-Fusion-Digital-Power-Designer-2.0.xxx.exe file and proceed through the installation by accepting the installer prompts and the license agreement. Use the Fusion GUI installer's suggested default installation locations to complete the install. When the Fusion GUI installation reaches the finished window, uncheck the Launch Application check box and close the window. SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 13 Test Procedure 7 www.ti.com Test Procedure The UCD90240EVM-704_Default_Configuration.xml file is found in the SLVC613 zip file on the TI website and is provided to allow the user to return the EVM to its originally configured state. Connect the EVM as shown in Figure 2: UCD90240 Recommended Test Setup. Apply the input voltage to the test setup. Open the Fusion Digital Power Designer GUI by navigating to the Start Texas Instruments Fusion Digital Power Designer Fusion Digital Power Designer (not the offline version which would have monitoring disabled). At the default Configuration Screen select the File Import Project and the Project Open Wizard window will open. Open the default configuration file (UCD90240EVM704_Default_Configuration.xml) and click Next. Follow the prompt to download the configuration file. 7.1 Voltage Monitoring Example In the default configuration file, all MON pins are assigned to corresponding rails. Apply an external voltage within the specification in Table 1 to a MON pin. The voltage applied on the MON pin will be displayed in the Fusion GUI Monitor page. 7.2 Rail Enable Example In the default configuration file, all EN pins are assigned to corresponding rails, and all rails are controlled by CONTROL pin. The pin assignments are shown in Fusion GUI Configure pagePin Assignment tab. The CONTROL pin status can be controlled in Fusion GUI Monitor page. Turn on the CONTROL Line in the Monitor page. Observe that all LEDs attached to EN pins are lit. 7.3 Fault Log Example (Including Blackbox Log) Make sure the EN pin of a rail is asserted. Adjust the external voltage applied to the rail's MON pin such that the voltage is above Power Good On threshold and below OV Warn/Fault thresholds. In the Status page, click the Clear Faults button, Clear Logged Faults button, and Clear Blackbox Log button. Adjust the external voltage applied to the MON pin such that the voltage is above OV fault threshold. In the Status page Status Registers tab, observe that the Vout OV Fault of the corresponding rail is raised. In the Logged Faults tab, observe that the Vout OV Fault of the corresponding rail is also raised. In the Blackbox Info tab, click Refresh Blackbox Log button. Observe that the fault information and all the GPI/GPO/Rail statuses when the fault occurred were recorded in the Blackbox Log. 7.4 Command GPO Example In the default configuration file, 12 GPIO pins are configured as command GPO. In the Configure page Pin Assignment tab, change the Command GPO states and then click the Write to Hardware button. Observe the LED of the corresponding GPO pin changes state. 7.5 Configurable Pullup/Pulldown Signals The UCD90240EVM-704 provides 32 configurable pullup/pulldown signals. The output pins of the pullup/pulldown signals are located in J17, J18, J19, and J20. Each pin is connected to 3.3 V or GND through a 680- resistor. The state of each pin can be configured by a 3-pin header next to it. The pullup/pulldown signals can be used as GPI pin input signals and pull up for open-drain GPO pins. 7.6 GPI and Logic GPO Example In the default configuration file, 12 GPIO pins are configured as GPI pin with GPI Fault feature enabled. Each of the 12 LGPO pins is configured to follow a corresponding GPI signal with a 960-ms time delay. The pin assignments are shown in the Configure page Pin Assignment tab. Connect a logic input signal to a GPI pin. Observe that the LED of the corresponding LGPO pin is lit after 960 ms. Also observe that the corresponding GPI Fault is logged in the Status page. Disconnect the logic input signal from the GPI pin. Observe that the LED of the corresponding LGPO pin is out after 960 ms. 14 UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback Test Procedure www.ti.com 7.7 Margin Example In the default configuration file, all 24 rails are configured with the margining function. The pin assignments are shown in the Configure pagePin Assignment tab. Connect the onboard POL output voltage (J30) to a rail's MON pin using a jumper wire. Then connect the rail's MARGIN pin to the onboard POL's margin input (J27) to close the margin loop. Connect the rail's EN pin to J29 which controls the onboard POL's enable signal. Connect J28's Pin 2 and Pin 3 using a shunt jumper. In the Fusion GUI Monitor page, turn on the CONTROL line. Observe that the rail's EN pin LED is lit, and the onboard POL is enabled. The POL's output voltage is monitored in the Monitor page, which should be at 1.2 V. In the Fusion GUI Monitor page, click to change the margin status to Low. Observe that the POL output voltage is regulated at Margin Low level defined in the Configure page Vout Config tab. Click to change the margin status to High. Observe that the POL output voltage is regulated at Margin High level. 7.8 7.8.1 Cascading Example Sync Clock Sync Clock can synchronize multiple UCD90240 devices such that they respond to the same GPI event synchronously and the same GPI event has the same time stamp in all synchronized UCD90240 devices. The Sync Clock I/O pin is located in J9. Implementing the Sync Clock feature requires two or more UCD90240EVM-704 boards. In the Fusion GUI Configure page Other Config tab, configure one EVM board as Sync Clock master, and all other boards as slaves. Connect the multiple EVM boards to the same ground. Connect all Sync Clock pins to the same node. Observe that the synchronized UCD90240 devices respond to the same GPI event synchronously. When the Sync Clock pin is not used, configure the UCD90240 device as Sync Clock master. 7.8.2 Fault Pin Multiple UCD90240 devices can be acknowledged on the same rail fault and react accordingly, even if the rail is monitored by only one UCD90240 device. This is achieved by the Fault Pin feature. In each UCD90240 device, up to 4 GPI pins can be configured as Fault Pins. Each Fault Pin is connected to a Fault Bus. Each Fault Bus is pulled up to 3.3 V by a 10-k resistor. When there is no fault on a Fault Bus, the Fault Pins are GPI pins and listen to the Fault Bus. When a rail fault is detected by a UCD90240 device, the corresponding Fault Pin is turned into active driven low state, pulling down the Fault Bus and informing all other UCD90240 devices of the corresponding fault. Refer to the UCD90240 datasheet for configuration and connection examples. The Fault Pin feature and the Sync Clock feature can work together to achieve better synchronized faultresponse performance. SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 15 EVM Assembly Drawing and PCB Layout 8 www.ti.com EVM Assembly Drawing and PCB Layout Figure 3 and Figure 4 illustrate the EVM assembly drawings and PCB layouts. Figure 3. UCD90240EVM-704 Top Assembly Drawing Figure 4. UCD90240EVM-704 Bottom Assembly Drawing 16 UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback EVM Assembly Drawing and PCB Layout www.ti.com Figure 5 illustrates the UCD90240EVM-704 fabrication drawing. Figure 5. UCD90240EVM-704 Fabrication Drawing SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 17 EVM Assembly Drawing and PCB Layout www.ti.com Figure 6 through Figure 17 illustrate the UCD90240EVM-704 PCB drawings. Figure 6. UCD90240EVM-704 Top Overlay Figure 7. UCD90240EVM-704 Top Solder Mask 18 UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback EVM Assembly Drawing and PCB Layout www.ti.com Figure 8. UCD90240EVM-704 Top Layer Figure 9. UCD90240EVM-704 Midlayer 1 SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 19 EVM Assembly Drawing and PCB Layout www.ti.com Figure 10. UCD90240EVM-704 Midlayer 2 Figure 11. UCD90240EVM-704 Midlayer 3 20 UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback EVM Assembly Drawing and PCB Layout www.ti.com Figure 12. UCD90240EVM-704 Midlayer 4 Figure 13. UCD90240EVM-704 Bottom Layer SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 21 EVM Assembly Drawing and PCB Layout www.ti.com Figure 14. UCD90240EVM-704 Bottom Solder Mask Figure 15. UCD90240EVM-704 Bottom Overlay 22 UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback EVM Assembly Drawing and PCB Layout www.ti.com Figure 16. UCD90240EVM-704 Drill Drawing Figure 17. UCD90240EVM-704 Board Dimensions SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 23 Bill of Materials (BOM) 9 www.ti.com Bill of Materials (BOM) Table 4. UCD90240EVM-704 Bill of Materials Designator Qty Value Description Package Reference Part Number Manufacturer C1, C3, C18-C20 5 0.01uF CAP, CERM, 0.01 F, 16 V, 10%, X7R, 0402 0402 C1005X7R1C103K TDK C2, C9-C11, C21-C24 8 0.1uF CAP, CERM, 0.1 F, 6.3 V, 10%, X5R, 0402 0402 C1005X5R0J104K TDK C4, C7, C8, C12-C14, C16, C25, C26 9 1uF CAP, CERM, 1 F, 25 V, 10%, X5R, 0603 0603 C1608X5R1E105K080AC TDK C5 1 1000pF CAP, CERM, 1000pF, 50V, 5%, X7R, 0603 0603 C0603C102J5RACTU Kemet C15, C27 2 10uF CAP, CERM, 10 F, 6.3 V, 10%, X6S, 0805 0805 GRM219C80J106KE39D Murata C17 1 0.01uF CAP, CERM, 0.01 F, 50 V, 5%, X7R, 0603 0603 C0603C103J5RACTU Kemet C28, C32 2 0.1uF CAP, CERM, 0.1 F, 16 V, 10%, X5R, 0402 0402 GRM155R61C104KA88D Murata C29-C31 3 22uF CAP, CERM, 22 F, 6.3 V, 20%, X5R, 0805 0805 GRM21BR60J226ME39L Murata C33 1 1000pF CAP, CERM, 1000 pF, 50 V, 5%, X7R, 0603 0603 C0603C102J5RACTU Kemet C34-C37 4 22uF CAP, CERM, 22 F, 6.3 V, 20%, X5R, 0603 0603 C1608X5R0J226M080AC TDK C38 1 2700pF CAP, CERM, 2700 pF, 50 V, 10%, X7R, 0402 0402 GRM155R71H272KA01D Murata D1-D84 84 Green LED, Green, SMD 1.7x0.65x0.8mm LG L29K-G2J1-24-Z OSRAM D85, D86 2 Green LED, Green, SMD LED_0805 LTST-C171GKT Lite-On D87 1 Red LED, Red, SMD LED_0805 LTST-C170KRKT Lite-On H9, H10, H11, H12 4 Bumpon, Hemisphere, 0.44 X 0.20, Clear Transparent Bumpon SJ-5303 (CLEAR) 3M J1-J11, J14-J20 18 Header, 100mil, 8x1, Tin, TH Header, 8x1, 100mil, TH PEC08SAAN Sullins Connector Solutions J12 1 Header (shrouded), 100mil, 5x2, Gold, TH TH, 10-Leads, Body 8.5x20mm, Pitch 2.54mm XG4C-1031 Omron Electronic Components J13 1 Header (shrouded), 100mil, 7x2, Gold, TH 7x2 Header N2514-6002-RB 3M J21-J23, J28, J31-J62 36 Header, 100mil, 3x1, Tin, TH Header, 3 PIN, 100mil, Tin PEC03SAAN Sullins Connector Solutions J24 1 Header, 100mil, 2x1, Tin, TH Header, 2 PIN, 100mil, Tin PEC02SAAN Sullins Connector Solutions J25 1 Power Jack, mini, 2.5mm OD, R/A, TH Jack, 14.5x11x9mm RAPC712X Switchcraft J26 1 TERMINAL BLOCK 5.08MM VERT 2POS, TH TERM_BLK, 2pos, 5.08mm ED120/2DS On-Shore Technology J27, J29, J30 3 Header, 1x1, Tin, TH Header, 1x1 PEC01SAAN Sullins Connector Solutions L1 1 1uH Inductor, Shielded, Ferrite, 1 H, 12 A, 0.0072 , SMD Inductor, 7.2x4x6.5mm SRP6540-1R0M Bourns Q1, Q2 2 60V MOSFET, N-CH, 60 V, 0.17 A, SOT-23 SOT-23 2N7002-7-F Diodes Inc. R1, R10, R39, R40 4 4.7k RES, 4.7 k, 5%, 0.1 W, 0603 0603 CRCW06034K70JNEA Vishay-Dale R2, R133, R136 3 330 RES, 330, 5%, 0.1 W, 0603 0603 CRCW0603330RJNEA Vishay-Dale R3 1 0.1 RES, 0.1, 1%, 0.1 W, 0603 0603 ERJ-3RSFR10V Panasonic R4 1 1.0 RES, 1.0, 5%, 0.1 W, 0603 0603 CRCW06031R00JNEA Vishay-Dale R5-R8 4 680 RES, 680, 5%, 0.0625 W, Resistor Array - 8x1 Resistor Array - 8x1 EXB-2HV681JV Panasonic R9 1 0 RES, 0, 5%, 0.1 W, 0603 0603 ERJ-3GEY0R00V Panasonic R11-R13 3 1.0k RES, 1.0 k, 5%, 0.1 W, 0603 0603 RC0603JR-071KL Yageo America 24 UCD90240EVM-704 24-Rail Sequencer Development Board Alternate Part Number Alternate Manufacturer - - None SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback Copyright (c) 2015, Texas Instruments Incorporated Bill of Materials (BOM) www.ti.com Table 4. UCD90240EVM-704 Bill of Materials (continued) Alternate Part Number Alternate Manufacturer Texas Instruments UCD90240ZRBT Texas Instruments REF5030AIDGKT Texas Instruments Equivalent None RTE0016F TPS54678RTER Texas Instruments TPS54678RTET Texas Instruments Single Output Low Noise LDO, 400 mA, Fixed 3.3 V Output, 1.7 to 5.5 V Input, with Reverse Current Protection, 8-pin SON (DRB), -40C to 85C, Green (RoHS & no Sb/Br) DRB0008A TPS73633DRBR Texas Instruments Equivalent None Single Inverter Gate, DBV0005A DBV0005A SN74LVC1G04DBVR Texas Instruments SN74LVC1G04DBVT Texas Instruments CAP, CERM, 22 pF, 50 V, 5%, C0G/NP0, 0402 0402 GRM1555C1H220JA01D Murata Alternate Part Number Alternate Manufacturer Designator Qty Value Description Package Reference Part Number Manufacturer R14, R41-R123 84 1.65k RES, 1.65 k, 1%, 0.1 W, 0603 0603 RC0603FR-071K65L Yageo America R15-R38 24 200 RES, 200, 0.1%, 0.1 W, 0603 0603 RG1608P-201-B-T5 Susumu Co Ltd R124 1 0 RES, 0, 5%, 0.063 W, 0402 0402 CRCW04020000Z0ED Vishay-Dale R125 1 40.2 RES, 40.2, 1%, 0.1 W, 0603 0603 RC0603FR-0740R2L Yageo America R126, R129 2 10k RES, 10 k, 5%, 0.063 W, 0402 0402 CRCW040210K0JNED Vishay-Dale R127, R128 2 20.0k RES, 20.0 k, 1%, 0.063 W, 0402 0402 CRCW040220K0FKED Vishay-Dale R130 1 97.6k RES, 97.6 k, 1%, 0.1 W, 0603 0603 RC0603FR-0797K6L Yageo America R131 1 100k RES, 100 k, 1%, 0.1 W, 0603 0603 CRCW0603100KFKEA Vishay-Dale R132 1 82.5k RES, 82.5 k, 1%, 0.063 W, 0402 0402 CRCW040282K5FKED Vishay-Dale R134, R135 2 30.1k RES, 30.1 k, 1%, 0.1 W, 0603 0603 RC0603FR-0730K1L Yageo America S1 1 Switch, Tactile, SPST-NO, 1VA, 32V, SMT Switch, 6.3x5.36x6.6 mm, SMT KT11P2JM34LFS C&K Components TP1-TP7 7 SMT Test Point, Compact, SMT Testpoint_Keystone_Compact 5016 Keystone TP8 1 Red Test Point, Multipurpose, Red, TH Red Multipurpose Testpoint 5010 Keystone TP9 1 Black Test Point, Miniature, Black, TH Black Miniature Testpoint 5001 Keystone TP10-TP14 5 Yellow Test Point, Miniature, Yellow, TH Yellow Miniature Testpoint 5004 Keystone U1 1 24-Rail PMBus Power Sequencer and Power Manager, ZRB0157A ZRB0157A UCD90240ZRBR U2 1 Low Noise, Very Low Drift, Precision Voltage Reference, -40C to 125C, 8-pin MSOP (DGK), Green (RoHS & no Sb/Br) DGK0008A U3 1 2.95 V to 6 V Input, 6 A Output, 2 MHz, Synchronous Step DOWN Switcher With Integrated FET ( SWIFTTM), RTE0016F U4 1 U5 1 C6 0 FID1- FID6 DNP Fiducial mark. There is nothing to buy or mount. N/A N/A N/A Quantity 0 Value Description Package Reference Part Number Manufacturer 2.93780573 0.01uF CAP, CERM, 0.01 F, 16 V, 10%, X7R, 0403 0402 C1005X7R1C103K TDK 2.809618195 0.1uF CAP, CERM, 0.1 F, 6.3 V, 10%, X5R, 0403 0402 C1005X5R0J104K TDK NOTE: Unless otherwise noted in the Alternate Part Number and/or Alternate Manufacturer columns, all parts may be substituted with equivalents. SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 25 UCD90240EVM-704 Schematics 10 www.ti.com UCD90240EVM-704 Schematics Figure 18 through Figure 23 illustrate the UCD90240EVM-704 schematics. R115 1.65k R109 1.65k R42 1.65k R119 1.65k R14 1.65k R70 1.65k R88 1.65k D29 D30 D31 D32 D33 D34 Green Green Green Green Green Green D13 R91 1.65k D14 Green GND GND GND GND GND R98 1.65k D15 Green R123 1.65k D16 Green R97 1.65k D17 R122 1.65k D18 Green Green Green GND U1A GND J13 MARGIN 01 L5 MARGIN 02 D8 MARGIN 03 K6 MARGIN 04 D4 MARGIN 05 E4 MARGIN 06 R75 1.65k D35 R94 1.65k R78 1.65k R85 1.65k F5 MARGIN 07 R110 1.65k N5 MARGIN 08 N6 MARGIN 09 D37 D36 R118 1.65k D38 D39 Green Green Green Green GND GND GND Green M6 MARGIN 11 L6 GND GND D11 MARGIN 13 C12 MARGIN 14 A13 MARGIN 15 B13 MARGIN 16 D12 MARGIN 17 C13 MARGIN 18 E12 MARGIN 19 E13 MARGIN 20 R52 1.65k R44 1.65k R56 1.65k R59 1.65k R45 1.65k R53 1.65k M13 MARGIN 21 L12 MARGIN 22 D42 D41 Green Green D43 Green D44 Green MRGN2 EN2 MRGN3 EN3 MRGN4 EN4 MRGN5 EN5 MRGN6 EN6 MRGN7 EN7 MRGN8 EN8 MRGN9 EN9 M9 D45 Green D46 M5 MARGIN 23 J12 MARGIN 24 Green MRGN10 EN10 MRGN11 EN11 MRGN12 EN12 MRGN13 EN13 MRGN14 EN14 MRGN15 EN15 MRGN16 EN16 MRGN17 EN17 MRGN18 EN18 MRGN19 EN19 MRGN20 EN20 MRGN21 EN21 MRGN22 EN22 MRGN23 EN23 MRGN24 EN24 GND GND GND GND GND EN1 N9 EN2 L10 EN3 K10 EN4 L9 EN5 K9 EN6 N8 EN7 M8 R92 1.65k EN8 L8 R87 1.65k R96 1.65k R93 1.65k R121 1.65k R86 1.65k EN9 D19 K5 MARGIN 12 GND EN1 D40 MARGIN 10 Green MRGN1 K8 D20 D21 D22 D23 D24 EN10 N7 M7 Green Green Green EN11 Green Green Green EN12 K7 EN13 L7 GND GND GND GND GND GND EN14 N4 EN15 N3 EN16 K3 EN17 K4 EN18 J4 EN19 J2 EN20 J3 R120 1.65k EN21 H4 R95 1.65k R79 1.65k R80 1.65k R116 1.65k R117 1.65k EN22 H3 EN23 G4 D25 D26 D27 D28 D84 D83 EN24 Green Green Green Green Green Green UCD90240ZRBR GND GND GND GND GND GND GND R71 1.65k D47 Green GND R72 1.65k D48 Green R83 1.65k D49 Green GND GND R100 1.65k R106 1.65k R114 1.65k R113 1.65k R111 1.65k R112 1.65k R65 1.65k R66 1.65k D50 D51 D52 D82 D81 D80 D79 D78 Green Green Green Green Green Green Green Green GND GND GND GND GND GND GND GND GND GND GND GND GND R68 1.65k D77 Green GND Figure 18. UCD90240EVM Schematic (1 of 6) 26 UCD90240EVM-704 24-Rail Sequencer Development Board SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback Copyright (c) 2015, Texas Instruments Incorporated UCD90240EVM-704 Schematics www.ti.com R108 1.65k D5 Green R82 1.65k R105 1.65k R81 1.65k D6 D7 D8 Green Green Green R74 1.65k R73 1.65k D60 D59 Green Green U1B GND GND GND GND GND L4 GPIO1 N1 GPIO2 M4 GPIO3 N2 GPIO4 F4 GPIO5 R67 1.65k R43 1.65k R99 1.65k R89 1.65k R90 1.65k R84 1.65k F3 GPIO6 G3 GPIO7 D58 D57 D56 Green Green D55 Green D54 Green D53 L11 GPIO9 Green Green D10 GPIO8 N12 GPIO10 GND GND GND GND GND N11 GPIO11 GND M11 GPIO12 F13 GPIO13 F12 GPIO14 G11 GPIO15 H10 GPIO16 R77 1.65k R76 1.65k R69 1.65k R64 1.65k R61 1.65k R62 1.65k H13 GPIO17 H12 GPIO18 D68 Green D67 Green D66 Green D65 Green D64 Green D63 H11 GPIO19 L13 GPIO20 Green B11 GPIO21 GND GND GND GND GND B12 GPIO22 GND C11 GPIO23 A12 GPIO24 R57 1.65k R50 1.65k GND GPIO1 LGP O1 GPIO2 LGP O2 GPIO3 LGP O3 GPIO4 LGP O4 GPIO5 LGP O5 GPIO6 LGP O6 GPIO7 LGP O7 GPIO8 LGP O8 GPIO9 LGP O9 GPIO10 LGP O10 GPIO11 LGP O11 GPIO12 LGP O12 C9 R54 1.65k R49 1.65k R41 1.65k R47 1.65k LGPO1 B9 LGPO2 A9 D76 D75 D74 D73 D72 D71 Green Green LGPO3 C8 LGPO4 D5 Green Green Green Green LGPO5 C5 GND LGPO6 C6 GND GND GND GND GND LGPO7 C4 LGPO8 L3 LGPO9 M1 LGPO10 M2 LGPO11 M3 LGPO12 GPIO13 R48 1.65k GPIO14 R46 1.65k R107 1.65k R102 1.65k R103 1.65k R104 1.65k GPIO15 D69 D70 GPIO16 GPIO17 Green Green D2 D1 Green Green D3 Green D4 Green GPIO18 GPIO19 SYNC_CLK K2 SYNC_CLOCK GND GND GND GND GND GND GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 UCD90240ZRBR R63 1.65k D62 Green GND R101 1.65k D9 D61 Green R60 1.65k Green GND R58 1.65k D10 Green GND GND R51 1.65k D11 Green R55 1.65k D12 Green GND GND Figure 19. UCD90240EVM Schematic (2 of 6) SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 27 UCD90240EVM-704 Schematics www.ti.com VDD U1C MON1 R15 200 E2 R16 200 E1 MON2 MON3 MON4 MON5 R17 200 F2 R18 200 F1 R19 200 B3 R20 200 A3 R21 200 B4 MON6 MON7 MON8 MON9 MON10 MON11 MON12 R22 200 A4 R23 200 B5 R24 200 A5 R25 200 B6 R26 200 A6 MON1 MON13 MON2 MON14 MON3 MON15 MON4 MON16 MON5 MON17 MON6 MON18 MON7 MON19 MON8 MON20 MON9 MON21 MON10 MON22 MON11 MON23 MON12 MON24 C1 R27 200 C2 R28 200 B1 R29 200 B2 R30 200 G2 R31 200 G1 R32 200 H1 R33 200 H2 R34 200 B7 R35 200 A7 R36 200 B8 R37 200 A8 R38 200 TP10 MON13 PMB_SDA MON14 TP12 J21 PMB_SCL U1D E10 PMB_SCL MON15 MON16 TP11 PMB_CTRL MON18 PMB_ALERT MON20 PMBUS_ADDR1 MON21 PMBUS_ADDR2 D2 J22 PMBUS_ADDR0 PMBUS_ADDR1 K1 PMBUS_ADDR2 UNUSED-NC UNUSED-NC UNUSED-NC UNUSED-NC MON22 MON23 JTAG_TMS MON24 JTAG_TDO A10 JTAG_TMS A11 VREF/VREFA+ UNUSED-DVSS UNUSED-DVSS UNUSED-DVSS UNUSED-DVSS JTAG_TDI C10 JTAG_TCK 1.0k A2 G13 M12 N10 GND VDD J23 JTAG_TDO B10 1 2 3 R12 PMBUS_ADDR1 L1 JTAG_TDI D1 GND VDD PMBUS_CNTRL L2 PMBUS_ADDR0 K12 1.0k PMBALERT E11 PMB_CTRL MON19 UNUSED-V33D 1 2 3 R11 PMBUS_ADDR0 PMBUS_DATA F11 PMB_ALERT MON17 PMBUS_CLK D13 PMB_SDA TP13 VDD JTAG_TCK G12 K11 M10 N13 1 2 3 R13 PMBUS_ADDR2 1.0k AVSS/VREFA- UCD90240ZRBR UCD90240ZRBR GND GND +3V0_VREF VDD U2A 6 5 4 C1 0.01F C2 0.1F C15 10F C7 1F VOUT TRIM/NR GND VIN VDD 2 TEMP 3 VDDA R4 +3V3 C4 C8 1F 1.0 R3 REF5030AIDGKT 1F C9 0.1 GND U2B NC DNC DNC C19 0.01F 7 1 8 C20 0.01F C21 0.1F C22 0.1F C23 0.1F C24 0.1F C25 1F C26 1F 0.1F C3 REF5030AIDGKT GND 0.01F GND GND U1E D3 TP1 TP2 TP3 TP4 TP5 TP6 TP7 D7 E6 E8 E9 F10 J7 J9 J10 VDDC GND C10 0.1F C11 0.1F C12 1F C13 1F C14 1F D6 J1 J6 K13 G10 V33A V33D V33D V33D V33D V33D V33D V33D V33D AVSS AVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS BPCAP BPCAP BPCAP BPCAP RESET C3 E3 A1 C7 D9 E5 F9 H5 H9 J5 J8 J11 GND VDD GND UCD90240ZRBR R1 4.7k TARGETTRSTn TP14 RESET 1 4 C5 1000pF S1 2 3 GND GND Figure 20. UCD90240EVM Schematic (3 of 6) 28 UCD90240EVM-704 24-Rail Sequencer Development Board SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback Copyright (c) 2015, Texas Instruments Incorporated UCD90240EVM-704 Schematics www.ti.com 1 2 3 4 5 6 7 8 MARGIN MARGIN MARGIN MARGIN MARGIN MARGIN MARGIN MARGIN 1 2 3 4 5 6 7 8 01 02 03 04 05 06 07 08 J1 1 2 3 4 5 6 7 8 EN1 EN2 EN3 EN4 EN5 EN6 EN7 EN8 J4 1 2 3 4 5 6 7 8 MARGIN MARGIN MARGIN MARGIN MARGIN MARGIN MARGIN MARGIN J7 1 2 3 4 5 6 7 8 09 10 11 12 13 14 15 16 J2 MARGIN MARGIN MARGIN MARGIN MARGIN MARGIN MARGIN MARGIN 1 2 3 4 5 6 7 8 J3 1 2 3 4 5 6 7 8 J6 PMBUS_ADDR0 PMBUS_ADDR1 PMBUS_ADDR2 SYNC_CLOCK GPIO21 GPIO22 GPIO23 GPIO24 MON17 MON18 MON19 MON20 MON21 MON22 MON23 MON24 J16 1 2 3 4 5 6 7 8 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 J11 EN17 EN18 EN19 EN20 EN21 EN22 EN23 EN24 1 2 3 4 5 6 7 8 MON1 MON2 MON3 MON4 MON5 MON6 MON7 MON8 J14 1 2 3 4 5 6 7 8 LGPO9 LGPO10 LGPO11 LGPO12 GPIO1 GPIO2 GPIO3 GPIO4 J8 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 J10 EN9 EN10 EN11 EN12 EN13 EN14 EN15 EN16 J5 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 LGPO1 LGPO2 LGPO3 LGPO4 LGPO5 LGPO6 LGPO7 LGPO8 MON9 MON10 MON11 MON12 MON13 MON14 MON15 MON16 J15 VDD Remove pin location 6 J12 PMB_CTRL PMB_SCL J9 1 3 5 7 9 2 4 6 8 10 J13 JTAG_TMS JTAG_TDI PMB_ALERT PMB_SDA R9 0 JTAG_TDO JTAG_TCK R39 4.7k 1 3 5 7 9 11 13 R40 4.7k GND R10 GND 4.7k 5V VIN 2 4 6 8 10 12 14 GND +3V3_USB J26 J24 +3V3 1 2 VDD VDD 4.5-5.5V GND R2 330 5V VIN J25 U4A 8 IN 5 3 2 OUT EN C16 1F NR 3 330 U5 GND 4 RAPC712X R133 330 R136 1 1 C27 10F 9 1 D86 C17 0.01F TPS73633DRBR Green PMB_ALERT 2 3 GND NC VCC 5 D87 D85 Red Green A GND Y SN74LVC1G04DBVR 4 R134 Q1 2N7002-7-F 30.1k R135 PMB_CTRL Q2 2N7002-7-F 30.1k U4B 2 6 7 NC NC NC GND GND GND GND GND TPS73633DRBR Figure 21. UCD90240EVM Schematic (4 of 6) SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 29 UCD90240EVM-704 Schematics www.ti.com +3V3 J31 R5 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 J17 9 10 11 12 13 14 15 16 DIO_01 DIO_02 DIO_03 DIO_04 DIO_05 DIO_06 DIO_07 DIO_08 1 2 3 DIO_01 J39 1 2 3 DIO_09 J32 680 1 2 3 DIO_02 J47 1 2 3 DIO_17 J40 1 2 3 DIO_10 J55 1 2 3 DIO_25 J48 1 2 3 DIO_18 J56 1 2 3 DIO_26 R6 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 J18 9 10 11 12 13 14 15 16 DIO_09 DIO_10 DIO_11 DIO_12 DIO_13 DIO_14 DIO_15 DIO_16 J33 1 2 3 DIO_03 J41 1 2 3 DIO_11 J49 1 2 3 DIO_19 J57 1 2 3 DIO_27 680 J34 1 2 3 DIO_04 J42 1 2 3 DIO_12 J50 1 2 3 DIO_20 J58 1 2 3 DIO_28 R7 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 J19 9 10 11 12 13 14 15 16 DIO_17 DIO_18 DIO_19 DIO_20 DIO_21 DIO_22 DIO_23 DIO_24 J35 1 2 3 DIO_05 J43 1 2 3 DIO_13 J51 1 2 3 DIO_21 J59 1 2 3 DIO_29 680 J36 1 2 3 DIO_06 J44 1 2 3 DIO_14 J52 1 2 3 DIO_22 J60 1 2 3 DIO_30 R8 1 2 3 4 5 6 7 8 J20 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 DIO_25 DIO_26 DIO_27 DIO_28 DIO_29 DIO_30 DIO_31 DIO_32 J37 1 2 3 DIO_07 J45 1 2 3 DIO_15 J53 1 2 3 DIO_23 J61 1 2 3 DIO_31 680 J38 1 2 3 DIO_08 GND J46 1 2 3 DIO_16 GND J54 1 2 3 DIO_24 GND J62 1 2 3 DIO_32 GND Figure 22. UCD90240EVM Schematic (5 of 6) 30 UCD90240EVM-704 24-Rail Sequencer Development Board SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback Copyright (c) 2015, Texas Instruments Incorporated UCD90240EVM-704 Schematics www.ti.com +3V3 J28 POL_EN 1 2 3 J29 To EN pin J30 POL_VOUT 5V VIN U3 1 2 16 C29 22F C30 22F C31 22F R126 10k C32 0.1F POL_EN 15 14 PGOOD 9 8 7 VIN VIN VIN BOOT PH PH PH EN PWRGD VSENSE SS/TR RT/CLK COMP AGND GND GND PAD 13 R124 0 10 11 12 C28 TP8 0.1F L1 1uH R125 40.2 12A 6 5 3 4 17 R127 20.0k C34 22F C35 22F C36 22F C37 22F GND R128 20.0k TPS54678RTER R129 10k R132 C18 0.01F 82.5k 500kHz C6 DNP R131 R130 100k 97.6k J27 POL_Margin C38 2700pF C33 1000pF TP9 GND Figure 23. UCD90240EVM Schematic (6 of 6) SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback UCD90240EVM-704 24-Rail Sequencer Development Board Copyright (c) 2015, Texas Instruments Incorporated 31 Revision History www.ti.com Revision History Changes from Original (March 2015) to A Revision ....................................................................................................... Page * * Changed input current to 135 mA in UCD90240EVM-704 Electrical Performance Specifications table....................... 3 Changed typo in device name in several figure titles. Corrected to UCD90240EVM-704. .................................... 16 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 32 Revision History SLVUAF3A - March 2015 - Revised March 2015 Submit Documentation Feedback Copyright (c) 2015, Texas Instruments Incorporated STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES 1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or documentation (collectively, an "EVM" or "EVMs") to the User ("User") in accordance with the terms and conditions set forth herein. Acceptance of the EVM is expressly subject to the following terms and conditions. 1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. 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Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as mandated by government requirements. TI does not test all parameters of each EVM. 2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM, or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day warranty period. 3 Regulatory Notices: 3.1 United States 3.1.1 Notice applicable to EVMs not FCC-Approved: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter. 3.1.2 For EVMs annotated as FCC - FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant: CAUTION This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. FCC Interference Statement for Class A EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER FCC Interference Statement for Class B EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: * * * * Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. 3.2 Canada 3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 Concerning EVMs Including Radio Transmitters: This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Concernant les EVMs avec appareils radio: Le present appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisee aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioelectrique subi, meme si le brouillage est susceptible d'en compromettre le fonctionnement. Concerning EVMs Including Detachable Antennas: Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. Concernant les EVMs avec antennes detachables Conformement a la reglementation d'Industrie Canada, le present emetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inferieur) approuve pour l'emetteur par Industrie Canada. Dans le but de reduire les risques de brouillage radioelectrique a l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnee equivalente (p.i.r.e.) ne depasse pas l'intensite necessaire a l'etablissement d'une communication satisfaisante. Le present emetteur radio a ete approuve par Industrie Canada pour fonctionner avec les types d'antenne enumeres dans le manuel d'usage et ayant un gain admissible maximal et l'impedance requise pour chaque type d'antenne. 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SPACER SPACER SPACER SPACER SPACER 1. 2. 3. 61118328173 3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page SPACER 4 EVM Use Restrictions and Warnings: 4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS. 4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling or using the EVM, including without limitation any warning or restriction notices. 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