MAX1121X Family Evaluation Kit General Description The evaluation kit (EV kit) demonstrates the MAX1121X family of 24-bit, 64ksps delta-sigma ADCs with integrated PGA. The EV kit includes a graphical user interface (GUI) that provides communication from the target device to the PC. The EV kit can operate in multiple modes: Evaluates: MAX11214/MAX11216 Features and Benefits High-Speed USB, FMC Connector, and PMOD Connector 5MHz SPI Interface Various Sample Sizes and Sample Rates 1) Standalone Mode: In "Standalone" mode, the EV kit is connected to the PC through a USB cable and performs a subset of the complete EV kit functions with limitation for sample rate and size. Collects Up to 1 Million Samples (with FPGA Platform) 2) FPGA Mode: In "FPGA" mode, the EV kit is connected to an Avnet ZedBoardTM through a low-pincount FMC connector. ZedBoard features a Xilinx(R) Zynq(R)-7000 SoC that connects to the PC through an Ethernet port, which allows the GUI to perform different operations with full control over mezzanine card functions. The EV kit with FPGA platform performs the complete suite of evaluation tests for the target IC Sync In and Sync Out for Coherent Sampling (with FPGA Platform) 3) User-Supplied SPI Mode: In addition to the USB and FMC interfaces, the EV kit provides two 12-pin PMOD-style headers for user-supplied SPI interface, to connect the signals for RDYB, SCLK, DIN, DOUT, and CSB. The EV kit includes Windows XP(R)-, Windows(R) 7 and Windows 8.1-compatible software to exercise the features of the IC. The EV kit GUI allows different sample sizes, adjustable sampling rates, on-board or external reference options, and graphing software that includes the FFT and histogram of the sampled signals with the ability to save plots in .jpg or .csv formats. The ZedBoard board accepts a +12V AC-DC wall adapter. The EV kit can be powered by the ZedBoard or by a local 12V supply. The EV kit has on-board transformers and digital isolators to separate the IC from the ZedBoard/ on-board processor. The MAX11214 EV kit comes installed with a MAX11214EUG+ in a 24-pin TSSOP package and the MAX11216 EV kit comes installed with a MAX11216EUG+ in a 24-pin TSSOP package. 19-7605; Rev 0; 4/15 Time Domain, Frequency Domain, and Histogram Plotting Save Plots as jpg, bmp or csv On-Board DAC (MAX542) for DC Signal-Level Generation On-Board Voltage Reference (MAX6126) Proven PCB Layout Fully Assembled and Tested Windows XP-, Windows 7-, and Windows 8.1-Compatible Software Savable ADC Configurations Ordering Information appears at end of data sheet. ZedBoard is a trademark of Avnet, Inc. Xilinx and Zynq are registered trademarks and Xilinx is a registered service mark of Xilinx, Inc. Windows and Windows XP are registered trademarks and registered service marks of Microsoft Corporation. Evaluates: MAX11214/MAX11216 MAX1121X Family Evaluation Kit MAX1121X EV Kit Photo System Block Diagram IN+ CH_A + MAX44241 ISOLATED DC-DC + CH_B MAX11214/216 ADC U25 DAC_OUT+ ADC_REFP CH_C + MAX44241 ADC_INN + EXT_REFP MAX44241 CH_D EXT_REFN DAC_OUT- IN- SCLK_ADC ADC_INP MAX44241 RDYB_ADC DOUT_ADC DIN_ADC ADC_REFP SCLK_DAC DAC_OUT+ + DAC_OUT- MAX9632 MAX542 DAC U15 MAX9632 x2 F M C CS_ADC ADC_REFN MAX6126 ADC_REFN SYNC IN, SYNC OUT CS_DAC DIN_DAC LDAC I S O L A T I O N H E A D E R FTDI U S B FPGA ZedBoard User-Supplied SPI PC - USB MAX6126 www.maximintegrated.com Maxim Integrated 2 MAX1121X Family Evaluation Kit MAX1121X EV Kit Files FILE DECRIPTION Application Program MAX11214_16EVKitSetupV1.1.exe (GUI) Boot.bin ZedBoard Firmware (SD Card to boot Zynq) Evaluates: MAX11214/MAX11216 7) From the Device menu, select Standalone and click Search for USB Device. Then select Standalone again and select a device in the list. Verify that the lower left status bar indicates the EV kit hardware is Connected. For FPGA mode (when connected to a ZedBoard): Required Equipment 8) Connect the Ethernet cable from the PC to the ZedBoard and configure the Internet Protocol Version 4 (TCP/Ipv4) properties in the local area connection to IP address 192.168.1.2 and subnet Mask to 255.255.255.0. +12V (500mA) power supply 9) Verify that the ZedBoard SD card contains the boot.bin file for the MAX1121X EV kit. Quick Start MAX1121X EV kit Micro-USB cable ZedBoard development board (optional - Not Included with EV kit) Function generator (optional) Windows XP, Windows 7, or Windows 8.1 PC with a spare USB port Note: In the following sections, software-related items are identified by bolding. Text in bold refers to items directly from the EV system software. Text in bold and underline refers to items from the Windows operating system. Procedure The EV kit is fully assembled and tested. Follow the steps below to verify board operation: 1) Visit www.maximintegrated.com/evkitsoftware to download the latest version of the EV kit software, MAX11214_16EVK.ZIP. Save the EV kit software to a temporary folder and uncompress the ZIP file. 2) Install the EV kit software and USB driver on your computer by running the MAX11214_16EVKitSetupV1.1.exe program inside the temporary folder. The program files are copied to your PC and icons are created in the Windows Start | Programs menu. At the end of the installation process, the installer will launch the installer for the FTDIChip CDM drivers. For Standalone mode: 3) Verify that all jumpers are in their default positions for the EV kit (Table 2). 4) Connect the PC to the EV kit using a micro-USB cable. 5) Connect the +12V adapter to the EV kit. 6) Start the EV kit software by opening its icon in the Start | Programs menu. The EV kit software appears as shown in Figure 1. Verify that the lower left status bar indicates the EV kit hardware is Connected. www.maximintegrated.com 10) Connect the EV kit FMC connector to the ZedBoard FMC connector. Gently press them together. 11) Verify that all jumpers are in their default positions for the ZedBoard (Table 1) and EV kit (Table 2). 12) Connect the 12V wall adapter power supply to the ZedBoard. Leave the ZedBoard powered off. Connect the PC to the ZedBoard with an Ethernet cable. 13) Enable the power supply by sliding SW8 to ON. 14) Start the EV kit software by opening its icon in the Start | Programs menu. The EV kit software appears as shown in Figure 1. From the Device menu, select FPGA. Verify that the lower left status bar indicates the EV kit hardware is Connected. For either Standalone or FPGA mode: 15) Connect the positive terminal of the function generator to the IN+ test point on the EV kit. Connect the negative terminal of the function generator to the IN- test point on the EV kit. Disable the function generator. 16) Enable the function generator. Configure the signal source to generate a 1kHz, 1VP-P sinusoidal wave with +500mV offset. 17) In the Calibration group, select Self Offset/Gain in the drop-down list and then click Calibrate. 18) Click on the Scope tab. 19) Check the Remove DC checkbox to remove the DC component of the sampled data. 20) Click the Capture button to read sampled data from the ADC. 21) The EV kit software appears as shown in Figure 4. 22) Verify the frequency is approximately 1kHz displayed on the right. The scope graph has buttons in the upper-right corner that allow zooming in to detail. Maxim Integrated 3 Evaluates: MAX11214/MAX11216 MAX1121X Family Evaluation Kit Table 1. ZedBoard Jumper Settings (Optional) JUMPER SHUNT POSITION J18 1-2 JP11 2-3 JP10 1-2 DESCRIPTION VDDIO set for 3.3V JP9 1-2 JP8 2-3 JP7 2-3 JP10 -- J12 -- J20 -- Connected to 12V wall adapter SW8 Off ZedBoard power switch, off while connecting boards Boot from SD card SD card installed Table 2. MAX1121X EV Kit User Configuration Jumper Settings* JUMPER J2 (Red) J3 (Red) J4 (Red) J5 (Red) J6 (Black) SHUNT POSITION 1-2 Connects the +10V rail to test point +10VEXT for external power (op amp + supply) 2-3* Connects the +10V rail to LDO U2 (op amp + supply) 1-2 Connects the +15V rail to test point +15EXT for external power (powers U2) 2-3* Connects the +15V rail to isolation transformer (powers U2) 1-2 Set ADC DVDD to +3.3V 2-3* Set ADC DVDD to +2.0V 1-2* Connect ADC AVSS to GND (unipolar mode - also set J8 for unipolar) 2-3 Connect ADC AVSS to -1.8V (bipolar mode - also set J8 for bipolar) 1-2 Apply an offset of ADC_REFP (2.5V default) to amplifier U24 2-3 Apply an offset of 2.5V to amplifier U24 Open* J7 (Black) J15 (Red) J17 (Red) J18 (Red) J20 (Red) J21 (Black) No offset for amplifier U24 1-2 Apply an offset of ADC_REFP (2.5V default) to amplifier U27 2-3 Apply an offset of 2.5V to amplifier U27 Open* J8 (Red) DESCRIPTION No offset for amplifier U27 1-2 Connect ADC AVDD to +1.8V (bipolar mode) 2-3* Connect ADC AVDD to 3.6V (unipolar mode) 1-2* Connects ZedBoard +12V to main power supply (U3). Diode D2 protects supplies. Open Disconnects ZedBoard +12V from main power supply 1-2 Connects U5 input to GND 3-4 Connects U5 input to test point -15VEXT for external power 5-6* Connects U5 input to isolation transformer 1-2 Do not connect 3-4 Do not connect 5-6 Connects U5 output to GND, which sets the reference for the -10V supply (op amp - supply) 1-2* Connects on-board FTDI chip to 3.3V, necessary for standalone mode Open Disconnects on-board FTDI chip power. This jumper does not interfere with the ZedBoard. 1-2* Drive ADC REFP pin with on-board voltage reference 2-3 Drive ADC REFP pin with external voltage reference www.maximintegrated.com Maxim Integrated 4 Evaluates: MAX11214/MAX11216 MAX1121X Family Evaluation Kit Table 2. MAX1121X EV Kit User Configuration Jumper Settings* (continued) JUMPER J22 (Black) J23 (Black) J24 (Black) J25 (Black) J26, J27 (Black) J28 (Black) J29 (Black) J30 (Black) J36 (Black) J37 (Red) J40 (Black) J44 (Black) J45 (Black) J46 (Red) SHUNT POSITION DESCRIPTION 1-2 Ground test point CH_D- 3-4 Ground test point CH_D+ 1-2* Drive ADC REFN pin with on-board voltage reference 2-3 Drive ADC REFN pin with external voltage reference 1-2 Ground test point CH_C- 3-4 Ground test point CH_C+ 1-2* Connect output of U23 (CH_C) to U24 inverting input 3-4 Connect CH_D- to U24 inverting input 5-6 Connect output of U23 (CH_C) to U24 noninverting input 7-8 Connect CH_D+ to U24 noninverting input 1-2* Set both jumpers to align with silkscreen text "EXT" to drive ADC_INP and ADC_INN with test points IN+ and IN- (also external connector J10 is on same net) 3-4 Set both jumpers to align with silkscreen text "AMP" to drive ADC_INP and ADC_INN with U27 and U24 amplifiers 5-6 Set both jumpers to align with silkscreen text "DAC" to drive ADC_INP and ADC_INN with DAC_ OUT+ and DAC_OUT- 7-8 Set both jumpers to align with silkscreen text "REF" to drive ADC_INP and ADC_INN with ADC_ REFP and ADC_REFN voltage reference 9-10 ADC_INP to ADC_REF/2, ADC_INN to GND 1-2 Ground test point CH_A- 3-4 Ground test point CH_A+ 1-2* Connect output of U26 (CH_A) to U27 inverting input 3-4 Connect CH_B- to U27 inverting input 5-6 Connect output of U26 (CH_A) to U27 noninverting input 7-8 Connect CH_B+ to U27 noninverting input 1-2 Ground test point CH_B- 3-4 Ground test point CH_B+ 1-2 Drive ADC CLK pin with signal from SMA connector J34 2-3* Drive ADC CLK pin with signal from on-board oscillator U20 1-2* Connect ADC to the DVDD voltage selection jumper J4 open Attach amp meter between pins 1-2 to measure current consumed by ADC DVDD 1-2* Connect ADC RST to DVDD (normal operation) 2-3 Connect ADC RST to GND (reset state) 1-2* Sets U18 noninverting input to 0V. Gain = -1 with offset = 0. Drives DAC_OUT-. 2-3 Sets U18 noninverting input to 2.5V. Gain = -1 with offset = 2.5V. Drives DAC_OUT-. 1-2* Sets U17 noninverting input to 0V. Gain = -1 with offset = 0. Drives DAC_OUT+. 2-3 Sets U17 noninverting input to 2.5V. Gain = -1 with offset = 2.5V. Drives DAC_OUT+. 1-2* Enables main power supply (U3) Open Disables main power supply (U3) *Red test points and red jumpers are used for power settings. Black test points are used for ground points. White test points are used for all signal points, black jumpers for signal settings. www.maximintegrated.com Maxim Integrated 5 Evaluates: MAX11214/MAX11216 MAX1121X Family Evaluation Kit Table 3. MAX1121X EV Kit User Off-Board Connectors CONNECTOR REFERENCE DESIGNATOR DESCRIPTION J1 USB connector for standalone mode J9 External reference input for EXT_REFP and EXT_REFN J10 External input for ADC IN+ and IN- J12, J16 External power connections, 12V. Both wall adapter and screw terminals are provided. When ZedBoard is used, these connectors are not necessary if jumper J15 is installed. J13 External connections for AVDD and AVSS J14 External enable, driven by GPIO1 via FET J19 Serial EEPROM signal J31 Sync clock input, SMA J32 PMOD A, connects to ADC, 12-pin connector J33 PMOD B, connects to DAC, 12-pin connector J34 External clock input, SMA J35 DAC SPI port signal J38, J41 Sync clock out, SMA J39 ADC SPI port signal J42 Split sync clock in, SMA J43 FMC connector for use with ZedBoard General Description of Software The main window of the EV kit software contains several tabs: ADC Config, DAC Config, Function Generator, Scope, DMM, Histogram, FFT, and ADC Registers. The ADC Config tab and ADC Registers tab provide control to communicate with the MAX1121X registers. The DAC Config tab and Function Generator tab provide control to communicate with the MAX542. The other four tabs are used for evaluating the sample data read from the ADC. ADC Config Tab The ADC Config tab provides an interface for configuring the IC from a functional perspective. The main block provides for calibration, GPIO control, input path selection, data format, filtering, power, and clocking. To read all the configuration settings, click the Read All button in www.maximintegrated.com the Serial Interface block. When a setting is changed, the register associated with that setting is automatically written. The Status Log at the bottom of the GUI shows the value and register that was changed. The primary mode for calibration is using the drop-down list to select a calibration mode, followed by clicking the Calibrate button. The checkboxes for Self Offset, Self Gain, System Offset, and System Gain allow for the user to enable or disable the calibration values. The calibration values can also be changed manually by entering a hex value in the SPI numeric box. The Power block allows the user to put the part in a power-down or standby state by selecting one of these options in the drop-down list. The configuration settings can be reset back to default by clicking the Reset Maxim Integrated 6 MAX1121X Family Evaluation Kit Registers button. For the Clock source selection, the IC internal clock is always a valid option. If the external clock is selected, a clock must be applied at the IC CLK pin by setting jumper J36 to either SMA or OSC. Once the above configurations are completed, start conversion by clicking Convert in the Serial Interface block. To read the data and status, click Read Data and Status on the lower right of the GUI. Evaluates: MAX11214/MAX11216 To save a configuration, select Save ADC Config As... in the File menu. This saves all the ADC register values to an XML file. To load a configuration, select Load ADC Config in the File menu. When the XML file is loaded, all the register values in the file are written to the ADC. Figure 1. MAX1121X EV Kit Software (ADC Config Tab) www.maximintegrated.com Maxim Integrated 7 MAX1121X Family Evaluation Kit DAC Config Tab In standalone mode, the ADC and DAC cannot operate concurrently. It is recommended to use FPGA mode when using the DAC for function generation. The DAC Config tab sheet provides an interface for configuring the MAX542 to drive the DAC_OUT+ and DAC_OUT- pins. Set J45 Offset and J44 Offset to match the jumper positions on the EV Kit. These jumper positions apply DC offset to DAC_OUT+ and DAC_OUT-, see the DAC amplifier section for more details. To write a value to the DAC, select the output of interest in the dropdown list, enter a value in the numeric box and then click DAC Single Shot. The outputs on the right display the voltage outputs and the decimal code written to the DAC. Evaluates: MAX11214/MAX11216 The voltage outputs are calculated based on the DAC code and jumper offsets. The Calibration section of the DAC Config tab can be used to calibrate the calculated voltages to be closer to the measured voltages. Select which output to calibrate with the radio buttons. Enter the maximum and minimum voltage for this output in the Ideal (V) numeric boxes. Find the measured voltages of the output for the maximum and minimum values using the DAC Single Shot to set the DAC output to the ideal voltages. Enter the measured voltages in the Measured (V) numeric boxes and click Calculate to find the new offset and gain. Check the Enable Calibration to use these values to calculate the voltage outputs. Figure 2. MAX1121X EV Kit Software (DAC Config Tab) www.maximintegrated.com Maxim Integrated 8 MAX1121X Family Evaluation Kit Function Generator When using the FPGA mode, the Function Generator tab allows the user to generate a signal with the DAC. Select the Number of Samples, DAC Update Rate, and Signal Frequency. Click Calculate to get the Adjust Frequency for the DAC signal needed for coherent sampling. Then select the Signal Type, Amplitude, Phase, and Offset to set up the waveform desired for the DAC. Click Evaluates: MAX11214/MAX11216 Generate to find the DAC codes for the waveform and generate the waveform on the DAC. The waveform codes sent to the DAC is displayed on the graph. The Average, RMS, Maximum, Minimum, and Peak to Peak are also calculated and displayed on the right. To save the DAC code waveform, go to Options > Save Graph > Function Generator. This saves the settings on the left and the data in the graph to a csv file. Figure 3. MAX1121X EV Kit Software (Function Generator Tab) www.maximintegrated.com Maxim Integrated 9 MAX1121X Family Evaluation Kit Scope Tab The Scope tab sheet is used to capture data and display it in the time domain. Sample Rate and Number of Samples can also be set in this tab if they were not appropriately adjusted in other tabs. The Display Unit drop-down list allows counts and voltages. Once the desired configuration is set, click on the Capture button. The right side of the tab sheet displays details of the wave- Evaluates: MAX11214/MAX11216 form, such as Average, Standard Deviation, Maximum, Minimum, and Fundamental Frequency. Figure 4 displays the ADC data when a sinusoidal signal is applied at the inputs on the EV kit. To save the captured data to a file, go to Options > Save Graph > Scope. This saves the setting on the left and the data captured to a csv file. Figure 4. MAX1121X EV Kit Software (Scope Tab) www.maximintegrated.com Maxim Integrated 10 MAX1121X Family Evaluation Kit DMM Tab The DMM tab sheet provides captured data as a digital multimeter. Once the desired configuration is set, click on the Capture button. Figure 5 displays the results shown Evaluates: MAX11214/MAX11216 by the DMM tab when ADC_INP and ADC_INN (J26 and J27 set as 7-8) are set to REF, see Table 2 for jumper positions. Figure 5. MAX1121X EV Kit Software (DMM Tab) www.maximintegrated.com Maxim Integrated 11 MAX1121X Family Evaluation Kit Histogram Tab The Histogram tab sheet is used to display a histogram of the captured data. Sampling rate and number of samples can also be set in this tab if they were not appropriately adjusted in other tabs. Once the desired configuration is set, click on the Capture button. The right side of the tab sheet displays details of the histogram such as Average, Standard Deviation, Maximum, Minimum, Peak-to-Peak Evaluates: MAX11214/MAX11216 Noise, Effective Resolution, and Noise-Free Resolution. To use this histogram feature, apply a DC voltage at the input. Figure 5 displays the results shown by the DMM tab when ADC_INP and ADC_INN are set to REF, see Table 2 for jumper positions. To save the histogram data to a file, go to Options > Save Graph > Histogram. This saves the setting on the left and the histogram data captured to a csv file. Figure 6. MAX1121X EV Kit Software (Histogram Tab) www.maximintegrated.com Maxim Integrated 12 MAX1121X Family Evaluation Kit FFT Tab The FFT tab sheet is used to display the frequency domain FFT of the captured data. Sample Rate and Number of Samples can also be set in this tab if they were not appropriately adjusted in other tabs. Once the desired configuration is set, click on the Capture button. The right side of Evaluates: MAX11214/MAX11216 the tab displays the performance based on the FFT, such as Fundamental Frequency, THD, SNR, SINAD, SFDR, ENOB, and Noise Floor. To save the FFT data to a file, go to Options > Save Graph > FFT. This saves the setting on the left and the FFT data captured to a csv file. Figure 7. MAX1121X EV Kit Software (FFT Tab) www.maximintegrated.com Maxim Integrated 13 MAX1121X Family Evaluation Kit ADC Registers Tab The ADC Registers tab sheet shows the ADC registers on the left. The middle section shows the bits and bit descriptions of the selected register. Click Read All to read all registers and refresh the window with the register settings. To write a register first, select the hex value in the Value (Hex) column, type the desired hex value and press Enter. Evaluates: MAX11214/MAX11216 The Command Byte is on the right side of the tab sheet. This byte precedes all SPI transactions and is described in the ADC data sheet. To send a command byte, enter a hex value in the Numeric box and click the Send button. The command byte has two different formats including Conversion Mode and Register Access Mode. Select the radio button for the desired mode to see the bit description in the table. Figure 8. MAX1121X EV Kit Software (ADC Registers Tab) www.maximintegrated.com Maxim Integrated 14 Evaluates: MAX11214/MAX11216 MAX1121X Family Evaluation Kit Detailed Description of Hardware This EV kit provides a proven layout to demonstrate the performance of the MAX1121X 24-bit delta-sigma ADC. Included in the EV kit are digital isolators (MAX14934), ultra-low-noise LDOs (MAX8842) to all supply pins of the IC, an on-board reference (MAX6126), a precision amplifier (MAX44241) for the analog inputs, 16-bit DAC (MAX542) with precision amplifiers (MAX9632), and syncin and sync-out signals for coherent sampling. An on-board controller is provided to allow for evaluation in standalone mode, which has limitations on maximum sample size and it cannot perform coherent sampling. The EV kit can be used with FPGA mode to achieve larger sample depth and coherent sampling. The ADC has several input options which are selected by J26 and J27. The external option allows for wires attached to the screw terminals at J10. The amplifier option allows for signals at testpoints CH_A to CH_D. The DAC option allows for inputs to be driven from an on-board DAC. The REF options connect the inputs to the voltage reference of the ADC. User-Supplied SPI To evaluate the ADC on this EV kit with a user-supplied SPI bus, disconnect from the FMC bus and remove jumper J20. Apply the user-supplied SPI signals to SCLK, CSB, DIN, and DOUT at the PMOD_A header (J32). Make sure the return ground is connected to PMOD ground. To communicate to the on-board DAC connect the user-supplied SPI signals to CSB, SCLK, DIN, and LDAC at the PMOD_B header (J33). Make sure the return ground is connected to PMOD ground. The on-board FTDI chip used for standalone mode does not conflict with the user-supplied SPI if it is powered off by removing jumper J20. Caution: Do not plug this header into a standard PMOD interface found on other FPGA or microcontroller products. The signal definition is unique to this EV kit. User-Supplied AVDD The AVDD supply is set to 3.6V or 1.8V by jumper J8. For user-supplied AVDD, remove the jumper from J8 and apply AVDD to the screw-terminals/testpoint at J13. Make sure that this external supply has the correct relation to system ground. Bipolar Powered vs. Unipolar Powered The ADC supports both unipolar and bipolar ranges. For unipolar mode, jumper J8 pins 2-3 to power AVDD with 3.6V and jumper J5 pins 1-2 to set AVSS to GND. For bipolar mode, jumper J8 pins 1-2 to power AVDD with 1.8V and jumper J5 pins 2-3 to set AVSS to -1.8V. External Clock When the ADC is configured to use an external clock, Jumper J36 pins 2-3 to select the on-board oscillator as the clock source. Jumper J36 pins 1-2 to select the SMA connector (and user-provided clock) as the clock source. GPIO Testpoints are provided for the three GPIO signals from the ADC, GPIO1, GPIO2, and GPIO3. The ADC Config tab can configure these as input/output and read/drive the GPIO pins. GPIO1 connects to a FET which allows J14.1 and TP2 to be connected to ground by driving GPIO1 high (note that DVDD should be to 3.3V to drive the FET). ADC Input Amplifiers The input amplifiers allow for significant flexibility. The amplifier input stage begins with testpoints labeled CH_A to CH_D. Each set of testpoints has options to ground either the inverting or noninverting inputs. The jumper block J29 and J25 allow for bypassing the first stage of amplifiers, or connecting the first stage to the second stage. Jumper J7 can provide an offset of 2.5V to the CH_A/CH_B signals - leave unpopulated to have an offset of 0V. Similarly, jumper J6 can provide an offset of 2.5V to the CH_C/CH_D signals - leave unpopulated to have an offset of 0V. DAC and DAC Amplifiers User-Supplied Reference In Figure 2, the GUI shows a functional diagram of the DAC and DAC amplifiers. Here jumper J45 can be connected to 2.5V to add a 2.5V offset to the DAC_OUT+ signal, and J44 can be connected to 2.5V to add 2.5V to the DAC_OUT- signal. User-Supplied AVSS The value at DAC_OUT+ and DAC_OUT- are available to drive to the ADC by use of jumpers J26 and J27. For user-supplied reference voltage, set jumpers at J21 and J23 to positions 2-3 and apply external reference to either J9 or to the EXT_REFN and EXT_REFP testpoints. The AVSS supply is set to GND or -1.8V by Jumper J5. For user-supplied AVSS, remove the jumper from J5 and apply AVSS to the screw-terminals/testpoint at J13. Make sure that this external supply has the correct relation to system ground. www.maximintegrated.com Also, please note that the DAC_OUT+ and DAC_OUTvalues shown by the GUI are only valid if the settings at J44 and J45 are the same on both the PCB and the GUI. Maxim Integrated 15 Evaluates: MAX11214/MAX11216 MAX1121X Family Evaluation Kit IN+ CH_A1 3 J28 2 4 MAX44241 MAX44241 1 J29 + CH_A+ 2 - 4 3 5 6 7 8 1 J27 3 MAX44241 + 2 ADC_INP 4 DAC_OUT+ 5 6 ADC_REFP 7 8 ADC_REF/2 9 10 ADC_REFP CH_B1 3 J7 J30 2 4 +2.5V CH_B+ MAX11214/MAX11216 Sigma-Delta ADC IN- CH_C1 3 J24 2 4 MAX44241 MAX44241 + CH_C+ 1 J25 2 3 4 5 6 7 8 - 1 MAX44241 + 3 J26 2 ADC_INN 4 DAC_OUT- 5 6 ADC_REFN 7 8 9 10 ADC_REFP CH_D1 3 J22 J6 2 4 +2.5V CH_D+ Figure 9. Analog Front-End www.maximintegrated.com Maxim Integrated 16 MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Table 4. Analog Input Configurations (Ch A - D) CONFIGURATION No. 1 2 3 4 DESCRIPTION Channel A and C Channel A and C Channel B and D Channel B and D www.maximintegrated.com SIGNAL-PATH INPUT CONFIGURATION Noninverting, differential, second-order LPF (default) Inverting, differential, second-order LPF Noninverting, differential, first-order LPF Inverting, differential, firstorder LPF INPUT CONNECTORS JUMPER POSITIONS CH_A- and CH_C- J28: 3-4 J30: 3-4 J24: 3-4 J22: 3-4 J29: 1-2 and 7-8 J25: 1-2 and 7-8 J26: 3-4 J27: 3-4 J7: 1-2 (for bipolar signal) or Open for unipolar signal J8: 1-2 (for bipolar signal) or Open for unipolar signal CH_A+ and CH_C+ J28: 1-2 J30: 3-4 J24: 1-2 J22: 3-4 J29: 1-2 and 7-8 J25: 1-2 and 7-8 J26: 3-4 J27: 3-4 J7: 1-2 (for bipolar signal) or Open for unipolar signal J8: 1-2 (for bipolar signal) or OPEN for unipolar signal CH_B+ and CH_D+ J28: 1-2 and 3-4 J30: 1-2 J24: 1-2 and 3-4 J22: 1-2 J29: 3-4 and 7-8 J25: 3-4 and 7-8 J26: 3-4 J27: 3-4 J7: 1-2 (for bipolar signal) or Open for unipolar signal J8: 1-2 (for bipolar signal) or Open for unipolar signal CH_B- and CH_D- J28: 1-2 and 3-4 J30: 3-4 J24: 1-2 and 3-4 J22: 3-4 J29: 3-4 and 7-8 J25: 3-4 and 7-8 J26: 3-4 J27: 3-4 J7: 1-2 (for bipolar signal) or Open for unipolar signal J8: 1-2 (for bipolar signal) or Open for unipolar signal Maxim Integrated 17 MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Table 4. Analog Input Configurations (Ch A - D) (continued) CONFIGURATION No. 5 6 7 DESCRIPTION External Inputs DAC Output ADC Voltage Reference www.maximintegrated.com SIGNAL-PATH INPUT CONFIGURATION User-supplied signals DAC output buffered with MAX9632 Voltage reference input to ADC from MAX6126 or external source (see J21 and J23) INPUT CONNECTORS JUMPER POSITIONS IN+ and IN- J28: 1-2 and 3-4 J30: 1-2 and 3-4 J24: 1-2 and 3-4 J22: 1-2 and 3-4 J29: 3-4 and 7-8 J25: 3-4 and 7-8 J26: 1-2 J27: 1-2 J7: Open J8: Open DAC_OUT+ and DAC_ OUT- J28: 1-2 and 3-4 J30: 1-2 and 3-4 J24: 1-2 and 3-4 J22: 1-2 and 3-4 J29: 3-4 and 7-8 J25: 3-4 and 7-8 J26: 5-6 J27: 5-6 J7: Open J8: Open ADC_REFP and ADC_ REFN J28: 1-2 and 3-4 J30: 1-2 and 3-4 J24: 1-2 and 3-4 J22: 1-2 and 3-4 J29: 3-4 and 7-8 J25: 3-4 and 7-8 J26: 7-8 J27: 7-8 J7: Open J8: Open Maxim Integrated 18 ADC_REFN ADC_REFP ADC_INP ADC_INP ADC_INN ADC_INN TP IN IN TP J40 DVDD_ADC TP 1 3 AVDD J11 G4 1 2 2 AGND +3.3V A3.6V +1.8V -1.8V +2.0V 3 3 A3.6V 0 R71 0 R70 AVSS J8 2 1000PF C114 1000PF C106 AVDD GPIO3 OUT GPIO2 OUT GPIO1 OUT DIN_ADC IN DOUT_ADC OUT SYNC_ADC IN EXT_REFP EXT_REFN +1.8V OUT OUT IN IN IN IN IN IN IN IN IN DAC_OUT+ DAC_OUTAVDD AVSS C109 0.01UF 0.01UF CB6 49.9 1 2 3 4 5 6 7 8 9 10 11 12 DGND REFP REFN AVSS AINN AINP AVSS CAPP CAPN AVDD GPIO1/MB1 RDYB/ICLK CLK CAPREG GPIO2 GPIO3/MSYNC RSTB CSB SYNC SCLK DVDD DOUT/MB0 DGND DIN MAX11214EUG+ U25 24 23 22 21 20 19 18 17 16 15 14 13 0.01UF C93 1 0.01UF C95 2 C85 PCC02SAAN 1000PF J37 SCLK_ADC CS_ADC C86 0.1UF AVSS 1UF C96 NOTE: MAX11214EVKIT AND MAX11216EVKIT USE DIFFERENT COMPONENTS FOR U25 AND U20 MAX11214EVKIT U25 IS POPULATED WITH MAX11214EUG+ MAX11216EVKIT U25 IS POPULATED WITH MAX11216EUG+ MAX11214EVKIT U20 IS POPULATED WITH FXO-HC730-8.192 (8.192MHZ OSCILLATOR) MAX11214EVKIT U20 IS POPULATED WITH FXO-HC730-4.096 (4.096MHZ OSCILLATOR) * OPEN C108 0.01UF C115 AVSS GPIO1 TP R72 IN IN C87 OPEN OPEN C83 * * 0.1UF CB5 TP 0.1UF 28 49.9 2 CLK ADC_REFN ADC_REFP TP TP -1.8V J5 J4 R63 R55 ADC_CAPR 2 DVDD_ADC CB4 OUT 1 3 1 3 IN BAT54S D4 OUT C84 1000PF R60 10K 10K R56 RDYB_ADC +2.0V +3.3V 0 R61 0 R53 J34 ADC_REFN ADC_REFP 49.9 2 4.7UF DNI C82 2 R49 J23 OUTF 7 U21 OUTS 2 1 NR EXT_REFN 3 U20 J36 VDD C81 0.1UF C80 0.1UF GND 1 AVSS C77 0.1UF OUTPUT E/D FXO-HC730-8.192 IN MAX6126AASA25 EXT_REFP 2 6 J21 SMA CONNECTOR CLOCK 1 EXTERNAL 73391-0060 2 4 3 5 IN PCC02SAAN 2 D3 BAT54S 1 1 3 2 1 3 1 1 3 I.C. I.C. 8 5 IN +3.3V 1 3 GNDS GND +3.3V 4 2 www.maximintegrated.com 4 3 MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Figure 10a. MAX1121X EV Kit Schematic (Sheet 1 of 6) Maxim Integrated 19 IN IN IN IN +5V CS_DAC DIN_DAC SCLK_DAC LDAC 4.7UF C31 +2.5V 0.1UF C32 C54 4.7UF C52 0.1UF 0.1UF C39 7 10 8 11 6 5 REFS REFF LDAC SCLK DIN CS DGND VDD RFB INV OUT IN NR 2 1 6 7 OUTS OUTF U10 MAX6126AASA25 1UF C48 1 2 13 +2.5V C23 10UF 0.1UF C47 +10V U15 MAX542AESD+ (MAX542V-18) 3 2 IN+ N.C. VEE +2.5V 1UF OUT -10V 6 +2.5V 0.1UF C69 J45 2 -10V C68 TP OUT N.C. VCC INSHDN U16 MAX9632AUA+ C132 180PF +10V 7 4 +5V AGNDF 1 14 AGNDS 8 5 C67 0.1UF NC GND GNDS 10K R30 R33 1UF C50 10K 10K BUFF_OUT R40 TP 0.1UF C49 +10V 0.1UF C61 3 2 +10V R41 C71 0.001UF 10K IN+ N.C. VEE OUT N.C. VCC INSHDN 7 4 1UF C64 6 U17 MAX9632AUA+ -10V -10V 1 1 3 8 5 12 3 4 9 I.C. I.C. 3 4 C65 0.1UF J44 2 TP R44 R29 R42 BUFF_OUT1 R36 10K 10K 10K 10 C46 1UF C45 10K IN+ N.C. VEE OUT N.C. VCC INSHDN 0.1UF +10V 0.1UF C58 3 2 +10V R43 C72 10PF 7 4 6 U18 C62 1UF 0.1UF C63 MAX9632AUA+ -10V -10V 1 1 3 8 5 www.maximintegrated.com 5 8 TP AGND +10V -10V +5V 10 R34 BUFF_OUT2 IN IN IN IN 0.047UF C51 C66 0.047UF C59 DAC_OUT- G2 TP DAC- TP OUT 0.047UF DAC_OUT+ DAC+ TP OUT MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Figure 10b. MAX1121X EV Kit Schematic (Sheet 2 of 6) Maxim Integrated 20 J1 USB SHIELD 5 4 3 2 1 L3 4 5 3 1 2 600 R1 R2 28 28 USB+5V 10K RB5 15K RB4 2.2K RB10 10K RB15 1 DO VSS VCC RB3 CS DI CLK C19 18PF CB2 18PF 12MHZ 1 13 3 2 61 3 14 6 TEST OSCO OSCI EEDATA EECLK EECS RESET# REF DP DM VREGOUT 49 7 8 VREGIN 50 63 62 2 YB1 12K C15 0.1UF 5 4 CB3 C24 4.7UF 4.7UF VPLL 2 1 FT2232HL UB2 ADBUS0 SUSPEND# PWREN# BCBUS7 BCBUS6 BCBUS5 BCBUS4 BCBUS3 BCBUS2 BCBUS1 BCBUS0 BDBUS7 BDBUS6 BDBUS5 BDBUS4 BDBUS3 BDBUS2 BDBUS1 BDBUS0 ACBUS7 ACBUS6 ACBUS5 ACBUS4 ACBUS3 ACBUS2 ACBUS1 ACBUS0 ADBUS7 ADBUS6 ADBUS5 ADBUS4 ADBUS3 ADBUS2 ADBUS1 36 60 58 59 55 57 54 52 53 48 45 46 43 44 41 39 40 38 33 34 30 32 29 27 28 26 23 24 21 22 18 19 17 16 C22 RB6 +3.3V_USB 93LC66BT-I/OT UB1 U3 CONFIG +3.3V_USB +1.8V +3.3V_USB C16 0.1UF 4 9 VPHY 0.1UF RB8 USB+5V C20 4.7UF C18 0.1UF C29 0.1UF RB11 +3.3V_USB GND C30 VCORE GND 0.1UF RB13 C17 VCORE GND AGND C21 0.1UF RB17 RB24 0.1UF GND GND RB20 C14 RB21 0.1UF VCCIO 10 4.7K DSB1 RB23 28 28 RB26 RB25 28 28 28 RB18 RB19 28 28 28 28 28 RB16 RB14 RB12 RB9 RB7 +3.3V_USB +3.3V_USB RB22 +1.8V VCCIO GND 10118192-0001LF 11 10 9 8 7 6 12 37 64 VCORE GND 6 2 20 31 42 56 VCCIO VCCIO GND 1 5 11 15 25 35 47 51 10K 10K 10K 10K 10K 10K 10K 10K A www.maximintegrated.com K IN IN IN OUT OUT OUT IN OUT IN IN LDAC_FPGA CS_DAC_FPGA SCLK_DAC_FPGA DIN_DAC_FPGA SYNC_ADC_FPGA RDYB_ADC_FPGA SCLK_ADC_FPGA DIN_ADC_FPGA DOUT_ADC_FPGA CS_ADC_FPGA OUT IN OUT GND USB+5V +3.3V_USB MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Figure 10c. MAX1121X EV Kit Schematic (Sheet 3 of 6) Maxim Integrated 21 CS_DAC LDAC SCLK_DAC DIN_DAC CS_ADC SCLK_ADC DIN_ADC SYNC_ADC DOUT_ADC RDYB_ADC IN IN OUT OUT OUT OUT 1 2 3 4 5 6 7 8 9 10 PBC10SAAN J35 DVDD_ADC RB50 RB49 RB51 RB48 DVDD_ADC VL I/O VL7 I/O VL8 9 EN I/O VL6 8 10 I/O VL5 7 I/O VL4 6 5 I/O VL3 I/O VL2 3 4 2 OUT OUT OUT OUT +3.3V RDYB_ADC CS_ADC SCLK_ADC DIN_ADC DOUT_ADC TEST CS_DAC SCLK_DAC DIN_DAC LDAC 28 28 28 28 I/O VL1 1 UB3 MAX3002EUP RB35 RB33 RB32 RB31 1 2 3 4 5 6 7 8 9 10 GND I/O VCC8 I/O VCC7 I/O VCC6 I/O VCC5 I/O VCC4 I/O VCC3 I/O VCC2 VCC I/O VCC1 J39 1UF 0.1UF C79 PBC10SAAN 11 28 28 28 28 9 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 1UF 10 C127 11 12 13 12 13 14 15 16 14 C76 C98 0.1UF 15 16 17 18 19 20 1UF C92 GND1 NC IND INC INB INA EN NC GND1 IND OUTD GND2 INB INC OUTC INA OUTA OUTB GND1 GND2 EN VCC1 VCC2 LDAC_FPGA 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 0.1UF C78 0.1UF C128 C97 0.1UF CS_ADC_FPGA DIN_ADC_FPGA DOUT_ADC_FPGA SCLK_ADC_FPGA MAX14934FAWE GND2 OUTD IND NC GND1 OUTB OUTA OUTC GND2 INA INC GND1 INB VCC2 U22 MAX14934FAWE U29 VCC1 GND1 VCC1 0.1UF C129 D3.6V GND2 EN OUTD OUTC OUTB OUTA GND2 VCC2 MAX14934FAWE U34 VDDIO 12 11 10 9 8 7 J1-2 J1-3 J1-4 J1-5 J1-6 J1-8 J1-9 J1-10 J1-11 J1-12 6 5 4 3 2 1 6 5 4 3 2 1 J1-10 J1-11 J1-12 J1-6 J1-9 J1-5 J1-8 J1-2 J1-3 J1-4 J1-7 J1-1 J32 TSW-106-08-S-D-RA PMOD PORT A J1-1 J1-7 TSW-106-08-S-D-RA J33 PMOD PORT B 12 11 10 9 8 7 VADJ R59 R62 VDDIO RDYB_ADC_FPGA SYNC_ADC_FPGA +12V_FPGA SCLK_DAC_FPGA CS_DAC_FPGA DIN_DAC_FPGA VDDIO DOUT_ADC_FPGA RDYB_ADC_FPGA SCLK_ADC_OUT_FPGA VDDIO CS_ADC_FPGA SCLK_ADC_FPGA DIN_ADC_FPGA SYNC_ADC_FPGA CS_DAC_FPGA SCLK_DAC_FPGA DIN_DAC_FPGA LDAC_FPGA 1UF C75 1UF C126 1UF C91 VDDIO 28 28 IN G40 G39 G38 G37 G36 G35 G34 G33 G32 G31 G30 G29 G28 G27 G26 G25 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 3 4 3 4 34 35 36 37 38 39 40 34 35 36 37 38 39 40 C40 C38 C39 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 H35 J43 13 14 15 16 17 18 19 20 21 22 23 24 25 13 14 15 16 17 18 19 20 21 22 23 24 25 35 36 37 38 39 40 37 38 39 40 34 36 34 35 33 32 32 33 31 30 29 28 27 31 30 29 28 27 26 12 12 26 11 8 11 7 9 6 10 10 8 9 7 4 4 6 3 5 2 3 5 1 2 H40 C38 1UF D40 D38 D39 D37 D36 D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 ASP-134604-01 R19 H38 H39 R21 H37 H36 R22 H34 R24 R25 R27 R23 H33 H32 H31 H30 H29 H28 R31 R35 H26 H27 R37 H25 H24 H23 H22 H21 H20 H19 R46 R47 H17 H18 R48 R50 R51 R52 R54 R57 R58 R65 H16 H15 H14 H13 H12 H11 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 1 ASP-134604-01 J43 33 29 29 32 28 28 33 27 27 32 26 26 30 25 31 24 31 23 30 22 25 19 19 24 18 18 23 17 17 22 16 16 20 15 15 21 14 14 21 13 20 12 13 9 12 8 10 11 10 11 9 7 6 8 7 6 5 2 2 5 1 J43 ASP-134604-01 1 ASP-134604-01 J43 FMC CONNECTOR VADJ DIN_DAC_FPGA CS_ADC_FPGA SYNC_ADC_FPGA SCLK_DAC_FPGA LDAC_FPGA CS_DAC_FPGA RDYB_ADC_FPGA DOUT_ADC_FPGA SCLK_ADC_OUT_FPGA SCLK_ADC_FPGA DIN_ADC_FPGA SYNC_CLK_IN SYNC_CLK_OUT 73391-0060 J31 TP 3V3_FPGA SYNC_CLK_OUT SYNC_CLK_OUT SYNC CLK OUT 1 SYNC CLK IN 49.9 R80 49.9 R84 SCK_EEPROM_FPGA CS_EEPROM_FPGA SO_EEPROM_FPGA SI_EEPROM_FPGA OUT OUT OUT OUT OUT OUT IN IN IN OUT OUT 5 7 2 1 5 7 2 1 2A 2OE 1A 1OE 2A 2OE 1A 1OE 3 4 5 DI CLK CS GND VCC VSS VCC 1000PF 0.1UF 6 3 GND 6 3 1Y 2Y 74LVC2G125DP 1000PF 0.1UF C116 U28 VDDIO 2Y 1Y IN IN IN IN IN IN PBC06SAAN J19 49.9 R85 SYNC_CLK_IN 1 J42 73391-0060 SYNC_CLK_IN SYNC CLK IN SPLIT SYNC CLK IN TP GND SO_EEPROM_FPGA 1 2 3 4 5 6 AGND GND D3.6V DVDD_ADC +3.3V 5V_FPGA VDDIO 49.9 R78 49.9 R75 1 J38 73391-0060 GND SYNC CLK OUT 49.9 R83 74LVC2G125DP U30 C130 C111 VCC U12 93LC66BT-I/OT 1 C42 C44 C131 VDDIO DO 0.1UF 1UF VDDIO FPGA INI SO_EEPROM_FPGA SI_EEPROM_FPGA SCK_EEPROM_FPGA CS_EEPROM_FPGA 6 2 D3.6V 2 4 3 5 8 4 ISOLATED 5 3 4 2 1 J41 73391-0060 5 3 4 2 8 4 IN www.maximintegrated.com 5 3 4 2 MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Figure 10d. MAX1121X EV Kit Schematic (Sheet 4 of 6) Maxim Integrated 22 GPIO3 GPIO2 TP TP TP TP CH_C- CH_D- 100 100 RB62 RB66 CH_D+ CH_C+ TP TP TP CH_B+ IN- TP TP CH_B- CH_A+ TP TP CH_A- TP RB64 J22 J24 J30 J28 100K IN- IN+ 3 1 3 1 3 1 3 1 RB61 100K RB36 3 1 RB34 RB41 3 1 RB37 RB63 3 1 RB65 RB56 3 1 RB52 1M 4 2 1M 1M 4 2 1M 1M 4 2 1M 1M 4 2 1M 4 2 4 2 4 2 4 2 IN IN 10K TP 10K TP GPIO3 GPIO2 C_INP1 3 10K RB39 R68 4 10K C105 1000PF A_INP1 RB38 R77 3 C124 10K RB54 1000PF 4 10K RB53 R66 INA+ INA- C99 INA+ INA- 1000PF R74 1000PF C118 10K VSS VDD OUTA +10V 5 2 10K -10V VSS VDD OUTA +10V 5 2 -10V OSTTA020161 J9 OSTTA020161 J10 U23 MAX44241AUK+ 1 U26 MAX44241AUK+ 1 1 2 1 2 0 R64 0 R73 1UF 1 3 5 7 1 3 5 7 EXT_REFN EXT_REFP IN- 1 3 5 7 TP TP 2 4 6 8 J25 PBC04DAAN 0.1UF C90 2 4 6 8 J29 PBC04DAAN 0.1UF C110 +10V 1 3 5 7 IN+ 1UF C88 C112 +10V RB57 RB55 RB42 RB40 0.1UF C103 -10V C100 1UF 0.1UF C119 R69 10K 10K R79 10K 10K EXT_REFN EXT_REFP J13 10K 10K OSTTA020161 J14 OSTTA020161 C107 1000PF C125 1000PF TERMINAL BLOCKS 2 4 6 8 2 4 6 8 1UF C121 -10V 1 2 1 2 RB28 RB30 TP C_INP2 3 RB44 3 4 RB27 0 0 INA+ INA- C102 INA+ INA- 1000PF R67 10K 10K RB59 A_INP2 TP 4 R76 C122 1000PF 10K VSS VDD 2 10K VSS VDD 2 OUTA +10V 5 2 -10V OUTA AVSS QB1 2N7002 PBC03SABN TP TP +2.5V J6 IN 49.9 RB45 S D G 1 AVSS AVDD 100K RB60 R81 R82 49.9 RB46 4.99 100 RB58 TP 4.99 +2.5V ADC_REFP U24 MAX44241AUK+ 1 J7 PBC03SABN ADC_REFP AVDD 0 1 U27 MAX44241AUK+ 1 3 +10V 5 2 -10V 1 3 IN+ 3 www.maximintegrated.com 2 TP2 1UF 0.1UF IN GPIO1 1UF C89 +10V J26 C94 0.1UF 9 7 5 3 1 10 8 6 4 2 ADC_REFN DAC_OUTAMPEXT- PBC05DAAN 2 4 6 8 10 J27 C123 PBC05DAAN 1UF C120 1 3 5 7 9 C113 0.1UF -10V EXT+ AMP+ DAC_OUT+ ADC_REFP ADC_REF/2 C117 +10V -10V C104 1UF 10 RB43 10 RB47 C101 0.1UF OUT OUT IN ADC_REF/2 IN IN IN OUT OUT OUT OUT IN IN IN ADC_INN ADC_INP ADC_REFN ADC_REFP EXT_REFP EXT_REFN AVDD AVSS DAC_OUT+ DAC_OUT- AGND -10V +10V 10K R87 R86 10K C133 1000PF TP G3 MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Figure 10e. MAX1121X EV Kit Schematic (Sheet 5 of 6) Maxim Integrated 23 +12V_FPGA USB+5V IN KLDX-0202-B J16 J12 IN A J15 C MBR0520L D1 PCC02SAAN +5V +5V C 2 MBR0520L DB1 +12V +12V TP C 1 MBR0520L D2 3 2 3 2 1 1 1 2 OSTTA020161 A 1UF C36 1UF C34 1UF C55 A 1 1 2 3 1 3 1 0.1UF C56 IN IN U7 OUT MAX8842ELT+ IN SHDN FB GND NC U9 SHDN FB GND NC OUT MAX8842ELT+ IN 4 6 4 6 OUT 6 GND EP NC OUT 5 MAX15006AATT+ U14 0.47UF C6 USB POWER 10UF CB1 J46 237K R16 453K R13 237K R17 453K 1 1K R6 R14 C57 10UF 2 VDDIO CLK ITH 3 5 TP G5 2 6.04K R10 6.04K R11 PCC02SAAN J20 EN 4 RB1 1K U3 1 1UF C27 1UF C25 TP A3.6V TP D3.6V OUT DS1 OUT OUT A3.6V D3.6V +3V3_USB VDDIO 8 OUT 10 ST2 6 ST1 FAULT MAX13256ATB+ 1K R7 7 2 4 4 5 6 T1 3 C74 +5V +5V 0.1UF -10V +15V 5 6 7 TGM-H240V8LF 8 8 1 3 2 1 ISOLATED 1UF C35 1UF C53 1UF C37 ~ D2 ~ U1 BAS4002A-RPP 3 1 3 1 4 3 5 2 0.1UF C33 1 2 ~ D2 ~ U4 BAS4002A-RPP IN IN GND EP NC OUT GND SHDN FB GND NC OUT MAX8842ELT+ IN U13 VSET VOUT2 VOUT1 MAX664ESA VINSHDN1 SHDN2 SENSE U19 IN OUT SHDN FB GND NC U8 MAX8842ELT+ - + 5 6 4 6 4 6 7 1 6 - D4 D4 + OUT MAX15006BATT+ U6 D1 D3 D1 D3 237K R15 R12 150K 237K R26 R28 105K 100K R38 39K R45 C28 10UF 1 1UF C8 1 1 1UF C1 1 0 1UF 0 R9 2 1 3 5 1UF C26 1UF C60 C73 TP +2.0V TP +1.8V 0.1UF TP J17 2 2 4 6 OUT OUT C12 +15V +1.8V OUT 0.1UF C41 -1.8V 1UF C43 180PF C11 0.1UF C10 1UF 180PF C4 0.1UF C3 +15V 1UF C2 +2.0V R39 100 2 4 6 TP +15VEXT +5V 1 3 5 -1.8V OUT 2 C70 R32 2 2 -15VEXT TP TP +5V L4 600 600 L5 L1 600 L2 600 PBC03SABN J3 1 3 G6 4 2 2 2 GND1 7 VDD1 GND2 9 VDD2 EP 11 A K 1 2 1 2 IN IN IN IN FB OUT GND EP NC U5 MAX15006CATT+ FB OUT GND EP NC U11 6 5 6 5 6 5 1 3 5 2 4 6 169K 100K 100K 0.1UF 2 4 6 100K 715K J18 2 0.1UF 715K R18 R5 C9 R8 1 3 5 R3 C5 R4 TP R20 TP +3.3V -10VEXT TP FB OUT GND EP NC MAX15006CATT+ IN IN 1 2 U2 MAX15006CATT+ +10VEXT J2 PBC03SABN 1 3 TERMINAL BLOCK TP 7 3 5 5 C40 10UF +10V 1K RB2 TP +3.3V -10V -10V OUT G1 TP OUT C13 10UF 10UF C7 TP +10V DS2 3 2 3 4 1 4 1 7 3 5 0 4 4 4 2 4 8 2 2 RB29 7 3 7 3 7 3 A K www.maximintegrated.com 5 OUT OUT OUT 5V_FPGA AGND GND OUT MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Figure 10f. MAX1121X EV Kit Schematic (Sheet 6 of 6) Maxim Integrated 24 MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Figure 11. MAX1121X EV Kit Component Placement Guide--Top Side www.maximintegrated.com Maxim Integrated 25 MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Figure 12. MAX1121X EV Kit PCB Layout--Layer 1 www.maximintegrated.com Maxim Integrated 26 MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Figure 13. MAX1121X EV Kit PCB Layout--Layer 2 www.maximintegrated.com Maxim Integrated 27 MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Figure 14. MAX1121X EV Kit PCB Layout--Layer 3 www.maximintegrated.com Maxim Integrated 28 MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Figure 15. MAX1121X EV Kit PCB Layout--Layer 4 www.maximintegrated.com Maxim Integrated 29 MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Figure 16. MAX1121X EV Kit PCB Layout--Layer 5 www.maximintegrated.com Maxim Integrated 30 MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Figure 17. MAX1121X EV Kit PCB Layout--Layer 6 www.maximintegrated.com Maxim Integrated 31 MAX1121X Family Evaluation Kit Evaluates: MAX11214/MAX11216 Figure 18. MAX1121X EV Kit Component Placement Guide--Bottom Side www.maximintegrated.com Maxim Integrated 32 MAX1121X Family Evaluation Kit Component List Refer to file "evkit_bom_max1121X_evkit_a.csv" attached to this data sheet for component information. Evaluates: MAX11214/MAX11216 Ordering Information PART TYPE MAX11214EVKIT# EVKIT MAX11216EVKIT# EVKIT #Denotes RoHS compliant. www.maximintegrated.com Maxim Integrated 33 Evaluates: MAX11214/MAX11216 MAX1121X Family Evaluation Kit Revision History REVISION NUMBER REVISION DATE 0 4/15 DESCRIPTION Initial release PAGES CHANGED -- For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated's website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. (c) 2015 Maxim Integrated Products, Inc. 34 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: MAX11214EVKIT# MAX11216EVKIT#