ISSI (R) IS65C1024AL PRELIMINARY INFORMATION AUGUST 2002 128K x 8 LOW POWER CMOS STATIC RAM FEATURES DESCRIPTION * High-speed access time: 55, 70 ns * Low active power: 50 mW (typical) * Low standby power: 100 W (typical) CMOS standby * Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications * Fully static operation: no clock or refresh required * TTL compatible inputs and outputs * Single 5V (10%) power supply * Temperature Offerings: Option A: 0C to 700C Option A1: -40C to +850C Option A2: -40C to +1050C Option A3: -40C to +1250C * Standard Pin Configuration: -- 32-pin SOP/ 32-pin TSOP (Type 1) The ISSI IS65C1024AL is a low power,131,072-word by 8bit CMOS static RAM. It is fabricated using high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 512 X 2048 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE1 CE2 OE WE CONTROL CIRCUIT Copyright (c) 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PREMINARY INFORMATION Rev. 00B 08/07/02 1 ISSI IS65C1024AL PIN CONFIGURATION PIN CONFIGURATION 32-Pin SOP 32-Pin TSOP (Type 1) NC 1 32 VCC A16 2 31 A15 A14 3 30 CE2 A12 4 29 WE A7 5 ISSI 28 A13 A6 6 65C1024 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE1 A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 GND 16 17 I/O3 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 PIN DESCRIPTIONS 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (R) OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 OPERATING RANGE A0-A16 Address Inputs Options Ambient Temperature VCC CE1 Chip Enable 1 Input A 0C to 70C 5V 10% CE2 Chip Enable 2 Input A1 -40C to +85C 5V 10% OE Output Enable Input A2 -40C to +105C 5V 10% WE Write Enable Input A3 -40C to +125C 5V 10% I/O0-I/O7 Input/Output Vcc Power GND Ground TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write 2 WE CE1 CE2 OE I/O Operation X X H H L H X L L L X L H H H X X H L X High-Z High-Z High-Z DOUT DIN Vcc Current ISB1, ISB2 ISB1, ISB2 I CC I CC I CC Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PREMINARY INFORMATION Rev. 00B 08/07/02 ISSI IS65C1024AL (R) ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value -0.5 to +7.0 -65 to +125 1.0 50 Unit V C W mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 5.0V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions VOH VOL VIH VIL ILI Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 2.1 mA ILO Output Leakage GND VOUT VCC CE1 = VIH, or CE2 = VIL, or OE = VIH or WE = VIL GND VIN VCC Options Min. Max. Unit A, A1 A2, A3 A, A1 A2, A3 2.4 -- 2.2 -0.5 -1 -10 -1 -10 -- 0.4 VCC + 0.5 0.8 1 10 1 10 V V V V A A Notes: 1. VIL = -3.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PREMINARY INFORMATION Rev. 00B 08/07/02 3 ISSI IS65C1024AL (R) POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -55 ns Min. Max. -70 ns Min. Max. Symbol Parameter Test Conditions Unit ICC Average operating Current CE1 = VIL, CE2 = VIH VIN = VIH or VIL, I I/O= 0 mA A A1 A2 A3 -- -- -- -- 10 10 15 15 -- -- -- -- 10 10 15 15 mA ICC1 Vcc Dynamic Operating Supply Current VCC = Max., CE1 = VIL IOUT = 0 mA, f = fMAX VIN = VIH or VIL CE2 = VIH A A1 A2 A3 -- -- -- -- 45 45 55 55 -- -- -- -- 45 45 55 55 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL, CE1 VIH, or CE2 VIL, f = 0 A A1 A2 A3 -- -- -- -- 2 2 5 5 -- -- -- -- 2 2 5 5 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., CE1 VCC - 0.2V, or CE2 0.2V, VIN VCC - 0.2V, or VIN VSS + 0.2V, f = 0 A A1 A2 A3 -- -- -- -- 40 40 50 50 -- -- -- -- 40 40 50 50 A Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter -55 ns Min. Max. -70 ns Min. Max. Unit tRC Read Cycle Time 55 -- 70 -- ns tAA Address Access Time -- 55 -- 70 ns tOHA Output Hold Time 10 -- 10 -- ns tACE1 CE1 Access Time -- 55 -- 70 ns tACE2 CE2 Access Time -- 55 -- 70 ns tDOE OE Access Time -- 35 -- 40 ns tLZOE(2) OE to Low-Z Output 5 -- 5 -- ns tHZOE OE to High-Z Output 0 20 0 25 ns (2) tLZCE1 CE1 to Low-Z Output 10 -- 10 -- ns tLZCE2(2) CE2 to Low-Z Output 10 -- 10 -- ns tHZCE(2) CE1 or CE2 to High-Z Output 0 20 0 25 ns (2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.6 to 2.4V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 4 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PREMINARY INFORMATION Rev. 00B 08/07/02 ISSI IS65C1024AL (R) AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.6V to 2.4V 5 ns 1.5V See Figures 1a and 1b AC TEST LOADS 1838 1838 5V 5V OUTPUT OUTPUT 100 pF Including jig and scope 993 5 pF Including jig and scope Figure 1a. 993 Figure 1b. AC WAVEFORMS READ CYCLE NO. 1(1,2) tRC ADDRESS tAA tOHA DOUT Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PREMINARY INFORMATION Rev. 00B 08/07/02 tOHA DATA VALID 5 ISSI IS65C1024AL (R) READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tHZOE tDOE CE1 tLZOE tACE1/tACE2 CE2 tLZCE1/ tLZCE2 tHZCE HIGH-Z DOUT DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power) Symbol Parameter -55 ns Min. Max. -70 ns Min. Max. Unit tWC Write Cycle Time 55 -- 70 -- ns tSCE1 CE1 to Write End 45 -- 60 -- ns tSCE2 CE2 to Write End 45 -- 60 -- ns tAW Address Setup Time to Write End 45 -- 60 -- ns tHA Address Hold from Write End 0 -- 0 -- ns tSA Address Setup Time 0 -- 0 -- ns tPWE(4) WE Pulse Width 40 -- 50 -- ns tSD Data Setup to Write End 25 -- 30 -- ns tHD Data Hold from Write End 0 -- 0 -- ns tHZWE(2) WE LOW to High-Z Output -- 20 -- 25 ns tLZWE(2) WE HIGH to Low-Z Output 5 -- 5 -- ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.6 to 2.4V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. 6 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PREMINARY INFORMATION Rev. 00B 08/07/02 ISSI IS65C1024AL (R) AC WAVEFORMS WE Controlled)(1,2) WRITE CYCLE NO. 1 (WE tWC ADDRESS tHA tSCE1 CE1 tSCE2 CE2 tAW tPWE(4) WE tSA DOUT tHZWE tLZWE HIGH-Z DATA UNDEFINED tSD DIN tHD DATA-IN VALID CE1 WRITE CYCLE NO. 2 (CE1 CE1, CE2 Controlled)(1,2) tWC ADDRESS tSA tHA tSCE1 CE1 tSCE2 CE2 tAW tPWE(4) WE tHZWE DOUT DATA UNDEFINED tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE = VIH. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PREMINARY INFORMATION Rev. 00B 08/07/02 7 ISSI IS65C1024AL (R) DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. VDR Vcc for Data Retention See Data Retention Waveform 2.0 IDR Data Retention Current Vcc = 2.0V, CE1 Vcc - 0.2V A, A1 or CE2 0.2V A2, A3 VIN VCC - 0.2V, or VIN VSS + 0.2V -- -- tSDR Data Retention Setup Time See Data Retention Waveform tRDR Recovery Time See Data Retention Waveform Typ. Max. Unit 5.5 V 40 50 A 0 -- ns tRC -- ns 5 10 Note: 1. Typical Values are measured at VCC = 5V, TA = 25oC and not 100% tested. CE1 Controlled) DATA RETENTION WAVEFORM (CE1 Data Retention Mode tSDR tRDR VCC 4.5V 2.2V VDR CE1 VCC - 0.2V CE1 GND DATA RETENTION WAVEFORM (CE2 Controlled) Data Retention Mode 4.5V VCC CE2 2.2V tSDR tRDR VDR 0.4V CE2 0.2V GND 8 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PREMINARY INFORMATION Rev. 00B 08/07/02 ISSI IS65C1024AL (R) PACKAGE INFORMATION 32pin 525mil Small Outline Package (Q) UNIT: INCH(mm) 0.444(11.278) 0.438(11.125) 0.810(20.574) 0.804(20.422) 0.564(14.326) 0.546(13.868) 0.109(2.769) 0.099(2.515) 0.011(0.279) 0.0125(0.318) 0.0061(0.155) 0.004(0.102) 0.0425(1.080) 0.050(1.27) BSC 0 deg 0.020(0.508) 0.0235(0.597) 8 deg 0.014(0.356) 32pin 8x20mm Small Outline Package (T) #32 #1 UNIT: INCH(mm) 0.319(8.103) 0.311(7.900) #16 #17 0.728(18.491) 0.720(18.288) 0.792(20.117) 0.784(19.914) 0.041(1.05) 0.037(0.95) 0.006(0.15) 0.002(0.05) 0.025(0.64) 0.008(0.21) 0.004(0.10) 0.020(0.50)BSC 0.011(0.27) 0.007(0.17) 0.021(0.54) Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PREMINARY INFORMATION Rev. 00B 08/07/02 9 ISSI IS65C1024AL (R) ORDERING INFORMATION Temperature Range (A): 0C to 70C Speed (ns) Order Part No. Package 55 55 IS65C1024AL-55QA IS65C1024AL-55TA Plastic SOP TSOP, Type 1 70 70 IS65C1024AL-70QA IS65C1024AL-70TA Plastic SOP TSOP, Type 1 Temperature Range (A1): -40C to +85C Speed (ns) Order Part No. Package 55 55 IS65C1024AL-55QA1 IS65C1024AL-55TA1 Plastic SOP TSOP, Type 1 70 70 IS65C1024AL-70QA1 IS65C1024AL-70TA1 Plastic SOP TSOP, Type 1 Temperature Range (A2): -40C to +105C Speed (ns) Order Part No. Package 55 55 IS65C1024AL-55QA2 IS65C1024AL-55TA2 Plastic SOP TSOP, Type 1 70 70 IS65C1024AL-70QA2 IS65C1024AL-70TA2 Plastic SOP TSOP, Type 1 Temperature Range (A3): -40C to +125C Speed (ns) Order Part No. Package 55 55 IS65C1024AL-55QA3 IS65C1024AL-55TA3 Plastic SOP TSOP, Type 1 70 70 IS65C1024AL-70QA3 IS65C1024AL-70TA3 Plastic SOP TSOP, Type 1 ISSI (R) Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com 10 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PREMINARY INFORMATION Rev. 00B 08/07/02