IDC Low Inductance Capacitors (RoHS) 0306/0612/0508 IDC (InterDigitated Capacitors) GENERAL DESCRIPTION 0612 + + - L - - Style 3 + 0508 0306 TYPICAL IMPEDANCE Impedance (Ohms) 10 MLCC_1206 1 LICC_0612 0.1 IDC_0612 0.01 0.001 1 10 100 1000 Frequency (MHz) LEAD-FREE COMPATIBLE COMPONENT HOW TO ORDER W - + Inter-Digitated Capacitors (IDCs) are used for both semiconductor package and board level decoupling. The equivalent series inductance (ESL) of a single capacitor or an array of capacitors in parallel determines the response time of a Power Delivery Network (PDN). The lower the ESL of a PDN, the faster the response time. A designer can use many standard MLCCs in parallel to reduce ESL or a low ESL Inter-Digitated Capacitor (IDC) device. These IDC devices are available in versions with a maximum height of 0.95mm or 0.55mm. IDCs are typically used on packages of semiconductor products with power levels of 15 watts or greater. Inter-Digitated Capacitors are used on CPU, GPU, ASIC, and ASSP devices produced on 0.13, 90nm, 65nm, and 45nm processes. IDC devices are used on both ceramic and organic package substrates. These low ESL surface mount capacitors can be placed on the bottom side or the top side of a package substrate. The low profile 0.55mm maximum height IDCs can easily be used on the bottom side of BGA packages or on the die side of packages under a heat spreader. IDCs are used for board level decoupling of systems with speeds of 300MHz or greater. Low ESL IDCs free up valuable board space by reducing the number of capacitors required versus standard MLCCs. There are additional benefits to reducing the number of capacitors beyond saving board space including higher reliability from a reduction in the number of components and lower placement costs based on the need for fewer capacitors. The Inter-Digitated Capacitor (IDC) technology was developed by AVX. This is the second family of Low Inductance MLCC products created by AVX. IDCs are a cost effective alternative to AVX's first generation low ESL family for high-reliability applications known as LICA (Low Inductance Chip Array). AVX IDC products are available with a lead-free finish of plated Nickel/Tin. 1 6 IDC Low Number Voltage Case Inductance of 4 = 4V Size Terminals 6 = 6.3V 2 = 0508 1 = 8 Terminals Z = 10V 3 = 0612 Y = 16V 4 = 0306 3 = 25V D 225 M T A 3 Dielectric Capacitance Capacitance Failure Termination Packaging Tolerance Rate T = Plated Ni C = X7R Code (In pF) Available D = X5R 2 Sig. Digits + M = 20% A = N/A and Sn 1=7" Reel Number of Z = X7S 3=13" Reel Zeros A Thickness Max. Thickness mm (in.) A=Standard S=0.55 (0.022) NOTE: Contact factory for availability of Termination and Tolerance Options for Specific Part Numbers. PERFORMANCE CHARACTERISTICS Capacitance Tolerance Operation Temperature Range Temperature Coefficient Voltage Ratings Dissipation Factor Insulation Resistance (@+25C, RVDC) 72 20% Preferred X7R = -55C to +125C X5R = -55C to +85C X7S = -55C to +125C 15% (0VDC), 22% (X7S) 4, 6.3, 10, 16, 25 VDC 6.3V = 6.5% max; 10V = 5.0% max; 16V = 3.5% max 100,000M min, or 1,000M per F min.,whichever is less Dielectric Strength No problems observed after 2.5 x RVDC for 5 seconds at 50mA max current CTE (ppm/C) 12.0 Thermal Conductivity 4-5W/M K Terminations Available Plated Nickel and Solder IDC Low Inductance Capacitors (RoHS) 0306/0612/0508 IDC (InterDigitated Capacitors) SIZE 0306 Thin 0508 0508 Thin 0612 0612 THICK 0612 Max. mm Thickness (in.) WVDC Cap (F) 0.010 0.55 (0.022) 0.55. (0.022) 6.3 10 16 0.95 (0.037) 6.3 10 16 0.55 (0.022) 6.3 10 0.95 (0.037) 6.3 10 16 1.22 (0.048) 6.3 10 4 6.3 4 25 4 25 4 16 4 25 4 16 0.022 0.033 0.047 0.068 0.10 0.22 0.33 0.47 0.68 1.0 1.5 2.2 3.3 Consult factory for additional requirements PHYSICAL DIMENSIONS AND PAD LAYOUT W = X7R = X5R P = X7S T E D BW A B C BL L PHYSICAL CHIP DIMENSIONS SIZE 0306 0508 0612 PAD LAYOUT DIMENSIONS millimeters (inches) W L BW BL P 1.60 0.20 (0.063 0.008) 2.03 0.20 (0.080 0.008) 3.20 0.20 (0.126 0.008) 0.82 0.10 (0.032 0.006 1.27 0.20 (0.050 0.008) 1.60 0.20 (0.063 0.008) 0.25 0.10 (0.010 0.004) 0.30 0.10 (0.012 0.004) 0.50 0.10 (0.020 0.004) 0.20 0.10 (0.008 0.004) 0.25 0.15 (0.010 0.006) 0.25 0.15 (0.010 0.006) 0.40 0.05 (0.015 0.002) 0.50 0.05 (0.020 0.002) 0.80 0.10 (0.031 0.004) SIZE A B C D E 0.38 0.89 1.27 0.20 0.40 0306 (0.015) (0.035) (0.050) (0.008) (0.015) 0.64 1.27 1.91 0.28 0.50 0508 (0.025) (0.050) (0.075) (0.011) (0.020) 0.89 1.65 2.54 0.45 0.80 0612 (0.035) (0.065) (0.010) (0.018) (0.031) 73 IDC Low Inductance Capacitors (SnPb) 0306/0612/0508 IDC with Sn/Pb Termination GENERAL DESCRIPTION 0612 + - + - 0508 + - + - 0306 TYPICAL IMPEDANCE 10 Impedance (Ohms) Inter-Digitated Capacitors (IDCs) are used for both semiconductor package and board level decoupling. The equivalent series inductance (ESL) of a single capacitor or an array of capacitors in parallel determines the response time of a Power Delivery Network (PDN). The lower the ESL of a PDN, the faster the response time. A designer can use many standard MLCCs in parallel to reduce ESL or a low ESL Inter-Digitated Capacitor (IDC) device. These IDC devices are available in versions with a maximum height of 0.95mm or 0.55mm. IDCs are typically used on packages of semiconductor products with power levels of 15 watts or greater. Inter-Digitated Capacitors are used on CPU, GPU, ASIC, and ASSP devices produced on 0.13, 90nm, 65nm, and 45nm processes. IDC devices are used on both ceramic and organic package substrates. These low ESL surface mount capacitors can be placed on the bottom side or the top side of a package substrate. The low profile 0.55mm maximum height IDCs can easily be used on the bottom side of BGA packages or on the die side of packages under a heat spreader. IDCs are used for board level decoupling of systems with speeds of 300MHz or greater. Low ESL IDCs free up valuable board space by reducing the number of capacitors required versus standard MLCCs. There are additional benefits to reducing the number of capacitors beyond saving board space including higher reliability from a reduction in the number of components and lower placement costs based on the need for fewer capacitors. The Inter-Digitated Capacitor (IDC) technology was developed by AVX. This is the second family of Low Inductance MLCC products created by AVX. IDCs are a cost effective alternative to AVX's first generation low ESL family for high-reliability applications known as LICA (Low Inductance Chip Array). AVX IDC products are available with a lead termination for high reliability military and aerospace applications that must avoid tin whisker reliability issues. MLCC_1206 1 LICC_0612 0.1 IDC_0612 0.01 0.001 1 10 100 1000 Frequency (MHz) Not RoHS Compliant HOW TO ORDER L 3 L 1 6 D 225 M B A 3 Voltage Dielectric Capacitance Capacitance Failure Termination Packaging Tolerance Rate B = 5% min. C = X7R Code (In pF) Available 4 = 4V Lead 1=7" Reel 6 = 6.3V D = X5R 2 Sig. Digits + M = 20% A = N/A Number of 3=13" Reel Z = 10V Z = X7S Zeros Y = 16V 3 = 25V NOTE: Contact factory for availability of Termination and Tolerance Options for Specific Part Numbers. Style IDC Low Number Case Inductance of Size Terminals 2 = 0508 1 = 8 Terminals 3 = 0612 4 = 0306 A Thickness Max. Thickness mm (in.) A=Standard S=0.55 (0.022) PERFORMANCE CHARACTERISTICS Capacitance Tolerance Operation Temperature Range Temperature Coefficient Voltage Ratings Dissipation Factor Insulation Resistance (@+25C, RVDC) 74 20% Preferred X7R = -55C to +125C X5R = -55C to +85C X7S = -55C to +125C 15% (0VDC), 22% (X7S) 4, 6.3, 10, 16, 25 VDC 6.3V = 6.5% max; 10V = 5.0% max; 16V = 3.5% max 100,000M min, or 1,000M per F min.,whichever is less Dielectric Strength No problems observed after 2.5 x RVDC for 5 seconds at 50mA max current CTE (ppm/C) 12.0 Thermal Conductivity 4-5W/M K Terminations Available Plated Nickel and Solder IDC Low Inductance Capacitors (SnPb) 0306/0612/0508 IDC with Sn/Pb Termination SIZE 0306 Thin 0508 0508 Thin 0612 0612 THICK 0612 Max. mm Thickness (in.) WVDC Cap (F) 0.010 0.55 (0.022) 0.55. (0.022) 6.3 10 16 0.95 (0.037) 6.3 10 16 0.55 (0.022) 6.3 10 0.95 (0.037) 6.3 10 16 1.22 (0.048) 6.3 10 4 6.3 4 25 4 25 4 16 4 25 4 16 0.022 0.033 0.047 0.068 0.10 0.22 0.33 0.47 0.68 1.0 1.5 2.2 3.3 Consult factory for additional requirements PHYSICAL DIMENSIONS AND PAD LAYOUT W = X7R = X5R P = X7S T E D BW A B C BL L PHYSICAL CHIP DIMENSIONS SIZE 0306 0508 0612 PAD LAYOUT DIMENSIONS millimeters (inches) W L BW BL P 1.60 0.20 (0.063 0.008) 2.03 0.20 (0.080 0.008) 3.20 0.20 (0.126 0.008) 0.82 0.10 (0.032 0.006 1.27 0.20 (0.050 0.008) 1.60 0.20 (0.063 0.008) 0.25 0.10 (0.010 0.004) 0.30 0.10 (0.012 0.004) 0.50 0.10 (0.020 0.004) 0.20 0.10 (0.008 0.004) 0.25 0.15 (0.010 0.006) 0.25 0.15 (0.010 0.006) 0.40 0.05 (0.015 0.002) 0.50 0.05 (0.020 0.002) 0.80 0.10 (0.031 0.004) SIZE A B C D E 0.38 0.89 1.27 0.20 0.40 0306 (0.015) (0.035) (0.050) (0.008) (0.015) 0.64 1.27 1.91 0.28 0.50 0508 (0.025) (0.050) (0.075) (0.011) (0.020) 0.89 1.65 2.54 0.45 0.80 0612 (0.035) (0.065) (0.010) (0.018) (0.031) 75