19-0108; Rev 1; 8/93 General Description The MAX121 is a complete, BICMOS, serial-output, sam- pling 14-bit analog-to-digital converter (ADC) that com- bines an on-chip track/hold and a low-drift, low-noise, buried-zener voltage reference with fast conversion speed and low power consumption. The throughput rate is as high as 308k samples per second (ksps). The full-scale analog input range is +5V. The MAX121 utilizes the successive-approximation ar- chitecture with a high-speed DAC to achieve both fast conversion speeds and low-power operation. Operating with +5V and -12V or -15V power supplies, power con- sumption is only 210mW. The MAX121 can be directly interfaced to the serial port of most popular digital-signal processors, and comes in space-saving 16-pin DIP and SO and smaller 20-pin SSOP packages. The MAX121 operates with TTL- /CMOS-compatible clocks in the frequency range from 0.1MHz to 5.5MHz. All logic inputs and outputs are TTL/CMOS compatible. This data sheet includes ap- plication notes for easy interface to TMS320, pPD77230, and ADSP2101 digital-signal processors, as well as Ps using the Motorola SPI and QSPI interface standards. Applications Digital Signal Processing Audio and Telecom Processing Speech Recognition and Synthesis DSP Servo Control Spectrum Analysis MAALAM 308ksps ADC with DSP Interface and 78dB SINAD Features 14-Bit Resolution @ 2.91s Conversion Time/308ksps Throughput # 400ns Acquisition Time @ Low Noise and Distortion: 78dB SINAD -85dB THD @ +5V Bipolar Input Range, Overvoltage Tolerant to +15V # 210mW Power Dissipation @ Continuous-Conversion Mode Available @ 30ppn//C, -5V Internal Reference @ Interfaces to DSP Processors @ 16-Pin DIP and SO Packages, 20-Pin SSOP Package KOoLXVIWN Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX121CPE 0C to +70C 16 Plastic DIP MAX121CWE OC to +70C 16 Wide SO MAX121CAP 0C to +70C 20 SSOP** MAX121C/D 0C to +70C Dice* Ordering Information continued on last page. * Contact factory for dice specifications. ** 20-pin SSOP is 50% smaller than 16-pin SOIC. Functional Diagram Pin Configurations BUFFER SAMPLING [2 COMPARATOR | AGND TOP VIEW AIN| 3k TRACK/HOLD ~ | OGND vss [| M He] MODE ; > | ss Voo [2 His] CS VREF | Cc AN [3] AALADCLAA [14] CLKIN ver fa) = MAX127_ Fis) const Leave AGND [5] Ha] SCLK = CLK INVCLK SDATA REFERENCE cre __ [6 4 INVERM [7| HO] FSTAT CLKIN| || CONTROL LOGIC SFRM Dano Fa Fa] see ro Z Ig 3 ie E DIP/SO 3 =z Pin Contigurations continued on last page. PA AXLRA Maxim integrated Products 7-25 Call toll free 1-800-998-8800 for free samples or literature.MAX121 308ksps ADC with DSP Interface and 78dB SINAD ABSOLUTE MAXIMUM RATINGS Vpop toDGND ... 0.2 ee eee -0.3V to +6V Continuous Power Dissipation (Ta = +70C) VsstoDGND ..0.0 000000. +0.3V to -17V 16-Pin Plastic DIP (derate 10.53mW/C above +70C) 842mW AINtoAGND ..0. 0.0... +15V 16-Pin Wide SO (derate 9.52mW/C above +70C) ... 762mW AGNDtoDGND 2... eee +0.3V 20-Pin SSOP (derate 8.00mW/C above +70C) ..... 640mW Digital inputstoDGND ................ -0.3V, (VoD + 0.3V) 16-Pin CERDIP (derate 10.00mW/'C above +70C) .. 8300mW (CS, CONVST, MODE, CLKIN, INVCLK, INVFRM) Operating Temperature Ranges: Digital Outputs to DGND .............. +0.3V, (VoD + 0.3V) MAX121C_ cee eee 0C to +70C (SFRM, FSTRT, SCLK, SDATA) MAX121E_ eee -40C to +85C MAXI2Z1MJE 20... eee -55C to +125C Storage Temperature Range .............. 65C to +160C Lead Temperature (soldering, 10sec) .............. +300C Stresses beyond those listed under Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VoD = 4.75V to 5.25V, Vss = -10.8V to -15.75V, MAX121C/E foLk = 5.5MHz, MAX121M folk = 5MHz, Ta = TMIN to TMAx, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS DYNAMIC PERFORMANCE (MAX121C/E: fs = 308kHz, AIN = 10Vp-p, 50kHz) (MAX 121M: fg 278kHz, AIN = 10Vp-p, 50kHz) . . . oo MAX121C 75 78 Signal-to-Noise Ratio SINAD | Including distortion dB MAX121E/M 73 77 a . ag . MAX121C/E -85 -77 Total Harmonic Distortion THD First five harmonics dB MAX121M -83 -76 . . MAX121C/E 77 86 Spurious-Free Dynamic Range SFDR dB MAX121M 76 84 ACCURACY Resolution RES 14 Bits Differential Nonlinearity (Note 1) DNL 12 bits no missing codes over temp. range +1.5 LSB Integral Nonlinearity INL +2 LSB . Code 00..00 to 00..01 transition, near AIN = OV +10 mV Bipolar Zero Error - Temperature drift +1 ppm/C . Including reference; adjusted for bipolar zero Full-Scale Error (Notes 1, 2) error. Ta = #25C 40.2 % Full-Scale Temperature Drift Excluding reference 41 ppm/C Vop only, 5Vt5% +1/2 +2 Power-Supply Rejection Vss only, -12V +10% +1 +2 LSB Vss only, -15V +5% +1 +2 ANALOG INPUT Input Range 5 +5 Vv Input Current AIN = 5V (Rin approximately 6kQ to REF) 2.5 mA Input Capacitance (Note 3) 10 pF Full-Power Bandwidth 1.5 MHz 7-26 MAXLAN308ksps ADC with DSP Interface and 78dB SINAD ELECTRICAL CHARACTERISTICS (continued) (VoD = 4.75V to 5.25V, Vss = -10.8V to -15.75V, MAX121C/E fcLk = 5.5MHz, MAX121M fcLk = 5MHz, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX [UNITS REFERENCE Output Voltage No external load, AIN = 5V, Ta = +25C -5.02 -4.98 Vv External Load Regulation OmA < ISINK < 5mA, AIN = OV 5 mV Temperature Drift (Note 4) MAMeICE #80 {pem/c MAX121M +35 CONVERSION TIME i MAX121C/E 2.91 Synchronous ICONV 16 tCLK | MAX121M 3.20 ys Clock Frequency fCLK MAN ZICIE o 58 MHz " MAX121M 01 5.0 DIGITAL INPUTS (CLKIN, CONVST, CS) Input High Voltage VIH 2.4 v Input Low Voltage Vit 0.8 V Input Capacitance (Note 3) 10 pF Input Current Vpp = OV or Vop +5 pA DIGITAL OUTPUTS (SCLK, SDATA, FSTRT, SFRM) Output Low Voltage VOL ISINK = 1.6mA 0.4 Vv Output High Voltage VOH ISOURCE = 1mA Vop- 0.5 Vv Leakage Current ILKG VouT = OV or Vob +5 BA Output Capacitance (Note 3) 10 pF POWER REQUIREMENTS Positive Supply Voltage Vpb By supply-rejection test 475 5.25 Vv Negative Supply Voltage Vss By supply-rejection test -10.8 -15.75 Vv Positive Supply Current lop v S ) = Set SS iope aN = OV, 9 15 mA Negative Supply Current iss CRP see $8 One OM AIN = OV, 14 20 | mA Power Dissipation CR est = Mobe eve 213 315 | mw Note 1: These tests are performed at Vpp = +5V, Vss = -15V. Operation over supply is guaranteed by supply-rejection tests. Note 2: Ideal full-scale transition is at +5V - 3/2LSB = +4.9991V, adjusted for offset error. Note 3: Guaranteed, not tested. Note 4: Temperature drift is defined as the change in output voltage from +25C to TmIn or TMAX. It is calculated as TC = (AVREF/VREF) / AT. MA AXLAA 7-27 S x = N =kMAX121 308ksps ADC with DSP Interface and 78dB SINAD TIMING CHARACTERISTICS (VoD = 5V, Vsg = -12V or -15V, Ta = TMIN to TMax, unless otherwise noted.) (Note 5) Ta =+25C MAX121C/E MAX121M PARAMETER SYMBOL | CONDITIONS UNITS MIN TYP MAX | MIN MAX MIN MAX CONVST Pulse Width (Note 6) tow 20 30 35 ns Data-Access Time {DA CL=50pF 25 50 65 80 ns Data-Hold Time tDH | 25 50 65 80 ns CLKIN to SCLK {CD Cy = 50pF 40 65 85 105 ns : SCLK to SDATA Skew tsc CL = 50pF +65 +80 +100 ns | SCLK to SFRM or FSTRTSkew| tsc__| Cu = 50pF $25 +35 +40 ns | Acquisition Time (Note 6) tag 400 400 400 ns , Aperture Delay tap 10 ns Aperture Jitter 30 ps Clock Setup/Hold Time tcK | 10 50 10 50 10 50 ns Note 5: Control! inputs specified with tr = tt = 5ns (10% to 90% of +5V) and timed from a voltage ievel of 1.6V. Output delays are measured to +0.8V if going low, or +2.4V if going high. For a data-hold time, a change of 0.5V is measured. See Figures 4 and 5 for load circuits. Note 6: Guaranteed, but not tested. Pin Description r PIN : FUNCTION {1 NAME DIP/SO| SSOP | a 1 1 Vss Negative Power Supply: -12V or -15V 2 2 Voo Positive Power Supply: +5V 3 3 AIN Sampling Analog Input: +5V bipolar input range 4 4 VREF -5V Reference Output. Bypass to AGND with 22yF IL 0. 1pF. 15 7 AGND Analog Ground | 6 8 INVCLK | Invert Serial Clock. Connect to DGND to invert the SCLK output (relative to CLKIN). / | Invert Serial Frame. This input sets the polarity of the SFRM output as follows: 7 7 9 INVFRM lf INVFRM = DGND, SFRM is high during a conversion. if INVFRM = Vop, SFRM is low during a conversion. 8 10 | DGND | Digital Ground 9 11 SFRM | Serial Frame Output. Normally high (INVFRM = Vpp), falls at the beginning of the conversion and rises at the end (after 16 tcLk) signaling the end of a 16-bit frame. 10 12 FSTRT | Frame Start Output. High pulse that lasts one clock cycle, falling edge indicates that a valid MSB is available. 11 13 SDATA | Serial Data Output. MSB first, twos-complement binary output code. 12 14 SCLK Serial Clock Output. Same polarity as CLKIN if INVCLK = Vpp, inverted CLKIN if INVCLK = DGND. Note that SCLK runs whenever CLKIN is active. i 13 17__| CONVST | Active-Low Convert Start Input. Conversions are initiated on falling edges. 14 18 CLKIN Clock input. Supply a TTL-/CMOS-compatible clock from 0.1MHz to 5.5MHz, 40%-60% duty cycle. 15 19 cS Active-Low Chip-Select input. CS = DGND enables the three-state outputs. Also, if CONVST is low, initiates a conversion on the falling edge of CS. 16 20 MODE | Hardwire to set operational mode: Vpp: single conversions, DGND: continuous conversions _ 2 oe N.C, No Connect - not internally connected. 7-28 MAXIAA308ksps ADC with DSP Interface and 78dB SINAD AGND tI 0. 1OuF -ravpsgyoOtmEy Y10HF |, MODE Pye +V0__ 94 Vop cs {pF 10uF 0. BY TS MAXIM agND CLOCK ANALOG = = AN MAXTZT CNT og pit Cte VREF CONVST + DGND O.1pF = 22uF = pes AGND sclk >) acno INVCLK TO SDATA f#- > SERIAL PORT Vpp (NVFRM FSTRT |-___. DGND DGND t+ SAMPLING Choy COMPARATOR 7pF 3k TRACK BUFFER figure 1. MAX121 In the Simplest Operational Mode (Continuous-Conversion Mode) Detailed Description ADC Operation The MAX121 uses successive approximation and input track/hold (T/H) circuitry to convert an analog signal to a 14-bit serial digital output code. The control logic inter- faces easily to most microprocessors (Ps) and digital- signal processors (DSPs), requiring only a few passive components for most applications. The T/H does not require an external capacitor. Figure 1 shows the MAX121 in its simplest operational configuration. Analog Input Track/Hold The Equivalent Input Circuit (Figure 2), illustrates the sampling architecture of the ADCs analog comparator. An internal buffer charges the hoid capacitor to minimize the required acquisition time between conversions. The analog input appears as a 6kQ resistor in parallel with a 10pF capacitor. Between conversions, the buffer input is connected to AIN through the input resistance. When a conversion starts, the buffer input is disconnected from AIN, thus sampling the input. At the end of the conversion, the buffer input is reconnected to AIN, and the hold capacitor tracks the input voltage. The T/H is in its tracking mode whenever a conversion is not in progress. Hold mode starts approximately 10ns after a conversion is initiated (aperture delay). The vari- ation in this delay from one conversion to the next (aper- ture jitter) is typically 30ps. Figures 7-9 detail the track/hold mode and interface timing for the three differ- ent interface modes. PAAXIAA Figure 2. Equivalent Input Circuit Internal Reference The MAX121 -5.00V buried-zener reference biases the internal DAC. The reference output is available at the VREF pin and must be bypassed to the AGND pin with a 0.1pF ceramic capacitor in parallel with a 22uF or greater electrolytic capacitor. The electrolytic capacitor's equivalent series resistance (ESR) must be 100mQ or less to properly compensate the reference output buffer. Sanyos organic semiconductor capaci- tors work well; telephone and FAX numbers are pro- vided below. Sanyo Video Components (USA) Phone: (619) 661-6835 FAX: (619) 661-1055 Sanyo Electric Company, LTD. (Japan) Phone: 0720-70-1005 FAX: 0720-70-1174 Sanyo Fisher Vertriebs GmbH (Germany) Phone: 06102-27041, ext. 44 FAX: 06102-27045 Proper bypassing minimizes reference noise and main- tains a low impedance at high frequencies. The internal- reference output buffer can sink up to 5mA from an external load. An external reference voltage can be used to overdrive the MAX121s internal reference, if the external refer- ence lies within the range from -5.05V to -5.10V. The external reference must be capable of sinking a mini- mum of 5mA. The external VREF bypass capacitors are still required. 7-29 KoLXVWMAX121 308ksps ADC with DSP Interface and 78dB SINAD SDATA, SCLK, SFRM+FSTRT ic IMPEDANCE HIGH IMPEDANCE OUTPUTS ENABLED Figure 3. Data-Access + Data-Hold Timing External Clock The MAX121 requires a TTL-/CMOS-compatible clock for proper operation. The MAX121 accepts clocks in the frequency range from 0.1MHz to 5.5MHz when operating in mode 1 or mode 2 (see Operating Modes section). To satisfy the 400ns acquisition-time require- ment with 2 clock cycles, the maximum clock frequency is limited to 5MHz when operating in mode 3 (continu- ous-conversion mode). The minimum clock frequency in all modes is limited to 0.1MHz due to the droop rate of the internal T/H. Output Data Format The conversion result is output as a 16-bit serial data stream, starting with the 14 data bits (MSB first) followed by 2 trailing zeros. The format of the output data is twos-complement binary. Data is clocked out of the SDATA pin on the rising edge of CLKIN. The output data can be framed using either the FSTRT or the SFRM output. FSTRT (normally low) goes high for 1 clock cycle preceding the MSB. A falling edge on FSTRT indicates that the MSB is available on the SDATA output. The SFRM output (normally high when INVFRM = Vpp) goes low coincident with the MSB appearing at the SDATA pin. SFRM returns high 16 clock cycles later. The polarity of SFRM can be inverted by tying the INVFRM input to DGND. A minimum of 18 clock cycles per conversion is required to obtain a valid SFRM output. See Figure 3 for the data-access and data-hold timing diagram if several devices share the serial bus. The equivalent load circuits for data-access and data-hold timing are shown in Figures 4 and 5. Digital Interface The MAX121 serial interface is compatible with SP! and QSPI serial interfaces. In addition, two framing signals (FSTRT and SFRM) are provided to allow the MAX121 to easily interface to most digital-signal processors (DSP) 7-30 SERIAL OUTPUTS SERIAL OUTPUTS. 3k G C. T [ L LL = DGND = = a. High-Z to Vou (toa) b. High-Z to Vor (toa) Figure 4. Load Circuits for Data-Access Time SERIAL OUTPUTS SERIAL OUTPUTS 3k 10pF = 10pF I te DGND = DGND = a. Vou to High-Z (tpH) b. Vor to High-Z (tox) Figure 5. Load Circuits for Data-Hold Time ENABLE DIGITAL OUTPUTS CONVERSION A tS SD ADC BUSY CONVST f qe_tt Figure 6. Conversion Control Logic with no external glue logic. The INVCLK input inverts the phase of SCLK relative to CLKIN, and the INVFRM input inverts the phase of the SFRM output. These control signals allow the MAX121 to directly interface to devices with many different serial-interface standards. Specific information for interfacing the MAX121 with SPI, QSPI and several DSP devices is included in the Applications Infor- mation section. MAXISA308ksps ADC with DSP Interface Timing and Control The MAX121 has 3 possible modes of operation, as outlined in the timing diagrams of Figures 7-9 and dis- cussed in the Operating Modes section. tn Mode 1, the CONVST input is used to control the start of the conversion. Mode 1 is intended for DSP and other applications where the analog input must be sampled at a precise instant in time. In Mode 2, the CS input controls the start of the conver- sion. This mode is useful when several devices are multiplexed on the same serial data bus, since the MAX121 outputs are placed in a high-impedance state when CS is pulled high. Mode 3 is the continuous-conversion mode. This mode is intended for data logging and similiar applications where the MAX121 is directly linked to memory through a first-in/first-out (FIFO) buffer or a direct memory access (DMA) port. In all three operating modes, the start of conversion is contralied by either the CS or the CONVST input. Both of these inputs must be low for a conversion to take place. Figure 6 shows the logic equivalent for the conversion circuitry. Once the conversion is in progress, it cannot be restarted. and 78dB SINAD Operating Modes Mode 1: CONVST Controls Conversion Starts (MODE = Vop, CS = DGND) Figure 7 shows the timing diagram for mode 1. In this mode, conversion start operations are controlled by the CONVST input. A falling edge on the CONVST input places the T/H into the hold mode and starts a conversion in the successive- approximation register (SAR). The FSTRT (normally low) output goes high on the next rising clock edge and remains high for one clock cycle. On the next rising clock edge, FSTRT goes low and the SFRM output goes low (INVFRM = Vpp), indicating that the MSB is ready to be latched. SFRM remains high for 16 clock cycies (14 data bits plus 2 trailing zeros). The T/H amplifier returns to the track mode when the 14th bit (DO) is clocked out of the SDATA pin. A new conver- sion can be initiated by the CONVST input after the 400ns minimum acquisition time has been satisfied. CS must be low to start a conversion. In applications where the MAX121 interfaces with a dedicated serial port, CS can be hardwired to DGND. To interface the MAX121 to a multiplexed serial bus, CS can be externally driven low to enable conversions, or driven high to place the serial outputs into a high-impedance state. CONVST . CLKIN ___ SFRM , . (INVFRM = Vop} | | \ | La a ' oF FSTRT to. \ by] / NSB 0 f SDATA (VER oo) Au PsA FB. SLL NL tap TH HOLD ee TRACK rk '-_ aq. * THESE CLOCK CYCLES MAY BE OMITTED IF THE SFAM SIGNAL IS NOT NEEDED | o Figure 7. CONVST Controls Conversion Starts (Mode 1) PMAMNXIAA 7-3A LOLXVUINMAX121 308ksps ADC with DSP Interface and 78dB SINAD Mode 2: GS Controls Conversion Starts (MODE = Vop, CONVST = DGND) Figure 8 shows the timing diagram for mode 2. In mode 2, CS controis the conversion start and enables the serial output pins. Mode 2 is useful in applica- tions where the MAX121 shares the output data bus with other devices. When CS is driven high, the MAX121 is disabled and its serial outputs (SCLK, SDATA, SFRM and FSTRT) are placed into a high-im- pedance state. A falling edge on the CS input places the T/H into the hold mode and starts a conversion in the SAR. The FSTRT and SFRM outputs can be used to frame the output data as described in the mode 1 section. CS must remain low for the duration of the conversion. The T/H amplifier returns to the track mode when the 14th bit (DO) is clocked out of the SDATA pin. A new conver- sion can be initiated by the CS input after the 400ns acquisition time has been satisfied. Mode 3:_Continuous-Conversion Mode (CONVST = CS = MODE = DGND) For applications that do not require precise control of sampling in time, such as data logging, the MAX121 can operate in continuous-conversion mode, directly linked to memory through DMA ports or a FIFO buffer. in this mode, conversions are performed continuously at the rate of one conversion for every 16 clock cycles, which includes 2 clock cycles for the T/H acquisition time. To satisfy the 400ns minimum acquisition-time requirement within 2 clock cycles, the MAX121's maxi- mum clock frequency is limited to 5MHz when operating in mode 3. The FSTRT output is used to frame data, as described in the mode 1 section and the mode 3 timing diagram (Figure 9). The SFRM output is meaningless in mode 3, since it will not change state. The MODE input should be hardwired to DGND, since this input must be low when the MAX121 powers up for proper operation of mode 3. To disable conversions, drive CONVST high. To put the serial outputs into a high-impedance state, drive CS high. SCLK HIGH 1 (INVCLK =Vop) IMPEDANCE tcp HIGH SDATA pEDANCE \ CLKIN ___SFRM HIGH HIGH (NVERM = Vo0) yypepaNcEt IMPEDANCE HIGH HIGH FSTAT i MpEDANCET _ IMPEDANCE HIGH IMPEDANCE HIGH IMPEDANCE HOLD TH TRACK tap THESE CLOCK CYCLES MAY BE OMITTED IF THE SFRM SIGNAL IS NOT NEEDED Figure 8. CS Controls Conversion Starts (Mode 2) 7-32 MAAXILAN308ksps ADC with DSP Interface Applications Information initialization After Power-Up Upon power-up, the first conversion of the MAX121 will be valid if the following conditions are met: 1) Allow 16 clock cycles for the internal T/H to enter the track mode, plus a minimum of 400ns in the track mode for the data-acquisition time. 2) Make sure the reference voltage has settled. Allow 0.5ms for each 1pF of reference bypass capacitance (11ms for a 22uF capacitor). Clock and Control Synchronization If the clock and conversion start inputs (CONVST or CS see Operating Modes section) are.not synchronized, the conversion time can vary from 15 to 16 clock cycles. The SAR always changes state on the rising edge of the CLKIN input. To ensure a fixed conversion time, refer to Figure 10 and the following guidelines: For a conversion time of 15 clock cycles, the conversion start input(s) should go low at least 50ns before the next rising edge of CLKIN. For a conversion time of 16 clock cycles, the conversion start input(s) should go low within and 78dB SINAD 10ns of the next rising edge of CLKIN. If the conversion start input(s) go low from 10ns to 50ns before the next rising edge of CLKIN, the number of clock cycles re- quired is undefined and can be either 15 or 16. For best analog performance, the conversion start inputs must be synchronized with CLKIN. CONVST or CS L tek CLKIN _" THE TIMING RELATIONSHIP BETWEEN CLKIN AND CONVST 0 OR CS DETERMINES IF A CLOCK CYCLE SLIPS OR NOT. USE THE FOLLOWING RU IF tcx < 10ns, CONVERSION TIME= 1 CLOCK EDEES IF tcx > 50ns, CONVERSION TIME = 15 CLOCK EDGES IF 10ns< tex < 50ns, CONVERSION TIME IS INDETERMINATE (15 OR 16) Figure 10. Clock and Control Synchronization 15 16 1 13 CLKIN FSTRT Of a 15 16 1 __ SCLK (INVCLK = Von) y SDATA LSB \ / MSB < HOLD 3 TRACK 14 15 16 1 14 15 16 1 x LSB \ MSB Figure 9. Continuous-Conversion Mode (Mode 3) PAAXLAA 7-33 KoLXUVINMAX121 308ksps ADC with DSP Interface and 78dB SINAD Maximum Clock Rate for Serial interface The maximum serial clock rate depends upon the mini- mum setup time required by the receiving processor's serial data input and the ADCs maximum clock-to-data delay. The MAX121 allows two fundamentally different methods of clocking data into the processor. In the first clocking method, CLKIN is both the input clock to the MAX121 and the serial clock for the processor. With the second method, CLKIN is the input clock for the MAX121 while SCLK is the serial clock for shifting data into the processor. (See Figure 11.) The first method would generally be used with simple serial-interface standards (such as SPI) where the processor does not support asynchronous data transfers. The maximum clock-to-data delay would be tcp + tsc. For this case, calculate the maximum serial clock rate with the following formula: fCLKIN = (1/2) x 1/(tsu + tcD + tsc) where tsu is the minimum data setup time required at the processor serial data input, tcD is the maximum CLKIN- to-SCLK delay of the MAX121, and tsc is the maximum SCLK-to-SDATA delay for the MAX121. The second type of interface is intended for applications where the processor supports asynchronous data trans- fers. The SCLK output of the MAX121 drives the serial clock of the processor, eliminating the tcp term from the above equation and allowing the use of faster clocks. For this case, calculate the maximum serial clock rate with the following formula: TCLKIN = (1/2) x 1Xtsu + tsc) where the variables are as defined above. Motorola SPI Serial interface (CPOL = 0, CPHA = 1) Figure 13 shows the MAX121 and processor interface connections required to support the SPI standard. Fig- ure 12 shows the SPI interface timing diagram. For SPI interfaces, the processor SS input should be pulled high, to configure the processor as the master. An I/O port from the processor drives the MAX121 CONVST (mode 1) or CS (mode 2) low to control the conversion starts. The SCK output of the processor will drive the CLKIN of the MAX121. The MISO 1/O of the processor is driven by the SDATA output of the MAX121. The SPI standard requires that all data transfers occur in blocks of 8 bits, but the MAX121 outputs data in 16-bit blocks. Therefore, two 1-byte read operations are required to receive the full 14 data bits from the MAX121. Aconversion is initiated by driving the processor I/O port low. Next, a write operation must be performed by the processor to activate the serial clock and read the first 8 bits of data from the MAX121. The MAX121 output data transitions on the rising edge of the clock. The processor reads data on the falling edge of the clock (CPHA = 1). This provides one half clock cycle to satisfy the minimum setup and hold time require- ment of the processor data input. The maximum clock rate for SPI interfaces is 2MHz. CLKIN le tcp >} tco _____. SCLK (INVCLK = Vop) tsc* SDATA, FSTRT, SFRM isc CAN BE POSITIVE OR NEGATIVE Figure 11. Timing Diagram for Serial Data 7-34 MAAXLMA308ksps ADC with DSP Interface and 78dB SINAD The first byte of data read by the processor will consist of = a leading zero followed by the 7 MSBs of data. A second write operation should then be initiated to read the second 45N > byte of data, which contains the 7 LSBs of conversion data < followed by a trailing zero. To minimize errors due to vo CONVST droop of the MAX121 internal T/H, limit the maximum time PROCESSOR mam | and, delay between the conversion start and the end of the sck MAXI21 '\ N second read operation to no more than 160us. ss CLIN, INVERM ak, Motorola QSPI Serial interface CPOL =0 s (CPOL = 0, CPHA = 1) CPHA=1 MISO SDATA Figure 14 shows the connections required to implement GND a QSPI interface with the MAX121. The timing diagram for this interface is shown in Figure 15. The QSPI stanaaras similiar to SPI, with the primary differences Figure 13. SPI Interface Circuit 1) QSPI allows arbitrary length data transfers from 8 to 16 bits, so only one read operation is required to receive the 14 bits of output data from the +5V MAX121, s CONST 2) QSPI allows clock rates up to 4MHz, compared to PROCESSOR am 2MHzZ with SPI. MAX127. (NVFRM |} ADSP2101 Serial Interface ss Sok CLRIN, _INVCLK Figure 16 shows the connections required to interface the CPOL =0 cs MAX121 to Analog Devices ADSP2101 DSP. Figure 17 CPHA=1 MISO SDATA is a plot of the timing diagram. The ADSP2101 has a = high-speed serial interface with a minimum serial data DGND setup time of 10ns (tscs) and a minimum data-hold time of 10ns (tSCH). This interface permits operation of the MAX121 at its maximum clock rate of 5.5MHz. Figure 14. QSPI Interface Circuit je__________ 1ST BYTE READ 4 ie 2NDBYTEREAD gy CLKIN 1 ASN S/4 5 6 7 8 1 2 3 4 5 6 7 8 COST TET TLE. LEADING TRAILING ZERO / MSB_X_D12_X_DH Xi X_be Xda X_o7 DS b3 ZERO SDATA Figure 12. SPI Interface Timing Diagram MAMAXLZAA 7-35MAX121 308ksps ADC with DSP Interface and 78dB SINAD fi\_/2 (1B) fA, fB\ fO\ fT\ 9 40 1 2\ /B 14 5 16 CLKIN L/P RST NY LENS CONVST THT 7 TTT TT Li L L LEADING TRAILING SDATA ZERO / SB X DI2 X Dit X D0 X De X 08 X O7 Y De Y DS XY D4 Y 03 X D2 X Or X SB \ ZERO Figure 15. QSPI interface Timing Diagram An_ output port of the ADSP2101 drives the MAX121 +5V CONVST input low to initiate a conversion. The SFRM | ff output of the MAX121 drives the RFS (Receive Frame OMS OR PMS CONST = WER Synchronization) input to the DSP low to indicate that the SCLK SCLK MSB has been shifted out of the MAX121 SDATA pin. On | ADSP2101 MAAXIMA the next falling edge on SCLK, the MSB is shifted into the RFS SFRM MAX?121 ADSP2101 serial input. Note that the MAX121 INVFRM input is grounded to provide the proper phase for the SFRM output. OR + SATA INVERM The SCLK terminal of the ADSP2101 is configured as an | CLKIN cs . a DGND input and is driven by the MAX121 SCLK output to clock 0.1MH2 < F <5.5MHz data into the DSP. The SFRM output remains low for 16 clock cycles, allowing the 14 data bits to be shifted into - the ADSP2101, followed by 2 trailing zeros. Figure 16. ADSP2101 to MAX121 Interface CONVST \ / LLL LES Lf \ CLIN / \ f- ft 2 fa 15 16 7 / \ Ny \/ / AL \ ____ SCLK fo N im \ \ 1 2. 14 15 16 7 Gwok=vo) =f \ ff XY \ fe /\ fO\ fo \ _______ SFRM xy (INVFRM = GND) \ tscs | tscH y SDATA MSB ce Dt x LSB 1S Figure 17, ADSP2101 interface Timing Diagram 7-36 MAXLAA308ksps ADC with DSP Interface +5V | I SDATA INVER Z | sick be 4 sexx iNVELR uPD77230 MAXIM SIEN sFaM MAX127 P2 CONVST ed CLKIN cs r] us = Figure 18. NEC ~PD77230 interface Circuit NEC 1. PD77230 Serial interface Figure 18 shows the connections required to interface the MAX121 to NECs pPD77230 DSP without external glue logic. The timing diagram is shown in Figure 19. See the Maximum Clock Rate for Serial interface section to deter- mine the maximum usable clock rate for this interface, substituting tsiss for tsu in the equations. The tHSsi term in the timing diagram is the minimum data-hold time for the pPD77230's serial data input. An I/O port of the wPD77230 drives the MAX121 CONVST pin low to initiate a conversion. The MAX121 SFRM output drives the SIEN (Serial Input Enable) terminal of the DSP low to frame the data. On the next falling edge of SCLK, the MSB is shifted into the SI (Serial Input) pin of the pPD77230. SDATA drives the SI terminal of the DSP. The MSB is followed by the other 13 data bits and two trailing zeros, after which the SFRM output returns high to disable the DSP serial input until the next conversion is initiated. TMS320 High-Speed Serial interface The flexibility of the MAX121 permits the implementation of a variety of interfaces with the Texas Instruments TMS320 DSP. The TMS320 Simple Serial interface sec- tion of this data sheet discusses the simplest type of MAX121-to-TMS320 interface, which works with serial clock rates up to 3.2MHz. This section describes an interface that allows the maxi- mum throughput to be obtained from the MAX121/TMS320 system, by operating the MAX121 at its FAAXIAA and 78dB SINAD maximum clock. Figure 20 shows the interconnections required to implement this interface. Figure 21 is the timing diagram for this interface. The MAX121 CLKIN is driven by an external clock oscil- lator. The XFO I/O port of the TMS320 drives the MAX121 CONVST input low to initiate a conversion. CLKR (Re- ceive Clock) of the TMS320 is configured as an input and driven by the MAX121 SCLK output. Data on the MAX121 SDATA output changes state on the rising edge of the clock, while data is latched into the DR input of the TMS320 on the falling edge. This provides one half clock cycle to meet the setup and hold time requirements of the TMS320 DR input. The maximum skew between the MAX121 SCLK and SDATA is +65ns at +25C, so one half clock cycle is more than sufficient to guarantee that the setup and hold time requirement is satisfied. The FSTRT output of the MAX121 drives the FSR input of the TMS320 to frame the data. A falling edge on the FSTRT output indicates that the MSB is ready to be latched. On the next falling clock edge, the MSB is latched into the TMS320. For this interface, the TMS320 is configured to receive a 16-bit word (RLEN = 01 in the TMS320 serial-port global control register) so the 14 bits of data are clocked into the DSP, followed by two trailing zeros. TMS320 Simple Serial interface Figure 22 shows an application circuit using the simplest interface between the MAX121 and the TMS320. The timing diagram for this circuit is shown in Figure 23. In this circuit, the CLKR port of the TMS320 is configured as a clock output and drives the CLKIN of the MAX121. The MAX121 output changes state on the rising edge of the CLKIN, while the data is latched into the DR port of the TMS320 on the falling edge. The XF1 1/O port of the TMS320 drives the MAX121 CONVST input low to initiate a conversion. The FSTRT output of the MAX121 drives the FSR input of the TMS320 to frame the data. A falling edge on the FSTRT output indicates that the MSB is ready to be latched. On the next falling clock edge, the MSB is latched into the TMS320. For this interface, the TMS320 is configured to receive a 16-bit word (RLEN = 01 in the TMS320 serial-port global control register) so the 14 bits of data are clocked into the DSP, followed by two trailing zeros. At TA = +25C, the clock frequency is limited to approximately 3.2MHz with this interface, due to the CLKIN-to-SDATA maximum delay of 130ns and the 25ns setup and hold time requirement for the TMS320. 7-37 KOLXVINMAX121 308ksps ADC with DSP Interface and 78dB SINAD CONVST CLKIN / \ J NTN Sf \ _/** JV LV SJ GEEK =o) SVS _f' KS NG NEN SON STN SFRM_-=<----- (INVFRM = GND) \ I siss_| tags) SDATA yowsa X pie Figure 19. NEC wPD77230 Interface Timing Diagram | XF CONVST = iNVERM [J | ee I | CLER I SCLK INVCLK [~~ TMS320 < MAXLAA SDATA MAX121 | FSR =e] FSTRT | | -t CLKIN co Be ! OSC | OAMHz<F <5.5MH2 DGND Figure 20, TMS320 High-Speed Serial-interface Circuit Figure 24 is a listing of a short program written in the TMS320 assembly language that initiates conversions in the TMS320 and ships the output data back to the host PC. The C language program listed in Figure 25 displays the results of every 30,000th conversion on the PC screen, along with the min and max values for all conversions performed during one operating sequence. Digital Bus/Clock Noise If the clock is active when the T/H is sampling the input signal, errors can be caused by coupling from the CLKIN pin to the analog input. If this is a problem, the clock 7-38 should be disabled for one clock cycle while the T/H is placed into hold mode. In mode 1, the clock should be disabled (CLKIN = DGND) for one cycle while CONVST is pulsed low. In mode 2, the clock should be disabled (CLKIN = DGND) for one clock cycle while CS is driven low. The clock should be re-activated on the first cycle after the conversion is started (CONVST or CS pulsed low). Layout, Grounding and Bypassing For best system performance, use printed circuit boards with separate analog and digital ground planes. Wire- wrap boards are not recommended. The two ground planes should be tied together at the low-impedance power-supply source, as shown in Figure 26. The board layout should ensure that digital and analog signal lines are kept separate, as much as possible. Take care not to run analog and digital (especially clock) lines parallel to one another. The high-speed comparator in the ADC is sensitive to high-frequency noise in the VDD and Vss power supplies. Bypass these supplies to the analog-ground plane with O.1pF and 10uF bypass capacitors. Keep capacitor leads at a minimum length for best supply-noise rejection. If the +5V power supply is very noisy, a 5Q resistor can be connected, as shown in Figure 26, to filter this noise. Figure 27 shows the negative power supply (Vss) rejec- tion vs. frequency. Figure 28 shows the positive power- supply (VDD) rejection vs. frequency, with and without the optional 5Q resistor. MAXIMA308ksps ADC with DSP Interface and 78dB SINAD CONVST FSTRT tsu(FSR) | tH(FS) CLKIN NS NS NS? Ns 14 5 SCLK NS NSN SX, " SS A y SDATA MSB DI2 ; DI Xx LSB L; 'y Figure 21. TMS320 High-Speed Serial-interface Timing Diagram +BY x convst NVFRM INVCLK CLKR CLKIN MS320 MAXIM DR SDATA MAX121 FSR ft FSTAT cS DGND Figure 22. TMS320 Simple Serial-intertace Circuit Dynamic Performance High-speed sampling capability and 308kHz throughput make the MAX121 ideal for wideband signal processing. To support these and other related applications, FFT (Fast Fourier Transform) test techniques are used to guarantee the ADC's dynamic frequency response, distortion, and noise at the rated throughput. Specifically, this involves applying a low-distortion sinewave to the ADC input and recording the digital conversion results for a specified time. The data is then analyzed using an FFT algorithm, which determines its spectral content. Conversion errors are then seen as spectral elements outside of the funda- mental! input frequency. IAAXIAA A/D converters have traditionally been evaluated by specifications such as Zero and Full-Scale Error, Integral Nonlinearity (INL), and Differential Nonlinearity (DNL). Such parameters are widely accepted for specifying per- formance with DC and slowly varying signals, but are less useful in signal processing applications where the ADCs impact on the system transfer function is the main concern. The significance of various DC errors does not translate well to the dynamic case, so different tests are required. Signal-to-Noise Ratio and Effective Number of Bits The signal-to-noise plus distortion ratio (SINAD) is the ratio of the fundamental input frequencys RMS amplitude to the RMS amplitude of all other ADC output signals. The output band is limited to frequencies above DC and below one-half the ADC sample (conversion) rate. The theoretical minimum ADC noise is caused by quan- tization error and is a direct result of the ADC's resolution: SINAD = (6.02N + 1.76)dB, where N is the number of bits of resolution. A perfect 14-bit ADC can, therefore, do no better than 86dB. An FFT plot of the output shows the output level in various spectral bands. Figure 29 shows the result of sampling a pure 50kHz sinusoid at a 300kHz rate with the MAX121. By transposing the equation that converts resolution to SINAD, we can, from the measured SINAD, determine the effective resolution (effective number of bits) that the ADC provides: N = (SINAD - 1.76)/6.02. Figure 30 shows the effective number of bits as a function of the input fre- quency for the MAX121. 7-39 = : 8MAX121 308ksps ADC with DSP Interface and 78dB SINAD CONVST Ty 7, cn NL \ SY PN 4 5 Ne 7 FSTRT } tie SDATA MSB Di2__ DI LSB Sy Figure 23. TMS320 Simple Serial-interface Timing Diagram bs Project: Maxim 121 to TI TMS320C30 Application Note + File: maximti.asm t Purpose: This file contains the code that is loaded onto the + TMS320C30 Evaluation Module (EVM). Its purpose is to a collect digitized samples from the Maxim 121 ADC at a MF regular rate and ship those values to the PC. iy Tabstops: 8 a $Log:$ i; Edit History: i Date By Description i 09/24/92 KHB Initial Creation Figure 24. TMS320 Assembly Language Program to Control Conversions Using the TMS320 Simple Serial-interface 7-40 MAXIMA308ksps ADC with DSP Interface and 78dB SINAD -global maxim -global wait_sample -global wait_loop -global next_sample global IOF_MASK_AMASK -GQlobal IOF_SET_XFl .global IOR_RESET_XF1 -global CTRL .global SERGLOB1 .global SERPRTX1 -global SERPRTR1 -global SERTIM1 -global SERTIM1VAL -global HOST_DATA -data IOF_AMASK word OOO000EH IOF SET_XFl .word 0000060H IOF_RESET_XF1 .word 0000020H CTRL -word 0808000H SERGLOB1 .word 8120280H SERPRTX1 .word 0000000H SERPRTRL .word 0000111H SERTIM1 -word 00003COH SERTIM1VAL .word 00020000H HOST_DATA -word 00804000H veaeccesees pee e eens eter easace DETEELRTRESE ascites cia pPUDLACs ss aaa aii: ; Preserve XFO settings ; Set XFl as output high ; Set XFl as. output low ; Pointer to peripheral-bus memory map Setup serial 1 global control (80) Use internal receive clock FSR active during entire transfer 16-bit rcv data length FSR active low Take rcvr out of reset Setup serial 1 xmt port control (82) Setup serial 1 rcv port control (83) CLKR1 = serial port pin DR1 = serial port pin FSRI1 = serial port pin Setup serial 1 timer control (84) Start rev timer, 50% duty cycle, internal clk src = 1/2 CLKOUT is used to increment rcvr timer. Timer period values RX and TX Revr timer is high order 16-bits (CLKOUT/2)/2 = 1.875Mhz CLKR1~>MAX121 CLKIN Nae Re Ne Ne See a Se Ne Ne Se Ne Se Ne Ne Ne te ; Memory address of host data port Figure 24. TMS320 Assembly Language Program to Control Conversions Using the TMS320 Simple Serial-interface (continued) MAAXLAA 7-41 s < =k i) =kMAX121 308ksps ADC with DSP Interface and 78dB SINAD SILELSEESLEEITELESL Ear pPUMCtlons aii i iaiiiaas .text maxim : Initialization Code , LDI 0,ST ; Initialize status register LDIU 128,DP ; Initialize data page register LDI 0985CH,SP : Initialize stack pointer LDI IOF,R1 Read in I/O Flags register to Rl AND @IOF_AMASK,R1 : Remove current XFl bits, preserve XFO settings OR @IOF_SET_XF1,R1 ; Set XF1l (CONVST*) Inactive (high) LDI R1,I0OF ; Make it so! LDI @CTRL ,ARO ; Load ARO w/ptr to control reg base LDI @HOST_DATA,AR1 ; Load AR1 w/host interface address LDI @SERTIM1VAL,RO STI RO, *+ARO (86) ; Setup serial chil timer period value LDI @SERGLOB1,RO STI RO, *+AR0(80) ; Setup serial chi global register LDI @SERPRTX1,RO STI RO, *+AR0(82) ; Setup serial chl xmt control register LDI @SERPRTR1,RO STI RO,*+AR0(83) ; Setup serial chi rcv control register LDI @SERTIM1,RO STI RO, *+ARO (84) ; Setup serial chi timer register next_samp.e: : Start Conversion --> [~~ | (CONVST* ) LDI I0F,R1 ; Read in I/O Flags register to Rl AND @IOF_AMASK,R1 ; Remove current XF1 bits, preserve XFO settings OR @IOF_SET_XF1,R1 ; Set XFl (CONVST*) Inactive (high) LDI R1,I0OF ; Make it so! AND @IOF_AMASK,R1 ; Remove current XFl bits, preserve XFO OR @IOF_RESET_XF1,R1 : Set XFl (CONVST*) Active (low) LDI R1,IOF ; Make it so! Figure 24. TMS320 Assembly Language Program to Control Conversions Using the TMS320 Simple Serial-interface (continued) 7-42 MAAXIAA308ksps ADC with DSP Interface and 78dB SINAD LOLXVIN wait_sample: Wait for completion of conversion MAX121 SFRM Active Signals TMS320 FSR1 that data transfer is ready to start. NA Ne we we LDI *+AR0(80),R2 ; Read in Serial Ch 1 global register AND 01H,R2 ; Check for RRDY Active (1) ; RRDY goes active when 16-bits have been rcvd BZ wait_sample ; Keep waiting if not ready LDI *+AR0(92),R3 ; Ready, read value from Data Receive register STI R3,*+AR1(0) ; Send out value to host : Arbitrary wait time until start of next convert. , LDI 100,R0 wait_loop: SUBI 1,R0 BNZ wait_loop ; Keep waiting until RO decremented to zero BR @next_sample 7; Go start next convert ieee eee ee ee eee eee eee eee eee eee eee eee ee ee eee ee ee eee eee) -end PEOPFOLER ROT E PEPE EEO ERE PEPER TEE ER EET EEE EROS POE EPROP EE EPO arr eee Re Figure 24. TMS320 Assembly Language Program to Control Conversions Using the TMS320 Simple Serial-interface (continued) MA AXIAA 7-43MAX121 308ksps ADC with DSP Interface and 78dB SINAD ZR ROI IO I IOI IOI I IOI IIIT III IOI I IT IR IIH I III III IR IKI RIKKI RIKER IER HIKER AKA EKER KK xk ** ak ak ax Project: Maxim 121 to TI TMS320C30 Application Note xk xe File: readdata.c kk xk Purpose: This file contains a PC based program used to read data x* from the TMS320C30 Evaluation Module (EVM) and display al the data on the PC screen. x* This file may be compiled with either the Microsoft C xx Compiler or Borland C++ Compiler. xk xk Tabstops: 4 K* Kx K* x* $Log:$ x* xe Edit History: x* xe Date By Description x ---- = em ee ee ae 09/24/92 KHB Initial Creation xx xk FIO IOI RII IO III III IO II III III ISO IO OI IOI SOO ISR IIIS IA IK I IK gk / #include <stdio.h> /** for printf() */ #include <conio.h> /* for kbhit(), getch(), and inpw() */ #define VERSION_STAMP 1 void main(void) { int x; int value; int quit = 0; int min 32767; int max = -32768; printf("\n"); printf("TMS320 EVM Data Display Program - Version *d\n", VERSION STAMP); printf("m = reset Max/Min values, ESC to quit\n\n"); Figure 25. C Language Program to Log Data From MAX121 Conversions 7-44 MAXIMA3O08ksps ADC with DSP Interface and 78dB SINAD while(!quit) s x ND mk if(kbhit()) switch(getch()) { case m: /* Clear Max/Min Storage Variables */ max = -32768; min = 32767; break; case q: /* Quit Program */ case Ox1B: quit = 1; break; } } for(x=0; x<30000; x++) ( /* Gather samples as fast as possible and update Max/Min */ /* Only output every 30,000th sample. The 30,000 has no */ /* specific origin other than the display updated at a */ /* comfortable rate. xf value = inpw(0x0240+0x0808); /* EVM Data Port */ value >>= 2; /* Shift from 16-bit back to 14-bit */ /* Update Max/Min */ if(value > max) max = value; else if(value < min) min = value; } /* Output the latest sample in decimal and hex along with Max/Min */ printf(" %06d %04Xh min:%06d max:%06d \r", value, value, min, max); 7* Exit */ printf("\n\n"); return; Figure 25. C Language Program to Log Data From MAX121 Conversions (continued) MAAXILAA 7-45MAX121 308ksps ADC with DSP Interface and 78dB SINAD ANALOG DIGITAL SUPPLY SUPPLY +15V -15V AGND +5V DGND * OPTIONAL rm rm 5Q. FILTER | be RESISTOR H | -15V AGND +5V DGND +5V DGND | MAXIAA DIGITAL MAXI21 CIRCUITRY : l| WITH PIEILTE 50 QM oy | s Voo MAX121 S NJ BV VV 9 Von PIN 3 10uF O.1pF 5 40 N oF DE Ot 3 N ee N Li td ~ NO PIFILTER 30 MS NY Tas 425C > 20 decane C 10k 100k iM FREQUENCY (Hz) Figure 26. Power-Supply Grounding 60 50 = Vss REJECTION (dB) 40 NS Ta = 425C oe 10k 100k FREQUENCY (Hz) Figure 28. Voo Power-Supply Rejection vs. Frequency SIGNAL AMPLITUDE (dB) 0 50 100 150 FREQUENCY (kHz) Figure 27. Vss Power-Supply Rejection vs. Frequency 7-46 Figure 29. MAX121 FFT Plot MAXIMA308ksps ADC with DSP Interface Fs = 300kHz EFFECTIVE BITS Ta = 425C 10k 100k 1M 10M INPUT FREQUENCY (Hz) and 78dB SINAD Figure 30. Effective Bits vs. Input Frequency Total Harmonic Distortion If a pure sine wave is sampled by an ADC at greater than the Nyquist frequency, the nonlinearities in the ADCs transfer function create harmonics of the input frequency present in the sampled output data. Total Harmonic Distortion (THD) is the ratio of the RMS sum of all the harmonics (in the frequency band above DC and below one- half the sample rate, but not including the DC component) to the RMS amplitude of the funda- mental frequency. This is expressed as follows: Wo274V374V474...4VN- V1 where V1 is the fundamental RMS amplitude, and V2 through VN are the amplitudes of the 2nd through Nth harmonics. The THD specification in the Electrical Char- acteristics includes the 2nd through 5th harmonics. THD = 20 log FPAMAXLAA On... 4 On... 4 000...0004+------------jJ--~---- -- W.. We... Wo... 100... 100... 4.99939V Figure 31. Bipolar Transfer Function Spurious-Free Dynamic Range Spurious-free dynamic range is the ratio of the fundamen- tal RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually the next largest spectral component occurs at some harmonic of the input frequency. However, if the ADC is exceptionally linear, it may occur only at a random peak in the ADCs noise floor. Transfer Function The plot in Figure 31 graphs the bipolar input/output transfer function for the MAX121. Code transitions occur halfway between successive integer LSB values. Output coding is two's-complement binary, with 1 LSB = 610uV (10V/16384). 7-47 5 x = N okMAX121 308ksps ADC with DSP Interface and 78dB SINAD _ Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE MAX121EPE -40C10+85C __16 Plastic DIP MAX121EWE -40C10+85C 16 Wide SO MAX121EAP -40C10+85'C -- 20SSOP* MAX121MJE 65C t0+125C 16 CERDIP** [PART TEMP. RANGE BOARD TYPE | MAXI21EVKIT-DIP 0C to +70C Through-Hole _ | ** 20-pin SSOP is 50% smaller than 16-pin SOIC. *** Contact factory for availability and processing to MIL-STD-883. __ Pin Configurations (continued) TOP VIEW vss [4 | Voo [2 | AIN [3 | VREF [a | NC. [5 | NC. [6 | AGND (7 | WOE [a DGND [ro| MAAXLMA MAX121 bo] MODE Hig] CS 1g) CLKIN 7] CONVST 116] NC. 115] NE. re SCLK fi3) SDATA li) FSTRT 11] SERM SSOP INVCLK (2,997 mm) Chip Topography 0.118" SUBSTRATE CONNECTED TO Vop; TRANSISTOR COUNT: 1,920. CONVST 0.122" (3.099 mm) SCLK SDATA j- MAXUM 7-48