VOLUME CONTROL
-80 dB TO +18 dB
MIXER/MULITPLEXER
I2C CONTROL
BIAS
FAULT
DETECTION
VDD
PVDD
+1.8V to +5.5V
I2CVDD
SDA
SCL
ADR
IN2
IN1
BIAS
GND PGND
FAULT
OUTA
OUTB
VDD
+6 dB
0.1 PF
0.1 PF
0.1 PF
0.1 PF
2.2 PF
1.5 k:
1 PF
VOLUME CONTROL
-80 dB TO +18 dB
3.0V to 5.5V
CBCB
CIN1
CIN2
CBIAS
CB
RPU
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
LM48100Q-Q1
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
LM48100Q-Q1 Boomer™ Mono, 1.3-W Audio Power Amplifier With Output Fault Detection
and Volume Control
Operating from a single 5-V supply, the LM48100Q-
1 Features Q1 delivers 1.3 W of continuous output power to an 8
1• Output Fault Detection Ωload with < 1% THD+N. Flexible power supply
• I2C Volume and Mode Control requirements allow operation from 3 V to 5.5 V. High
power supply rejection ratio (PSRR), 74 dB at 1 kHz,
• Input Mixer and Multiplexer allows the device to operate in noisy environments
• High PSRR without additional power supply conditioning.
• Individual 32-Step Volume Control The LM48100Q-Q1 features dual audio inputs that
• Short Circuit and Thermal Protection can be mixed/multiplexed to the device output. Each
• Advanced Click-and-Pop Suppression input path has its own independent, 32-step volume
control. The mixer, volume control and device mode
• Low-Power Shutdown Mode select are controlled through an I2C compatible
• Available in 14-Pin HTSSOP Package interface. An open drain FAULT output indicates
• Key Specifications: when a fault has occurred. Comprehensive output
– Output Power at VDD =5V,RL= 8 Ω,short circuit and thermal overload protection prevent
the device from being damaged during a fault
THD+N ≤1% 1.3 W (Typical) condition.
– Quiescent Power Supply Current at 5 V,
6 mA (Typical) A low power shutdown mode reduces supply current
consumption to 0.01 µA. Superior click and pop
– PSRR at 1 kHz 74 dB (Typical) suppression eliminates audible transients on power-
– Shutdown current 0.01 μA (Typical) up/down and during shutdown. The LM48100Q-Q1 is
available in an 14-pin HTSSOP PowerPAD™ IC
2 Applications package.
• Automotive Instrument Clusters Device Information(1)
• Hands-Free Car Kits PART NUMBER PACKAGE BODY SIZE (NOM)
• Medical LM48100Q-Q1 HTSSOP (14) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
3 Description the end of the datasheet.
The LM48100Q-Q1 is a single supply, mono, bridge-
tied load amplifier with I2C volume control, ideal for
automotive applications. A comprehensive output
fault detection system senses the load conditions,
protecting the device during short circuit events, as
well as detecting open circuit conditions.
Typical Audio Amplifier Application Circuit
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM48100Q-Q1
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1 Features.................................................................. 17 Detailed Description............................................ 11
7.1 Overview................................................................. 11
2 Applications ........................................................... 17.2 Functional Block Diagram....................................... 11
3 Description............................................................. 17.3 Feature Description................................................. 12
4 Revision History..................................................... 27.4 Device Functional Modes........................................ 15
5 Pin Configuration and Functions......................... 37.5 Programming........................................................... 16
6 Specifications......................................................... 47.6 Register Maps......................................................... 17
6.1 Absolute Maximum Ratings ...................................... 48 Application and Implementation ........................ 18
6.2 ESD Ratings.............................................................. 48.1 Application Information............................................ 18
6.3 Recommended Operating Conditions....................... 48.2 Typical Application.................................................. 18
6.4 Thermal Information.................................................. 49 Power Supply Recommendations...................... 20
6.5 Electrical Characteristics for VDD = 5 V .................... 510 Layout................................................................... 20
6.6 Electrical Characteristics for VDD = 5 V at Extended
Temperature Limits.................................................... 510.1 Layout Guidelines ................................................. 20
6.7 Electrical Characteristics for VDD = 3.6 V ................. 610.2 Layout Example .................................................... 21
6.8 Electrical Characteristics for VDD = 3.6 V at Extended 11 Device and Documentation Support................. 22
Temperature Limits.................................................... 711.1 Community Resources.......................................... 22
6.9 I2C Interface Characteristics for VDD = 5 V, 2.2 V ≤11.2 Trademarks........................................................... 22
I2C VDD ≤5.5 V.......................................................... 811.3 Electrostatic Discharge Caution............................ 22
6.10 I2C Interface Characteristics for VDD = 5 V, 1.8 V ≤11.4 Glossary................................................................ 22
I2C VDD ≤2.2 V.......................................................... 812 Mechanical, Packaging, and Orderable
6.11 Typical Characteristics............................................ 9Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
10/14/08 1.0 Initial release.
10/20/08 1.01 Text edits.
11/07/08 1.02 Added a column (Limits) in the Electrical tables.
11/12/08 1.03 Text edits.
03/21/2013 D Changed layout of the National Data Sheet to TI format
Added Pin Configuration and Functions section, ESD Ratings table, Feature Descriptionsection,
Device Functional Modes,Application and Implementation section, Power Supply
Recommendations section, Layoutsection, Device and Documentation Supportsection, and
11/2015 E Mechanical, Packaging, and Orderable Information section
Removed LM48100Q-Q1TL Demo board Bill of Materials table.
2Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM48100Q-Q1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
FAULT
SDA
SCL
I2CVDD
GND
ADR
OUTA PGND
OUTB
PVDD
IN2
IN1
BIAS
VDD
LM48100Q-Q1
www.ti.com
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
5 Pin Configuration and Functions
PWP Package
14-Pin HTSSOP with PowerPAD
Top View
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 FAULT O Open-Drain output fault flag. FAULT = 0 indicates that a fault condition has occurred.
2 SCL I I2C Clock Input
3 SDA I/O I2C Serial Data Input
4 I2CVDD — I2C Interface Power Supply
5 GND — Ground
I2C Address Bit. Connect to I2CVDD to set address bit, B1 = 1. Connect to GND to set address
6 ADR I bit B1 = 0
7 OUTA O Non-Inverting Audio Output
8 PGND — Power Ground
9 OUTB O Inverting Audio Output
10 PVDD — Output Amplifier Power Supply
11 IN2 I Audio Input 2
12 IN1 I Audio Input 1
13 BIAS — Bias Bypass
14 VDD — Power Supply
— Exposed Pad — Exposed paddle. Connect to GND.
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LM48100Q-Q1
LM48100Q-Q1
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
See (1)(2)(3)
MIN MAX UNIT
Supply voltage, continuous 6 V
Input voltage −0.3 VDD + 0.3 °C
Power dissipation(4) Internally Limited
Junction temperature 150 °C
Lead temperature (soldering 4 sec)(5) 260 °C
Storage temperature −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The Electrical Characteristics tables found in Specifications list ensured specifications under the listed Recommended Operating
Conditions except as otherwise modified or specified by the Electrical Characteristics Test Conditions, Notes, or both. Typical
specifications are estimations only and are not ensured.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4) θJA measured with a 4 layer JEDEC board.
(5) For detailed information on soldering plastic HTSSOP and LLP packages go to the TI Packaging site, ti.com/packaging.
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1) 2500
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per AEC Q100-011 300
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions MIN MAX UNIT
Temperature TMIN ≤TA≤TMAX −40 105 °C
Supply voltage VDDand PVDD 3 5.5 V
1.8 5.5 V
I2C Supply voltage I2CVDD I2CVDD VDD V
6.4 Thermal Information LM48100Q-Q1
THERMAL METRIC(1) PWP (HTSSOP) UNIT
14 PINS
RθJA Junction-to-ambient thermal resistance 37.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 5.2 °C/W
RθJB Junction-to-board thermal resistance — °C/W
ψJT Junction-to-top characterization parameter — °C/W
ψJB Junction-to-board characterization parameter — °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM48100Q-Q1
LM48100Q-Q1
www.ti.com
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
6.5 Electrical Characteristics for VDD = 5 V
Programmable Gain = 0 dB, RL= 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA= 25°C, unless otherwise
specified. PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX UNIT
RL= 8 Ω4.4 9
IDD Quiescent Power Supply Current VIN = 0 V, Both channels active mA
RL=∞4.2 6
Diagnostic Mode Quiescent Power
IDD Diagnostic Mode Enabled, RL=∞12.5 14.5 mA
Supply Current
ISD Shutdown Current Shutdown Enabled 0.01 1 µA
VOS Differential Output Offset Voltage VIN = 0 V, RL= 8 Ω8.8 50 mV
TWU Wake-Up Time Time from shutdown to audio available 11.6 50 ms
Minimum Gain Setting –55 –54 –53
AVGain dB
Maximum Gain Setting 17 18 19
Mute Mute Attenuation –80 –77 dB
AV= 18 dB 11.5 12.5 13.5
RIN Input Resistance kΩ
AV= –54 dB 98 110 120
THD+N = 10% 1.6
POOutput Power RL= 8 Ω, f = 1 kHz W
THD+N = 1% 1.05 1.3
THD+N Total Harmonic Distortion + Noise PO= 850 mW, f = 1 kHz, RL= 8 Ω0.04%
f = 217 Hz 66 79
VRIPPLE = 200 mVP-P Sine, Inputs AC GND,
PSRR Power Supply Rejection Ratio dB
CIN_= 1 μF, Input Referred, CBIAS = 2.2 μFf = 1 kHz 74
SNR Signal-to-Noise-Ratio POUT = 450 mW, f = 1 kHz 104 dB
∈OS Output Noise AV= 0 dB, A-weighted Filter 12 μV
IOUT(FAULT) FAULT Output Current FAULT = 0, VOUT(FAULT)= 0.4 V 3 mA
Short Circuit 3
Output to Supply Short Circuit Short between either OUTA to VDD or GND, or
RFAULT kΩ
Detection Threshold OUTB to VDD or GND Open Circuit 7.5
Short Circuit 6
Output to Supply Short Circuit Short between both OUTA and
RFAULT kΩ
Detection Threshold OUTB to VDD or GND Open Circuit 15
ROPEN Open Circuit Detection Threshold Open circuit between OUTA and OUTB 100 200 Ω
Output to Output Short Circuit
RSHT Short circuit between OUTA and OUTB 2 6 Ω
Detection Threshold
ISHTCKT Short Circuit Current Limit 1.47 1.67 A
TSD Thermal Shutdown Threshold 170 °C
tDIAG Diagnostic Time 58 ms
(1) Datasheet min/max specification limits are specified by test or statistical analysis.
(2) Typical Values are given for TA= 25°C.
6.6 Electrical Characteristics for VDD = 5 V at Extended Temperature Limits
Programmable Gain = 0 dB, RL= 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA= –40°C to 105°C, unless
otherwise specified.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX UNIT
RL= 8 Ω4.4 10.8
IDD Quiescent Power Supply Current VIN = 0 V, Both channels active mA
RL=∞4.2 7.9
Diagnostic Mode Quiescent Power
IDD Diagnostic Mode Enabled, RL=∞12.5 mA
Supply Current
ISD Shutdown Current Shutdown Enabled 0.01 µA
VOS Differential Output Offset Voltage VIN = 0 V, RL= 8 Ω8.8 75 mV
TWU Wake-Up Time Time from shutdown to audio available 11.6 ms
Minimum Gain Setting –56 –54 –52
AVGain dB
Maximum Gain Setting 17 18 19
Mute Mute Attenuation –80 –74 dB
(1) Datasheet min/max specification limits are specified by test or statistical analysis.
(2) Typical Values are given for TA= 25°C.
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LM48100Q-Q1
LM48100Q-Q1
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
www.ti.com
Electrical Characteristics for VDD = 5 V at Extended Temperature Limits (continued)
Programmable Gain = 0 dB, RL= 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA= –40°C to 105°C, unless
otherwise specified.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX UNIT
AV= 18 dB 12.5
RIN Input Resistance kΩ
AV= –54 dB 89 110 130
THD+N = 10% 1.6
POOutput Power RL= 8 Ω, f = 1 kHz W
THD+N = 1% 0.96 1.3
THD+N Total Harmonic Distortion + Noise PO= 850 mW, f = 1 kHz, RL= 8 Ω0.04%
f = 217 Hz 63 79
VRIPPLE = 200 mVP-P Sine, Inputs AC GND,
PSRR Power Supply Rejection Ratio dB
CIN_= 1 μF, Input Referred, CBIAS = 2.2 μFf = 1 kHz 74
SNR Signal-to-Noise-Ratio POUT = 450 mW, f = 1 kHz 104 dB
∈OS Output Noise AV= 0 dB, A-weighted Filter 12 μV
IOUT(FAULT) FAULT Output Current FAULT = 0, VOUT(FAULT)= 0.4 V 3 mA
Short Circuit 3
Output to Supply Short Circuit Short between either OUTA to VDD or GND, or
RFAULT kΩ
Detection Threshold OUTB to VDD or GND Open Circuit 7.5
ISHTCKT Short Circuit Current Limit 1.47 2 A
TSD Thermal Shutdown Threshold 170 °C
tDIAG Diagnostic Time 58 ms
6.7 Electrical Characteristics for VDD = 3.6 V
Programmable Gain = 0 dB, RL= 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA= 25°C, unless otherwise
specified. PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX UNIT
RL= 8 Ω3.8 8.5
IDD Quiescent Power Supply Current VIN = 0 V, Both channels active mA
RL=∞3.6 5
Diagnostic Mode Quiescent Power
IDD Diagnostic Mode Enabled, RL=∞11.7 14.5 mA
Supply Current
ISD Shutdown Current Shutdown Enabled 0.01 1 µA
VOS Differential Output Offset Voltage VIN = 0 V, RL= 8 Ω8.8 50 mV
TWU Wake-Up Time Time from shutdown to audio available 11.5 50 ms
Minimum Gain Setting –55 –54 –53
AVGain dB
Maximum Gain Setting 17 18 19
Mute Mute Attenuation –79 –77 dB
AV= 18 dB 11.5 12.5 13.5
RIN Input Resistance kΩ
AV= –54 dB 98 110 120
THD+N = 10% 820
POOutput Power RL= 8 Ω, f = 1 kHz mW
THD+N = 1% 480 660
THD+N Total Harmonic Distortion + Noise PO= 400 mW, f = 1 kHz, RL= 8 Ω0.04%
f = 217 Hz 66 78
VRIPPLE = 200 mVP-P Sine, Inputs AC GND,
PSRR Power Supply Rejection Ratio dB
CIN_= 1 μF, Input Referred, CBIAS = 2.2 μFf = 1 kHz 75
SNR Signal-to-Noise-Ratio POUT = 780 mW, f = 1 kHz 106 dB
∈OS Output Noise AV= 0 dB, A-weighted Filter 12.5 μV
IOUT(FAULT) FAULT Output Current FAULT = 0, VOUT(FAULT)= 0.4 V 3 mA
Short Circuit 3
Output to Supply Short Circuit Short between either OUTA to VDD or GND, or
RFAULT kΩ
Detection Threshold OUTB to VDD or GND Open Circuit 7.5
Short Circuit 6
Output to Supply Short Circuit Short between both OUTA and
RFAULT kΩ
Detection Threshold OUTB to VDD or GND Open Circuit 15
ROPEN Open Circuit Detection Threshold Open circuit between OUTA and OUTB 100 200 Ω
Output to Output Short Circuit
RSHT Short circuit between OUTA and OUTB 2 6 Ω
Detection Threshold
ISHTCKT Short Circuit Current Limit 1.43 A
(1) Datasheet min/max specification limits are specified by test or statistical analysis.
(2) Typical Values are given for TA= 25°C.
6Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM48100Q-Q1
LM48100Q-Q1
www.ti.com
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
Electrical Characteristics for VDD = 3.6 V (continued)
Programmable Gain = 0 dB, RL= 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA= 25°C, unless otherwise
specified. PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX UNIT
TSD Thermal Shutdown Threshold 170 °C
tDIAG Diagnostic Time 63 ms
6.8 Electrical Characteristics for VDD = 3.6 V at Extended Temperature Limits
Programmable Gain = 0 dB, RL= 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA= –40°C to 105°C, unless
otherwise specified.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX UNIT
RL= 8 Ω3.8 10.8
IDD Quiescent Power Supply Current VIN = 0 V, Both channels active mA
RL=∞3.6 7
Diagnostic Mode Quiescent Power
IDD Diagnostic Mode Enabled, RL=∞11.7 mA
Supply Current
ISD Shutdown Current Shutdown Enabled 0.01 µA
VOS Differential Output Offset Voltage VIN = 0 V, RL= 8 Ω8.8 76 mV
TWU Wake-Up Time Time from shutdown to audio available 11.5 ms
Minimum Gain Setting –54
AVGain dB
Maximum Gain Setting 18
Mute Mute Attenuation –79 dB
AV= 18 dB 12.5
RIN Input Resistance kΩ
AV= –54 dB 89 110 135
THD+N = 10% 820
POOutput Power RL= 8 Ω, f = 1 kHz mW
THD+N = 1% 660
THD+N Total Harmonic Distortion + Noise PO= 400 mW, f = 1 kHz, RL= 8 Ω0.04%
f = 217 Hz 60 78
VRIPPLE = 200 mVP-P Sine, Inputs AC GND,
PSRR Power Supply Rejection Ratio dB
CIN_= 1 μF, Input Referred, CBIAS = 2.2 μFf = 1 kHz 75
SNR Signal-to-Noise-Ratio POUT = 780 mW, f = 1 kHz 106 dB
∈OS Output Noise AV= 0 dB, A-weighted Filter 12.5 μV
IOUT(FAULT) FAULT Output Current FAULT = 0, VOUT(FAULT)= 0.4 V 3 mA
ISHTCKT Short Circuit Current Limit 1.43 A
TSD Thermal Shutdown Threshold 170 °C
tDIAG Diagnostic Time 63 ms
(1) Datasheet min/max specification limits are specified by test or statistical analysis.
(2) Typical Values are given for TA= 25°C.
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LM48100Q-Q1
LM48100Q-Q1
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
www.ti.com
6.9 I2C Interface Characteristics for VDD = 5 V, 2.2 V ≤I2C VDD ≤5.5 V
AV= 0 dB, RL= 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA= 25 °C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN(1) MAX UNIT
t1SCL Period 2.5 µs
t2SDA Setup Time 100 ns
t3SDA Stable Time 0 ns
t4Start Condition Time 100 ns
t5Stop Condition Time 100 ns
t6SDA Data Hold Time 100 ns
VIH Logic High Input Threshold 0.7 x I2CVDD V
VIL Logic Low Input Threshold 0.3 x I2CVDD V
(1) Datasheet min/max specification limits are specified by test or statistical analysis.
6.10 I2C Interface Characteristics for VDD = 5 V, 1.8 V ≤I2C VDD ≤2.2 V
AV= 0 dB, RL= 8 Ω, f = 1 kHz, unless otherwise specified. Limits apply for TA= 25 °C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN(1) MAX UNIT
t1SCL Period 2.5 µs
t2SDA Setup Time 250 ns
t3SDA Stable Time 0 ns
t4Start Condition Time 250 ns
t5Stop Condition Time 250 ns
t6SDA Data Hold Time 250 ns
0.7 x
VIH Logic High Input Threshold V
I2CVDD 0.3 x
VIL Logic Low Input Threshold V
I2CVDD
(1) Datasheet min/max specification limits are specified by test or statistical analysis.
8Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM48100Q-Q1
0.01
0.1
1
10
100
0.001 0.01 0.1 1 10
OUTPUT POWER (W)
THD+N (%)
VDD = 3.6V
VDD = 5V
0.01
0.1
1
10
100
0.001 0.01 0.1 1 10
OUTPUT POWER (W)
THD+N (%)
VDD = 3.6V
VDD = 5V
0.001
0.01
0.1
1
10
100
10 100 1000 10000 100000
FREQUENCY (Hz)
THD+N (%)
0.001
0.01
0.1
1
10
100
10 100 1000 10000 100000
FREQUENCY (Hz)
THD+N (%)
0.001
0.01
0.1
1
10
100
10 100 1000 10000 100000
FREQUENCY (Hz)
THD+N (%)
LM48100Q-Q1
www.ti.com
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
6.11 Typical Characteristics
VDD = 3.6 V POUT = 600 mW RL= 4 ΩVDD = 3.6 V POUT = 400 mW RL= 8 Ω
Figure 1. THD+N vs Frequency Figure 2. THD+N vs Frequency
VDD = 5 V POUT = 850 mW RL= 8 Ω
VDD = 5 V POUT = 1.2 W RL= 4 Ω
Figure 4. THD+N vs Frequency
Figure 3. THD+N vs Frequency
f = 1 kHz RL= 4 Ωf = 1 kHz RL= 8 Ω
Figure 5. THD+N vs Output Power Figure 6. THD+N vs Output Power
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: LM48100Q-Q1
-120
-100
-80
-60
-40
-20
0
10 100 1000 10000 100000
FREQUENCY (Hz)
PSRR (dB)
0
0.5
1
1.5
2
3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
THD+N = 10%
THD+N = 1%
0
0.5
1
1.5
2
2.5
3
3.5
3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
THD+N = 1%
THD+N = 10%
0
200
400
600
800
1000
1200
1400
0 500 1000 1500 2000 2500
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
VDD = 5V
VDD = 3.6V
0
100
200
300
400
500
600
700
800
0 250 500 750 1000 1250 1500
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
VDD = 5V
VDD = 3.6V
LM48100Q-Q1
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
www.ti.com
Typical Characteristics (continued)
f = 1 kHz RL= 8 Ω
f = 1 kHz RL= 4 Ω
Figure 8. Power Dissipation vs Output Power
Figure 7. Power Dissipation vs Output Power
f = 1 kHz RL= 4 Ωf = 1 kHz RL= 8 Ω
Figure 9. Output Power vs Supply Voltage Figure 10. Output Power vs Supply Voltage
VDD = 3.6 V VRIPPLE = 200 mVP-P RL= 8 Ω
Figure 11. PSRR vs Frequency
10 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM48100Q-Q1
VOLUME CONTROL
-80 dB TO +18 dB
MIXER/MULITPLEXER
I2C CONTROL
BIAS
FAULT
DETECTION
VDD
PVDD
+1.8V to +5.5V
I2CVDD
SDA
SCL
ADR
IN2
IN1
BIAS
GND PGND
FAULT
OUTA
OUTB
VDD
+6 dB
0.1 PF
0.1 PF
0.1 PF
0.1 PF
2.2 PF
1.5 k:
1 PF
VOLUME CONTROL
-80 dB TO +18 dB
3.0V to 5.5V
CBCB
CIN1
CIN2
CBIAS
CB
RPU
LM48100Q-Q1
www.ti.com
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
7 Detailed Description
7.1 Overview
The LM48100Q-Q1 integrates a comprehensive output fault detection system, which can sense the load
conditions, protecting the device during short circuit events and detecting open circuit conditions. High power
supply rejection ratio allows the device to operate in noisy environments without additional power supply
conditioning. Dual audio inputs can be mixed or multiplexed to the device output. Each input path has its own
independent, 32-step volume control. The mixer, volume control and device mode select are controlled through
an I2C compatible interface. An open drain FAULT output indicates when a fault has occurred. Comprehensive
output short circuit and thermal overload protection prevent the device from damage during fault conditions.
Superior click and pop suppression eliminates audible transients on power-up, power-down, and during
shutdown.
7.2 Functional Block Diagram
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LM48100Q-Q1
LM48100Q-Q1
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
www.ti.com
7.3 Feature Description
7.3.1 Diagnostic Control
The LM48100Q-Q1 output fault diagnostics are controlled through the I2C interface. When power is initially
applied to the device, the LM48100Q-Q1 initializes, performing the full diagnostic sequence; output short to VDD
and GND, outputs shorted together, and no load condition, is performed. The device remains in shutdown while
the initial diagnostic check is performed. Any I2C commands written to the device during this time are stored and
implemented once the diagnostic check is complete. The initial diagnostic sequence can be terminated by setting
DG_RESET = 1.
The Diagnostic Control register, register 1, controls the LM48100Q-Q1 diagnostic process. Bit B4, DG_EN,
enables the output fault detection. Set DG_EN = 1 to enable the output diagnostic test sequence. The
LM48100Q-Q1 treats the DG_EN bit as rising-edge-sensitive; once DG_EN = 1 is clocked into the device, the
diagnostic test is performed. If the LM48100Q-Q1 is in one-shot mode, once the test sequence is performed, the
DG_EN bit is ignored and the test sequence will not be run again. Cycle DG_EN from high-to-low-to-high to re-
enable the one-shot diagnostic test sequence.
In continuous diagnostic mode, the test sequence is repeated until either a fault condition occurs, DG_RESET is
cycled, or the device is taken out of continuous diagnostic mode. Set DG_CONT = 1 before setting DG_EN = 1
to initiate a continuous diagnostic. Set DG-CONT = 0 to disable continuous diagnostic mode. When the device is
active and DG_EN = 0, the LM48100Q-Q1 does not perform the output short, or no load diagnostics, however,
the thermal overload and output over current protection circuitry remains active, and disables the device should a
thermal or over-current fault occur. The initial diagnostic operation when power is applied to the device occurs
regardless of the state of DG_EN. The LM48100Q-Q1 output fault detection can be set to either continuous
mode where the output diagnostic occurs every 60ms, or a one-shot mode. Set bit B3 (DG_CONT) to 1 for
continuous mode, set B3 = 0 for one-shot mode.
Bit B2, DG_RESET, restores the LM48100Q-Q1 to normal operation after an output fault is detected. Toggle
DG_RESET to re-enable the device outputs and set FAULT high.
Table 1. Diagnostic Control Register
BIT NAME VALUE DESCRIPTION
B0 RESERVED 0 Unused
0 Fixed output current limit
B1 ILIMIT 1 Supply dependent output current limit
Normal operation. FAULT remains low and device is disabled
0
DG once a fault occurs.
B2 _RESET 1 Reset FAULT output. Device returns to pre-fault operation.
0 One shot diagnostic
DG
B3 _CONT 1 Continuous diagnostic
0 Disable diagnostic
B4 DG_EN 1 Enable diagnostic
7.3.2 Fault Detection Control Register
The LM48100Q-Q1 output fault tests are individually controlled through the Fault Detection Control register,
register 2. Setting any of the bits in the Fault Detection Control register to 1 causes the FAULT circuitry to ignore
the associated test. For example, if B2 (RAIL_SHT) = 1 and the output is shorted to VDD, the FAULT output
remains high. Although the FAULT circuitry ignores the selected test, the LM48100Q-Q1 protection circuitry
remains active, and disables the device. This feature is useful for diagnosing which fault caused a FAULT
condition.
If DG_EN = 1, and a diagnostic sequence is initiated, all the tests are performed regardless of their state in the
Fault Detection Control register. If DG_EN = 0, the RAIL_SHT, OUTPUT_OPEN and OUTPUT_SHT tests are
not performed, however, the thermal overload and output over-current detection circuitry remains active.
12 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM48100Q-Q1
LM48100Q-Q1
www.ti.com
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
Table 2. Fault Detection Control Register
BIT NAME VALUE DESCRIPTION
0 Normal operation
B0 OUTPUT_SHT 1 Ignore output short circuit fault (outputs shorted together)
0 Normal operation
B1 OUTPUT_OPEN 1 Ignore output short circuit fault
0 Normal operation
RAIL
B2 _SHT 1 Ignore output short to VDD or GND fault
0 Normal operation
B3 OVF 1 Ignore output over-current fault
0 Normal operation
B4 TSD 1 Ignore thermal overload fault
7.3.3 General Amplifier Function
7.3.3.1 Bridge Configuration Explained
The LM48100Q-Q1 is designed to drive a load differentially, a configuration commonly referred to as a bridge-
tied load (BTL). The BTL configuration differs from the single-ended configuration, where one side of the load is
connected to ground. A BTL amplifier offers advantages over a single-ended device. By driving the load
differentially, the output voltage is doubled, compared to a single-ended amplifier under similar conditions. This
doubling of the output voltage leads to a quadrupling of the output power. For example, the theoretical maximum
output power for a single-ended amplifier driving 8 Ωand operating from a 5 V supply is 158 mW, while the
theoretical maximum output power for a BTL amplifier operating under the same conditions is 633 mW. Since the
amplifier outputs are both biased about VDD/2, there is no net DC voltage across the load, eliminating the DC
blocking capacitors required by single-ended, single-supply amplifiers.
7.3.3.2 Input Mixer/Multiplexer
The LM48100Q-Q1 features an input mixer/multiplexer controlled through the I2C interface. The mixer/multiplexer
allows either input, or the combination of both inputs to appear at the device output. Bits B2 (INPUT_1) and B3
(INPUT_2) of the Mode Control Register select the individual input channels. Set INPUT_1 = 1 to select the
audio signal on IN1. Set INPUT_2 = 1 to select the audio signal on IN2. Setting both INPUT_1 and INPUT_2 = 1
mixes VIN1 and VIN2, and the LM48100Q-Q1 outputs the result as a mono signal (Table 3).
Table 3. Input Multiplexer Control
INPUT_1 INPUT_2 LM48100Q-Q1 OUTPUT
0 0 MUTE. No input selected
1 0 IN1 ONLY
0 1 IN2 ONLY
1 1 IN1 + IN2
7.3.4 Output Fault Detection
7.3.4.1 Output Short to Supplies (VDD or GND)
With a standard speaker load (6 Ωto 100 Ω) connected between OUTA and OUTB, the LM48100Q-Q1 can
detect a short between the outputs and either VDD or GND. A short is detected if the impedance between either
OUTA or OUTB and VDD or GND is less than 3 kΩ. A short is also detected if the impedance between BOTH
OUTA and OUTB and either VDD or GND is less than 6 kΩ. Under either of these conditions, the amplifier
outputs are disabled and FAULT is driven low. No short is detected if the impedance between either output and
VDD or GND is greater than 7.5 kΩ. Likewise, no short is detected if the impedance between BOTH outputs and
VDD or GND is greater than 15 kΩ.
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM48100Q-Q1
LM48100Q-Q1
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
www.ti.com
7.3.4.2 Output Short Circuit and Open Circuit Detection
The LM48100Q-Q1 can detect whether the amplifier outputs have been shorted together or, an output open
circuit condition has occurred. An output short circuit is detected if the impedance between OUTA and OUTB is
less than 2 Ω. An open circuit is detected if the impedance between OUTA and OUTB is greater than 200 Ω.
Under either of these conditions, the amplifier outputs are disabled and FAULT is driven low. The device remains
in normal operation if the impedance between OUTA and OUTB is in the range of 6 Ωto 100 Ω. The output open
circuit test is only performed during the initial diagnostic sequence during power up, or when DG_ENABLE is set
to 1.
7.3.4.3 Output Over-Current Detection
The LM48100Q-Q1 has two over current detection modes, a fixed current limit, and a supply dependent current
limit. Bit B1 (ILIMIT) of the Diagnostic Control Register selects the over-current detection mode. Set ILIMIT = 0 to
select a fixed current limit of 1.47 A (typ). Set ILIMIT = 1 to select the supply dependent current limit mode. In
supply dependent mode, the current limit is determined by Equation 1:
ISHTCKT = 0.264 x VDD (A) (1)
If the output current exceeds the current limit, the device outputs are disabled and FAULT is driven low. The
output over-current detection circuitry remains active when the diagnostics have been disabled (DG_EN = 0).
7.3.4.4 Thermal Overload Detection
The LM48100Q-Q1 has thermal overload threshold of 170 °C (typ). If the die temperature exceeds 170 °C, the
outputs are disabled and FAULT is driven low. The thermal overload detection circuitry remains active when the
diagnostics have been disabled (DG_EN = 0).
7.3.5 Open FAULT Output
The LM48100Q-Q1 features an open drain, fault indication output, FAULT , that asserts when a fault condition is
detected by the device. FAULT goes low when either an output short, output open, over current, or thermal
overload fault is detected, and the diagnostic test is not ignored, see Fault Detection Control Register section.
FAULT remains low even after the fault condition has been cleared and the diagnostic tests are repeated. Toggle
DG_RESET to clear FAULT.
Connect a 1.5-kΩor higher pullup resistor between FAULT and VDD.
7.3.6 Volume Control
Table 4. Volume Control
VOLUME STEP VOL4 VOL3 VOL2 VOL1 VOL0 GAIN (dB)
1 0 0 0 0 0 –80
2 0 0 0 0 1 –54
3 0 0 0 1 0 –40.5
4 0 0 0 1 1 –34.5
5 0 0 1 0 0 –30
6 0 0 1 0 1 –27
7 0 0 1 1 0 –24
8 0 0 1 1 1 –21
9 0 1 0 0 0 –18
10 0 1 0 0 1 –15
11 0 1 0 1 0 –13.5
12 0 1 0 1 1 –12
13 0 1 1 0 0 –10.5
14 0 1 1 0 1 –9
15 0 1 1 1 0 –7.5
16 0 1 1 1 1 –6
17 1 0 0 0 0 –4.5
14 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM48100Q-Q1
LM48100Q-Q1
www.ti.com
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
Table 4. Volume Control (continued)
VOLUME STEP VOL4 VOL3 VOL2 VOL1 VOL0 GAIN (dB)
18 1 0 0 0 1 –3
19 1 0 0 1 0 –1.5
20 1 0 0 1 1 0
21 1 0 1 0 0 1.5
22 1 0 1 0 1 3
23 1 0 1 1 0 4.5
24 1 0 1 1 1 6
25 1 1 0 0 0 7.5
26 1 1 0 0 1 9
27 1 1 0 1 0 10.5
28 1 1 0 1 1 12
29 1 1 1 0 0 13.5
30 1 1 1 0 1 15
31 1 1 1 1 0 16.5
32 1 1 1 1 1 18
7.3.7 Shutdown Function
The LM48100Q-Q1 features an I2C selectable low power shutdown mode that disables the device, reducing
quiescent current consumption to 0.01 μA. Set bit B4 (POWER_ON) in the Mode Control Register to 0 to disable
the device. Set B0 to 1 to enable the device.
7.3.8 Power Dissipation
The increase in power delivered by a BTL amplifier leads to a direct increase in internal power dissipation. The
maximum power dissipation for a BTL amplifier for a given supply voltage and load is given by Equation 2:
PDMAX = 4 x VDD2/ 2π2RL(Watts) (2)
The maximum power dissipation of the HTSSOP package is calculated by Equation 3:
PDMAX (PKG) = TJMAX – TA/θJA (Watts)
where
• TJMAX is 150 °C
• TAis the ambient temperature
•θJA is the thermal resistance specified in the Absolute Maximum Ratings (3)
If the power dissipation for a given operating condition exceeds the package maximum, either decrease the
ambient temperature, increase air flow, add heat sinking to the device, or increase the load impedance and/or
supply voltage. The LM48100Q-Q1 HTSSOP package features an exposed die attach pad (DAP) that can be
used to increase the maximum power dissipation of the package, see Exposed DAP Mounting Considerations.
The LM48100Q-Q1 features thermal overload protection that disables the amplifier output stage when the die
temperature exceeds 170 °C. See the Thermal Overload Detection section.
7.4 Device Functional Modes
The LM48100Q-Q1 output fault diagnostics support two different modes: one-shot mode and continuous
diagnostic mode.
7.4.1 One-Shot Mode
If the LM48100Q-Q1 is in one-shot mode, once the test sequence is performed, the DG_EN bit is ignored and
the test sequence will not be run again.
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM48100Q-Q1
SCL
SDA
Data In
SDA
Data Out
t1
t4
t2
t3
t5
LM48100Q-Q1
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
www.ti.com
Device Functional Modes (continued)
7.4.2 Continuous Diagnostic Mode
In continuous diagnostic mode, the test sequence is repeated until either a fault condition occurs, DG_RESET is
cycled, or the device is taken out of continuous diagnostic mode.
7.5 Programming
7.5.1 Write-Only I2C Compatible Interface
The LM48100Q-Q1 is controlled through an I2C compatible serial interface that consists of a serial data line
(SDA) and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The
LM48100Q-Q1 and the master can communicate at clock rates up to 400 kHz. Figure 12 shows the I2C interface
timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM48100Q-Q1 is a
transmit/receive slave-only device, reliant upon the master to generate the SCL signal. Each transmission
sequence is framed by a START condition and a STOP condition (Figure 13). Each data word, device address
and data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 14).
The LM48100Q-Q1 device address is 111110X, where X is determined by ADR (Table 6). ADR = 1 sets the
device address to 1111101. ADR = 0 sets the device address to 1111100.
7.5.2 I2C Bus Format
The I2C bus format is shown in Figure 14. The START signal, the transition of SDA from HIGH to LOW while
SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0
indicates the master is writing to the slave device, RW = 1 indicates the master wants to read data from the slave
device. Set R/W = 0; the LM48100Q-Q1 is a WRITE-ONLY device and will not respond the R/W = 1. The data is
latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last
address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is
generated by the slave device. If the LM48100Q-Q1 receives the correct address, the device pulls the SDA line
low, generating an acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable
while SCL is HIGH. After the 8-bit register data word is sent, the LM48100Q-Q1 sends another ACK bit.
Following the acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go
high.
Figure 12. I2C Timing Diagram
16 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM48100Q-Q1
START MSB DEVICE ADDRESS LSB ACK
SCL
SDA STOPMSB REGISTER DATA LSB ACK
R/W
SDA
SCL SP
START condition STOP condition
LM48100Q-Q1
www.ti.com
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
Programming (continued)
Figure 13. Start and Stop Diagram
Figure 14. Example Write Sequence
Table 5. Device Address
B7 B6 B5 B4 B3 B2 B1 B0 R/W
ADR = 0 1 1 1 1 1 0 0 0
ADR = 1 1 1 1 1 1 0 1 0
7.6 Register Maps
Table 6. I2C Control Registers
Register Register Name B7 B6 B5 B4 B3 B2 B1 B0
Address
0 MODE CONTROL 0 0 0 POWER_ON INPUT_2 INPUT_1 0 0
DIAGNOSTIC
1 0 0 1 DG_EN DG_CONT DG_RESET ILIMIT 0
CONTROL
FAULT DETECTION OUTPUT OUTPUT
2 0 1 0 TSD OCF RAIL_SHT
CONTROL _OPEN _SHORT
VOLUME CONTROL
3 0 1 1 VOL1_4 VOL1_3 VOL1_2 VOL1_1 VOL1_0
1
VOLUME CONTROL
4 1 0 0 VOL2_4 VOL2_3 VOL2_2 VOL_2 VOL2_0
2
Table 7. Mode Control Registers
BIT NAME VALUE DESCRIPTION
B0, B1 RESERVED 0 Unused
0 IN1 Input unselected
B2 INPUT_1 1 IN1 Input selected
0 IN2 Input unselected
B3 INPUT_2 1 IN2 Input selected
0 Device Disabled
B4 POWER_ON 1 Device Enabled
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM48100Q-Q1
BIAS
U1
VDD
C4
2.2 PF
C3
0.1 PF
13
5
14
GND
VDD
I2CVDD
VDD
IN1
12
IN1
0.1 PF
C7
I2CVDD
IN2
11
IN2
0.1 PF
C6
PGND
PVDD
8
10
C2
1 PFC1
10 PF
VDD
+
GND
OUTA
OUTA
OUTB
OUTB
FAULT
FAULT
9
7
1
4
I2CVDD
JU1
6
ADR
VDD
R3
1.5k
LM48100
3
1
2
C5
0.1 PF
VDD
JU3
I2CVDD
2
SCLSCL
3
SDASDA
R2
5k
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
MOUNTING
SUPPORT
JU2
R1
5k
I2CVDD
SDA
SCL
J2
LM48100Q-Q1
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM48100Q-Q1 is a single-supply, mono, bridge-tied load amplifier with I2C volume control, ideal for
automotive applications. It integrates a comprehensive output fault detection system, which can sense the load
conditions, protecting the device during short circuit events and detecting open circuit conditions. High power
supply rejection ratio allows the device to operate in noisy environments without additional power supply
conditioning. The LM48100Q-Q1 features dual audio inputs that can mixed or multiplexed to the device output.
Each input path has its own independent, 32-step volume control. The mixer, volume control and device mode
select are controlled through an I2C compatible interface. The LM48100Q-Q1 device has an I2C selectable low
power shutdown mode that disables the device, reducing quiescent current consumption to 0.01μA
8.2 Typical Application
Figure 15. LM48100Q-Q1 Demo Board Schematic
18 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM48100Q-Q1
LM48100Q-Q1
www.ti.com
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 8 as the input parameters.
Table 8. Design Parameters
DESIGN PARAMETER EXAMPLE VALUES
Supply Voltage Range 3 V to 5.5 V
I2C Supply Voltage Range 1.8 V to 5.5 V
Temperature Range –40 °C to 105 °C
Input Voltage Range –0.3 V to VDD = 0.3 V
8.2.2 Detailed Design Procedure
8.2.2.1 Power Supply Bypassing/Filtering
Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass
capacitors as close to the device as possible. Place a 1-µF ceramic capacitor from VDD to GND. Additional bulk
capacitance may be added as required.
8.2.2.2 Input Capacitor Selection
Input capacitors may be required for some applications, or when the audio source is single-ended. Input
capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of
the audio source and the bias voltage of the LM48100Q-Q1. The input capacitors create a high-pass filter with
the input resistors RIN. The –3 dB point of the high-pass filter is found using Equation 4.
f = 1 / 2πRINCIN (Hz)
where
• RIN is given in the Electrical Characteristics tables found in Specifications (4)
High pass filtering the audio signal helps protect the speakers. When the LM48100Q-Q1 is using a single-ended
source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the
power supply noise frequencies, filters out the noise such that it is not amplified and heard on the output.
Capacitors with a tolerance of 10% or better are recommended for impedance matching and improved PSRR.
8.2.2.3 Bias Capacitor Selection
The LM48100Q-Q1 internally generates a VDD/2 common-mode bias voltage. The BIAS capacitor CBIAS,
improves PSRR and THD+N by reducing noise at the BIAS node. Use a 2.2-µF ceramic placed as close to the
device as possible.
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM48100Q-Q1
LM48100Q-Q1
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
www.ti.com
8.2.3 Application Curve
(1) IN1
(2) OUTB
(3) OUTA
Figure 16. Input and Output Waveforms for a 1kHz Sine Wave
9 Power Supply Recommendations
The LM48100Q-Q1 is designed be operate with a power supply between 3.0 V and 5.5 V. Proper power supply
bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close to
the device as possible. Place a 1-μF ceramic capacitor from VDD to GND. Additional bulk capacitance may be
added as required.
10 Layout
10.1 Layout Guidelines
Minimize trace impedance of the power, ground and all output traces for optimum performance. Voltage loss due
to trace resistance between the LM48100Q-Q1 and the load results in decreased output power and efficiency.
Trace resistance between the power supply and ground has the same effect as a poorly regulated supply,
increased ripple and reduced peak output power. Use wide traces for power supply inputs and amplifier outputs
to minimize losses due to trace resistance, as well as route heat away from the device. Proper grounding
improves audio performance, minimizes crosstalk between channels and prevents digital noise from interfering
with the audio signal. Use of power and ground planes is recommended.
Place all digital components and route digital signal traces as far as possible from analog components and
traces. Do not run digital and analog traces in parallel on the same PCB layer. If digital and analog signal lines
must cross either over or under each other, ensure that they cross in a perpendicular fashion.
10.1.1 Exposed DAP Mounting Considerations
The LM48100Q-Q1 HTSSOP-EP package features an exposed die-attach (thermal) pad on its backside. The
exposed pad provides a direct heat conduction path from the die to the PCB, reducing the thermal resistance of
the package. Connect the exposed pad to GND with a large pad and via to a large GND plane on the bottom of
the PCB for best heat distribution.
20 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM48100Q-Q1
Use wide traces for power supply
inputs and amplifier outputs
Place bypass capacitors close
to the device
Route digital signal traces far
from analog traces
LM48100Q-Q1
www.ti.com
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
10.2 Layout Example
Figure 17. Example Board Layout Implementing Layout Guidelines
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM48100Q-Q1
LM48100Q-Q1
SNAS470E –OCTOBER 2008–REVISED NOVEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
Boomer, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM48100Q-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM48100QMH/NOPB ACTIVE HTSSOP PWP 14 94 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 L48100Q
LM48100QMHE/NOPB ACTIVE HTSSOP PWP 14 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 L48100Q
LM48100QMHX/NOPB ACTIVE HTSSOP PWP 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 L48100Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2015
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM48100QMHE/NOPB HTSSOP PWP 14 250 178.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
LM48100QMHX/NOPB HTSSOP PWP 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM48100QMHE/NOPB HTSSOP PWP 14 250 210.0 185.0 35.0
LM48100QMHX/NOPB HTSSOP PWP 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2015
Pack Materials-Page 2
MECHANICAL DATA
PWP0014A
www.ti.com
MXA14A (Rev A)
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
LM48100QMH LM48100QMH/NOPB LM48100QMHE/NOPB LM48100QMHEVAL LM48100QMHX
LM48100QMHX/NOPB