W49F020 256K x 8 CMOS FLASH MEMORY 1. GENERAL DESCRIPTION The W49F020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K x 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49F020 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. 2. FEATURES * Single 5-volt operations: - 5-volt read - 5-volt erase - 5-volt program * Low power consumption - Active current: 25 mA (typ.) - Standby current: 20 A (typ.) * Automatic program and erase timing with internal VPP generation * Fast Program operation: - Byte-by-Byte programming: 50 S (max.) * End of program or erase detection * Fast erase operation: 100 mS (typ.) - Toggle bit * Fast read access time: 70/90 nS - Data polling * Endurance: 10K cycles (typ.) * Latched address and data * Twenty-year data retention * TTL compatible I/O * Hardware data protection * JEDEC standard byte-wide pinouts * One 8K Byte boot block with lockout protection * Available packages: 32-pin DIP and 32-pin TSOP and 32-pin-PLCC -1- Publication Release Date: April 14, 2005 Revision A4 W49F020 3. PIN CONFIGURATIONS #RESET 1 32 VDD A16 2 31 #WE A15 3 30 A12 4 29 A17 A14 A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 32-pin DIP A3 9 24 #OE A2 10 23 A10 A1 11 22 #CE A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 Vss 16 17 DQ3 4. BLOCK DIAGRAM VDD VSS #CE #OE #WE #RESET OUTPUT BUFFER CONTROL A0 . MAIM MEMORY 248K BYTES DECODER . BOOT BLOCK 8K BYTES A17 A7 5 29 A14 A6 6 28 A13 A5 7 27 A8 A4 8 A3 9 A2 A1 A0 12 DQ0 13 26 A9 25 A11 10 24 11 23 #OE A10 22 21 5. PIN DESCRIPTION #CE DQ7 14 15 16 17 18 19 20 SYMBOL D D V D D D D Q Q s Q Q Q Q 1 2 s 3 4 5 6 A0 - A17 A11 A9 A8 A13 A14 A17 1 2 6 27 #WE VDD #RESET A16 A15 A12 A7 A6 A5 A4 7 26 25 32 31 30 3 8 9 10 11 12 13 14 15 16 29 28 32-pin TSOP 02000 01FFF 00000 4 3 2 1 32 31 30 4 5 DQ7 3FFFF # R A A A E V # A 1 1 1 S E D W 1 2 5 6 T D E 7 32-pin PLCC DQ0 . . 24 23 22 2 1 20 19 18 17 DQ0 - DQ7 #OE A10 #CE DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3 Address Inputs Data Inputs/Outputs #CE Chip Enable #OE Output Enable #WE Write Enable #RESET -2- PIN NAME Reset VDD Power Supply VSS Ground NC No Connection W49F020 6. FUNCTIONAL DESCRIPTION Read Mode The read operation of the W49F020 is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the timing waveforms for further details. Reset Operation The #RESET pin provides a hardware method of resetting the device to reading array data. When the system drives the #RESET pin low for at least a period of tRSTP, the device immediately terminates any operation in progress and ignores all attempts for the duration of the #RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the #RESET pulse. When #RESET is held at VIL, the device enters the TTL standby mode; if #RESET is held at Vss, the device enters the CMOS standby mode. The #RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Boot Block Operation There is an 8K-byte boot block in this device, which can be used to store boot code. The boot block locates in the first 8K bytes of the memory with the address range from 0000(hex) to 1FFF(hex). For the specific code, please see Command Codes for Boot Block Lockout Enable. When the boot block is enabled, data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. When the boot block programming lockout feature is activated, the chip erase function cannot erase the boot block any longer. In order to detect whether the boot block feature is set on the 8K-bytes block or not, users can perform software command sequence to check it. First, enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 hex". If the output data is "1," the boot block programming lockout feature is activated; if the output data is "0," the lockout feature is inactivated and the block can be erased/programmed. To return to normal operation, perform a three-byte command sequence (or an alternate single-word command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection. Chip Erase Operation The chip-erase mode can be initiated by a six-word command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed in a fast 100 mS (typical). The host system is not required to provide any control or timing during this operation. If the boot block programming lockout is activated, only the data in the main memory blocks will be erased to FF(hex), and the data in the boot block will not be erased (remains same as before the chip erase operation). The entire memory array will be erased to FF hex by the chip erase operation if the boot block programming lockout feature is not activated. Once the boot block lockout feature is activated, the chip erase function erase the main memory block but not the boot block. The device will -3- Publication Release Date: April 14, 2005 Revision A4 W49F020 automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle. Program Operation The W49F020 is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0." The erase operation (changed entire data in main memory blocks and/or boot block from "0" to "1") is needed before programming. The program operation is initiated by a 4-word command cycle (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byte-program command is entered. The internal program timer will automatically time-out (50 S max. TBP) when completing programming and return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle. Hardware Data Protection The integrity of the data stored in the W49F020 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse with less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is less than 2.5V typical. (3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation. Data Polling (DQ7)- Write Status Detection The W49F020 features a data polling function which used to indicate the end of a program or erase cycle. When the W49F020 is in the internal program or erase cycle, any attemption to read DQ7 of the last word loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and become logical "1" or true data when the erase cycle has been completed. Toggle Bit (DQ6)- Write Status Detection In addition to data polling, the W49F020 provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In software access mode, a three-word (or JEDEC 3-word) command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code DA(hex); and a read from address 0001H outputs the device code 8C(hex) for W49F020. The product ID operation can be terminated by a three-word command sequence or an alternated one-word command sequence (see Command Definition table). -4- W49F020 In the hardware access mode, access to the product ID will be activated by forcing #CE and #OE low, #WE high, and raising A9 to 12 volts. Table of Operating Modes Operating Mode Selection (VHH = 12V 5%) PINS MODE #CE #OE #WE #RESET Read VIL VIL VIH VIH AIN Dout Write VIL VIH VIL VIH AIN Din Standby VIH X X VIH X High Z X VIL X X X High Z/DOUT X X VIH VIH X High Z/DOUT Output Disable X VIH X VIH X High Z Reset X X X VIL X High Z VIL VIL VIH VIH A0 = VIL; A1 - A17 = VIL; Manufacturer Code DA (Hex) A9 = VHH VIL VIL VIH VIH A0 = VIL; A1 - A17 = VIL; Device Code 8C (Hex) A9 = VHH Write Inhibit Product ID ADDRESS DQ0-DQ7 Table of Command Definition COMMAND DESCRIPTION NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 2AAA 55 5555 10 2AAA 55 5555 40 Read 1 Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA Byte Program 4 5555 AA 2AAA 55 5555 A0 AIN Boot Block Lockout 6 5555 AA 2AAA 55 5555 80 5555 AA Product ID Entry AIN DOUT 3 5555 AA 2AAA 55 5555 90 Product ID Exit (1) 3 5555 AA 2AAA 55 5555 F0 Product ID Exit (1) 1 XXXX F0 DIN Notes: 1. Address Format: A14 - A0 (Hex); Data Format: DQ7 - DQ0 (Hex) 2. Either one of the two Product ID Exit commands can be used. -5- Publication Release Date: April 14, 2005 Revision A4 W49F020 Embedded Programming Algorithm Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit Pause TBP No Increment Address Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data -6- W49F020 Embedded Erase Algorithm Start Write Erase Command Sequence (see below) #Data Polling or Toggle Bit Successfully Completed Pause TEC/TSEC Erasure Completed Chip Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H 5555H/10H -7- Publication Release Date: April 14, 2005 Revision A4 W49F020 Embedded #Data Polling Algorithm Start Read Byte (DQ0 - DQ7) Address = VA No VA = Byte address for programming = Any sector group address during chip erase DQ7 = Data ? Yes Pass Embedded Toggle Bit Algorithm Start Read Byte (DQ0-DQ7) Address = Don't Care Yes DQ6 = Toggle ? No Pass -8- W49F020 Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Product Identification and Boot Block Lockout Detection Mode (3) Product Identification Exit (6) Load data AA to address 5555 Load data 55 to address 2AAA Read address = 00000 data = DA Load data 90 to address 5555 Read address = 00001 data = 8C Pause 10 S Read address = 00002 data = FF/FE (2) Load data 55 to address 2AAA (2) Load data F0 to address 5555 (4) Pause 10 S (5) Normal Mode Notes for software product identification/boot block lockout detection: (1) Data Format: DQ15-DQ8 (Don't Care), DQ7 - DQ0 (Hex); Address Format: A14 - A0 (Hex) (2) A1 - A15 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is inactivated and the block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection. -9- Publication Release Date: April 14, 2005 Revision A4 W49F020 Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause 1 Sec. Exit Notes for boot block lockout enable: Data Format: DQ7 - DQ0 (Hex) Address Format: A14 - A0 (Hex) - 10 - W49F020 7. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +7.0 V 0 to +70 C -65 to +150 C D.C. Voltage on Any Pin to Ground Potential except #OE -0.5 to VDD +1.0 V Transient Voltage (<20 nS) on Any Pin to Ground Potential -1.0 to VDD +1.0 V -0.5 to 12.5 V Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature Voltage on #OE Pin to Ground Potential Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Operating Characteristics (VDD = 5.0V 10%, VSS = 0V, TA = 0 to 70 C) PARAMETER SYM. TEST CONDITIONS #CE = #OE = VIL, #WE = VIH, all DQs open Power Supply Current ICC Standby VDD ISB1 #CE = VIH, all DQs open (CMOS input) MIN. TYP. MAX. UNIT - 25 50 mA - 2 3 mA - 20 100 A Address inputs = VIL/VIH, at f = 5 MHz Other inputs = VIL/VIH Current (TTL input) Standby VDD Current LIMITS ISB2 #CE = VDD -0.3V, all DQs open Other inputs = VDD -0.3V/ VSS Input Leakage Current ILI VIN = VSS to VDD - - 10 A Output Leakage Current ILO VOUT = VSS to VDD - - 10 A Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.0 - VDD +0.5 V Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V - 11 - W49F020 Power-up Timing PARAMETER Power-up to Read Operation SYMBOL TPU. READ Power-up to Write Operation TPU. WRITE TYPICAL 100 5 UNIT S mS Capacitance (VDD = 5.0V, TA = 25 C, f = 1 MHz) PARAMETER I/O Pin Capacitance SYMBOL CI/O Input Capacitance CONDITIONS VI/O = 0V CIN VIN = 0V MAX. 12 UNIT pF 6 pF AC Test Conditions PARAMETER Input Pulse Levels CONDITIONS 0V to 3.0V Input Rise/Fall Time < 5 nS Input/Output Timing Level Output Load 1.5V/1.5V 1 TTL Gate and CL = 100 pF for 90 nS CL = 30 pF for 70 nS AC Test Load and Waveform +5V 1.8K 1.3K D OUT 30 pF for 70nS 100 pF for 90nS (Including Jig and Scope) Input Output 3V 1.5V 1.5V 0V Test Point - 12 - Test Point W49F020 Read Cycle Timing Parameters (VDD = 5.0V 10%, VDD = 0V, TA = 0 to 70 C) PARAMETER SYM. W49F020-70 W49F020-90 MIN. MAX. MIN. MAX. UNIT Read Cycle Time TRC 70 - 90 - nS Chip Enable Access Time TCE - 70 - 90 nS Address Access Time TAA - 70 - 90 nS Output Enable Access Time TOE - 35 - 40 nS #CE Low to Active Output TCLZ 0 - 0 - nS #OE Low to Active Output TOLZ 0 - 0 - nS #CE High to High-Z Output TCHZ - 25 - 25 nS #OE High to High-Z Output TOHZ - 25 - 25 nS TOH 0 - 0 - nS SYMBOL MIN. TYP. MAX. UNIT Output Hold from Address Change Write Cycle Timing Parameters PARAMETER Address Setup Time TAS 0 - - nS Address Hold Time TAH 50 - - nS #WE and #CE Setup Time TCS 0 - - nS #WE and #CE Hold Time TCH 0 - - nS #OE High Setup Time TOES 0 - - nS #OE High Hold Time TOEH 0 - - nS #CE Pulse Width TCP 100 - - nS #WE Pulse Width TWP 100 - - nS #WE High Width TWPH 100 - - nS Data Setup Time TDS 50 - - nS Data Hold Time TDH 0 - - nS Byte programming Time TBP - 10 50 S Erase Cycle Time TEC - 0.1 1 S Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL. - 13 - Publication Release Date: April 14, 2005 Revision A4 W49F020 Data Polling and Toggle Bit Timing Parameters PARAMETER SYMBOL W49F020-70 W49F020-90 MIN. MAX. MIN. MAX. UNIT #OE to Data Polling Output Delay TOEP - 35 - 40 nS #CE to Data Polling Output Delay TCEP - 70 - 90 nS #OE to Toggle Bit Output Delay TOET - 35 - 40 nS #CE to Toggle Bit Output Delay TCET - 70 - 90 nS Reset Timing Parameters PARAMETER SYMBOL MIN. TYP. MAX. UNIT VDD stable to Reset Active TPRST 1 - - mS Reset Pulse Width TRSTP 500 - - nS Reset Active to Output Float TRSTF - - 50 nS Reset Inactive to Input Active TRST 1 - - S - 14 - W49F020 9. TIMING WAVEFORMS Read Cycle Timing Diagram TRC Address A17-0 TCE #CE TOE #OE T OHZ TOLZ VIH #WE TCLZ TOH DQ7-0 TCHZ High-Z High-Z Data Valid Data Valid TAA #WE Controlled Command Write Cycle Timing Diagram TAS TAH Address A17-0 #CE TCS TCH TOES T OEH #OE TWP #WE TWPH TDS DQ7-0 Data Valid TDH - 15 - Publication Release Date: April 14, 2005 Revision A4 W49F020 Timing Waveforms, continued #CE Controlled Command Write Cycle Timing Diagram TAS TAH Address A17-0 TCPH TCP #CE TOES TOEH #OE #WE TDS DQ7-0 High Z Data Valid TDH Program Cycle Timing Diagram Byte Program Cycle Address A17-0 2AAA 5555 AA DQ7-0 5555 55 Address A0 Data-In #CE #OE TWP T WPH TBP #WE Byte 0 Byte 1 Byte 2 - 16 - Byte 3 Internal Write Start W49F020 Timing Waveforms, continued #DATA Polling Timing Diagram Address A17-0 #WE TCEP #CE TOEH TOES #OE TOEP DQ7 X X X X TBP or TEC Toggle Bit Timing Diagram Address A17-0 #WE #CE TOES TOEH #OE DQ6 TBP or TEC - 17 - Publication Release Date: April 14, 2005 Revision A4 W49F020 Timing Waveforms, continued Boot Block Lockout Enable Timing Diagram Six byte code for Boot Block Lockout Feature Enable Address A17-0 DQ7-0 5555 2AAA XX55 XXAA 5555 5555 XX80 2AAA XXAA XX55 5555 XX40 #CE #OE TWP TEC #WE TWPH SB0 SB1 SB2 SB3 SB4 SB5 Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase Address A17-0 DQ7-0 5555 2AAA XXAA XX55 5555 5555 XX80 XXAA 2AAA XX55 5555 XX10 #CE #OE TWP TEC #WE TWPH SB0 SB1 SB2 - 18 - SB3 SB4 SB5 Internal Erase starts W49F020 Timing Waveforms, continued Reset Timing Diagram VDD TPRST TRSTP #RESET TRSTF TRST Address A17-0 DQ7-0 - 19 - Publication Release Date: April 14, 2005 Revision A4 W49F020 10. ORDERING INFORMATION PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VDD CURRENT MAX. (A) PACKAGE CYCLE W49F020-90B 90 50 100 (CMOS) 32-pin DIP 10K W49F020T-70B 70 50 100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 10K W49F020T-90B 90 50 100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 10K W49F020P-70B 70 50 100 (CMOS) 32-pin PLCC 10K W49F020P-90B 90 50 100 (CMOS) 32-pin PLCC 10K Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. The part number shown in the Ordering Information table is only for Bottom Boot Block part, which is in the lower address range. For the requirement of the higher address range boot block, the Top Boot Block, please contact Winbond FAE for details. 11. HOW TO READ THE TOP MARKING Example: The top marking of 32-pin PLCC W49F020P-90B W49F020P-90B 2138977A-A12 149OBSA 1st line: winbond logo 2nd line: the part number: W49F020P-90B 3rd line: the lot number 4th line: the tracking code: 149 O B SA 149: Packages made in '01, week 49 O: Assembly house ID: A means ASE, O means OSE, ...etc. B: IC revision; A means version A, B means version B, ...etc. SA: Process code - 20 - W49F020 12. PACKAGE DIMENSIONS 32-pin P-DIP Symbol A A1 A2 B B1 c D E E1 e1 L D 17 32 E1 16 1 E S A1 L a B1 0.25 0.150 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.048 0.050 0.054 1.22 1.27 1.37 0.008 0.010 0.014 0.20 0.25 0.36 1.650 1.660 41.91 42.16 0.600 0.610 14.99 15.24 15.49 0.545 0.550 0.555 13.84 13.97 14.10 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 15 0 0.670 16.00 16.51 17.02 0.590 eA S Notes: 0.630 0.650 15 0.085 2.16 1.Dimensions D Max. & S include mold flash or tie bar burrs. 2.Dimension E1 does not include interlead flash. 3.Dimensions D & E1. include mold mismatch and are determined at the mold parting line. 4.Dimension B1 does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches 6.General appearance spec. should be based on final visual inspection spec. Base Plane e1 5.33 0.210 0.010 0 Seating Plane B Dimension in mm Min. Nom. Max. Min. Nom. Max. a c A A2 Dimension in inches eA 32-pin PLCC Symbol HE E 4 1 32 30 5 29 GD D HD 21 13 A A1 A2 b1 b c D E e GD GE HD HE L y Dimension in Inches Min. Nom. Max. Dimension in mm Min. Nom. Max. 2.67 2.80 2.93 0.81 3.56 0.140 0.50 0.020 0.105 0.110 0.026 0.028 0.016 0.115 0.66 0.71 0.018 0.022 0.41 0.46 0.008 0.010 0.014 0.20 0.25 0.35 0.547 0.550 0.553 13.89 13.97 14.05 0.447 0.450 0.453 11.35 11.43 11.51 0.044 0.050 0.056 1.12 1.27 1.42 0.490 0.51 0.530 12.45 13.46 0.032 0.56 0.390 0.410 0.430 9.91 12.9 5 10.41 0.585 0.590 0.595 14.86 14.99 15.11 0.485 0.49 0 0.090 0.495 12.32 12.45 12.57 0.095 1.91 2.29 2.41 0.075 0.10 0.004 0 10 10.92 0 10 Notes: 14 1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection sepc. c 20 L A2 e b b1 Seating Plane GE A A1 y - 21 - Publication Release Date: April 14, 2005 Revision A4 W49F020 Package Dimensions, continued 32-pin TSOP HD Dimension in Inches Dimension in mm Symbol D A c A1 M e E 0.10(0.004) b __ 0.002 0.006 0.05 __ Max. 1.20 0.15 0.039 0.041 0.95 1.00 1.05 0.009 0.17 0.20 0.23 c 0.005 0.006 0.007 0.12 0.15 0.17 D 0.720 0.724 0.728 18.30 18.40 18.50 E 0.311 0.315 0.319 7.90 8.00 8.10 HD 0.780 0.787 0.795 19.80 20.00 20.20 __ 0.016 __ 1 Y 0.000 1 0.020 0.020 0.031 __ 3 __ __ 0.024 0.40 __ __ 0.004 0.00 5 1 Note: Controlling dimension: Millimeters - 22 - __ 0.008 A1 Y Nom. __ 0.037 A2 L1 __ 0.047 Min. 0.007 L L __ Max. b L Nom. A2 e A Min. 0.50 0.50 0.80 __ 3 __ 0.60 __ 0.10 5 W49F020 13. VERSION HISTORY VERSION DATE PAGE A1 Oct. 1999 - A2 Dec. 18, 2002 1, 21 DESCRIPTION Initial Issued Delete 1K endurance 21 Change W49F020Q 70/90 to W49F020T-70/90 4 Modify the description of VDD Power Up/Down Detection in Hardware Data Protection 6-10 Delete old flow chart and add embedded algorithm Correct Part. No for ordering information 21 Delete Part. No of W49F020-70B for ordering information 21 Add HOW TO READ THE TOP MARKING 2, 3, 14, 19 A3 A4 Feb. 21, 2003 April 14 , 2005 Add in #RESET function 7 Correct Embedded Erase Algorithm (Delete Main-memory Erase Command Sequence) 8 Correct VA(Valid Address) definition in Embedded #Data Polling Algorithm 23 Add important notice Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 23 - Publication Release Date: April 14, 2005 Revision A4 W49F020 Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 24 -