PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM DDR2 SDRAM SODIMM MT8HTF3264HD - 256MB MT8HTF6464HD - 512MB (ADVANCE) MT8HTF12864HD - 1GB (ADVANCE) For the latest data sheet, please refer to the Microna Web site: www.micron.com/moduleds Features Figure 1: 200-Pin SODIMM (MO-224 R/C "A") * 200-pin, small outline, dual in-line memory module (SODIMM) * Fast data transfer rates: PC2-3200 or PC2-4300 * Utilizes 400 MT/s and 533 MT/s DDR2 SDRAM components * 256MB (32 Meg x 64), 512MB (64 Meg x 64) 1GB (128 Meg x 64) * VDD = +1.8V 0.1V * VDDSPD = +1.7V to +3.6V * JEDEC standard 1.8V I/O (SSTL_18-compatible) * Differential data strobe (DQS, DQS#) option * Four-bit prefetch architecture * Differential clock inputs (CK, CK#) * Commands entered on each rising CK edge * DQS edge-aligned with data for READs * DQS center-aligned with data for WRITEs * DLL to align DQ and DQS transitions with CK * Four or eight internal device banks for concurrent operation * Data mask (DM) for masking write data * Programmable CAS# latency (CL): 3 and 4 * Posted CAS# additive latency (AL): 0, 1, 2, 3, and 4 * WRITE latency = READ latency - 1 tCK * Programmable burst lengths: 4 or 8 * READ burst interrupt supported by another READ * WRITE burst interrupt supported by another WRITE * Adjustable data-output drive strength * Concurrent auto precharge option is supported * Auto Refresh (CBR) and Self Refresh Mode 7.8125s maximum average periodic refresh interval * 64ms, 8,192-cycle refresh Table 1: Off-chip driver (OCD) impedance calibration On-die termination (ODT) Serial Presence Detect (SPD) with EEPROM Gold edge contacts OPTIONS MARKING * Package 200-pin SODIMM (standard) 200-pin SODIMM (lead-free)1 * Frequency/CAS Latency2 3.75ns @ CL = 4 (DDR2-533) 5.0ns @ CL = 3 (DDR2-400) NOTE: G Y -53E -40E 1. Consult factory for availability of lead-free products. 2. CL = CAS (READ) Latency. Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN PRODUCTS * * * * 256MB 512MB 1GB 8K 8K (A0-A12) 4 (BA0, BA1) 256Mb (16 Meg x 16) 512 (A0-A8) 2 (S0#, S1#) 8K 8K (A0-A12) 4 (BA0, BA1) 512Mb (32 Meg x 16) 1K (A0-A9) 2 (S0#, S1#) 8K 8K (A0-A12) 8 (BA0, BA1, BA2) 1Gb (64 Meg x 16) 1K (A0-A9) 2 (S0#, S1#) 1 (c)2003 Micron Technology, Inc. AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 1: Key Timing Parameters DATA RATE (MHz) SPEED GRADE CL = 3 CL = 4 RCD (ns) t RP (ns) t RC (ns) -40E -53E 400 400 400 533 15 15 15 15 60 60 Table 2: t Part Numbers and Timing Parameters MODULE DENSITY CONFIGURATION MODULE BANDWIDTH MEMORY CLOCK/ DATA RATE LATENCY (CL - tRCD - tRP) MT8HTF6464HDG-40E__2 256MB 256MB 256MB 256MB 512MB 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 64 Meg x 64 3.2 GB/s 3.2 GB/s 4.3 GB/s 4.3 GB/s 3.2 GB/s 5.0ns/400 MT/s 5.0ns/400 MT/s 3.75ns/533 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 3-3-3 3-3-3 4-4-4 4-4-4 3-3-3 MT8HTF6464HDY-40E__2 512MB 64 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT8HTF6464HDG-53E__2 512MB 64 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4 PART NUMBER1 MT8HTF3264HDG-40E__ MT8HTF3264HDY-40E__ MT8HTF3264HDG-53E__ MT8HTF3264HDY-53E__ 512MB 64 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4 2 1GB 128 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3 2 1GB 128 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3 2 MT8HTF12864HDG-53E__ 1GB 128 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4 MT8HTF12864HDY-53E__2 1GB 128 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4 MT8HTF6464HDY-53E__2 MT8HTF12864HDG-40E__ MT8HTF12864HDY-40E__ NOTE: 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8HTF6464HDG-40EC2. 2. Contact Micron for product availability. 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 3: Pin Assignment (200-pin SODIMM Front) Table 4: Pin Assignment (200-pin SODIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 Vss DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC NC/BA2 VDD A12 A9 A8 VDD A5 A3 101 A1 151 103 VDD 153 105 A10/AP 155 107 BA0 157 109 WE# 159 111 VDD 161 113 CAS# 163 115 S1# 165 117 VDD 167 119 ODT1 169 121 VSS 171 123 DQ32 173 125 DQ33 175 127 VSS 177 129 DQS4# 179 131 DQS4 181 133 VSS 183 135 DQ34 185 137 DQ35 187 139 VSS 189 141 DQ40 191 143 DQ41 193 145 VSS 195 147 DM5 197 149 VSS 199 DQ42 DQ43 VSS DQ48 DQ49 VSS NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS CKE1 VDD NC NC VDD A11 A7 A6 VDD A4 A2 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 A0 VDD BA1 RAS# S0# VDD ODT0 NC VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1 NOTE: Pin 85 is No Connect for 256MB and 512MB, BA2 for 1GB. Figure 2: Pin Locations Front View U1 Back View U2 U3 U4 U5 U6 U8 U9 U7 PIN 1 (all odd pins) PIN 199 PIN 200 Indicates a VDD or VDDQ pin 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 3 (all even pins) PIN 2 Indicates a VSS pin Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION 114, 119 ODT0, ODT1 Input 30, 32, 164, 166 CK0, CK0# CK1, CK1# Input 79, 80 CKE0, CKE1 Input 110, 115 S0#, S1# Input 108, 109, 113 RAS#, CAS#, WE# Input 85 (1GB), 106, 107 BA0, BA1, BA2 (1GB) Input 89, 90, 91, 92, 93, 94, 97, 98, 99, 100, 101, 102, 105 A0-A12 Input On-Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. Clock Enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWERDOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry, POWER-DOWN exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_18 input but will detect a LVCMOS LOW level once VDD is applied during first power-up. After Vref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh operation VREF must be maintained to this input. Chip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# provides for external rank selection on systems with multiple ranks. S# is considered part of the command code. Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Bank Address Inputs: BA0-BA2 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0-BA2 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for Read/ Write commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0-BA2) or all device banks (A10 HIGH). The address inputs also provide the opcode during a LOAD MODE command. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. 10, 26, 52, 67, 130, 147, 170, DM0-DM7 185 UDM = DM0, DM2, DM5, DM7 LDM = DM 1, DM3, DM4, DM6 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN Input 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DQ0-DQ63 I/O Data Input/Output: Bidirectional data bus. DQS0-DQS7, DQS0#-DQS7# I/O 197 SCL Input 198, 200 SA0-SA1 Input 195 SDA Input/ Output 81, 82, 87, 88, 95, 96, 103, 104, 111, 112, 117, 118 1 2, 3, 8, 9, 12, 15, 18, 21, 24, 27, 28, 33, 34, 39, 40, 41, 42, 47, 48, 53, 54, 59, 60, 65, 66, 71, 72, 77, 78, 121, 122, 127, 128, 132, 133, 138, 139, 144, 145, 149, 150, 155, 156, 161, 162, 165, 168, 171, 172, 177, 178, 183, 184, 187, 190, 193, 196 199 50, 69, 83, 84, 85 (256MB and 512MB), 86, 116, 120, 163, VDD Supply VREF VSS Supply Supply Data Strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. Power Supply: +1.8V 0.1V. Also connects to VDDS/VDDQ, VDDL, and VSSL on the DDR2 SDRAM device. SSTL_18 reference voltage. Ground. Also connects to VDDS/VDDQ, VDDL, and VSSL on the DDR2 SDRAM device. 4, 5, 6, 7, 14, 16, 17, 19, 20, 22, 23, 25, 35, 36, 37, 38, 43, 44, 45, 46, 55, 56, 57, 58, 61, 62, 63, 64, 73, 74, 75, 76, 123, 124, 125, 126, 134, 135, 136, 137, 140, 141, 142, 143, 151, 152, 153, 154, 157, 158, 159, 160, 173, 174, 175, 176, 179, 180, 181, 182, 189, 191, 192, 194 11, 13, 29, 31, 49, 51, 68, 70, 129, 131, 146, 148, 167, 169, 186, 188 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN VDDSPD NC DESCRIPTION Supply Serial EEPROM positive power supply: +1.7V to +3.6V. -- No Connect: These pins should be left unconnected. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Figure 3: Functional Block Diagram 3 S1# S0# DQS0 DQS0# DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1# DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2# DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3# DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UDQS UDQS# UDM DQ DQ DQ DQ DQ DQ DQ DQ LDQS LDQS# LDM DQ DQ DQ DQ DQ DQ DQ DQ UDQS UDQS# UDM DQ DQ DQ DQ DQ DQ DQ DQ LDQS LDQS# LDM DQ DQ DQ DQ DQ DQ DQ DQ CS# U1 CS# U2 UDQS UDQS# UDM DQ DQ DQ DQ DQ DQ DQ DQ LDQS LDQS# LDM DQ DQ DQ DQ DQ DQ DQ DQ UDQS UDQS# UDM DQ DQ DQ DQ DQ DQ DQ DQ LDQS LDQS# LDM DQ DQ DQ DQ DQ DQ DQ DQ BA0-BA1: DDR2 SDRAMs BA0-BA2: DDR2 SDRAMs A0-A12: DDR2 SDRAMs A0-A13: DDR2 SDRAMs RAS#: DDR2 SDRAMs CAS#: DDR2 SDRAMs WE#: DDR2 SDRAMs CKE0: DDR2 SDRAMs CKE1: DDR2 SDRAMs ODT0: DDR2 SDRAMs ODT1: DDR2 SDRAMs BA0-BA1 (256MB, 512MB) BA0-BA2 (1GB) A0-A12 (256MB, 512MB) A0-A13 (1GB) RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 CS# LDQS LDQS# LDM DQ DQ DQ DQ DQ DQ DQ DQ UDQS UDQS# UDM DQ DQ DQ DQ DQ DQ DQ DQ DQS4 DQS4# DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U9 DQS5 DQS5# DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CS# LDQS LDQS# LDM DQ DQ DQ DQ DQ DQ DQ DQ UDQS UDQS# UDM DQ DQ DQ DQ DQ DQ DQ DQ DQS6 DQS6# DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U8 DQS7 DQS7# DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U7 Serial PD SCL WP A0 A1 CS# U3 CS# LDQS LDQS# LDM DQ DQ DQ DQ DQ DQ DQ DQ UDQS UDQS# UDM DQ DQ DQ DQ DQ DQ DQ DQ U4 CS# U6 CS# U5 200 SDA CK0 CK0# A2 SA0 SA1 VDDSPD VDD, VDDQ, VDDL VREF VSS LDQS LDQS# LDM DQ DQ DQ DQ DQ DQ DQ DQ UDQS UDQS# UDM DQ DQ DQ DQ DQ DQ DQ DQ U1, U2, U8, U9 200 200 CK1 CK1# Serial PD DDR2 SDRAMS DDR2 SDRAMS DDR2 SDRAMS, EEPROM U3, U4, U5, U6 200 3 NOTE: 1. Unless otherwise noted, resistor values are 22W. 2. Micron module part numbers are explained in the Module Part Numbering Guide at www.micron.com/numberguide. 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 6 MT47H16M16FP = DDR2 SDRAM used in 256MB Module MT47H32M16FP = DDR2 SDRAM fused in 512MB Module MT47H64M16FP = DDR2 SDRAM used in 1GB Module Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM General Description The MT8HTF3264HD, MT8HTF6464HD, and MT8HTF12864HD DDR2 SDRAM modules are highspeed, CMOS, dynamic random-access 256MB, 512MB, and 1GB memory modules organized in x64 configuration. DDR2 SDRAM modules use internally configured quad-bank (256MB, 512MB) or eight-bank (1GB) DDR2 SDRAM devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-wide, one-clockcycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR2 SDRAM modules are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting column location for the burst access. DDR2 SDRAM modules provide for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read, or a burst write of eight with 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR2 SDRAMs allows for concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a powersaving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18-compatible. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (SODIMM) occur via a standard I2C bus using the SODIMM's SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique SODIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Functional Description DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The DDR2 architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bitwide, one-half-clock-cycle data transfers at the I/O pins. Prior to normal operation, DDR2 SDRAM modules must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Initialization The following sequence is required for power-up and initialization and is shown in Figure 4. When the sequence has been completed, the DDR2 SDRAM device is ready for normal operation. Apply power; if CKE is maintained below 20 percent of VDDQ, outputs remain disabled. To guarantee ODT is off, VREF must be valid and a low level must be applied to the ODT pin (all other inputs may be undefined). At least one of the following two sets of conditions (A or B) must be met: A. CONDITION SET A * VDD, VDDL and VDDQ are driven from a single power converter output * VTT is limited to 0.95V MAX * VREF tracks VDDQ/2. B. CONDITION SET B * Apply VDD before or at the same time as VDDL. * Apply VDDL before or at the same time as VDDQ. * Apply VDDQ before or at the same time as VTT and VREF. 3. For a minimum of 200ms after stable power and clock (CK, CK#), apply NOP or DESELECT commands and take CKE HIGH. 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 4. Wait a minimum of 400ns, then issue a PRECHARGE ALL command. 5. Issue an EMR(2) command. (To issue an EMR(2) command, provide LOW to BA0, and HIGH to BA1.) 6. Issue an EMR(3) command. (To issue an EMR(3) command, provide HIGH to BA0 and BA1.) 7. Issue an EMR to enable DLL. (To issue a DLL ENABLE command, provide LOW to BA1, A0 and provide HIGH to BA0.) 8. Issue a MODE REGISTER SET command for DLL RESET. 200 cycles of clock input is required to lock the DLL. (To issue a DLL RESET command, provide HIGH to A8 and provide LOW to BA0 and BA1.) 9. Issue PRECHARGE ALL command. 10. Issue two or more REFRESH commands. 11. Issue a MODE REGISTER SET command with LOW to A8 to initialize device operation (i.e., to program operating parameters without resetting the DLL). 12. At least 200 clocks after step 7, execute EMR OCD adjust mode if desired. If OCD adjust mode is not desired, then EMR OCD Default command is required followed by EMR OCD Exit command. 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Figure 4: DDR2 Power-Up and Initialization VDD VDDL VDDQ tVTD1 VTT1 VREF T0 CK tCL LVCMOS CKE LOW LEVEL8 tCL SSTL_18 LOW LEVEL8 ODT (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) COMMAND6 NOP2 Tc0 Tb0 Ta0 tCK CK# Ti0 Tj0 Tk0 Tl0 Tm0 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) PRE (( )) (( )) (( )) (( )) ADDRESS9 (( )) (( )) (( )) (( )) (( )) (( )) Rtt Th0 (( )) (( )) DM DQ Tg0 Tf0 (( )) (( )) (( )) (( )) DQS7 Te0 Td0 (( )) (( )) (( )) (( )) LM9 (( )) (( )) (( )) (( )) LM9 (( )) (( )) (( )) (( )) CODE9 (( )) (( )) (( )) (( )) LM (( )) (( )) CODE9 (( )) (( )) LM (( )) (( )) (( )) (( )) CODE9 CODE9 PRE (( )) (( )) REF4 (( )) (( )) REF4 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) LM5 (( )) (( )) LM5 (( )) (( )) CODE9 (( )) (( )) (( )) (( )) LM (( )) (( )) VALID3 (( )) (( )) (( )) (( )) CODE9 (( )) (( )) CODE9 (( )) (( )) VALID High-Z (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) High-Z (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) High-Z (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) tMRD t RP tRFC tRFC tMRD tMRD tMRD T = 200s (min) Power-up: VDD and stable clock (CK, CK#) T = 400ns (min) tRP tMRD EMR(2)9 tMRD EMR(3)9 tMRD MR w/o DLL Reset EMR with DLL Enable EMR with OCD Default5 EMR with OCD Exit5 200 cycles of CK3 MR with DLL Reset DON'T CARE NORMAL OPERATION NOTE: 1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up. One of the following two conditions (a or b) MUST be met: a) VDD, VDDL, and VDDQ are driven from a single power converter output. VTT may be 0.95V maximum during power up. VREF tracks VDDQ/2. b) Apply VDD before or at the same time as VDDL. Apply VDDL before or at the same time as VDDQ. Apply VDDQ before or at the same time as VTT and VREF. 2. Either a NOP or DESELECT command may be applied. 3. 200 cycles of clock (CK, CK#) are required before a READ command can be issued. 4. Two or more REFRESH commands are required. 5. EMR OCD Default command is required unless OCD adjust mode is used by the system; either command must be followed by an EMR OCD Exit command. 6. PRE = PRECHARGE command, LM = LOAD MODE command, REF = REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Device Bank Address. 7. DQS represents DQS, DQS#, RDQS, RDQS#. 8. CKE pin uses LVCMOS input levels prior to state T0. After state T0, CKE pin uses SSTL_18 input levels. 9. The LM command for EMR(2) and EMR(3) may be before or after LM command for MR (Tf0) and EMR (Te0). ADDRESS represents A0-A12, BA0, and BA1 (256MB, 512MB), or A0-A12, BA0, BA1, and BA2 (1GB). A10 should be HIGH at states Tb0 and Tg0 to ensure a PRECHARGE (all device banks) command is issued. 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Mode Register Burst Type The mode register is used to define the specific mode of operation of the DDR2 SDRAM. This definition includes the selection of a burst length, burst type, CAS latency, operating mode, DLL reset, write recovery, and power-down mode as shown in Figure 5. Contents of the mode register can be altered by reexecuting the LOAD MODE (LM) command. If the user chooses to modify only a subset of the MR variables, all variables (M0-M12 for 256MB, M0-M13 for 512MB, 1GB) must be programmed when the LOAD MODE command is issued. The mode register is programmed via the LM command with BA1, BA0 = 0,0. All other bits (M0-M12 for 256MB and M0-M13 for 512MB, 1GB) will retain the stored information until it is programmed again or the device loses power (except for bit M8, which is selfclearing). Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. The LOAD MODE command can only be issued (or reissued) when all device banks are in the precharged state. The controller must wait the specified time t MRD before initiating any subsequent operations such as an ACTIVE command. Violating either of these requirements will result in unspecified operation. Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3 as shown in Figure 5. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address as shown in Table 6. DDR2 SDRAM supports 4-bit burst and 8-bit burst modes only. For 8-bit burst mode, full interleave address ordering is supported; however, sequential address ordering is nibble-based. Operating Mode The normal operating mode is selected by issuing a LOAD MODE command with bit M7 set to zero, and all other bits set to the desired values as shown in Figure 5. When bit M7 is `1,' no other bits of the mode register are programmed. Programming bit M7 to `1' places the DDR2 SDRAM into a test mode that is only used by the Manufacturer and should NOT be used. No operation or functionality is guaranteed if M7 bit is `1.' Figure 5: Mode Register (MR) Definition BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 13 12 11 10 PD MR WR Burst Length Burst length is defined by bits M0-M3 as shown in Figure 5. Read and write accesses to the DDR2 SDRAM are burst-oriented, with the burst length being programmable to either four or eight. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2-A8 (256MB) or A2-A9 (512MB, 1GB) when the burst length is set to four and by A3-A9 when the burst length is set to eight (where A8 or A9 is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. 9 8 7 6 5 4 3 2 1 0 DLL TM CAS# Latency BT Burst Length M7 Mode PD Mode 0 Fast Exit (Normal) 1 Test M8 DLL Reset Slow Exit (Low Power) M11 M10 M9 M14 M13 1 Mode Register (Mx) M2 M1 M0 Burst Length 0 Normal M12 Address Bus 0 0 0 Reserved 0 0 1 Reserved 0 1 0 4 0 1 1 8 0 No 1 0 0 Reserved 1 Yes 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Write Recovery 0 0 0 Reserved 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 Reserved 1 1 1 Reserved Mode Register 0 0 Mode Register (MR) 0 1 Extended Mode Register (EMR) 1 0 Extended Mode Register (EMR2) 1 1 Extended Mode Register (EMR3) M3 Burst Type 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 Reserved 1 1 1 Reserved NOTE: 1GB mode register TBD. 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 6: STARTING COLUMN ADDRESS (A2, A1, BURST A0) LENGTH 4 8 enabled. The tXARD parameter is used for `fast-exit' active power-down exit timing. The DLL is expected to be enabled and running during this mode. When bit M12 = 1, a lower power active power-down mode or `slow-exit' active power-down mode is enabled. The tXARDS parameter is used for `slow-exit' active power-down exit timing. The DLL can be enabled, but `frozen' during active power-down mode since the exit-to-READ command timing is relaxed. The power difference expected between PD `normal' and PD `low-power' mode is defined in the IDD table. Burst Definition 000 001 010 011 000 001 010 011 100 101 110 111 ORDER OF ACCESSES WITHIN A BURST BURST TYPE = SEQUENTIAL BURST TYPE = INTERLEAVED 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 0,1,2,3,4,5,6,7 1,2,3,0,5,6,7,4 2,3,0,1,6,7,4,5 3,0,1,2,7,4,5,6 4,5,6,7,0,1,2,3 5,6,7,4,1,2,3,0 6,7,4,5,2,3,0,1 7,4,5,6,3,0,1,2 0,1,2,3 1,0,3,2 2,3,0,1 3,2,1,0 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 CAS Latency (CL) The CAS Latency (CL) is defined by bits M4-M6 as shown in Figure 5. CAS Latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CAS Latency can be set to 2, 3, 4, or 5 clocks. DDR2 SDRAM does not support any half clock latencies. Reserved states should not be used as unknown operation or incompatibility with future versions may result. DDR2 SDRAM also supports a feature called Posted CAS additive latency (AL). This feature allows the READ command to be issued prior to tRCD(MIN) by delaying the internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in more detail in the Extended Mode Register (EMR) and Operational sections. Examples of CL = 3 and CL = 4 are shown in Figure 6; both assume AL = 0. If a READ command is registered at clock edge n, and the CAS Latency is m clocks, the data will be available nominally coincident with clock edge n + m (this assumes AL = 0). DLL Reset DLL reset is defined by bit M8 as shown in Figure 5. Programming bit M8 to `1' will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of `0' after the DLL RESET function has been issued. Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. Write Recovery Extended Mode Register Write recovery time is defined by bits M9-M11 as shown in Figure 5. Write recovery values of 2, 3, 4, 5, or 6 may be used for programming bits M9-M11. The user is required to program the value of write recovery, which is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a noninteger value to the next integer; WR [cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used as unknown operation or incompatibility with future versions may result. The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, ODT (RTT), Posted CAS additive latency (AL), off-chip driver impedance calibration (OCD), DQS# enable/disable, and OUTPUT disable/enable. These functions are controlled via the bits shown in Figure 7. The extended mode register is programmed via the LOAD MODE (LM) command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the extended mode register will not alter the contents of the memory array, provided it is performed correctly. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating Power-Down Mode Active power-down (PD) mode is defined by bit M12 as shown in Figure 5. PD mode allows the user to determine the active power-down mode, which determines performance vs. power savings. PD mode bit M12 does not apply to precharge power-down mode. When bit M12 = 0, standard Active Power-down mode or `fast-exit' active power-down mode is 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Output Drive Strength either of these requirements could result in unspecified operation. The output drive strength is defined by bit E1 as shown in Figure 7. The normal drive strength for all outputs are specified to be SSTL_18. Programming bit E1 = 0 selects normal (100 percent) drive strength for all outputs. Selecting a reduced drive strength option (bit E1 = 1) will reduce all outputs to approximately 60 percent of the SSTL_18 drive strength. This option is intended for the support of the lighter load and/or point-to-point environments. DLL Enable/Disable The DLL may be enabled or disabled by programming bit E0 during the LOAD MODE command as shown in Figure 7. The DLL must be enabled for normal operation. DLL enable is required during powerup initialization and upon returning to normal operation after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using a LOAD MODE command. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled and reset upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. DQS# Enable/Disable The DQS# enable function is defined by bit E10. When enabled (bit E10 = 0), DQS# is the complement of the differential data strobe pair DQS/DQS#. When disabled (bit E10 = 1), DQS is used in a single-ended mode and the DQS# pin is disabled. RDQS Enable/Disable RDQS/RDQS# is not applicable at the module level. RDQS is defined by bit E11 as shown in Figure 7, Extended Mode Register Definition, and must be set to 0. Figure 6: CAS Latency (CL) CK# T0 T1 T2 T3 T4 T5 T6 READ NOP NOP NOP NOP NOP NOP CK COMMAND DQS, DQS# DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 CL = 3 (AL = 0) CK# T0 T1 T2 T3 T4 T5 T6 READ NOP NOP NOP NOP NOP NOP CK COMMAND DQS, DQS# DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 CL = 4 (AL = 0) Burst length = 4 Posted CAS# additive latency (AL) = 0 Shown with nominal tAC, tDQSCK, and tDQSQ 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN TRANSITIONING DATA 12 DON'T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Figure 7: Extended Mode Register Definition BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EMR out RDQS DQS# OCD Program RTT Posted CAS# RTT ODS DLL Address Bus Extended Mode Register (Ex) E12 Outputs E0 DLL Enable 0 Enabled E6 E2 RTT (nominal) 0 Enable (Normal) 1 Disabled 0 0 RTT Disabled 1 Disable (Test/Debug) 75 ohm 0 1 E11 RDQS Enable 0 No 1 Reserved include E6, E2 = 0,0, ODT not enabled, E6, E2 = 0,1 Rtt(effective) = 75W or E6, E2 = 1,0 RTT (EFF) = 150W. of 150 (RTT (EFF2) = `R2'/2). Reserved states should not be used, as unknown operation or incompatibility with future versions may result. The ODT control pin is used to determine when RTT(EFF) is turned on and off, assuming ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input pin are only used during active, active power-down (both fast-exit and slow-exit modes), and precharge power-down modes of operation. If SELF REFRESH operation is used, RTT (EFF) should always be disabled and the ODT input pin is disabled by the DDR2 SDRAM. During power-up and initialization of the DDR2 SDRAM, ODT should be disabled until the EMR command is issued to enable the ODT feature, at which point the ODT pin will determine the RTT (EFF) value. 1 0 150 ohm E1 Output Drive Strength 1 1 Reserved 0 100% 1 60% E10 DQS# Enable E5 E4 E3 Posted CAS# Additive Latency (AL) 0 Enable 0 0 0 0 1 Disable 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved E9 E8 E7 OCD Operation 0 0 0 OCD calibration mode exit 0 0 1 Drive(1) pull-up 0 1 0 Drive(0) pull-down 1 0 0 OCD enter adjust mode 1 1 1 OCD calibration default Off-Chip Driver (OCD) Impedance Calibration The DDR2 SDRAM output off-chip (OCD) driver impedance calibration operation is defined by bits E7- E9. OCD is intended to allow the system to calibrate and match pull-up to pull-down impedance to 18W nominal. OCD is not indended to allow a wide range of impedance calibration outside of the 18W nominal driver impedance. M14 M13 Mode Register 0 0 Mode Register (MR) 0 1 Extended Mode Register (EMR) 1 0 Extended Mode Register (EMR2) 1 1 Extended Mode Register (EMR3) NOTE: 1GB extended mode register TBD. Posted CAS Additive Latency (AL) Posted CAS additive latency (AL) is supported to make the command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. Bits E3-E5 define the value of AL as shown in Figure 7. Bits E3-E5 allow the user to program the DDR2 SDRAM with a CAS# Additive latency of 0, 1, 2, 3, or 4 clocks. Reserved states should not be used as unknown operation or incompatibility with future versions may result. In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued prior to tRCD (MIN) with the requirement that AL tRCD(MIN). A typical application using this feature would set AL = tRCD (MIN) - 1 x tCK. The READ or WRITE command is held for the time of the additive latency (AL) before it is issued internally to the DDR2 SDRAM device. READ Latency (RL) is controlled by the sum of the Posted CAS additive latency (AL) and CAS Latency (CL); RL = AL + CL. Write latency (WL) is equal to READ latency minus one clock; WL = AL + CL - 1 x tCK. An example of a READ latency is shown in Figure 8. An example of a WRITE latency is shown in Figure 9. Output Enable/Disable The OUTPUT enable function is defined by bit E12 as shown in Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#) function normally. When disabled (E12 = 1), all DDR2 SDRAM outputs (DQs, DQS, DQS#) are disabled removing output buffer current. The OUTPUT disable feature is intended to be used during IDD characterization of read current. On Die Termination (ODT) ODT effective resistance RTT (EFF) is defined by bits E2 and E6 of the EMR as shown in Figure 7. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DDR2 SDRAM controller to independently turn on/off ODT for any or all devices. RTT effective resistance values of 75W and 150W are selectable and apply to each DQ, DQS/DQS#, and DM signals. Bits (E6, E2) determine what ODT resistance is enabled and the effective resistance value. Options 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Figure 8: READ Latency CK# T0 T1 T2 T3 T4 T5 T6 T7 T8 ACTIVE n READ n NOP NOP NOP NOP NOP NOP NOP CK COMMAND DQS, DQS# tRCD (MIN) DOUT n DQ AL = 2 CL = 3 DOUT n+1 DOUT n+2 DOUT n+3 RL = 5 Burst length = 4 Shown with nominal tAC, tDQSCK, and tDQSQ CAS# latency (CL) = 3 Additive latency (AL) = 2 READ latency (RL) = AL + CL = 5 TRANSITIONING DATA DON'T CARE Figure 9: Write Latency T0 T1 ACTIVE n WRITE n CK# T2 T3 T4 T5 T6 T7 NOP NOP NOP NOP NOP NOP CK COMMAND t RCD (MIN) DQS, DQS# AL = 2 CL - 1 = 2 Din n DQ Din n+1 Din n+2 Din n+3 WL = AL + CL - 1 = 4 Burst length = 4 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN CAS# latency (CL) = 3 Additive latency (AL) = 2 WRITE latency = AL + CL -1 = 4 14 TRANSITIONING DATA DON'T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Extended Mode Register 2 (EMR2) Extended Mode Register Set 3 (EMR3) The Extended Mode Register 2 (EMR2) controls functions beyond those controlled by the mode register. Currently all bits in EMR2 are reserved as shown in Figure 10. The EMR2 is programmed via the LOAD MODE command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the extended mode register will not alter the contents of the memory array, provided it is performed correctly. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. The Extended Mode Register 3 (EMR3) controls functions beyond those controlled by the mode register. Currently all bits in EMR3 are reserved as shown in Figure 11. The EMR3 is programmed via the LOAD MODE command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the extended mode register will not alter the contents of the memory array, provided it is performed correctly. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. Figure 10: Extended Mode Register 2 (EMR2) Definition Figure 11: Extended Mode Register 3 (EMR3) Definition BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EMR(2) 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* E14 E13 Mode Register 0 0 Mode Register (MR) 0 1 1 0 1 1 Address Bus BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Extended Mode 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EMR(3) 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Register (Ex) E14 E13 Mode Register * E12 (A12)-E0 (A0) are reserved for future use and must all be programmed to '0.' 0 0 Mode Register (MR) Extended Mode Register (EMR) 0 1 Extended Mode Register (EMR) Extended Mode Register (EMR2) 1 0 Extended Mode Register (EMR2) Extended Mode Register (EMR3) 1 1 Extended Mode Register (EMR3) NOTE: Address Bus Extended Mode Register (Ex) * E12 (A12)-E0 (A0) are reserved for future use and must all be programmed to '0.' NOTE: 512MB and 1GB extended mode registers TBD. 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN A1 A0 512MB and 1GB extended mode registers TBD. 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Command Truth Tables Table 7, Commands Truth Table provides a quick reference of DDR2 SDRAM available commands. Refer to the 256Mb, 512Mb, or 1Gb DDR2 SDRAM compo- Table 7: nent data sheet for more Truth Table definitions, including CKE power-down modes and device bankto-bank commands. Commands Truth Table Notes: 1, 5 CKE FUNCTION PREVIOUS CURRENT CYCLE CYCLE Mode Register Set Refresh Self Refresh Entry Self Refresh Exit H H H L H H L H Single Device Bank Precharge ALL Device Banks Precharge Device Bank Activate Write H Write with Auto Precharge Read CS# RAS# CAS# WE# BA28, BA1, BA0 A12- A11 A10 A9-A0 NOTES H L L L X L L L L L X H L L L L X H H L H H X H L BA X X X X BA X X X X X OP Code X X X X L X X X X X 2, 6 H H L L H L X X H X 6 H H H H L L L H H L H L BA BA H H L H L L BA H H L H L H BA Read with Auto Precharge No Operation Device Deselect Power-Down Entry H H L H L H BA H H H X X L Power-Down Exit L H L H H L H L H X X H X H H X X H X H H X X H X H X X X X X X Row Address Column L Column Address Address Column H Column Address Address Column L Column Address Address Column H Column Address Address X X X X X X X X X X X X X X X X X X 2 6 6, 7 6 2, 3 2, 3 2, 3 2, 3 6 6 4, 6 4, 6 NOTE: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock. 2. Device Bank addresses (BA) determine which device bank is to be operated upon. For EMR, BA selects an extended mode register. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See sections "Read Interrupted by a Read" and "Write Interrupted by a Write" in the 256Mb, 512Mb, or 1Gb DDR2 SDRAM component data sheet for other restrictions and details. 4. The Power Down Mode does not perform any refresh operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC parametric section. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See the ODT section for details. 6. "X" means "H or L" (but a defined logic level). 7. Self refresh exit is asynchronous. 8. BA2 valid for 1GB only. 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- Table 8: SYMBOL tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Absolute Maximum DC Ratings PARAMETER MIN MAX UNITS VDD Supply Voltage Relative to VSS -1.0 2.3 V VDDQ VDDQ Supply Voltage Relative to VSS -0.5 2.3 V VDDL VDDL Supply Voltage Relative to Vss -0.5 2.3 V Voltage on any Pin Relative to VSS Storage Temperature Operating Temperature (Ambient) -0.5 -55 0 2.3 100 65 V C C Input Leakage Current; Any input 0V VIN VDD; Command/Address, VREF input 0V VIN 0.95V; (All other pins not under RAS#, CAS#, WE# test = 0V) S#, CKE, CK, CK# DM Output Leakage Current; 0V VOUT VDDQ; DQs and DQ, DQS, DQS# ODT are disabled -40 40 A -20 -10 -10 20 10 10 A A A MAX UNITS NOTES VDD VIN, VOUT TSTG TOPR II IOZ Table 9: Recommended DC Operating Conditions All voltages referenced to VSS PARAMETER Supply Voltage VDDL Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) SYMBOL VDD VDDL VDDQ VREF VTT MIN NOM 1.7 1.8 1.7 1.8 1.7 1.8 0.49 x VDDQ 0.50 x VDDQ VREF - 40 VREF 1.9 1.9 1.9 0.51 X VDDQ VREF + 40 V V V V mV 1 4 4 2 3 NOTE: 1. VDD and VDDQ must track each other. VDDQ must be less than or equal to VDD. 2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peakto-peak noise (non-common mode) on VREF may not exceed 1percent of the DC value. Peak-to-peak AC noise on VREF may not exceed 2 percent of VREF (DC). This measurement is to be taken at the nearest VREF bypass capacitor. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 4. VDDQ tracks with VDD; VDDL tracks with VDD. Input Electrical Characteristics and Operating Conditions Table 10: Input DC Logic Levels All voltages referenced to VSS PARAMETER Input High (Logic 1) Voltage Input Low (Logic 0) Voltage 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 17 SYMBOL MIN MAX UNITS VIH(DC) VIL(DC) VREF + 125 -300 VDDQ + 300 VREF - 125 mV mV NOTES Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 11: Input AC Logic Levels All voltages referenced to VSS PARAMETER SYMBOL MIN MAX UNITS VIH(AC) VIL(AC) VREF + 250 - VREF - 250 mV mV Input High (Logic 1) Voltage Input Low (Logic 0) Voltage NOTES IDD Specifications and Conditions * STABLE is defined as inputs stable at a HIGH or LOW level * FLOATING is defined as inputs at VREF = VDDQ/2 * SWITCHING is defined as inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals * Switching is defined as inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes IDD specifications are tested after the device is properly initialized. 0C TOPR +65C. VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V, VDDL= +1.8V 0.1V, VREF=VDDQ/2. Input slew rate is specified by AC Parametric Test Conditions. IDD parameters are specified with ODT disabled. Data bus consists of DQ, DM, DQS, DQS#. IDD values must be met with all combinations of EMR bits 10 and 11. Definitions for IDD Conditions: * LOW is defined as VIN VIL (AC) (MAX) * HIGH is defined as VIN VIH (AC) (MIN) Table 12: General IDD Parameters IDD PARAMETER -53E -40E 4 3 t 15 15 CK ns t 60 60 ns t 7.5 7.5 ns t 3.75 5 ns t 45 45 ns t 70,000 70,000 ns CL (IDD) RCD (IDD) RC (IDD) RRD (IDD) CK (IDD) RAS MIN (IDD) RAS MAX (IDD) UNITS t t 15 15 ns t 75 105 127.5 75 105 127.5 ns ns ns RP (IDD) 256MB 512MB 1GB RFC (IDD) IDD7 Conditions required if timing parameter changes are made to the specification. Table 13, IDD7: Operating Current, specifies detailed timing requirements for IDD7. Changes will be Table 13: IDD7: Operating Current All Bank Interleave Read operation; legend: A = active; RA = read auto precharge; D = deselect SPEED GRADE -53E -40E IDD7 TIMING PATTERNS A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D NOTE: All device banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) using a burst length of 4. Control and address bus inputs are STABLE during DESELECTs. IOUT = 0mA. 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 14: DDR2 IDD Specifications and Conditions - 256MB Notes: 1-5; notes appear on page 25. Values shown for DDR2 SDRAM components only. PARAMETER/CONDITION Operating one bank active-precharge current; t CK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W. Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Fast PDN Exit Active power-down current; t t All device banks open; CK = CK (IDD); CKE is LOW; Other control MR[12] = 0 and address bus inputs are STABLE; Data bus inputs are FLOATING. Slow PDN Exit MR[12] = 1 Active standby current; All device banks open; tCK = tCK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst write current; All device banks open, Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst read current; All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Burst refresh current; t CK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. Operating bank interleave read current; All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD)-1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING; See IDD7 Conditions for detail. SYMBOL -53E -40E UNITS IDD0a 340 314 mA IDD1a 380 354 mA IDD2Pb 40 28 mA IDD2Qb 200 168 mA IDD2Nb 240 200 mA 152 120 mA 72 56 mA IDD3Nb 312 256 mA IDD4Wa 700 534 mA IDD4Ra 620 474 mA IDD3Pb IDD5b 1,360 1,320 mA IDD6b 24 24 mA IDD7a 980 934 mA NOTE: a - Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. b - Value calculated reflects all module ranks in this operating condition. 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 15: DDR2 IDD Specifications and Conditions - 512MB Notes: 1-5; notes appear on page 25. Values shown for DDR2 SDRAM components only. PARAMETER/CONDITION Operating one bank active-precharge current; t CK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W. Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Fast PDN Exit Active power-down current; t t MR[12] = 0 All device banks open; CK = CK (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Slow PDN Exit MR[12] = 1 Active standby current; All device banks open; tCK = tCK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst write current; All device banks open, Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst read current; All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Burst refresh current; t CK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. Operating bank interleave read current; All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD)-1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING; See IDD7 Conditions for detail. SYMBOL -53E -40E UNITS IDD0a TBD TBD mA IDD1a TBD TBD mA IDD2Pb TBD TBD mA IDD2Qb TBD TBD mA IDD2Nb TBD TBD mA TBD TBD mA TBD TBD mA IDD3Nb TBD TBD mA IDD4Wa TBD TBD mA IDD4Ra TBD TBD mA IDD5b TBD TBD mA IDD6b TBD TBD mA IDD7a TBD TBD mA IDD3Pb NOTE: a - Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. b - Value calculated reflects all module ranks in this operating condition. 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 16: DDR2 IDD Specifications and Conditions - 1GB Notes: 1-5; notes appear on page 25; values shown for DDR2 SDRAM components only PARAMETER/CONDITION SYMBOL Operating one bank active-precharge current; t CK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W. Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Fast PDN Exit Active power-down current; t t All device banks open; CK = CK (IDD); CKE is LOW; Other control and MR[12] = 0 Slow PDN Exit address bus inputs are STABLE; Data bus inputs are FLOATING. MR[12] = 1 Active standby current; All device banks open; tCK = tCK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst write current; All device banks open, Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst read current; All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Burst refresh current; t CK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. Operating bank interleave read current; All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD)-1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING; See IDD7 Conditions for detail. -53E -40E UNITS IDD0a TBD TBD mA IDD1a TBD TBD mA IDD2Pb TBD TBD mA IDD2Qb TBD TBD mA IDD2Nb TBD TBD mA TBD TBD mA TBD TBD mA IDD3Nb TBD TBD mA IDD4Wa TBD TBD mA IDD4Ra TBD TBD mA IDD5b TBD TBD mA IDD6b TBD TBD mA IDD7a TBD TBD mA IDD3Pb NOTE: a - Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. b - Value calculated reflects all module ranks in this operating condition. 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 17: Capacitance Parameters are sampled; VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V, VREF = VSS, f = 100 MHz, 0C TOPR +65C, VOUT (DC) = VDDQ/2, VOUT (peak to peak) = 0.1V; DM input is grouped with I/O pins, reflecting the fact that they are matched in loading PARAMETER SYMBOL MIN MAX UNITS CI1 CI2 CI2 CIO 4.0 8.0 4.0 5.0 8.0 16.0 8.0 8.0 pF pF pF pF Input Capacitance: CK, CK# Input Capacitance: BA0-BA2, A0-A12, RAS#, CAS#, WE# Input Capacitance: S#, ODT, CKE Input/Output Capacitance: DQ, DQS, DM Table 18: AC Operating Conditions Notes: 1-5; notes appear on page 25; 0C TOPR +65C; VDDQ = +1.8V 0.1V, VDD = +1.8V 0.1V AC CHARACTERISTICS -53E PARAMETER Clock Clock cycle time SYMBOL CL = 4 t CL = 3 t CK (4) CK (3) CK high-level width t CK low-level width t MIN MAX MIN MAX 3,750 8,000 5,000 8,000 5,000 8,000 5,000 8,000 0.45 CH 0.55 CL 0.45 HP MIN t ( CH, tCL) 0.45 0.55 0.45 UNITS NOTES ps 16, 25 ps 16, 25 0.55 t CK 19 0.55 t CK 19 ps 20 18 t MIN ( CH, t CL) Half clock period t Clock jitter t JIT TBD TBD TBD TBD ps DQ output access time from CK/CK# t AC -500 +500 -600 +600 ps t AC MAX ps 8, 9 t ps 8, 10 Data-out high-impedance window from CK/ CK# Data-out low-impedance window from CK/ CK# DQ and DM input setup time relative to DQS Data -40E t t Data hold skew factor 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN t LZ AC MIN t t AC MAX AC MIN AC MAX DS 100 150 ps 7, 15, 22 t DH 225 275 ps 7, 15, 22 DIPW 0.35 0.35 t t 400 QHS DQ-DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) AC MAX t DQ and DM input hold time relative to DQS DQ and DM input pulse width (for each input) t HZ t t QH t HP -tQHS t QH DQSQ DVW t 22 t 450 t HP -tQHS CK ps ps 15, 17 ns 15, 17 t QH DQSQ t Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 18: AC Operating Conditions (Continued) Notes: 1-5; notes appear on page 25; 0C TOPR +65C; VDDQ = +1.8V 0.1V, VDD = +1.8V 0.1V AC CHARACTERISTICS -53E PARAMETER SYMBOL Data Strobe MIN MAX UNITS NOTES t DQSH 0.35 0.35 t CK DQS input low pulse width t DQSL 0.35 0.35 t CK DQSCK -450 t DQS falling edge to CK rising - setup time t DQS falling edge from CK rising - hold time t t DQS read preamble t DQS read postamble t -500 0.2 +500 ps 0.2 t CK 0.2 t CK 300 DQSQ 350 ps 0.9 1.1 0.9 1.1 t CK RPST 0.4 0.6 0.4 0.6 t CK WPRES 0 RPRE t DQS write preamble t DQS write postamble t 0.4 WPST t 0 0.25 WPRE Write command to first DQS latching transition Address and control input pulse width for each input +450 0.2 DSS DSH DQS-DQ skew, DQS to last DQ valid, per group, per access DQS write preamble setup time 0.6 ps 0.25 t CK 0.4 t CK t CK t CK 0.6 WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 DQSS t IPW 0.6 0.6 Address and control input setup time t IS 250 350 Address and control input hold time t IH 375 475 t CAS# to CAS# command delay Command and Address MAX DQS input high pulse width DQS output access time from CK/CK# 6, 22 2 65 ns CK RC ACTIVE bank a to ACTIVE bank b command t RRD 7.5 7.5 ns ACTIVE to READ or WRITE delay t 15 20 ns ACTIVE to PRECHARGE command t Internal READ to precharge command delay t Write recovery time t Auto precharge write recovery + precharge time t Internal WRITE to READ command delay t RTP WR DAL OCD Drive mode delay t CKE low to CK,CK# uncertainty Average periodic refresh interval 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 256MB 512MB 1GB 70,000 45 70,000 28 ns 21 7.5 7.5 ns 24, 28 15 15 ns 28 WR + tRP ns 23 ns 28 t WR + tRP t WTR 7.5 10 t RP 15 20 MRD 2 2 t OIT 0 12 0 12 ns DELAY 4.375 4.375 5.83 5.83 ns 29 75 105 127.5 70,000 75 105 127.5 70,000 ns 14 7.8 s 14 t LOAD MODE command cycle time REFRESH to REFRESH command interval 45 11 ps t 2 RAS 12, 13 6, 22 60 RCD 15, 17 ps t CCD ACTIVE to ACTIVE (same bank) command PRECHARGE command period Refresh MIN -40E t RFC t 7.8 REFI 23 ns t CK Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 18: AC Operating Conditions (Continued) Notes: 1-5; notes appear on page 25; 0C TOPR +65C; VDDQ = +1.8V 0.1V, VDD = +1.8V 0.1V AC CHARACTERISTICS Self Refresh PARAMETER -53E SYMBOL MIN t XSNR t RFC (MIN) + 10 t RFC (MIN) + 10 Exit self refresh to READ command t XSRD 200 200 Exit self refresh timing reference t ISXR 250 350 AOND 2 t t AON AC (MIN) AOFD 2.5 2.5 t t ODT turn-off delay 2 AC (MAX) + 1,000 t ODT turn-on t t AC (MIN) t ODT turn-off ODT MAX Exit self refresh to non-READ command ODT turn-on delay AOF t ODT turn-on (power-down mode) ODT turn-off (power-down mode) Power-Down MIN -40E t AONPD t AOFPD t ODT power-down exit latency t AXPD t CKE minimum high/low time 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN t CK ps 2 t AC t AC (MIN) (MAX) + 1000 CK 2.5 2.5 ps t CK AC AC (MIN) (MAX) + 600 ps 2 x tCK + t AC (MAX) + 1000 ps 2.5 x tCK AC (MIN) + tAC + 2,000 (MAX) + 1,000 ps t t AC (MIN) + 2,000 t CK 8 8 t CK XARD 2 2 tCK XARDS 6 - AL 6 - AL t CK XP 2 2 t CK XPRD 6 - AL 6 - AL t CK 3 3 t CK t t CKE 24 26 t t t 6, 30 t 3 3 ANPD t UNITS NOTES ns 2 2 x tCK + t AC (MAX) + 1,000 2.5 x tCK AC (MIN) + tAC + 2,000 (MAX) + 1,000 t ODT to power-down entry latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] Exit precharge power-down to any nonREAD command. Exit precharge power-down to READ command. AC (MIN) + 2000 AC (MAX) + 600 MAX 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: 10. tLZ (MIN) supercedes a tDQSCK (MIN) + tRPRE (MAX) condition. 11. The intent of the Don't Care state after completion of the postamble is the DQS-driven signal should either be high, low or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is if DQS transitions high [above VIHDC (MIN)] then it must not transition low (below VIHDC) prior to t DQSH(min). 12. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 13. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 14. The refresh period is 64ms. This equates to an average refresh rate of 7.8125s. However, an REFRESH command must be asserted at least once every 70.3s or tRFC (MAX); issuing more than eight REFRESH commands back-to-back at t RFC (MIN) is not allowed. 15. Each byte lane has a corresponding DQS. 16. CK and CK# input slew rate must be 1 V/ns ( 2 V/ns if measured differentially). 17. The data valid window is derived by achieving other specifications: tHP, (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practicle data valid window can be derived. t 18. JIT specification is currently TBD. 19. MIN( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t CL and tCH). For example, tCL and tCH are = 50 percent of the period, less the half period jitter [tJIT(HP)] of the clock source, and less the half period jitter due to cross talk [tJIT(cross talk)] into the clock traces. t 20. HP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs. VTT = VDDQ/2 Output (VOUT) 25 Reference Point 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.0V in the test environment and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1.0V/ns for signals in the range between VIL (AC) and VIH (AC). 5. The AC and DC input level specifications are as defined in the SSTL_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. Command/Address minimum input slew rate = 1.0V/ns and is referenced to the crosspoint of CK/ CK#. tIS timing is referenced to Vih(ac) for a rising signal and VIL (AC) for a falling signal . tIH timing is referenced to VIH (DC) for a rising signal and VIL (DC) for a falling signal. Derating values for Command/Address input signal slew rates < 1.0V/ns are TBD. 7. Data minimum input slew rate = 1.0V/ns and is referenced to the crosspoint of DQS/DQS# if differential strobe feature is enabled. tDS timing is referenced to VIH (AC) for a rising signal and VIL (AC) for a falling signal. tDH timing is referenced to VIH (DC) for a rising signal and VIL (DC) for a falling signal. Derating values for Data input signal slew rates < 1.0V/ns are TBD. 8. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (tHZ) or begins driving (tLZ). 9. This maximum value is derived from the referenced test load. tHZ (MAX) supercedes tDQSCK (MAX) + tRPST (MAX) condition. 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM 21. READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) is satisfied since tRAS lockout feature is supported in DDR2 SDRAM. 22. VIL/VIH DDR2 overshoot/undershoot. Refer to 256Mb, 512Mb, or 1Gb DDR2 SDRAM component data sheet for more detailed information. 23. tDAL = (nWR) + (tRP/tCK): For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period; nWR refers to the tWR parameter stored in the MR[11,10,9]. Example: For -53E at tCK = 3.75 ns with tWR programmed to four clocks. tDAL = 4 + (15 ns/3.75 ns) clocks = 4 +(4)clocks = 8 clocks. 24. This is a minimum requirement. Minimum READ to internal PRECHARGE timing is AL + BL/2 providing the tRTP and tRAS (MIN) have been satisfied. The DDR2 SDRAM will automatically delay the internal PRECHARGE command until tRAS (MIN) has been satisfied. 25. Operating frequency is only allowed to change during self refresh mode or precharge power- 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 26. 27. 28. 29. 30. 26 down mode. Anytime the operating frequency is changed, not including jitter, the DLL is required to be reset, followed by 200 clock cycles. ODT turn-on time tAON (MIN) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn-on time tAON (MAX) is when the ODT resistance is fully on. Both are measured from tAOND. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time tAOF (MAX) is when the bus is in high impedance. Both are measured from tAOFD. This parameter has a two clock minimum requirement at any tCK. t DELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed prior to CK, CK# being removed in a system RESET condition. t ISXR is equal to tIS and is used for CKE setup time during self refresh exit. Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figure 12, Data Validity, and Figure 13, Definition of Start and Stop). Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (Figure 14, Acknowledge Response From Receiver). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure 12: Data Validity Figure 13: Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT STOP BIT Figure 14: Acknowledge Response From Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 19: EEPROM Device Select Code The most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER SELECT CODE CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW Memory Area Select Code (two arrays) Protection Register Select Code Table 20: EEPROM Operating Modes MODE RW BIT WC BYTES 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 1 1 1 1 16 Current Address Read Random Address Read Sequential Read Byte Write Page Write INITIAL SEQUENCE START, Device Select, RW = `1' START, Device Select, RW = `0', Address reSTART, Device Select, RW = `1' Similar to Current or Random Address Read START, Device Select, RW = `0' START, Device Select, RW = `0' Figure 15: SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 21: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Output Low Voltage: IOUT = 3mA Input Leakage Current: VIN = GND to VDD Output Leakage Current: VOUT = GND to VDD Standby Current: Power Supply Current, READ: SCL clock frequency = 100 KHz VDDSPD VIH VIL VOL ILI ILO ISB ICCR 1.7 VDDSPD X 0.7 -0.6 - 0.10 0.05 1.6 0.4 3.6 VDDSPD + 0.5 VDDSPD x 0.3 0.4 3 3 4 1 V V V V A A A mA Powr Supply Current, WRITE: SCL clock frequency = 100 KHz ICCW 2 3 mA Table 22: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V PARAMETER/CONDITION SYMBOL t AA BUF t DH t F t HD:DAT t HD:STA t HIGH t I t LOW t R f SCL t SU:DAT t SU:STA t SU:STO t WRC SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time t MIN MAX UNITS NOTES 0.2 1.3 200 0.9 s s ns ns s s s ns s s KHz ns s s ms 1 300 0 0.6 0.6 50 1.3 0.3 400 100 0.6 0.6 10 2 2 3 4 NOTE: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 23: Serial Presence-Detect Matrix "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW" BYTE DESCRIPTION ENTRY (VERSION) 0 1 2 3 Number of SPD Bytes Used by Micron Total Number of Bytes in SPD Device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly SODIMM Height at Module Ranks Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, tCK (CAS Latency = 4) SDRAM Access from Clock,tAC (CAS Latency = 4) Module Configuration Type Refresh Rate/Type SDRAM Device Width (Primary SDRAM) Error-checking SDRAM Data Width Minimum Clock Delay, Back-to-Back Random Column Access Burst Lengths Supported Number of Banks on SDRAM Device CAS Latencies Supported Reserved DDR2 SODIMM Type SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, tCK, (CAS Latency = 3) SDRAM Access from CK, tAC, (CAS Latency = 3) SDRAM Cycle Time, tCK, (CAS Latency = 2) SDRAM Access from CK, tAC, (CAS Latency = 2) Minimum Row Precharge Time, tRP 128 256 SDRAM DDR2 13 80 08 08 0D TBD TBD TBD TBD TBD TBD TBD TBD 9 or 10 09 TBD TBD 1.18in., Dual Rank 64 0 SSTL 1.8V -53E -40E -53E -40E TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 7.81s/SELF 16 61 40 00 05 3D 50 50 60 00 82 10 TBD TBD TBD TBD TBD TBD N/A 1 clock 00 00 TBD TBD TBD TBD 4, 8 4 or 8 3, 4 0 SODIMM Weak Driver -53E -40E -53E -40E N/A 0C 04 18 00 04 00 01 50 50 50 60 00 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD N/A 00 TBD TBD -53E -40E -53E -40E -53E -40E -53E -40E 128MB, 256MB, 512MB 3C 3C 1E 1E 3C 3C 2D 2D 20 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Minimum Row Active to Row Active, t RRD Minimum RAS# to CAS# Delay, tRCD 30 Minimum RAS# Pulse Width, tRAS 31 Module Rank Density 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 30 MT8HTF3264HD MT8HTF6464HD MT8HTF12864HD Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Table 23: Serial Presence-Detect Matrix "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW" BYTE 32 33 34 35 36 37 DESCRIPTION Address and Command Setup Time, t IS Address and Command Hold Time, t IH Data/ Data Mask Input Setup Time, t DS Data/ Data Mask Input Hold Time, t DH Write Recovery Time, tWR Write to Read CMD Delay, tWTR Read to Precharge CMD Delay, tRTP Mem Analysis Probe Extension for bytes 41 and 42 Min Active Auto Refresh Time, tRC Minimum Auto Refresh to Active/ Auto Refresh Command Period, tRFC 43 SDRAM Device Max Cycle Time, t CKMAX 44 SDRAM Device Max DQS-DQ Skew Time, tDQSQ 45 SDRAM Device Max Read Data Hold Skew Factor, tQHS 46 PLL Relock Time 47-61 Reserved 62 SPD Revision 63 Checksum For Bytes -62 ENTRY (VERSION) -53E -40E -53E -40E 50 60 50 60 TBD TBD TBD TBD -53E -40E -53E -40E 35 40 35 40 3C 1E 28 1E 00 00 3C 4B TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 80 TBD TBD 1E 23 28 2D 0F 00 10 09 86 2C FF 01-0C Variable Data 01-09 00 Variable Data Variable Data Variable Data - TBD TBD TBD TBD TBD TBD 10 TBD TBD 2C FF 01-0C Variable Data 01-09 00 Variable Data Variable Data Variable Data - TBD TBD 10 TBD TBD 2C FF 01-0C Variable Data 01-09 00 Variable Data Variable Data Variable Data - -53E -40E 38 39 40 41 42 64 65-71 72 73-90 91 92 93 94 95-98 99-127 Manufacturer's JEDEC ID Code Manufacturer's JEDEC ID Code Manufacturing Location Module Part Number (ASCII) PCB Identification Code Identification Code (Continued) Year of Manufacture in BCD Week of Manufacture in BCD Module Serial Number Manufacturer-Specific Data (RSVD) 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN MT8HTF3264HD MT8HTF6464HD MT8HTF12864HD -53E -40E -53E -40E Reserved Release 1.0 -53E -40E MICRON (Continued) 01-12 1-9 0 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. PRELIMINARY 256MB, 512MB, 1GB (x64, DR) PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM Figure 16: 200-pin DDR2 SODIMM Dimensions 0.157 (3.80) MAX FRONT VIEW 2.667 (67.75) 2.656 (67.45) 0.079 (2.00) R (2X) U1 U2 U3 U4 1.175 (29.85) 1.187 (31.15) 0.071 (1.80) (2X) 0.787 (20.00) TYP 0.236 (6.00) 0.091 (2.3) 0.079 (2.00) 0.043 (1.10) 0.035 (0.90) 0.039 (0.99) TYP 0.024 (0.60) TYP 0.018 (0.45) TYP PIN 199 PIN 1 2.504 (63.60) TYP BACK VIEW U5 U8 U6 U9 U7 0.165 (4.2) TYP PIN 200 PIN 2 1.87 (47.4) TYP 0.45 (11.4) TYP NOTE: MAX All dimensions are in inches (millimeters); MIN or typical where noted. Data Sheet Designation Advance: This data sheet contains initial descriptions of products still under development. The Advance designation applies to MT8HTF6464HD and MT8HTF12864HD only. Preliminary: Initial characterization limits, subject to change upon full characterization of production devices. The Preliminary designation applies to MT8HTF3264HD only. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. 09005aef80ebbc49 HTF8C32_64_128x64HDG_A.fm - Rev. A 11/03 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice.. (c)2003 Micron Technology, Inc