MT8HTF12864HDG-53EXX - Micron Technology, Inc.

‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

09005aef80ebbc49

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY‡

DDR2 SDRAM

SODIMM

MT8HTF3264HD – 256MB

MT8HTF6464HD – 512MB (ADVANCE‡)

MT8HTF12864HD – 1GB (ADVANCE‡)

For the latest data sheet, please refer to the Micronâ Web

site: www.micron.com/moduleds

Features

• 200-pin, small outline, dual in-line memory module

(SODIMM)

• Fast data transfer rates: PC2-3200 or PC2-4300

• Utilizes 400 MT/s and 533 MT/s DDR2 SDRAM

components

• 256MB (32 Meg x 64), 512MB (64 Meg x 64)

1GB (128 Meg x 64)

•V

DD = +1.8V ±0.1V

•V

DDSPD = +1.7V to +3.6V

• JEDEC standard 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS, DQS#) option

• Four-bit prefetch architecture

• Differential clock inputs (CK, CK#)

• Commands entered on each rising CK edge

• DQS edge-aligned with data for READs

• DQS center-aligned with data for WRITEs

• DLL to align DQ and DQS transitions with CK

• Four or eight internal device banks for concurrent

operation

• Data mask (DM) for masking write data

• Programmable CAS# latency (CL): 3 and 4

• Posted CAS# additive latency (AL): 0, 1, 2, 3, and 4

• WRITE latency = READ latency - 1 tCK

• Programmable burst lengths: 4 or 8

• READ burst interrupt supported by another READ

• WRITE burst interrupt supported by another WRITE

• Adjustable data-output drive strength

• Concurrent auto precharge option is supported

• Auto Refresh (CBR) and Self Refresh Mode 7.8125µs

maximum average periodic refresh interval

• 64ms, 8,192-cycle refresh

Figure 1: 200-Pin SODIMM (MO-224 R/C “A”)

• Off-chip driver (OCD) impedance calibration

• On-die termination (ODT)

• Serial Presence Detect (SPD) with EEPROM

•Gold edge contacts

NOTE: 1. Consult factory for availability of lead-free prod-

ucts.

2. CL = CAS (READ) Latency.

OPTIONS MARKING

•Package

200-pin SODIMM (standard) G

200-pin SODIMM (lead-free)1Y

•Frequency/CAS Latency

3.75ns @ CL = 4 (DDR2-533) -53E

5.0ns @ CL = 3 (DDR2-400) -40E

Table 1: Address Table

256MB 512MB 1GB

Refresh Count 8K 8K 8K

Row Addressing 8K (A0–A12) 8K (A0–A12) 8K (A0–A12)

Device Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 8 (BA0, BA1, BA2)

Device Configuration 256Mb (16 Meg x 16) 512Mb (32 Meg x 16) 1Gb (64 Meg x 16)

Column Addressing 512 (A0-A8) 1K (A0-A9) 1K (A0-A9)

Module Rank Addressing 2 (S0#, S1#) 2 (S0#, S1#) 2 (S0#, S1#)

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

09005aef80ebbc49 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory

for current revision codes. Example: MT8HTF6464HDG-40EC2.

2. Contact Micron for product availability.

Table 1: Key Timing Parameters

SPEED GRADE

DATA RATE (MHz) tRCD

(ns)

tRP

(ns)

tRC

(ns)CL = 3 CL = 4

-40E 400 400 15 15 60

-53E 400 533 15 15 60

Table 2: Part Numbers and Timing Parameters

PART NUMBER1MODULE

DENSITY

CONFIGURATION MODULE

BANDWIDTH

MEMORY CLOCK/

DATA RATE

LATENCY

(CL - tRCD - tRP)

MT8HTF3264HDG-40E__ 256MB 32 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3

MT8HTF3264HDY-40E__ 256MB 32 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3

MT8HTF3264HDG-53E__ 256MB 32 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4

MT8HTF3264HDY-53E__ 256MB 32 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4

MT8HTF6464HDG-40E__2512MB 64 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3

MT8HTF6464HDY-40E__2512MB 64 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3

MT8HTF6464HDG-53E__2512MB 64 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4

MT8HTF6464HDY-53E__2512MB 64 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4

MT8HTF12864HDG-40E__21GB 128 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3

MT8HTF12864HDY-40E__21GB 128 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3

MT8HTF12864HDG-53E__21GB 128 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4

MT8HTF12864HDY-53E__21GB 128 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

09005aef80ebbc49 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

Pin 85 is No Connect for 256MB and 512MB, BA2 for 1GB.

Figure 2: Pin Locations

Table 3: Pin Assignment

(200-pin SODIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

1VREF 51 DQS2 101 A1 151 DQ42

SS 53 VSS 103 VDD 153 DQ43

5DQ055DQ18105 A10/AP 155 VSS

7DQ157 DQ19 107 BA0 157 DQ48

SS 59 VSS 109 WE# 159 DQ49

11 DQS0# 61 DQ24 111 VDD 161 VSS

13 DQS0 63 DQ25 113 CAS# 163 NC

15 VSS 65 VSS 115 S1# 165 VSS

17 DQ2 67 DM3 117 VDD 167 DQS6#

19 DQ3 69 NC 119 ODT1 169 DQS6

21 VSS 71 VSS 121 VSS 171 VSS

23 DQ8 73 DQ26 123 DQ32 173 DQ50

25 DQ9 75 DQ27 125 DQ33 175 DQ51

27 VSS 77 VSS 127 VSS 177 VSS

29 DQS1# 79 CKE0 129 DQS4# 179 DQ56

31 DQS1 81 VDD 131 DQS4 181 DQ57

33 Vss 83 NC 133 VSS 183 VSS

35 DQ10 85 NC/BA2 135 DQ34 185 DM7

37 DQ11 87 VDD 137 DQ35 187 VSS

39 VSS 89 A12 139 VSS 189 DQ58

41 VSS 91 A9 141 DQ40 191 DQ59

43 DQ16 93 A8 143 DQ41 193 VSS

45 DQ17 95 VDD 145 VSS 195 SDA

47 VSS 97 A5 147 DM5 197 SCL

49 DQS2# 99 A3 149 VSS 199 VDDSPD

Table 4: Pin Assignment

(200-pin SODIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

2VSS 52 DM2 102 A0 152 DQ46

4DQ4 54 VSS 104 VDD 154 DQ47

6 DQ5 56 DQ22 106 BA1 156 VSS

8VSS 58 DQ23 108 RAS# 158 DQ52

10 DM0 60 VSS 110 S0# 160 DQ53

12 VSS 62 DQ28 112 VDD 162 VSS

14 DQ6 64 DQ29 114 ODT0 164 CK1

16 DQ7 66 VSS 116 NC 166 CK1#

18 VSS 68 DQS3# 118 VDD 168 VSS

20 DQ12 70 DQS3 120 NC 170 DM6

22 DQ13 72 VSS 122 VSS 172 VSS

24 VSS 74 DQ30 124 DQ36 174 DQ54

26 DM1 76 DQ31 126 DQ37 176 DQ55

28 VSS 78 VSS 128 VSS 178 VSS

30 CK0 80 CKE1 130 DM4 180 DQ60

32 CK0# 82 VDD 132 VSS 182 DQ61

34 VSS 84 NC 134 DQ38 184 VSS

36 DQ14 86 NC 136 DQ39 186 DQS7#

38 DQ15 88 VDD 138 VSS 188 DQS7

40 VSS 90 A11 140 DQ44 190 VSS

42 VSS 92 A7 142 DQ45 192 DQ62

44 DQ20 94 A6 144 VSS 194 DQ63

46 DQ21 96 VDD 146 DQS5# 196 VSS

48 VSS 98 A4 148 DQS5 198 SA0

50 NC 100 A2 150 VSS 200 SA1

U1 U2 U3 U4 U5 U6

U8 U9

PIN 1 PIN 199

(all odd pins)

PIN 2

PIN 200 (all even pins)

Front View Back View

Indicates a VDD or VDDQ pin Indicates a VSS pin

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

09005aef80ebbc49 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 5: Pin Descriptions

Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information

PIN NUMBERS SYMBOL TYPE DESCRIPTION

114, 119 ODT0, ODT1 Input On-Die Termination: ODT (registered HIGH) enables termination

resistance internal to the DDR2 SDRAM. When enabled, ODT is

only applied to each of the following pins: DQ, DQS, DQS#, and

DM. The ODT input will be ignored if disabled via the LOAD

MODE command.

30, 32, 164, 166 CK0, CK0#

CK1, CK1#

Input Clock: CK and CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the positive

edge of CK and negative edge of CK#. Output data (DQs and

DQS/DQS#) is referenced to the crossings of CK and CK#.

79, 80 CKE0, CKE1 Input Clock Enable: CKE (registered HIGH) activates and CKE

(registered LOW) deactivates clocking circuitry on the DDR2

SDRAM. The specific circuitry that is enabled/disabled is

dependent on the DDR2 SDRAM configuration and operating

mode. CKE LOW provides PRECHARGE POWER-DOWN and SELF

REFRESH operations (all device banks idle), or ACTIVE POWER-

DOWN (row ACTIVE in any device bank). CKE is synchronous for

POWER-DOWN entry, POWER-DOWN exit, output disable, and

for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH

exit. Input buffers (excluding CK, CK#, CKE, and ODT) are

disabled during POWER-DOWN. Input buffers (excluding CKE)

are disabled during SELF REFRESH. CKE is an SSTL_18 input but

will detect a LVCMOS LOW level once VDD is applied during first

power-up. After Vref has become stable during the power on

and initialization sequence, it must be maintained for proper

operation of the CKE receiver. For proper self-refresh operation

VREF must be maintained to this input.

110, 115 S0#, S1# Input Chip Select: S# enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when

S# is registered HIGH. S# provides for external rank selection on

systems with multiple ranks. S# is considered part of the

command code.

108, 109, 113 RAS#, CAS#, WE# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define

the command being entered.

85 (1GB), 106, 107 BA0, BA1,

BA2 (1GB)

Input Bank Address Inputs: BA0–BA2 define to which device bank an

ACTIVE, READ, WRITE, or PRECHARGE command is being

applied. BA0–BA2 define which mode register including MR,

EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE

command.

89, 90, 91, 92, 93, 94, 97, 98,

99, 100, 101, 102, 105

A0–A12 Input Address Inputs: Provide the row address for ACTIVE commands,

and the column address and auto precharge bit (A10) for Read/

Write commands, to select one location out of the memory array

in the respective bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one

device bank (A10 LOW, device bank selected by BA0–BA2) or all

device banks (A10 HIGH). The address inputs also provide the op-

code during a LOAD MODE command.

10, 26, 52, 67, 130, 147, 170,

185

DM0–DM7

UDM = DM0, DM2,

DM5, DM7

LDM = DM 1, DM3,

DM4, DM6

Input Input Data Mask: DM is an input mask signal for write data.

Input data is masked when DM is sampled HIGH along with that

input data during a WRITE access. DM is sampled on both edges

of DQS. Although DM pins are input-only, the DM loading is

designed to match that of DQ and DQS pins.

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

09005aef80ebbc49 Micron Technology, Inc., reserves the right to change products or specifications without notice.

4, 5, 6, 7, 14, 16, 17, 19, 20,

22, 23, 25, 35, 36, 37, 38, 43,

44, 45, 46, 55, 56, 57, 58, 61,

62, 63, 64, 73, 74, 75, 76,

123, 124, 125, 126, 134, 135,

136, 137, 140, 141, 142, 143,

151, 152, 153, 154, 157, 158,

159, 160, 173, 174, 175, 176,

179, 180, 181, 182, 189, 191,

192, 194

DQ0–DQ63 I/O Data Input/Output: Bidirectional data bus.

11, 13, 29, 31, 49, 51, 68, 70,

129, 131, 146, 148, 167, 169,

186, 188

DQS0–DQS7,

DQS0#–DQS7#

I/O Data Strobe: Output with read data, input with write data for

source synchronous operation. Edge-aligned with read data,

center aligned with write data. DQS# is only used when

differential data strobe mode is enabled via the LOAD MODE

command.

197 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the

presence-detect data transfer to and from the module.

198, 200 SA0–SA1 Input Presence-Detect Address Inputs: These pins are used to configure

the presence-detect device.

195 SDA Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to

transfer addresses and data into and out of the presence-detect

portion of the module.

81, 82, 87, 88, 95, 96, 103,

104, 111, 112, 117, 118

VDD Supply Power Supply: +1.8V ±0.1V. Also connects to VDDS/VDDQ, VDDL,

and VSSL on the DDR2 SDRAM device.

REF Supply SSTL_18 reference voltage.

2, 3, 8, 9, 12, 15, 18, 21, 24,

27, 28, 33, 34, 39, 40, 41, 42,

47, 48, 53, 54, 59, 60, 65, 66,

71, 72, 77, 78, 121, 122, 127,

128, 132, 133, 138, 139, 144,

145, 149, 150, 155, 156, 161,

162, 165, 168, 171, 172, 177,

178, 183, 184, 187, 190, 193,

196

VSS Supply Ground. Also connects to VDDS/VDDQ, VDDL, and VSSL on the

DDR2 SDRAM device.

199 VDDSPD Supply Serial EEPROM positive power supply: +1.7V to +3.6V.

50, 69, 83, 84, 85 (256MB

and 512MB), 86, 116, 120,

163,

NC — No Connect: These pins should be left unconnected.

Table 5: Pin Descriptions

Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information

PIN NUMBERS SYMBOL TYPE DESCRIPTION

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

09005aef80ebbc49 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 3: Functional Block Diagram

BA0-BA1 (256MB, 512MB)

BA0-BA2 (1GB)

A0-A12 (256MB, 512MB)

A0-A13 (1GB)

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

BA0-BA1: DDR2 SDRAMs

BA0-BA2: DDR2 SDRAMs

A0-A12: DDR2 SDRAMs

A0-A13: DDR2 SDRAMs

RAS#: DDR2 SDRAMs

CAS#: DDR2 SDRAMs

WE#: DDR2 SDRAMs

CKE0: DDR2 SDRAMs

CKE1: DDR2 SDRAMs

ODT0: DDR2 SDRAMs

ODT1: DDR2 SDRAMs

3Ω

U1, U2, U8, U9

CK0

CK0#

U3, U4, U5, U6

CK1

CK1#

200Ω

Serial PD

A1 A2

SA0 SA1

SDA

SCL

VDDSPD

VDD, VDDQ, VDDL

VREF

VSS

Serial PD

DDR2 SDRAMS

DDR2 SDRAMS, EEPROM

UDQS

UDQS#

UDM

LDQS

LDQS#

LDM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS0

DQS0#

DM0

DQS1

DQS1#

DM1

CS#

UDQS

UDQS#

UDM

LDQS

LDQS#

LDM

CS#

UDQS

UDQS#

UDM

LDQS

LDQS#

LDM

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS2

DQS2#

DM2

DQS3

DQS3#

DM3

CS#

UDQS

UDQS#

UDM

LDQS

LDQS#

LDM

CS#

LDQS

LDQS#

LDM

UDQS

UDQS#

UDM

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS4

DQS4#

DM4

DQS5

DQS5#

DM5

CS#

LDQS

LDQS#

LDM

UDQS

UDQS#

UDM

CS#

LDQS

LDQS#

LDM

UDQS

UDQS#

UDM

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQS6

DQS6#

DM6

DQS7

DQS7#

DM7

CS#

LDQS

LDQS#

LDM

UDQS

UDQS#

UDM

CS#

S1#

S0#

200Ω

NOTE:

1. Unless otherwise noted, resistor values are 22W.

2. Micron module part numbers are explained in the Module Part Numbering

Guide at www.micron.com/numberguide.

MT47H16M16FP = DDR2 SDRAM used in 256MB Module

MT47H32M16FP = DDR2 SDRAM fused in 512MB Module

MT47H64M16FP = DDR2 SDRAM used in 1GB Module

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

09005aef80ebbc49 Micron Technology, Inc., reserves the right to change products or specifications without notice.

General Description

The MT8HTF3264HD, MT8HTF6464HD, and

MT8HTF12864HD DDR2 SDRAM modules are high-

speed, CMOS, dynamic random-access 256MB,

512MB, and 1GB memory modules organized in x64

configuration. DDR2 SDRAM modules use internally

configured quad-bank (256MB, 512MB) or eight-bank

(1GB) DDR2 SDRAM devices.

DDR2 SDRAM modules use double data rate archi-

tecture to achieve high-speed operation. The double

data rate architecture is essentially a 4n-prefetch

architecture with an interface designed to transfer two

data words per clock cycle at the I/O pins. A single

read or write access for the DDR2 SDRAM module

effectively consists of a single 4n-bit-wide, one-clock-

cycle data transfer at the internal DRAM core and four

corresponding n-bit-wide, one-half-clock-cycle data

transfers at the I/O pins.

A bidirectional data strobe (DQS, DQS#) is transmit-

ted externally, along with data, for use in data capture

at the receiver. DQS is a strobe transmitted by the

DDR2 SDRAM device during READs and by the mem-

ory controller during WRITEs. DQS is edge-aligned

with data for READs and center-aligned with data for

WRITEs.

DDR2 SDRAM modules operate from a differential

clock (CK and CK#); the crossing of CK going HIGH

and CK# going LOW will be referred to as the positive

edge of CK. Commands (address and control signals)

are registered at every positive edge of CK. Input data

is registered on both edges of DQS, and output data is

referenced to both edges of DQS, as well as to both

edges of CK.

Read and write accesses to DDR2 SDRAM modules

are burst-oriented; accesses start at a selected location

and continue for a programmed number of locations

in a programmed sequence. Accesses begin with the

registration of an ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command

are used to select the device bank and row to be

accessed. The address bits registered coincident with

the READ or WRITE command are used to select the

device bank and the starting column location for the

burst access.

DDR2 SDRAM modules provide for programmable

read or write burst lengths of four or eight locations.

DDR2 SDRAM supports interrupting a burst read of

eight with another read, or a burst write of eight with

another write. An auto precharge function may be

enabled to provide a self-timed row precharge that is

initiated at the end of the burst access.

The pipelined, multibank architecture of DDR2

SDRAMs allows for concurrent operation, thereby pro-

viding high, effective bandwidth by hiding row pre-

charge and activation time.

A self refresh mode is provided, along with a power-

saving power-down mode.

All inputs are compatible with the JEDEC standard

for SSTL_18. All full drive-strength outputs are

SSTL_18-compatible.

Serial Presence-Detect Operation

DDR2 SDRAM modules incorporate serial pres-

ence-detect (SPD). The SPD function is implemented

using a 2,048-bit EEPROM. This nonvolatile storage

device contains 256 bytes. The first 128 bytes can be

programmed by Micron to identify the module type

and various SDRAM organizations and timing parame-

ters. The remaining 128 bytes of storage are available

for use by the customer. System READ/WRITE opera-

tions between the master (system logic) and the slave

EEPROM device (SODIMM) occur via a standard I2C

bus using the SODIMM’s SCL (clock) and SDA (data)

signals, together with SA (2:0), which provide eight

unique SODIMM/EEPROM addresses. Write protect

(WP) is tied to ground on the module, permanently

disabling hardware write protect.

Functional Description

DDR2 SDRAM modules use double data rate archi-

tecture to achieve high-speed operation. The DDR2

architecture is essentially a 4n-prefetch architecture,

with an interface designed to transfer two data words

per clock cycle at the I/O pins. A single read or write

access for the DDR2 SDRAM module consists of a sin-

gle 4n-bit-wide, one-clock-cycle data transfer at the

internal DRAM core and four corresponding n-bit-

wide, one-half-clock-cycle data transfers at the I/O

pins.

Prior to normal operation, DDR2 SDRAM modules

must be initialized. The following sections provide

detailed information covering device initialization,

operation.

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

09005aef80ebbc49 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Initialization

The following sequence is required for power-up

and initialization and is shown in Figure 4. When the

sequence has been completed, the DDR2 SDRAM

device is ready for normal operation.

Apply power; if CKE is maintained below 20 percent

of VDDQ, outputs remain disabled. To guarantee ODT

is off, VREF must be valid and a low level must be

applied to the ODT pin (all other inputs may be unde-

fined). At least one of the following two sets of condi-

tions (A or B) must be met:

A.CONDITION SET A

•V

DD, VDDL and VDDQ are driven from a sin-

gle power converter output

•V

TT is limited to 0.95V MAX

•V

REF tracks VDDQ/2.

B.CONDITION SET B

•Apply V

DD before or at the same time as

VDDL.

•Apply V

DDL before or at the same time as

VDDQ.

•Apply V

DDQ before or at the same time as

VTT and VREF.

3. For a minimum of 200ms after stable power and

clock (CK, CK#), apply NOP or DESELECT com-

mands and take CKE HIGH.

4. Wait a minimum of 400ns, then issue a PRE-

CHARGE ALL command.

5. Issue an EMR(2) command. (To issue an EMR(2)

command, provide LOW to BA0, and HIGH to

BA1.)

6. Issue an EMR(3) command. (To issue an EMR(3)

command, provide HIGH to BA0 and BA1.)

7. Issue an EMR to enable DLL. (To issue a DLL

ENABLE command, provide LOW to BA1, A0 and

provide HIGH to BA0.)

8. Issue a MODE REGISTER SET command for DLL

RESET. 200 cycles of clock input is required to

lock the DLL. (To issue a DLL RESET command,

provide HIGH to A8 and provide LOW to BA0 and

BA1.)

9. Issue PRECHARGE ALL command.

10. Issue two or more REFRESH commands.

11. Issue a MODE REGISTER SET command with

LOW to A8 to initialize device operation (i.e., to

program operating parameters without resetting

the DLL).

12. At least 200 clocks after step 7, execute EMR OCD

adjust mode if desired. If OCD adjust mode is not

desired, then EMR OCD Default command is

required followed by EMR OCD Exit command.

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

09005aef80ebbc49 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 4: DDR2 Power-Up and Initialization

NOTE:

1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up.

One of the following two conditions (a or b) MUST be met:

a) VDD, VDDL, and VDDQ are driven from a single power converter output.

VTT may be 0.95V maximum during power up.

VREF tracks VDDQ/2.

b) Apply VDD before or at the same time as VDDL.

Apply VDDL before or at the same time as VDDQ.

Apply VDDQ before or at the same time as VTT and VREF.

2. Either a NOP or DESELECT command may be applied.

3. 200 cycles of clock (CK, CK#) are required before a READ command can be issued.

4. Two or more REFRESH commands are required.

5. EMR OCD Default command is required unless OCD adjust mode is used by the system; either command must be fol-

lowed by an EMR OCD Exit command.

6. PRE = PRECHARGE command, LM = LOAD MODE command, REF = REFRESH command, ACT = ACTIVE command, RA =

Row Address, BA = Device Bank Address.

7. DQS represents DQS, DQS#, RDQS, RDQS#.

8. CKE pin uses LVCMOS input levels prior to state T0. After state T0, CKE pin uses SSTL_18 input levels.

9. The LM command for EMR(2) and EMR(3) may be before or after LM command for MR (Tf0) and EMR (Te0). ADDRESS

represents A0–A12, BA0, and BA1 (256MB, 512MB), or A0–A12, BA0, BA1, and BA2 (1GB). A10 should be HIGH at states

Tb0 and Tg0 to ensure a PRECHARGE (all device banks) command is issued.

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tVTD1

CKE

Rtt

Power-up:

and stable

clock (CK, CK#)

T = 200µs (min)

High-Z

DQS

High-Z

ADDRESS9

CK#

tCL

REF

DDL

COMMAND6

NOP

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EMR with

DLL Enable

MR with

DLL Reset

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LM PRELM REF

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Tg0 Th0 Ti0 Tj0

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MR w/o

DLL Reset

tMRD

EMR with

OCD Default5

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CODE

EMR with

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Te0 Tf0

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VALID

NORMAL

OPERATION

EMR(2)

EMR(3)

tMRD tMRD

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LVCMOS

LOW LEVEL

SSTL_18

LOW LEVEL

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256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

09005aef80ebbc49 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Mode Register

The mode register is used to define the specific

mode of operation of the DDR2 SDRAM. This defini-

tion includes the selection of a burst length, burst type,

CAS latency, operating mode, DLL reset, write recov-

ery, and power-down mode as shown in Figure 5. Con-

tents of the mode register can be altered by re-

executing the LOAD MODE (LM) command. If the

user chooses to modify only a subset of the MR vari-

ables, all variables (M0–M12 for 256MB, M0–M13 for

512MB, 1GB) must be programmed when the LOAD

MODE command is issued.

The mode register is programmed via the LM com-

mand with BA1, BA0 = 0,0. All other bits (M0–M12 for

256MB and M0–M13 for 512MB, 1GB) will retain the

stored information until it is programmed again or the

device loses power (except for bit M8, which is self-

clearing). Reprogramming the mode register will not

alter the contents of the memory array, provided it is

performed correctly.

The LOAD MODE command can only be issued (or

reissued) when all device banks are in the precharged

state. The controller must wait the specified time

tMRD before initiating any subsequent operations

such as an ACTIVE command. Violating either of these

requirements will result in unspecified operation.

Burst Length

Burst length is defined by bits M0–M3 as shown in

Figure 5. Read and write accesses to the DDR2 SDRAM

are burst-oriented, with the burst length being pro-

grammable to either four or eight. The burst length

determines the maximum number of column loca-

tions that can be accessed for a given READ or WRITE

command.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively

selected. All accesses for that burst take place within

this block, meaning that the burst will wrap within the

block if a boundary is reached. The block is uniquely

selected by A2–A8 (256MB) or A2–A9 (512MB, 1GB)

when the burst length is set to four and by A3–A9 when

the burst length is set to eight (where A8 or A9 is the

most significant column address bit for a given config-

uration). The remaining (least significant) address

bit(s) is (are) used to select the starting location within

the block. The programmed burst length applies to

both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved. The burst type is

selected via bit M3 as shown in Figure 5. The ordering

of accesses within a burst is determined by the burst

length, the burst type, and the starting column address

as shown in Table 6. DDR2 SDRAM supports 4-bit

burst and 8-bit burst modes only. For 8-bit burst mode,

full interleave address ordering is supported; however,

sequential address ordering is nibble-based.

Operating Mode

The normal operating mode is selected by issuing a

LOAD MODE command with bit M7 set to zero, and all

other bits set to the desired values as shown in

Figure 5. When bit M7 is ‘1,’ no other bits of the mode

places the DDR2 SDRAM into a test mode that is only

used by the Manufacturer and should NOT be used. No

operation or functionality is guaranteed if M7 bit is ‘1.’

Figure 5: Mode Register (MR)

Definition

NOTE:

1GB mode register TBD.

Burst LengthCAS# Latency BT

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Mode Register (Mx)

Address Bus

9765438210

A10A12 A11BA0BA1

10111213

Burst Length

Reserved

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Mode

Normal

Test

DLL TM

DLL Reset

Yes

Write Recovery

Reserved

M10

M11

Mode Register

Mode Register (MR)

Extended Mode Register (EMR)

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

M14

PD Mode

Fast Exit

(Normal)

Slow Exit

(Low Power)

M12

M13

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

09005aef80ebbc49 Micron Technology, Inc., reserves the right to change products or specifications without notice.

DLL Reset

DLL reset is defined by bit M8 as shown in Figure 5.

Programming bit M8 to ‘1’ will activate the DLL RESET

function. Bit M8 is self-clearing, meaning it returns

back to a value of ‘0’ after the DLL RESET function has

been issued.

Anytime the DLL RESET function is used, 200 clock

cycles must occur before a READ command can be

issued to allow time for the internal clock to be syn-

chronized with the external clock. Failing to wait for

synchronization to occur may result in a violation of

the tAC or tDQSCK parameters.

Write Recovery

Write recovery time is defined by bits M9–M11 as

shown in Figure 5. Write recovery values of 2, 3, 4, 5, or

6 may be used for programming bits M9–M11. The

user is required to program the value of write recovery,

which is calculated by dividing tWR (in ns) by tCK (in

ns) and rounding up a noninteger value to the next

integer; WR [cycles] = tWR [ns] / tCK [ns]. Reserved

states should not be used as unknown operation or

incompatibility with future versions may result.

Power-Down Mode

Active power-down (PD) mode is defined by bit M12

as shown in Figure5. PD mode allows the user to

determine the active power-down mode, which deter-

mines performance vs. power savings. PD mode bit

M12 does not apply to precharge power-down mode.

When bit M12 = 0, standard Active Power-down

mode or ‘fast-exit’ active power-down mode is

enabled. The tXARD parameter is used for ‘fast-exit’

active power-down exit timing. The DLL is expected to

be enabled and running during this mode.

When bit M12 = 1, a lower power active power-down

mode or ‘slow-exit’ active power-down mode is

enabled. The tXARDS parameter is used for ‘slow-exit’

active power-down exit timing. The DLL can be

enabled, but ‘frozen’ during active power-down mode

since the exit-to-READ command timing is relaxed.

The power difference expected between PD ‘normal’

and PD ‘low-power’ mode is defined in the IDD table.

CAS Latency (CL)

The CAS Latency (CL) is defined by bits M4–M6 as

shown in Figure 5. CAS Latency is the delay, in clock

cycles, between the registration of a READ command

and the availability of the first bit of output data. The

CAS Latency can be set to 2, 3, 4, or 5 clocks. DDR2

SDRAM does not support any half clock latencies.

Reserved states should not be used as unknown opera-

tion or incompatibility with future versions may result.

DDR2 SDRAM also supports a feature called Posted

CAS additive latency (AL). This feature allows the

READ command to be issued prior to tRCD(MIN) by

delaying the internal command to the DDR2 SDRAM

by AL clocks. The AL feature is described in more detail

in the Extended Mode Register (EMR) and Operational

sections.

Examples of CL = 3 and CL = 4 are shown in Figure 6;

both assume AL = 0. If a READ command is registered

at clock edge n, and the CAS Latency is m clocks, the

data will be available nominally coincident with clock

edge n + m (this assumes AL = 0).

Extended Mode Register

The extended mode register controls functions

beyond those controlled by the mode register; these

additional functions are DLL enable/disable, output

drive strength, ODT (RTT), Posted CAS additive latency

(AL), off-chip driver impedance calibration (OCD),

DQS# enable/disable, and OUTPUT disable/enable.

These functions are controlled via the bits shown in

Figure 7. The extended mode register is programmed

via the LOAD MODE (LM) command and will retain

the stored information until it is programmed again or

the device loses power. Reprogramming the extended

mode register will not alter the contents of the mem-

ory array, provided it is performed correctly.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,

and the controller must wait the specified time tMRD

before initiating any subsequent operation. Violating

Table 6: Burst Definition

BURST

LENGTH

STARTING

COLUMN

ADDRESS

(A2, A1,

A0)

ORDER OF ACCESSES WITHIN

A BURST

BURST TYPE =

SEQUENTIAL

BURST TYPE =

INTERLEAVED

4 0 0 0 0,1,2,3 0,1,2,3

0 0 1 1,2,3,0 1,0,3,2

0 1 0 2,3,0,1 2,3,0,1

0 1 1 3,0,1,2 3,2,1,0

8 0 0 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7

0 0 1 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6

0 1 0 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5

0 1 1 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4

1 0 0 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3

1 0 1 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2

1 1 0 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1

1 1 1 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

09005aef80ebbc49 Micron Technology, Inc., reserves the right to change products or specifications without notice.

either of these requirements could result in unspeci-

fied operation.

DLL Enable/Disable

The DLL may be enabled or disabled by program-

ming bit E0 during the LOAD MODE command as

shown in Figure 7. The DLL must be enabled for nor-

mal operation. DLL enable is required during power-

up initialization and upon returning to normal opera-

tion after having disabled the DLL for the purpose of

debugging or evaluation. Enabling the DLL should

always be followed by resetting the DLL using a LOAD

MODE command.

The DLL is automatically disabled when entering

self refresh operation and is automatically re-enabled

and reset upon exit of self refresh operation.

Any time the DLL is enabled (and subsequently

reset), 200 clock cycles must occur before a READ

command can be issued to allow time for the internal

clock to be synchronized with the external clock. Fail-

ing to wait for synchronization to occur may result in a

violation of the tAC or tDQSCK parameters.

Output Drive Strength

The output drive strength is defined by bit E1 as

shown in Figure 7. The normal drive strength for all

outputs are specified to be SSTL_18. Programming bit

E1 = 0 selects normal (100 percent) drive strength for

all outputs. Selecting a reduced drive strength option

(bit E1 = 1) will reduce all outputs to approximately 60

percent of the SSTL_18 drive strength. This option is

intended for the support of the lighter load and/or

point-to-point environments.

DQS# Enable/Disable

The DQS# enable function is defined by bit E10.

When enabled (bit E10 = 0), DQS# is the complement

of the differential data strobe pair DQS/DQS#. When

disabled (bit E10 = 1), DQS is used in a single-ended

mode and the DQS# pin is disabled.

RDQS Enable/Disable

RDQS/RDQS# is not applicable at the module level.

RDQS is defined by bit E11 as shown in Figure 7,

Extended Mode Register Definition, and must be set to

Figure 6: CAS Latency (CL)

DOUT

n + 3

DOUT

n + 2

DOUT

n + 1

CK#

COMMAND

DQS, DQS#

CL = 3 (AL = 0)

READ

Burst length = 4

Posted CAS# additive latency (AL) = 0

Shown with nominal tAC, tDQSCK, and tDQSQ

T0 T1 T2

DON’T CARETRANSITIONING DATA

NOP NOP NOP

DOUT

T3 T4 T5

NOP NOP

NOP

DOUT

n + 3

DOUT

n + 2

DOUT

n + 1

CK#

COMMAND

DQS, DQS#

CL = 4 (AL = 0)

READ

T0 T1 T2

NOP NOP NOP

DOUT

T3 T4 T5

NOP NOP

NOP

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

09005aef80ebbc49 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 7: Extended Mode Register

Definition

NOTE:

1GB extended mode register TBD.

Output Enable/Disable

The OUTPUT enable function is defined by bit E12

as shown in Figure 7. When enabled (E12 = 0), all out-

puts (DQs, DQS, DQS#) function normally. When dis-

abled (E12 = 1), all DDR2 SDRAM outputs (DQs, DQS,

DQS#) are disabled removing output buffer current.

The OUTPUT disable feature is intended to be used

during IDD characterization of read current.

On Die Termination (ODT)

ODT effective resistance RTT (EFF) is defined by bits

E2 and E6 of the EMR as shown in Figure 7. The ODT

feature is designed to improve signal integrity of the

memory channel by allowing the DDR2 SDRAM con-

troller to independently turn on/off ODT for any or all

devices. RTT effective resistance values of 75W and

150W are selectable and apply to each DQ, DQS/DQS#,

and DM signals.

Bits (E6, E2) determine what ODT resistance is

enabled and the effective resistance value. Options

include E6, E2 = 0,0, ODT not enabled, E6, E2 = 0,1

Rtt(effective) = 75W or E6, E2 = 1,0 RTT (EFF) = 150W. of

150 (RTT (EFF2) = ‘R2’/2). Reserved states should not

be used, as unknown operation or incompatibility with

future versions may result.

The ODT control pin is used to determine when

RTT(EFF) is turned on and off, assuming ODT has been

enabled via bits E2 and E6 of the EMR. The ODT fea-

ture and ODT input pin are only used during active,

active power-down (both fast-exit and slow-exit

modes), and precharge power-down modes of opera-

tion. If SELF REFRESH operation is used, RTT (EFF)

should always be disabled and the ODT input pin is

disabled by the DDR2 SDRAM. During power-up and

initialization of the DDR2 SDRAM, ODT should be dis-

abled until the EMR command is issued to enable the

ODT feature, at which point the ODT pin will deter-

mine the RTT (EFF) value.

Off-Chip Driver (OCD) Impedance

Calibration

The DDR2 SDRAM output off-chip (OCD) driver

impedance calibration operation is defined by bits E7–

E9. OCD is intended to allow the system to calibrate

and match pull-up to pull-down impedance to 18W

nominal. OCD is not indended to allow a wide range of

impedance calibration outside of the 18W nominal

driver impedance.

Posted CAS Additive Latency (AL)

Posted CAS additive latency (AL) is supported to

make the command and data bus efficient for sustain-

able bandwidths in DDR2 SDRAM. Bits E3–E5 define

the value of AL as shown in Figure 7. Bits E3–E5 allow

the user to program the DDR2 SDRAM with a CAS#

Additive latency of 0, 1, 2, 3, or 4 clocks. Reserved states

should not be used as unknown operation or incom-

patibility with future versions may result.

In this operation, the DDR2 SDRAM allows a READ

or WRITE command to be issued prior to tRCD (MIN)

with the requirement that AL £ tRCD(MIN). A typical

application using this feature would set AL = tRCD

(MIN) - 1 x tCK. The READ or WRITE command is held

for the time of the additive latency (AL) before it is

issued internally to the DDR2 SDRAM device. READ

Latency (RL) is controlled by the sum of the Posted

CAS additive latency (AL) and CAS Latency (CL); RL =

AL + CL. Write latency (WL) is equal to READ latency

minus one clock; WL = AL + CL - 1 x tCK. An example

of a READ latency is shown in Figure 8. An example of

a WRITE latency is shown in Figure 9.

DLLPosted CAS# RTTout

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

A10A12 A11BA0BA1

10111213

Output Drive Strength

100%

60%

Posted CAS# Additive Latency (AL)

Reserved

DLL Enable

Enable (Normal)

Disable (Test/Debug)

RDQS Enable

Reserved

E11

OCD Program

ODS

RTT

DQS#

DQS# Enable

Enable

Disable

E10

RDQS

RTT (nominal)

RTT Disabled

75 ohm

150 ohm

Reserved

OCD Operation

OCD calibration mode exit

Drive(1) pull-up

Drive(0) pull-down

OCD enter adjust mode

OCD calibration default

Outputs

Enabled

Disabled

E12

Mode Register

Mode Register (MR)

Extended Mode Register (EMR)

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

M14

M13

EMR

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

09005aef80ebbc49 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 8: READ Latency

Figure 9: Write Latency

DOUT

n + 3

DOUT

n + 2

DOUT

n + 1

CK#

COMMAND

DQS, DQS#

AL = 2

ACTIVE n

Burst length = 4

Shown with nominal tAC, tDQSCK, and tDQSQ

T0 T1 T2

DON’T CARETRANSITIONING DATA

READ nNOP NOP

DOUT

T3 T4 T5

NOP

T7 T8

NOP NOP

CL = 3

RL = 5

CAS# latency (CL) = 3

Additive latency (AL) = 2

READ latency (RL) = AL + CL = 5

tRCD (MIN)

NOP

CK#

COMMAND

DQS, DQS#

ACTIVE n

Burst length = 4

T0 T1 T2

DON’T CARETRANSITIONING DATA

NOP NOP

T3 T4 T5

NOPWRITE n

NOP

Din

n + 3

Din

n + 2

Din

n + 1

WL = AL + CL - 1 = 4

NOP

Din

CAS# latency (CL) = 3

Additive latency (AL) = 2

WRITE latency = AL + CL -1 = 4

tRCD (MIN)

NOP

AL = 2 CL - 1 = 2

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

09005aef80ebbc49 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Extended Mode Register 2 (EMR2)

The Extended Mode Register 2 (EMR2) controls

functions beyond those controlled by the mode regis-

ter. Currently all bits in EMR2 are reserved as shown in

Figure 10. The EMR2 is programmed via the LOAD

MODE command and will retain the stored informa-

tion until it is programmed again or the device loses

power. Reprogramming the extended mode register

will not alter the contents of the memory array, pro-

vided it is performed correctly.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,

and the controller must wait the specified time tMRD

before initiating any subsequent operation. Violating

either of these requirements could result in unspeci-

fied operation.

Figure 10: Extended Mode Register 2

(EMR2) Definition

NOTE:

512MB and 1GB extended mode registers TBD.

Extended Mode Register Set 3 (EMR3)

The Extended Mode Register 3 (EMR3) controls

functions beyond those controlled by the mode regis-

ter. Currently all bits in EMR3 are reserved as shown in

Figure 11. The EMR3 is programmed via the LOAD

MODE command and will retain the stored informa-

tion until it is programmed again or the device loses

power. Reprogramming the extended mode register

will not alter the contents of the memory array, pro-

vided it is performed correctly.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,

and the controller must wait the specified time tMRD

before initiating any subsequent operation. Violating

either of these requirements could result in unspeci-

fied operation.

Figure 11: Extended Mode Register 3

(EMR3) Definition

NOTE:

512MB and 1GB extended mode registers TBD.

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

A10A12 A11BA0BA1

10111213

* E12 (A12)–E0 (A0) are reserved for future

use and must all be programmed to '0.'

Mode Register

Mode Register (MR)

Extended Mode Register (EMR)

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

E14

E13

EMR(2) 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

A10A12 A11BA0BA1

10111213

* E12 (A12)–E0 (A0) are reserved for future

use and must all be programmed to '0.'

Mode Register

Mode Register (MR)

Extended Mode Register (EMR)

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

E14

E13

EMR(3) 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

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Command Truth Tables

Table 7, Comman ds Tr ut h Ta ble provides a quick

reference of DDR2 SDRAM available commands. Refer

to the 256Mb, 512Mb, or 1Gb DDR2 SDRAM compo-

nent data sheet for more Truth Table definitions,

including CKE power-down modes and device bank-

to-bank commands.

NOTE:

1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.

2. Device Bank addresses (BA) determine which device bank is to be operated upon. For EMR, BA selects an extended mode

3. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See sections “Read Interrupted by a Read” and

“Write Interrupted by a Write” in the 256Mb, 512Mb, or 1Gb DDR2 SDRAM component data sheet for other restrictions

and details.

4. The Power Down Mode does not perform any refresh operations. The duration of power-down is therefore limited by

the refresh requirements outlined in the AC parametric section.

5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh.

See the ODT section for details.

6. “X” means “H or L” (but a defined logic level).

7. Self refresh exit is asynchronous.

8. BA2 valid for 1GB only.

Table 7: Commands Truth Table

Notes: 1, 5

FUNCTION

CKE

CS# RAS# CAS# WE#

BA28,

BA1,

BA0

A12–

A11 A10 A9–A0 NOTES

CYCLE

CURRENT

CYCLE

Mode Register Set H H LLLLBA OP Code 2

Refresh H H LLLHXXXX6

Self Refresh Entry H L LLLHXXXX

Self Refresh Exit L H XXXX XXXX 6, 7

LHHHXXXX

Single Device Bank

Precharge

HHLLHLBAXLX2, 6

ALL Device Banks

Precharge

HHLLHLXXHX6

Device Bank Activate H H L L H H BA Row Address 6

Write HHLHLLBAColumn

Address

L Column

Address

2, 3

Write with Auto

Precharge

HHLHLLBAColumn

Address

H Column

Address

2, 3

Read HHLHLHBAColumn

Address

L Column

Address

2, 3

Read with Auto

Precharge

HHLHLHBAColumn

Address

H Column

Address

2, 3

No Operation H X LHHHXXXX6

Device Deselect H X HXXXXXXX6

Power-Down Entry H L HXXXXXXX4, 6

LHHHXXXX

Power-Down Exit L H HXXXXXXX4, 6

LHHHXXXX

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Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,

and functional operation of the device at these or any

other conditions above those indicated in the opera-

tional sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

NOTE:

1. VDD and VDDQ must track each other. VDDQ must be less than or equal to VDD.

2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-

to-peak noise (non-common mode) on VREF may not exceed ±1percent of the DC value. Peak-to-peak AC noise on

VREF may not exceed ±2 percent of VREF (DC). This measurement is to be taken at the nearest VREF bypass capacitor.

3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal

to VREF and must track variations in the DC level of VREF.

4. VDDQ tracks with VDD; VDDL tracks with VDD.

Input Electrical Characteristics and Operating Conditions

Table 8: Absolute Maximum DC Ratings

SYMBOL PARAMETER MIN MAX UNITS

VDD VDD Supply Voltage Relative to VSS -1.0 2.3 V

VDDQVDDQ Supply Voltage Relative to VSS -0.5 2.3 V

VDDLVDDL Supply Voltage Relative to Vss -0.5 2.3 V

VIN, VOUT Voltage on any Pin Relative to VSS -0.5 2.3 V

TSTG Storage Temperature -55 100 °C

TOPR Operating Temperature (Ambient) 065°C

IIInput Leakage Current; Any input 0V £ VIN £ VDD;

VREF input 0V £ VIN £0.95V; (All other pins not under

test = 0V)

Command/Address,

RAS#, CAS#, WE#

-40 40 µA

S#, CKE, CK, CK# -20 20 µA

DM -10 10 µA

IOZ Output Leakage Current; 0V £ VOUT £ VDDQ; DQs and

ODT are disabled

DQ, DQS, DQS# -10 10 µA

Table 9: Recommended DC Operating Conditions

All voltages referenced to VSS

PARAMETER SYMBOL MIN NOM MAX UNITS NOTES

Supply Voltage VDD 1.7 1.8 1.9 V 1

VDDL Supply Voltage VDDL 1.7 1.8 1.9 V 4

I/O Supply Voltage VDDQ 1.7 1.8 1.9 V 4

I/O Reference Voltage VREF 0.49 x VDDQ0.50 x VDDQ0.51 X VDDQV 2

I/O Termination Voltage (system) VTT VREF - 40 VREF VREF + 40 mV 3

Table 10: Input DC Logic Levels

All voltages referenced to VSS

PARAMETER SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH(DC)VREF + 125 VDDQ + 300 mV

Input Low (Logic 0) Voltage VIL(DC)-300 VREF - 125 mV

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IDD Specifications and Conditions

specifications are tested after the device is prop-

erly initialized. 0°C

OPR

+65°C. V

= +1.8V ±0.1V,

Q = +1.8V ±0.1V, V

L= +1.8V ±0.1V, V

REF

Q/2.

Input slew rate is specified by AC Parametric Test

Conditions. IDD parameters are specified with ODT

disabled. Data bus consists of DQ, DM, DQS, DQS#.

IDD values must be met with all combinations of EMR

bits 10 and 11.

Definitions for IDD Conditions:

•LOW is defined as V

IN £ VIL (AC) (MAX)

• HIGH is defined as VIN ³ VIH (AC) (MIN)

• STABLE is defined as inputs stable at a HIGH or

LOW level

• FLOATING is defined as inputs at VREF = VDDQ/2

• SWITCHING is defined as inputs changing

between HIGH and LOW every other clock cycle

(once per two clocks) for address and control sig-

nals

• Switching is defined as inputs changing between

HIGH and LOW every other data transfer (once

per clock) for DQ signals not including masks or

strobes

IDD7 Conditions

Table 13 , IDD7: Operating Current, specifies detailed

timing requirements for IDD7. Changes will be

required if timing parameter changes are made to the

specification.

NOTE:

All device banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) using a burst length of 4. Con-

trol and address bus inputs are STABLE during DESELECTs. IOUT = 0mA.

Table 11: Input AC Logic Levels

All voltages referenced to VSS

PARAMETER SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH(AC)VREF + 250 - mV

Input Low (Logic 0) Voltage VIL(AC)– VREF - 250 mV

Table 12: G eneral IDD Parameters

IDD PARAMETER -53E -40E UNITS

CL (IDD)43

tCK

tRCD (IDD)15 15 ns

tRC (IDD)60 60 ns

tRRD (IDD)7.5 7.5 ns

tCK (IDD)3.75 5 ns

tRAS MIN (IDD)45 45 ns

tRAS MAX (IDD)70,000 70,000 ns

tRP (IDD)15 15 ns

tRFC (IDD)256MB 75 75 ns

512MB 105 105 ns

1GB 127.5 127.5 ns

Table 13: IDD7: Operating Current

All Bank Interleave Read operation; legend: A = active; RA = read auto precharge; D = deselect

SPEED GRADE IDD7 TIMING PATTERNS

-53E

A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D

-40E

A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D

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Table 14: D DR 2 IDD Specifications and Conditions – 256MB

Notes: 1–5; notes appear on page 25. Values shown for DDR2 SDRAM components only.

PARAMETER/CONDITION SYMBOL -53E -40E UNITS

Operating one bank active-precharge current;

tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is HIGH

between valid commands; Address bus inputs are SWITCHING; Data bus inputs are

SWITCHING.

IDD0a340 314 mA

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS

MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are SWITCHING; Data pattern is same as IDD4W.

IDD1a380 354 mA

Precharge power-down current;

All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs

are STABLE; Data bus inputs are FLOATING.

IDD2Pb40 28 mA

Precharge quiet standby current;

All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING.

IDD2Qb200 168 mA

Precharge standby current;

All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

IDD2Nb240 200 mA

Active power-down current;

All device banks open; tCK = tCK (IDD); CKE is LOW; Other control

and address bus inputs are STABLE; Data bus inputs are FLOATING.

Fast PDN Exit

MR[12] = 0 IDD3Pb

152 120 mA

Slow PDN Exit

MR[12] = 1 72 56 mA

Active standby current;

All device banks open; tCK = tCK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP(IDD); CKE is

HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING.

IDD3Nb312 256 mA

Operating burst write current;

All device banks open, Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK

(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

IDD4Wa700 534 mA

Operating burst read current;

All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL =

0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH

between valid commands; Address bus inputs are SWITCHING; Data bus inputs are

SWITCHING.

IDD4Ra620 474 mA

Burst refresh current;

tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is HIGH, CS# is HIGH

between valid commands; Other control and address bus inputs are SWITCHING; Data

bus inputs are SWITCHING.

IDD5b1,360 1,320 mA

Self refresh current;

CK and CK# at 0V; CKE £ 0.2V; Other control and address bus inputs are FLOATING;

Data bus inputs are FLOATING.

IDD6b24 24 mA

Operating bank interleave read current;

All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD)-1

x tCK (IDD); tCK = tCK (IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = tRCD(IDD); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during

DESELECTs; Data bus inputs are SWITCHING; See IDD7 Conditions for detail.

IDD7a980 934 mA

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in I

(CKE LOW) mode.

b - Value calculated reflects all module ranks in this operating condition.

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Table 15: D DR 2 IDD Specifications and Conditions – 512MB

Notes: 1–5; notes appear on page 25. Values shown for DDR2 SDRAM components only.

PARAMETER/CONDITION SYMBOL -53E -40E UNITS

Operating one bank active-precharge current;

tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is HIGH

between valid commands; Address bus inputs are SWITCHING; Data bus inputs are

SWITCHING.

IDD0aTBD TBD mA

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS

MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are SWITCHING; Data pattern is same as IDD4W.

IDD1aTBD TBD mA

Precharge power-down current;

All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs

are STABLE; Data bus inputs are FLOATING.

IDD2PbTBD TBD mA

Precharge quiet standby current;

All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING.

IDD2QbTBD TBD mA

Precharge standby current;

All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

IDD2NbTBD TBD mA

Active power-down current;

All device banks open; tCK = tCK (IDD); CKE is LOW; Other control

and address bus inputs are STABLE; Data bus inputs are FLOATING.

Fast PDN Exit

MR[12] = 0 IDD3Pb

TBD TBD mA

Slow PDN Exit

MR[12] = 1 TBD TBD mA

Active standby current;

All device banks open; tCK = tCK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP(IDD); CKE is

HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING.

IDD3NbTBD TBD mA

Operating burst write current;

All device banks open, Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK

(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

IDD4WaTBD TBD mA

Operating burst read current;

All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL =

0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH

between valid commands; Address bus inputs are SWITCHING; Data bus inputs are

SWITCHING.

IDD4RaTBD TBD mA

Burst refresh current;

tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is HIGH, CS# is HIGH

between valid commands; Other control and address bus inputs are SWITCHING; Data

bus inputs are SWITCHING.

IDD5bTBD TBD mA

Self refresh current;

CK and CK# at 0V; CKE £ 0.2V; Other control and address bus inputs are FLOATING;

Data bus inputs are FLOATING.

IDD6bTBD TBD mA

Operating bank interleave read current;

All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD)-1

x tCK (IDD); tCK = tCK (IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = tRCD(IDD); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during

DESELECTs; Data bus inputs are SWITCHING; See IDD7 Conditions for detail.

IDD7aTBD TBD mA

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in I

(CKE LOW) mode.

b - Value calculated reflects all module ranks in this operating condition.

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Table 16: D DR 2 IDD Specifications and Conditions – 1GB

Notes: 1–5; notes appear on page 25; values shown for DDR2 SDRAM components only

PARAMETER/CONDITION SYMBOL -53E -40E UNITS

Operating one bank active-precharge current;

tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is HIGH

between valid commands; Address bus inputs are SWITCHING; Data bus inputs are

SWITCHING.

IDD0aTBD TBD mA

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS

MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are SWITCHING; Data pattern is same as IDD4W.

IDD1aTBD TBD mA

Precharge power-down current;

All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs

are STABLE; Data bus inputs are FLOATING.

IDD2PbTBD TBD mA

Precharge quiet standby current;

All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING.

IDD2QbTBD TBD mA

Precharge standby current;

All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

IDD2NbTBD TBD mA

Active power-down current;

All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING.

Fast PDN Exit

MR[12] = 0 IDD3Pb

TBD TBD mA

Slow PDN Exit

MR[12] = 1 TBD TBD mA

Active standby current;

All device banks open; tCK = tCK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP(IDD); CKE is

HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING.

IDD3NbTBD TBD mA

Operating burst write current;

All device banks open, Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK

(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

IDD4WaTBD TBD mA

Operating burst read current;

All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL =

0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH

between valid commands; Address bus inputs are SWITCHING; Data bus inputs are

SWITCHING.

IDD4RaTBD TBD mA

Burst refresh current;

tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is HIGH, CS# is HIGH

between valid commands; Other control and address bus inputs are SWITCHING; Data

bus inputs are SWITCHING.

IDD5bTBD TBD mA

Self refresh current;

CK and CK# at 0V; CKE £ 0.2V; Other control and address bus inputs are FLOATING;

Data bus inputs are FLOATING.

IDD6bTBD TBD mA

Operating bank interleave read current;

All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD)-1

x tCK (IDD); tCK = tCK (IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = tRCD(IDD); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during

DESELECTs; Data bus inputs are SWITCHING; See IDD7 Conditions for detail.

IDD7aTBD TBD mA

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in I

(CKE LOW) mode.

b - Value calculated reflects all module ranks in this operating condition.

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Table 17: Capacitance

Parameters are sampled; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VREF = VSS, f = 100 MHz, 0°C £ TOPR £ +65°C, VOUT (DC) =

VDDQ/2, VOUT (peak to peak) = 0.1V; DM input is grouped with I/O pins, reflecting the fact that they are matched in loading

PARAMETER SYMBOL MIN MAX UNITS

Input Capacitance: CK, CK# CI1 4.0 8.0 pF

Input Capacitance: BA0–BA2, A0–A12, RAS#, CAS#, WE# CI2 8.0 16.0 pF

Input Capacitance: S#, ODT, CKE CI2 4.0 8.0 pF

Input/Output Capacitance: DQ, DQS, DM CIO 5.0 8.0 pF

Table 18: AC Operating Conditions

Notes: 1–5; notes appear on page 25; 0°C £ TOPR £ +65°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V

AC CHARACTERISTICS -53E -40E

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Clock

Clock cycle time CL = 4 tCK (4) 3,750 8,000 5,000 8,000 ps 16, 25

CL = 3 tCK (3) 5,000 8,000 5,000 8,000 ps 16, 25

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 19

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 19

Half clock period tHP MIN

(tCH, tCL)

MIN (tCH,

tCL) ps 20

Clock jitter tJIT TBD TBD TBD TBD ps 18

Data

DQ output access time from CK/CK# tAC -500 +500 -600 +600 ps

Data-out high-impedance window from CK/

CK# tHZ tAC MAX tAC MAX ps 8, 9

Data-out low-impedance window from CK/

CK# tLZ tAC MIN tAC MAX tAC MIN tAC MAX ps 8, 10

DQ and DM input setup time relative to

DQS tDS 100 150 ps 7, 15, 22

DQ and DM input hold time relative to DQS tDH 225 275 ps 7, 15, 22

DQ and DM input pulse width (for each

input) tDIPW 0.35 0.35 tCK

Data hold skew factor tQHS 400 450 ps

DQ–DQS hold, DQS to first DQ to go

nonvalid, per access tQH tHP -tQHS tHP -tQHS ps 15, 17

Data valid output window (DVW) tDVW

tQH -

tDQSQ

tQH -

tDQSQ ns 15, 17

256MB, 512MB, 1GB (x64, DR)

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Data Strobe

DQS input high pulse width tDQSH 0.35 0.35 tCK

DQS input low pulse width tDQSL 0.35 0.35 tCK

DQS output access time from CK/CK# tDQSCK -450 +450 -500 +500 ps

DQS falling edge to CK rising – setup time tDSS 0.2 0.2 tCK

DQS falling edge from CK rising – hold time tDSH 0.2 0.2 tCK

DQS–DQ skew, DQS to last DQ valid, per

group, per access tDQSQ 300 350 ps 15, 17

DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK

DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK

DQS write preamble setup time tWPRES 00ps12, 13

DQS write preamble tWPRE 0.25 0.25 tCK

DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK 11

Write command to first DQS latching

transition tDQSS WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 tCK

Command and Address

Address and control input pulse width for

each input tIPW 0.6 0.6 tCK

Address and control input setup time tIS 250 350 ps 6, 22

Address and control input hold time tIH 375 475 ps 6, 22

CAS# to CAS# command delay tCCD 22

tCK

ACTIVE to ACTIVE (same bank) command tRC 60 65 ns

ACTIVE bank a to ACTIVE bank b command tRRD 7.5 7.5 ns 28

ACTIVE to READ or WRITE delay tRCD 15 20 ns

ACTIVE to PRECHARGE command tRAS 45 70,000 45 70,000 ns 21

Internal READ to precharge command

delay tRTP 7.5 7.5 ns 24, 28

Write recovery time tWR 15 15 ns 28

Auto precharge write recovery + precharge

time tDAL tWR + tRP tWR + tRP ns 23

Internal WRITE to READ command delay tWTR 7.5 10 ns 28

PRECHARGE command period tRP 15 20 ns

LOAD MODE command cycle time tMRD 22

tCK

OCD Drive mode delay tOIT 012012ns

CKE low to CK,CK# uncertainty tDELAY 4.375 4.375 5.83 5.83 ns 29

Refresh

REFRESH to REFRESH command

interval

256MB

tRFC

70,000

70,000 ns 14512MB 105 105

1GB 127.5 127.5

Average periodic refresh interval tREFI 7.8 7.8 µs 14

Table 18: AC Operating Conditions (Continued)

Notes: 1–5; notes appear on page 25; 0°C £ TOPR £ +65°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V

AC CHARACTERISTICS -53E -40E

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

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Self Refresh

Exit self refresh to non-READ command tXSNR

tRFC

(MIN) +

tRFC

(MIN) +

Exit self refresh to READ command tXSRD 200 200 tCK

Exit self refresh timing reference tISXR 250 350 ps 6, 30

ODT

ODT turn-on delay tAOND 2222

tCK

ODT turn-on tAON

tAC

(MIN)

tAC

(MAX) +

1,000

tAC (MIN)

tAC

(MAX) +

1000

ps 26

ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK

ODT turn-off tAOF

tAC

(MIN)

tAC

(MAX) +

600

tAC (MIN)

tAC

(MAX) +

600

ps 27

ODT turn-on (power-down mode) tAONPD

tAC

(MIN) +

2000

2 x tCK +

tAC

(MAX) +

1,000

tAC

(MIN) +

2,000

2 x tCK +

tAC

(MAX) +

1000

ODT turn-off (power-down mode) tAOFPD

tAC (MIN)

+ 2,000

2.5 x tCK

+ tAC

(MAX) +

1,000

tAC (MIN)

+ 2,000

2.5 x tCK

+ tAC

(MAX) +

1,000

ODT to power-down entry latency tANPD 33

tCK

ODT power-down exit latency tAXPD 88

tCK

Power-Down

Exit active power-down to READ command,

MR[bit12=0] tXARD 22tCK

Exit active power-down to READ command,

MR[bit12=1] tXARDS 6 - AL 6 - AL tCK

Exit precharge power-down to any non-

READ command. tXP 22

tCK

Exit precharge power-down to READ

command. tXPRD 6 - AL 6 - AL tCK

CKE minimum high/low time tCKE 33

tCK

Table 18: AC Operating Conditions (Continued)

Notes: 1–5; notes appear on page 25; 0°C £ TOPR £ +65°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V

AC CHARACTERISTICS -53E -40E

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

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Notes

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC

characteristics may be conducted at nominal ref-

erence/supply voltage levels, but the related spec-

ifications and device operation are guaranteed for

the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC timing and IDD tests may use a VIL-to-VIH swing

of up to 1.0V in the test environment and parame-

ter specifications are guaranteed for the specified

AC input levels under normal use conditions. The

minimum slew rate for the input signals used to

test the device is 1.0V/ns for signals in the range

between VIL (AC) and VIH (AC).

5. The AC and DC input level specifications are as

defined in the SSTL_18 standard (i.e., the receiver

will effectively switch as a result of the signal

crossing the AC input level and will remain in that

state as long as the signal does not ring back

above [below] the DC input LOW [HIGH] level).

6. Command/Address minimum input slew rate =

1.0V/ns and is referenced to the crosspoint of CK/

CK#. tIS timing is referenced to Vih(ac) for a rising

signal and VIL (AC) for a falling signal . tIH timing

is referenced to VIH (DC) for a rising signal and VIL

(DC) for a falling signal. Derating values for Com-

mand/Address input signal slew rates < 1.0V/ns

are TBD.

7. Data minimum input slew rate = 1.0V/ns and is

referenced to the crosspoint of DQS/DQS# if dif-

ferential strobe feature is enabled. tDS timing is

referenced to VIH (AC) for a rising signal and VIL

(AC) for a falling signal. tDH timing is referenced

to VIH (DC) for a rising signal and VIL (DC) for a

falling signal. Derating values for Data input sig-

nal slew rates < 1.0V/ns are TBD.

8. tHZ and tLZ transitions occur in the same access

time windows as valid data transitions. These

parameters are not referenced to a specific voltage

level, but specify when the device output is no

longer driving (tHZ) or begins driving (tLZ).

9. This maximum value is derived from the refer-

enced test load. tHZ (MAX) supercedes tDQSCK

(MAX) + tRPST (MAX) condition.

10. tLZ (MIN) supercedes a tDQSCK (MIN) + tRPRE

(MAX) condition.

11. The intent of the Don’t Care state after completion

of the postamble is the DQS-driven signal should

either be high, low or high-Z and that any signal

transition within the input switching region must

follow valid input requirements. That is if DQS

transitions high [above VIHDC (MIN)] then it must

not transition low (below VIHDC) prior to

tDQSH(min).

12. This is not a device limit. The device will operate

with a negative value, but system performance

could be degraded due to bus turnaround.

13. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The

case shown (DQS going from High-Z to logic

LOW) applies when no WRITEs were previously in

progress on the bus. If a previous WRITE was in

progress, DQS could be HIGH during this time,

depending on tDQSS.

14. The refresh period is 64ms. This equates to an

average refresh rate of 7.8125µs. However, an

REFRESH command must be asserted at least

once every 70.3µs or tRFC (MAX); issuing more

than eight REFRESH commands back-to-back at

tRFC (MIN) is not allowed.

15. Each byte lane has a corresponding DQS.

16. CK and CK# input slew rate must be ³ 1 V/ns (³ 2

V/ns if measured differentially).

17. The data valid window is derived by achieving

other specifications: tHP, (tCK/2), tDQSQ, and tQH

(tQH = tHP - tQHS). The data valid window derates

in direct proportion to the clock duty cycle and a

practicle data valid window can be derived.

18. tJIT specification is currently TBD.

19. MIN( tCL, tCH) refers to the smaller of the actual

clock low time and the actual clock high time as

provided to the device (i.e. this value can be

greater than the minimum specification limits for

tCL and tCH). For example, tCL and tCH are = 50

percent of the period, less the half period jitter

[tJIT(HP)] of the clock source, and less the half

period jitter due to cross talk [tJIT(cross talk)] into

the clock traces.

20. tHP (MIN) is the lesser of tCL minimum and tCH

minimum actually applied to the device CK and

CK# inputs.

Output

(VOUT)

Reference

Point

25Ω

VTT = VDDQ/2

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21. READs and WRITEs with auto precharge are

allowed to be issued before tRAS (MIN) is satisfied

since tRAS lockout feature is supported in DDR2

SDRAM.

22. VIL/VIH DDR2 overshoot/undershoot. Refer to

256Mb, 512Mb, or 1Gb DDR2 SDRAM component

data sheet for more detailed information.

23. tDAL = (nWR) + (tRP/tCK): For each of the terms

above, if not already an integer, round to the next

highest integer. tCK refers to the application clock

period; nWR refers to the tWR parameter stored in

the MR[11,10,9]. Example: For -53E at tCK = 3.75

ns with tWR programmed to four clocks. tDAL = 4

+ (15 ns/3.75 ns) clocks = 4 +(4)clocks = 8 clocks.

24. This is a minimum requirement. Minimum READ

to internal PRECHARGE timing is AL + BL/2 pro-

viding the tRTP and tRAS (MIN) have been satis-

fied. The DDR2 SDRAM will automatically delay

the internal PRECHARGE command until tRAS

(MIN) has been satisfied.

25. Operating frequency is only allowed to change

during self refresh mode or precharge power-

down mode. Anytime the operating frequency is

changed, not including jitter, the DLL is required

to be reset, followed by 200 clock cycles.

26. ODT turn-on time tAON (MIN) is when the device

leaves high impedance and ODT resistance

begins to turn on. ODT turn-on time tAON (MAX)

is when the ODT resistance is fully on. Both are

measured from tAOND.

27. ODT turn-off time tAOF (MIN) is when the device

starts to turn off ODT resistance. ODT turn off

time tAOF (MAX) is when the bus is in high

impedance. Both are measured from tAOFD.

28. This parameter has a two clock minimum require-

ment at any tCK.

29. tDELAY is calculated from tIS + tCK + tIH so that

CKE registration LOW is guaranteed prior to CK,

CK# being removed in a system RESET condition.

30. tISXR is equal to tIS and is used for CKE setup time

during self refresh exit.

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SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions (Fig-

ure 12, Data Validity, and Figure 13, Definition of Start

and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL

is HIGH. The SPD device continuously monitors the

SDA and SCL lines for the start condition and will not

respond to any command until this condition has been

met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data (Figure 14,

Acknowledge Response From Receiver).

The SPD device will always respond with an

acknowledge after recognition of a start condition and

its slave address. If both the device and a WRITE oper-

ation have been selected, the SPD device will respond

with an acknowledge after the receipt of each subse-

quent eight-bit word. In the read mode the SPD device

will transmit eight bits of data, release the SDA line and

monitor the line for an acknowledge. If an acknowl-

edge is detected and no stop condition is generated by

the master, the slave will continue to transmit data. If

an acknowledge is not detected, the slave will termi-

nate further data transmissions and await the stop

condition to return to standby power mode.

Figure 12: Data Validity Figure 13: Definition of Start and Stop

Figure 14: Acknowledge Response From Receiver

SCL

SDA

DATA STABLE DATA STABLEDATA

CHANGE

SCL

SDA

START

BIT

STOP

BIT

SCL from Master

Data Output

from Transmitter

Data Output

from Receiver

Acknowledge

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Figure 15: SPD EEPROM Timing Diagram

Table 19: EEPROM Device Select Code

The most significant bit (b7) is sent first

SELECT CODE DEVICE TYPE IDENTIFIER CHIP ENABLE RW

b7 b6 b5 b4 b3 b2 b1 b0

Memory Area Select Code (two arrays) 1 0 1 0 SA2 SA1 SA0 RW

Protection Register Select Code 0 1 1 0 SA2 SA1 SA0 RW

Table 20: EEPROM Operating Modes

MODE RW BIT WC BYTES INITIAL SEQUENCE

Current Address Read 1V

IH or VIL 1START, Device Select, RW = ‘1’

Random Address Read 0VIH or VIL 1START, Device Select, RW = ‘0’, Address

1VIH or VIL 1reSTART, Device Select, RW = ‘1’

Sequential Read 1VIH or VIL ³ 1Similar to Current or Random Address Read

Byte Write 0V

IL 1START, Device Select, RW = ‘0’

Page Write 0VIL £ 16 START, Device Select, RW = ‘0’

SCL

SDA IN

SDA OUT

tLOW

tSU:STA tHD:STA

tFtHIGH tR

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

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NOTE:

1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising

edge of SDA.

2. This parameter is sampled.

3. For a reSTART condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of

the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA

remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

Table 21: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS

Supply Voltage VDDSPD 1.7 3.6 V

Input High Voltage: Logic 1; All inputs VIH VDDSPD X 0.7 VDDSPD + 0.5 V

Input Low Voltage: Logic 0; All inputs VIL -0.6 VDDSPD x 0.3 V

Output Low Voltage: IOUT = 3mA VOL –0.4V

Input Leakage Current: VIN = GND to VDD ILI 0.10 3 µA

Output Leakage Current: VOUT = GND to VDD ILO 0.05 3 µA

Standby Current: ISB 1.6 4 µA

Power Supply Current, READ: SCL clock frequency = 100 KHz ICCR0.4 1 mA

Powr Supply Current, WRITE: SCL clock frequency = 100 KHz ICCW23mA

Table 22: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1

Time the bus must be free before a new transition can start tBUF 1.3 µs

Data-out hold time tDH 200 ns

SDA and SCL fall time tF 300 ns 2

Data-in hold time tHD:DAT 0 µs

Start condition hold time tHD:STA 0.6 µs

Clock HIGH period tHIGH 0.6 µs

Noise suppression time constant at SCL, SDA inputs tI50ns

Clock LOW period tLOW 1.3 µs

SDA and SCL rise time tR0.3µs2

SCL clock frequency fSCL 400 KHz

Data-in setup time tSU:DAT 100 ns

Start condition setup time tSU:STA 0.6 µs 3

Stop condition setup time tSU:STO 0.6 µs

WRITE cycle time tWRC 10 ms 4

256MB, 512MB, 1GB (x64, DR)

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Table 23: Serial Presence-Detect Matrix

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”

BYTE DESCRIPTION ENTRY (VERSION) MT8HTF3264HD

MT8HTF6464HD MT8HTF12864HD

0Number of SPD Bytes Used by Micron 128 80 TBD TBD

1Total Number of Bytes in SPD Device 256 08 TBD TBD

2Fundamental Memory Type SDRAM DDR2 08 TBD TBD

3Number of Row Addresses on

Assembly

13 0D TBD TBD

4Number of Column Addresses on

Assembly

9 or 10 09 TBD TBD

5SODIMM Height at Module Ranks 1.18in., Dual Rank 61 TBD TBD

6Module Data Width 64 40 TBD TBD

7Module Data Width (Continued) 000TBDTBD

8Module Voltage Interface Levels SSTL 1.8V 05 TBD TBD

9SDRAM Cycle Time, tCK (CAS Latency

= 4)

-53E

-40E

TBD TBD

10 SDRAM Access from Clock,tAC (CAS

Latency = 4)

-53E

-40E

TBD TBD

11 Module Configuration Type 00 TBD TBD

12 Refresh Rate/Type 7.81µs/SELF 82 TBD TBD

13 SDRAM Device Width (Primary

SDRAM)

16 10 TBD TBD

14 Error-checking SDRAM Data Width N/A 00 TBD TBD

15 Minimum Clock Delay, Back-to-Back

Random Column Access

1 clock 00 TBD TBD

16 Burst Lengths Supported 4, 8 0C TBD TBD

17 Number of Banks on SDRAM Device 4 or 8 04 TBD TBD

18 CAS Latencies Supported 3, 4 18 TBD TBD

19 Reserved 000TBDTBD

20 DDR2 SODIMM Type SODIMM 04 TBD TBD

21 SDRAM Module Attributes 00 TBD TBD

22 SDRAM Device Attributes: General Weak Driver 01 TBD TBD

23 SDRAM Cycle Time, tCK, (CAS Latency

= 3)

-53E

-40E

TBD TBD

24 SDRAM Access from CK, tAC, (CAS

Latency = 3)

-53E

-40E

TBD TBD

25 SDRAM Cycle Time, tCK, (CAS Latency

= 2)

N/A 00 TBD TBD

26 SDRAM Access from CK, tAC, (CAS

Latency = 2)

N/A 00 TBD TBD

27 Minimum Row Precharge Time, tRP -53E

-40E

TBD TBD

28 Minimum Row Active to Row Active,

tRRD

-53E

-40E

TBD TBD

29 Minimum RAS# to CAS# Delay, tRCD -53E

-40E

TBD TBD

30 Minimum RAS# Pulse Width, tRAS -53E

-40E

TBD TBD

31 Module Rank Density 128MB, 256MB,

512MB

20 TBD TBD

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32 Address and Command Setup Time,

tIS

-53E

-40E

TBD TBD

33 Address and Command Hold Time,

tIH

-53E

-40E

TBD TBD

34 Data/ Data Mask Input Setup Time,

tDS

-53E

-40E

TBD TBD

35 Data/ Data Mask Input Hold Time,

tDH

-53E

-40E

TBD TBD

36 Write Recovery Time, tWR 3C TBD TBD

37 Write to Read CMD Delay, tWTR -53E

-40E

TBD TBD

38 Read to Precharge CMD Delay, tRTP 1E TBD TBD

39 Mem Analysis Probe 00 TBD TBD

40 Extension for bytes 41 and 42 00 TBD TBD

41 Min Active Auto Refresh Time, tRC 3C TBD TBD

42 Minimum Auto Refresh to Active/

Auto Refresh Command Period, tRFC

4B TBD TBD

43 SDRAM Device Max Cycle Time,

tCKMAX

80 TBD TBD

44 SDRAM Device Max DQS-DQ Skew

Time, tDQSQ

-53E

-40E

TBD TBD

45 SDRAM Device Max Read Data Hold

Skew Factor, tQHS

-53E

-40E

TBD TBD

46 PLL Relock Time 0F TBD TBD

47-61 Reserved Reserved 00 TBD TBD

62 SPD Revision Release 1.0 10 10 10

63 Checksum For Bytes –62 -53E

-40E

TBD

64 Manufacturer’s JEDEC ID Code MICRON 2C 2C 2C

65-71 Manufacturer’s JEDEC ID Code (Continued) FF FF FF

72 Manufacturing Location 01–12 01–0C 01–0C 01–0C

73-90 Module Part Number (ASCII) Variable Data Variable Data Variable Data

91 PCB Identification Code 1-9 01-09 01-09 01-09

92 Identification Code (Continued) 0000000

93 Year of Manufacture in BCD Variable Data Variable Data Variable Data

94 Week of Manufacture in BCD Variable Data Variable Data Variable Data

95-98 Module Serial Number Variable Data Variable Data Variable Data

99-127 Manufacturer-Specific Data (RSVD) –––

Table 23: Serial Presence-Detect Matrix

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”

BYTE DESCRIPTION ENTRY (VERSION) MT8HTF3264HD

MT8HTF6464HD MT8HTF12864HD

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

256MB, 512MB, 1GB (x64, DR)

PC2-3200, PC2-4300, 200-Pin DDR2 SDRAM SODIMM

PRELIMINARY

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Figure 16: 200-pin DDR2 SODIMM Dimensions

NOTE:

All dimensions are in inches (millimeters); or typical where noted.

Data Sheet Designation

Advance: This data sheet contains initial descrip-

tions of products still under development. The

Advance designation applies to MT8HTF6464HD and

MT8HTF12864HD only.

Preliminary: Initial characterization limits, subject

to change upon full characterization of production

devices. The Preliminary designation applies to

MT8HTF3264HD only.

0.157 (3.80)

MAX

PIN 1

2.667 (67.75)

2.656 (67.45)

0.787 (20.00)

TYP

0.071 (1.80)

(2X)

0.024 (0.60)

TYP

0.018 (0.45)

TYP

0.079 (2.00) R

(2X)

PIN 199

PIN 200 PIN 2

FRONT VIEW

0.079 (2.00)

0.236 (6.00)

2.504 (63.60)

TYP

0.091 (2.3)

0.039 (0.99)

TYP

1.175 (29.85)

1.187 (31.15)

BACK VIEW

0.043 (1.10)

0.035 (0.90)

U1 U2 U3 U4

U5 U6

U8 U9

1.87 (47.4)

TYP 0.45 (11.4)

TYP

0.165 (4.2)

TYP

MAX

MIN