D> OATEL ADS-118, ADS-118A INNOVATION and EXCELLENCE 12-Bit, 5MHz, Low-Power Sampling A/D Converters FEATURES 12-bit resolution e 5MHz minimum sampling rate e Functionally complete Small 24-pin DDIP e Requires only +5V supplies e Low-power, 1.3 Watts Outstanding dynamic performance e No missing codes over full military temperature range e Edge-triggered, no pipeline delay e Ideal for both time and frequency-domain applications INPUT/OUTPUT CONNECTIONS GENERAL DESCRIPTION PIN FUNCTION PIN FUNCTION DATEL's ADS-118 and ADS-118A are 12-bit, 5SMHz, sampling A/D converters packaged in space-saving 24-pin DDIPs. The 1 BIT 12 (LSB) 24 NO CONNECTION ADS-118 offers an input range of +1V and has three-state 2 BIT 11 23 ANALOG GROUND outputs. The ADS-118A has an input range of +1.25V and 3 BIT 10 22 NO CONNECTION features direct adjustment of offset error. 4 BIT 9 21 45V ANALOG SUPPLY These functionally complete low-power devices (1.3 Watts) 5 BIT 8 20 5V SUPPLY contain an internal fast-settling sample/hold amplifier, a 12-bit 6 BIT7 19 | ANALOG INPUT subranging A/D converter, a precise voltage reference, timing/ 7 BIT 6 18 ANALOG GROUND control logic, and error-correction circuitry. All timing and 8 BIT 5 17* | ENABLE/OFFSET ADJ. control logic operates from the rising edge of a single start 9 BIT 4 16 START CONVERT convert pulse. Digital input and output levels are TTL. Models 10 BIT 3 15 Eoc are available for use in either commercial (0 to +70C) or 11 BIT 2 14 DIGITAL GROUND military (-55 to +125C) operating temperature ranges. 12 BIT 1 (MSB) 13 45V DIGITAL SUPPLY Applications include radar, transient signal analysis, process * ADS-118, Pin 17 is ENABLE control, medical/graphic imaging, and FFT spectrum analysis. ADS-118A, Pin 17 is OFFSET ADJUST OFFSET ADJUST 17 /}-AAA--#-VA r----4 17 ENABLE (ADS-118A only) I (ADS-118A only) BUFFER 1 ~ Y ANALOG INPUT 19 -~~A | 12 BIT 1 (MSB) S/H ti > > FLASH F\] 5 \\ 11 BIT2 L ADC 2 J - po 9 10 BITS 1 W 5 | /-| G ew & Er 9 BiT4 7 56 btw &G Ls] 8 Bs cc oc rer fo Go -m - | 7 Bits DAC id a = \g & [> E pL 6 a7 ) 8 Let 3 Leys airs Ww = p>} & [Ll 4 Bits = EF osu fi S > & L-+ 3 Birt % \ __ Lp! 2 pirat ADC 3 2 w J |_p| |_| 1 BIT 12 (LSB) A a a a START CONVERT 16 > TIMING AND __ . CONTROL LOGIC EOC 15 24 13 14 20 18, 23 22, 24 +5V ANALOG 45V DIGITAL DIGITAL -5V SUPPLY ANALOG NO CONNECT SUPPLY SUPPLY GROUND GROUND Figure 1. ADS-118/118A Functional Block Diagram DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048-1151 (U.S.A.) Tel: (508) 339-3000 Fax: (508) 339-6356 For immediate assistance: (800) 233-2765ADS-118/118A D OATEL ABSOLUTE MAXIMUM RATINGS PHYSICAL/ENVIRONMENTAL PARAMETERS LIMITS UNITS PARAMETERS MIN. TYP. MAX. | UNITS +5V Supply (Pins 13, 21) 0 to +6 Volts Operating Temp. Range, Case -5V Supply (Pin 20) 0 to -6 Volts ADS-118/118AMC 0 _ +70 C Digital Input (Pin 16, 17) -0.3 to +Vo0 +0.3 Volts ADS-118/118AMM, GM, 883 55 +125 c Analog Input (Pin 19) +5 Volts Thermal Impedance jc - 2 - C/Watt Lead Temperature (10 seconds) +300 ct @ca _ 23 _ CiWatt Storage Temperature Range -65 - +150 Cc Package Type 24-pin, metal-sealed, ceramic DDIP or SMT Weight 0.42 ounces (12 grams) FUNCTIONAL SPECIFICATIONS (Ta = +25 C, +Vbp = +5V, 5MHz sampling rate, and a minimum 3 minute warmup unless otherwise specified.) +25C 0 to +70C 55 to +125C ANALOG INPUT MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. | UNITS Input Voltage Range, ADS-118 - +1 - - +1 - - +1 - Volts Input Resistance 475 500 475 500 475 500 Q Input Capacitance 6 15 6 15 6 15 pF DIGITAL INPUT Logic Levels Logic "1" +2.0 +2.0 +2.0 _ _ Volts Logic "0" +0.8 +0.8 +0.8 Volts Logic Loading "1" +20 +20 +20 pA Logic Loading "0" -20 -20 -20 pA Start Convert Positive Pulse Width @ 50 100 50 100 50 100 ns STATIC PERFORMANCE Resolution _ 12 _ _ 12 _ _ 12 _ Bits Integral Nonlinearity (fin = 10kHz) - 40.75 - - +1.0 - - 41.5 - LSB Differential Nonlinearity (fin = 10kHz) - +0.5 +0.75 - +0.5 +0.95 - +0.75 +0.95 LSB Full Scale Absolute Accuracy 40.1 40.5 40.5 40.75 40.75 41.5 %FSR Bipolar Zero Error (Tech Note 2) - +0.1 +0.5 - +0.5 +0.85 - +0.85 +2.0 %FSR Bipolar Offset Error (Tech Note 2) - +0.1 +0.5 - +0.5 +15 - +15 42.5 %FSR Gain Error (Tech Note 2) - +0.1 +0.5 - +0.5 +1.0 - +1.0 42.5 % No Missing Codes (fin = 10kHz) 12 _ _ 12 _ _ 12 _ _ Bits DYNAMIC PERFORMANCE Peak Harmonics (-0.5dB) de to 500kHz _ -76 -71 _ -74 -10 _ -72 -66 dB 500kHz to 1MHz _ -15 -71 _ -14 -70 _ -70 -65 dB 1MHz to 2.5MHz _ -69 -69 _ -13 -67 _ -66 -60 dB Total Harmonic Distortion (-0.5dB) de to 500kHz _ -72 -68 _ -71 -67 _ -10 -65 dB 500kHz to 1MHz _ -71 -67 _ -10 -66 _ -67 -63 dB 1MHz to 2.5MHz _ -10 -66 _ -69 -65 _ -66 -60 dB Signal-to-Noise Ratio (w/o distortion, -0.5dB) de to 500kHz 67 69 _ 66 69 _ 64 67 _ dB 500kHz to 1MHz 66 69 _ 65 68 _ 63 66 _ dB 1MHz to 2.5MHz 66 69 _ 65 68 _ 63 66 _ dB Signal-to-Noise Ratio (& distortion, -0.5dB) de to 500kHz 65 68 _ 64 67 _ 62 66 _ dB 500kHz to 1MHz 65 68 _ 64 67 _ 61 65 _ dB 1MHz to 2.5MHz 64 67 _ 63 66 _ 60 64 _ dB Noise 195 195 195 pVirms Two-tone intermodulation Distortion (fin = 1MHz, 975kHz, fs = 5MHz, -0.5dB) - -74 - - -74 -74 dB Input Bandwidth (-3dB) Small Signal (-20dB input) - 20 - - 20 - - 20 - MHz Large Signal (-0.5dB input) _ 10 _ _ 10 _ _ 10 _ MHz Feedthrough Rejection (fin = 2.5MHz) - 80 - - 80 - - 80 - dB Slew Rate - +400 - - +400 - - +400 - Vips Aperture Delay Time - +10 - +10 - +10 ns Aperture Uncertainty _ 3 _ _ 3 _ _ 3 _ ps rmsD OATEL ADS-118/118A +25C 0 to +70C 55 to +125C DYNAMIC PERFORMANCE (Cont.)) = MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. | UNITS S/H Acquisition Time (to +0.001%FSR, 10V step) _ 85 90 _ 85 90 _ 85 90 ns Overvoltage Recovery Time 200 200 200 ns AID Conversion Rate 5 _ _ 5 _ _ 5 _ _ MHz DIGITAL OUTPUTS Logic Levels Logic "1" +24 +24 +24 _ Volts Logic "0" - _ +0.4 _ _ +0.4 _ _ +0.4 Volts Logic Loading "1" _- _- -4 _- _- -4 _- _- -4 mA Logic Loading"Q" __ _ _ +4 _ _ +4 _ _ +4 mA Delay, Falling Edge of EOC to Output Data Valid _ _ 20 _ _ 20 _ _ 20 MHz Delay, Falling Edge of ENABLE to Output Data Valid _ _ 10 _ _ 10 _ _ 10 MHz Output Coding Offset Binary POWER REQUIREMENTS Power Supply Ranges +5V Supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.9 +5.0 +5.25 Volts -5V Supply 4.75 -5.0 5.25 4.75 -5.0 5.25 -4.9 -5.0 5.25 Volts Power Supply Currents +5V Supply +205 +220 _ +205 +220 +205 +220 mA -5V Supply _ -80 -90 _ -80 -90 _ -80 -90 mA Power Dissipation - 1.3 1.5 - 1.3 1.5 - 1.3 1.5 Watts Power Supply Rejection _ _ +0.1 _ _ +0.1 _ _ +0.1 YF SRIMV Footnotes: All power supplies should be on before applying a start convert pulse. All Effective bits is equal to: ; supplies and the clock (start convert pulses) must be present during warmup (SNR + Distortion) - 1.76 + | 2010 Full Scale Amplitude periods. The device must be continuously converting during this time. Actual Input Amplitude @ Input voltage ranges for ADS-118A is +1.25V 6.02 @ A100ns wide start convert pulse is used for all production testing. For This is the time required before the A/D output data is valid once the analog input applications requiring less than an 5MHz sampling rate, wider start convert pulses can be used. NOTE: The device only requires the rising edge of a start convert pulse to operate. co) is back within the specified range. The minimum supply voltages of +4.9V and -4.9V for +Vpp are required for -55 operation only. The minimum limits are +4.75V and -4.75V when operating at +125 TECHNICAL NOTES 1. Obtaining fully specified performance from the ADS-118 requires careful attention to pc-card layout and power supply decoupling. The devices analog and digital ground systems are connected to each other internally. For optimal perfor- mance, tie all ground pins (14, 18, and 23) directly to a large analog ground plane beneath the package. Bypass all power supplies to ground with 4.7HF tantalum capacitors in parallel with 0.1HF ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. 2. The ADS-118 achieves its specified accuracies without the need for external calibration. If required, the devices small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figures 2a and 2b. When using this circuitry, or any similar offset and gain-calibration hardware, make adjustments following warmup. To avoid interaction, always adjust offset before gain. . To enable the three-state outputs, connect ENABLE (pin 17) to a logic "0" (low). To disable, connect pin 17 to logic "1" (high). The three-state outputs are permanently enabled in the ADS-118A. . Applying a start convert pulse while a conversion is in progress (EOC = logic "1") will initiate a new and inaccurate conversion cycle.ADS-118/118A D OATEL CALIBRATION PROCEDURE Any offset and/or gain calibration procedures should not be implemented until devices are fully warmed up. To avoid interaction, offset must be adjusted before gain. The ranges of adjustment for the circuits in Figures 2a and 2b are guaranteed to compensate for the ADS-118's initial accuracy errors and may not be able to compensate for additional system errors. A/D converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. This can be accomplished by connecting LEDs to the digital outputs and adjusting until certain LED's "flicker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. For the ADS-118, offset adjusting is normally accomplished at the point where the MSB is a 1 and all other output bits are 0s and the LSB just changes from a0 to a1. This digital output transition ideally occurs when the applied analog input is +eLSB (+244uV for ADS-118; +305uV for ADS-118A). Gain adjusting is accomplished when all bits are 1s and the LSB just changes from a1 to a0. This transition ideally occurs when the analog input is at +full scale minus 1/2 LSB's (+0.99927V for ADS-118; +1.249085V for ADS-118A). Zero/Offset Adjust Procedure 1. Apply a train of pulses to the START CONVERT input (pin 16) so the converter is continuously converting. 2. Apply +244uV (ADS-118) or +305uV (ADS-118A) to the ANALOG INPUT (pin 19). +15V 20kQ 1.2MQ 2kQ ZERO/ << OFFSET << MN AMA, ADJUST GAIN ADJUST -15V +15V 1.98kQ INPUT WN ~ SIGNAL 502 | + To Pinig of ADS-118 -15V Figure 2a. Optional ADS-118 External Gain and Offset Adjust Circuits 3. Adjust the offset potentiometer until the output bits are 1000 0000 00000 and the LSB flickers between 0 and 1. Gain Adjust Procedure 1. Apply +0.99927V (ADS-118) or +1.249085V (ADS-118A) to the ANALOG INPUT (pin 19). 2. Adjust the gain potentiometer until all output bits are 1's and the LSB flickers between 1 and 0. 3. To confirm proper operation of the device, vary the input signal to obtain the output coding listed in Table 1. Table 1. Output Coding for Bipolar Operation ADS-118 | OUTPUTCODING | ADS-118A INPUT INPUT BIPOLAR RANGE OFFSET BINARY RANGE SCALE (41V ) MSB LSB (41.25V ) +FS-1 LSB | +0.99951V 1444 1144 1111 +1.2494V +3/4 FS +0.75000V 1110 0000 0000 +0.9375V +1/2 FS +0.50000V 1100 0000 0000 +0.6250V 0 0.00000V 1000 0000 0000 0.0000V -1/2 FS 0.50000V 0100 0000 0000 0.6250V -3/4 FS 0.75000V 0010 0000 0000 0.9375V -FS+1LSB | -0.99951V 0000 0000 0001 1.2494V -FS 1,00000V 0000 0000 0000 1.2500V GAIN ADJUST SIGNAL___| A p ToPint9 INPUT of ADS-118A 50Q Potentiometer is at 25Q during the device's factory trim procedure. +15V (or +5V) 20k ZERO! To Pint7 OFFSET _ ADJUST of ADS-118A 15V (or -5V) Figure 2b. Optional ADS-118A Gain and Offset Adjust CircuitsD OATEL ADS-118/118A ot" | 12 BIT 1 (MSB) = 4.7UF= o4uE - 11 BIT2 Osyo bor] 13, 21 10 BITS IL 9_ BIT 4 L___ g_ BITS VO 7 20 ADS-118 lL 7 BIT6 4.7uUF . t 6 BIT7 FT o.tpr ADS-118A |e aire 18, 23 L___ 4 BIT9 L 3 BIT 10 ANALOG ___lig L 2 BIT 11 INPUT L___ 1 BIT 12 (LSB) L_15 EOC convent 116 L147 ENABLE (1-12) or OFFSET ADJUST Asingle +5V supply should be used for both the +5V analog and +5V digital. If separate supplies are used, the difference between the two cannot exceed 100mV. Figure 3. Typical Connection Diagram N N+1 START CONVERT a 100ns typ. J Le H Le tons typ. Acquisition Time INTERNAL S/H Hold Ht 85ns typ. 90ns max. k 35ns min., 40ns typ., 50ns max. }t- 30ns, +5ns __ Conversion Time 140ns typ., 150ns max. Oo > << 20ns typ. ATA DATA N-1 VALID <A] DATAN VALID a Ad }~< 130ns min. INVALID DATA INVALID DATA 150ns typ. 5Ons typ. : . : a 7Ons max. Note: Scale is approximately 10ns per division. Figure 4. ADS-118/118A Timing DiagramADS-118/118A D OATEL THERMAL REQUIREMENTS All DATEL sampling A/D converters are fully characterized Electrically-insulating, thermally-conductive "pads" may be and specified over operating temperature (case) ranges of installed underneath the package. Devices should be soldered 0 to +70C and 55 to +125C. All room temperature to boards rather than socketed, and of course, minimal air flow (TA = +25C) production testing is performed without the use over the surface can greatly help reduce the package of heat sinks or forced air cooling. Thermal impedance temperature. figures for each device are listed in their respective specification tables. In more severe ambient conditions, the package/junction temperature of a given device can be reduced dramatically These devices do not normally require heat sinks, however, (typically 35%) by using one of DATEL's HS Series heat sinks. standard precautionary design and layout procedures should See Ordering Information for the assigned part number. See be used to ensure devices do not overheat. The ground and page 1-183 of the DATEL Data Acquisition Components power planes beneath the package, as well as all pcb signal Catalog for more information on the HS Series. Request DATEL runs to and from the device, should be as heavy as possible Application Note AN8, Heat Sinks for DIP Data Converters", to help conduct heat away from the package. or contact DATEL directly, for additional information. Amplitude Relative to Full Scale (dB) 0 250 500 750 1 1.25 1.5 1.75 2 2.25 2.5 kHz kHz kHz MHz MHz MHz MHz MHz MHz MHz Frequency (fs = 5MHz, fin = 2.45MHz, Vin = 0.5cB, 4,096-point FFT) Figure 5. FFT Analysis of ADS-118 +0.67 DNL (LSB's) 0.47 4096 Digital Output Code Number of Occurences 0 Digital Output Code 4096 Figure 6. ADS-118 Histogram and Differential NonlinearityL ADS-118/118A D> SS SS iii&Aaldadd:{|dMnMa&_\Qil[kAadA&QXQlqaoqnMdMndnddddddddddM hn hddddnddddaldffdffddnddnM Md dd ddd vd dvd dvd d{d [ddd d{d{d{vd{ {Tada Md. MA Vd Td OA a aAaXiQaA_eoaQebyaAa_ aia SALVD 3uVvVdS (8LL@-SdVv) dHewayds pueog uolenjeg yeLL/SLt-sdv Z enbi4 = Co ( 9B8LOHPZ v bb eb SL 2b 6b be ee Se N z 62 ee OL aX sn ie 6 AAS+ 98LOHPZ (a ra smo ane <o( eT &% vz = Ze Se ao r ALO Tt Tt ae @ = = O10 d of AS+ z a0 aan = pede + << x108 ag}+l 4 & zt 6 AILO'0 Ane 2 $1 | (asl) 9 OL az Lo Z18 er 8 AGH T T 4 AFIINOZ AHINOZ 8 8 D9 ag Lg +h Z AWLO" g oo 7 a a OL 0S zn as ro 19 ore $F 9 vAgt=<J I I AAS b 2 ra or ar 6g 1 Ss T Zrg 003 a AHWOZ 27 Zd ve De ae 4a 8g va ? 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Lead Material: Kovar alloy . (20.32) Lead Finish: 50 microinches (minimum) gold plating ADS 1 1 8MM over 100 microinches (nominal) nickel plating ADS-118AMC 1 12 ADS-118AMM goaoppacsog 0.100 TYP. (2.540) 1.100 (27.940) 0.235 MAX. (5.969) PIN 1 INDEX 0.200 MAX. { \ J (6.080) 0.010 Soo: 1-4 (0.254) 0.190 MAX. 0.100 0.100 (4.826) (2.540) 0.600 +0.010 (2.540) SEATING 0.018 0.002 9.040 Noe 15240) (0.457) (1.016) : ; (0.635) 1.31 MAX. (33.02) 24-Pin 4 13 Dimension Tolerances (unless otherwise indicated): Surface Mount 2 2 place decimal (.XX) 0.010 (+0.254) Versions 3 place decimal (.XXX) +0.005 (40.127) 0.80 MAX. Lead Material: Kovar alloy (20.32) Lead Finish: 50 microinches (minimum) gold plating over 100 micrainches (nominal) nickel plating 1 12 0.020 TYP. 0.060 TYP. 0.015 0.190 MAX. (0.508) (1.524) (0.381) (4.826) PIN 4 0.130 TYP. MAX. radius INDEX tf (3.302) for any pin To Po S te thee ff + (0.508) (0.254) 0.100 TYP. 0.040 (2.540) (1.018) ORDERING INFORMATION OPERATING 24-PIN MODEL NUMBER_ TEMP. RANGE PACKAGE ACCESSORIES ADS-118MC 0 to +70C DDIP ADS-B118 Evaluation Board (without ADS-118) ADS-118MM 55 to +125C DDIP HS-24 Heat Sink for all ADS-118 DDIP models ADS-118AMC 0 to +70C SMT ADS-118AMM 55 to +125C SMT Receptacles for PC board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead Socket), 24 required. For MIL-STD-883 product, or surface mount packaging, contact DATEL. D OATEL INNOVATION and EXCELLENCE DS-0231D 10/96 DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.