10.7 Gbps Active Back-Termination,
Differential Laser Diode Driver
ADN2525
Rev. A
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FEATURES
Up to 10.7 Gbps operation
Very low power: 670 mW (IBIAS = 40 mA, IMOD = 40 mA)
Typical 24 ps rise/fall times
Full back-termination of output transmission lines
Compatible with XMD-MSA TOSA
Drives TOSAs with resistances ranging from 5 Ω to 50 Ω
PECL-/CML-compatible data inputs
Bias current range: 10 mA to 100 mA
Differential modulation current range: 10 mA to 80 mA
Automatic laser shutdown (ALS)
3.3 V operation
Compact 3 mm × 3 mm LFCSP
Voltage input control for bias and modulation currents
XFP-compliant bias current monitor
Optical evaluation board available
APPLICATIONS
SONET OC-192 optical transceivers
SDH STM-64 optical transceivers
10 Gb Ethernet optical transceivers
XFP/X2/XENPAK/XPAK/MSA 300 optical modules
SR and VSR optical links
GENERAL DESCRIPTION
The ADN2525 laser diode driver is designed for direct modula-
tion of packaged laser diodes having a differential resistance
ranging from 5 Ω to 50 Ω. The active back-termination technique
provides excellent matching with the output transmission lines
while reducing the power dissipation in the output stage. The
back-termination in the ADN2525 absorbs signal reflections
from the TOSA end of the output transmission lines, enabling
excellent optical eye quality to be achieved even when the
TOSA end of the output transmission lines is significantly
misterminated. The small package provides the optimum
solution for compact modules where laser diodes are packaged
in low pin-count optical subassemblies.
The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with
control voltages, the user has the flexibility to implement
various average power and extinction ratio control schemes,
including closed-loop control and look-up tables. The automatic
laser shutdown (ALS) feature allows the user to turn on/off the
bias and modulation currents by driving the ALS pin with the
proper logic levels.
The product is available in a space-saving 3 mm × 3 mm LFCSP
specified from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
50
200
800
2002
VCC
DATAP
DATAN
MSET GND BSET
IBMON
IBIAS
IMODP
IMODN
ADN2525
V
C
C
A
LS
GND
VCC
VCC
5050
200
800
IMOD
05077-001
Figure 1.
ADN2525
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Thermal Specifications ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Input Stage..................................................................................... 9
Bias Current ...................................................................................9
Automatic Laser Shutdown (ALS) ........................................... 10
Modulation Current................................................................... 10
Load Mistermination ................................................................. 12
Power Consumption .................................................................. 12
Applications Information.............................................................. 13
Typical Application Circuit ....................................................... 13
Layout Guidelines....................................................................... 13
Design Example.......................................................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
8/06—Rev. 0 to Rev. A
Changes to Format .............................................................Universal
Changes to Features and Figure 1................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 3............................................................................ 5
Changes to Figure 19........................................................................ 9
Changes to Figure 25...................................................................... 10
Changes to Modulation Current Section and Figure 29 ........... 11
Changes to Typical Application Circuit Section......................... 13
Changes to Ordering Guide .......................................................... 15
3/05—Revision 0: Initial Version
ADN2525
Rev. A | Page 3 of 16
SPECIFICATIONS
VCC = VCCMIN to VCCMAX, TA = −40°C to +85°C, 50 Ω differential load resistance, unless otherwise noted. Typical values are specified at
25°C, IMOD = 40 mA.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
BIAS CURRENT (IBIAS)
Bias Current Range 10 100 mA
Bias Current while ALS Asserted 100 μA ALS = high
Compliance Voltage10.6 VCC – 1.2 V IBIAS = 100 mA
0.6 VCC – 0.8 V IBIAS = 10 mA
MODULATION CURRENT (IMODP, IMODN)
Modulation Current Range 10 80 mA diff RLOAD = 5 Ω to 50 Ω differential
Modulation Current While ALS Asserted 0.5 mA diff ALS = high
Rise Time (20% to 80%)2, 3 24 32.5 ps
Fall Time (20% to 80%)2, 3 24 32.5 ps
Random Jitter2, 3 0.4 0.9 ps rms
Deterministic Jitter3, 4 7.2 12 ps p-p Includes pulse-width distortion
Pulse-Width Distortion2, 3 2 5 ps PWD = ABS(THIGH − TLOW)/2
Differential |S22| −10 dB 5 GHz < f < 10 GHz, Z0 = 50 Ω differential
−14 dB f < 5 GHz, Z0 = 50 Ω differential
Compliance Voltage1VCC − 1.1 VCC + 1.1 V
DATA INPUTS (DATAP, DATAN)
Input Data Rate 10.7 Gbps NRZ
Differential Input Swing 0.4 1.6 V p-p diff Differential ac-coupled
Differential |S11| −16.8 dB f < 10 GHz, Z0 = 100 Ω differential
Input Termination Resistance 85 100 115 Ω Differential
BIAS CONTROL INPUT (BSET)
BSET Voltage to IBIAS Gain 75 100 120 mA/V
BSET Input Resistance 800 1000 1200 Ω
MODULATION CONTROL INPUT (MSET)
MSET Voltage to IMOD Gain 70 88 110 mA/V See Figure 29
MSET Input Resistance 800 1000 1200 Ω
BIAS MONITOR (IBMON)
IBMON to IBIAS Ratio 10 μA/mA
Accuracy of IBIAS to IBMON Ratio −5.0 +5.0 % 10 mA ≤ IBIAS < 20 mA, RIBMON = 1 kΩ
−4.0 +4.0 % 20 mA ≤ IBIAS < 40 mA, RIBMON = 1 kΩ
−2.5 +2.5 % 40 mA ≤ IBIAS < 70 mA, RIBMON = 1 kΩ
−2 +2 % 70 mA ≤ IBIAS < 100 mA, RIBMON = 1 kΩ
AUTOMATIC LASER SHUTDOWN (ALS)
VIH 2.4 V
VIL 0.8 V
IIL −20 +20 μA
IIH 0 200 μA
ALS Assert Time 2 μs Rising edge of ALS to fall of IBIAS and
IMOD below 10% of nominal; see Figure 2
ALS Negate Time 10 μs Falling edge of ALS to rise of IBIAS and
IMOD above 90% of nominal; see Figure 2
POWER SUPPLY
VCC 3.07 3.3 3.53 V
ICC5 39 45 mA VBSET = VMSET = 0 V
ISUPPLY6 157 176 mA VBSET = VMSET = 0 V; ISUPPLY = ICC + IMODP + IMODN
See notes on next page.
ADN2525
Rev. A | Page 4 of 16
1 Refers to the voltage between the pin for which the compliance voltage is specified and GND.
2 The pattern used is composed by a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.
3 Measured using the high speed characterization circuit shown in Figure 3.
4 The pattern used is K28.5 (00111110101100000101) at a 10.7 Gbps rate.
5 Only includes current in the ADN2525 VCC pins.
6 Includes current in ADN2525 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the Power Consumption section for total supply current calculation.
THERMAL SPECIFICATIONS
Table 2.
Parameter Min Typ Max Unit Conditions/Comments
θJ-PAD 2.6 5.8 10.7 °C/W Thermal resistance from junction to bottom of exposed pad
θJ-TOP 65 72.2 79.4 °C/W Thermal resistance from junction to top of package
IC Junction Temperature 125 °C
90%
10%
ALS
IBIAS
AND IMOD
ALS
ASSERT TIME
A
LS
NEGATE TIME
t
t
0
5077-002
Figure 2. ALS Timing Diagram
MSET NC1 ALS GND
BSET IBMON IBIAS GND
VCC
IMODP
IMODN
VCC
10nF
10nF
J8 J5
V
EE
V
EE
TP1 10nF
ADN2525
22µF
VEE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
50
50
OSCILLOSCOPE
BIAS TEE: PICOSECOND PULSE LABS MODEL 5542-219
ADAPTER: PASTERNACK PE-9436 2.92mm FEMALE-TO-FEMALE ADAPTER
ATTENUATOR: PASTERNACK PE-7046 2.92mm 20dB ATTENUATOR
ADAPTER
VBSET
Z
0
= 50Z
0
= 25Z
0
= 50
Z
0
= 25Z
0
= 50Z
0
= 50Z
0
= 50
Z
0
= 50
1k
V
EE
VEE
VMSET
GND GND GND
TP2
10
70
35
35
10nF GND
VEE
J2
GND GND GND
GND
VCC
VCC
DATAN
DATAP
GND
GNDGND
J3
GND GND
BIAS
TEE
BIAS
TEE
ADAPTER
ATTENUATOR
ATTENUATOR
05077-003
Figure 3. High Speed Characterization Circuit
ADN2525
Rev. A | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Min Max Unit
Supply Voltage, VCC to GND −0.3 +4.2 V
IMODP, IMODN to GND VCC − 1 .5 4.75 V
DATAP, DATAN to GND VCC − 1.8 VCC − 0.4 V
All Other Pins −0.3 VCC + 0.3 V
Junction Temperature 150 °C
Storage Temperature Range −65 +150 °C
Soldering Temperature
(Less than 10 sec)
300 °C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADN2525
Rev. A | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
12
11
10
9
GND
IBIAS
IBMON
BSET
1
MSET
2
3
5
VCC
IMODN
IMODP
VCC
6
7
8
4
GND
ALS
NC
16
15
14
13
ADN2525
TOP VIEW
(Not to Scale
PIN 1
INDICATOR
VCC
DATAN
DATAP
VCC
0
5077-016
Figure 4. Pin Configuration
Note that the exposed pad on the bottom of the package must be connected to the VCC or GND plane.
Table 4. Pin Function Description
Pin No. Mnemonic I/O Description
1 MSET Input Modulation Current Control Input
2 NC N/A No Connect—Leave Floating
3 ALS Input Automatic Laser Shutdown
4 GND Power Negative Power Supply
5 VCC Power Positive Power Supply
6 IMODN Output Modulation Current Negative Output
7 IMODP Output Modulation Current Positive Output
8 VCC Power Positive Power Supply
9 GND Power Negative Power Supply
10 IBIAS Output Bias Current Output
11 IBMON Output Bias Current Monitoring Output
12 BSET Input Bias Current Control Input
13 VCC Power Positive Power Supply
14 DATAP Input Data Signal Positive Input
15 DATAN Input Data Signal Negative Input
16 VCC Power Positive Power Supply
Exposed Pad Pad Power Connect to GND or VCC
ADN2525
Rev. A | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 3.3 V, unless otherwise noted.
DIFFERENTIAL MODULATION CURRENT (mA)
1000 20406080
RISE TIME (ps)
28.0
23.5
24.0
24.5
25.0
25.5
26.0
26.5
27.0
27.5
23.0
05077-004
Figure 5. Rise Time vs. IMOD
DIFFERENTIAL MODULATION CURRENT (mA)
1000 20406080
FALL TIME (ps)
27.5
26.5
27.0
25.5
26.0
25.0
24.0
24.5
23.5
23.0
05077-005
Figure 6. Fall Time vs. IMOD
DIFFERENTIAL MODULATION CURRENT (mA)
1000 20406080
RANDOM JITTER (ps rms)
0.7
0.5
0.6
0.4
0.3
0.2
0.1
0
05077-006
Figure 7. Random Jitter vs. IMOD
DIFFERENTIAL MODULATION CURRENT (mA)
1000 20406080
DETERMINISTIC JITTER (ps p-p)
9
8
7
4
3
6
5
2
1
0
05077-007
Figure 8. Deterministic Jitter vs. IMOD
DIFFERENTIAL MODULATION CURRENT (mA)
1000 20406080
TOTAL SUPPLY CURRENT (mA)
350
300
250
200
150
100
50
0
IBIAS = 10mA
IBIAS = 50mA
IBIAS = 100mA
05077-008
Figure 9. Total Supply Current vs. IMOD
FREQUENCY (GHz)
1501234567891011121314
DIFFERENTIAL |S11| (dB)
0
–40
–35
–30
–25
–20
–15
–10
–5
05077-009
Figure 10. Differential |S11|
ADN2525
Rev. A | Page 8 of 16
FREQUENCY (GHz)
1501234567891011121314
DIFFERENTIAL |S22| (dB)
0
–40
–35
–30
–25
–20
–15
–10
–5
05077-010
Figure 11. Differential |S22|
RISE TIME (ps)
3023 24 25 26 27 28 29
% OCCURRENCE
16
10
12
14
6
8
4
2
0
05077-011
Figure 12. Worst-Case Rise Time Distribution
(VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, TA = 85°C)
FALL TIME (ps)
3023 24 25 26 27 28 29
% OCCURRENCE
16
10
12
14
8
6
4
2
0
05077-012
Figure 13. Worst-Case Fall Time Distribution
(VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, TA = 85°C)
(ACQ LIMIT TEST) WAVEFORMS: 1000
0
5077-013
Figure 14. Electrical Eye Diagram
(10.7 Gbps, PRBS31, IMOD = 80 mA)
05077-014
Figure 15. Filtered SONET OC192 Optical Eye Diagram (for Reference)
(PRBS31 Pattern, PAV = −2 dBm, ER = 7 dB,
17% Mask Margin, NEC NX8341UJ TOSA)
05077-015
Figure 16. Filtered 10G Ethernet Optical Eye
(PRBS31 Pattern, PAV = −2 dBm, ER = 5 dB,
41% Mask Margin, NEC NX8341UJ TOSA)
ADN2525
Rev. A | Page 9 of 16
THEORY OF OPERATION
As shown in Figure 1, the ADN2525 consists of an input stage
and two voltage-controlled current sources for bias and
modulation. The bias current is available at the IBIAS pin. It is
controlled by the voltage at the BSET pin and can be monitored
at the IBMON pin. The differential modulation current is
available at the IMODP and IMODN pins. It is controlled by
the voltage at the MSET pin. The output stage implements the
active back-match circuitry for proper transmission line
matching and power consumption reduction. The ADN2525
can drive a load having differential resistance ranging from 5 Ω
to 50 Ω. The excellent back-termination in the ADN2525
absorbs signal reflections from the TOSA end of the output
transmission lines, enabling excellent optical eye quality to be
achieved even when the TOSA end of the output transmission
lines is significantly misterminated.
INPUT STAGE
The input stage of the ADN2525 converts the data signal applied
to the DATAP and DATAN pins to a level that ensures proper
operation of the high speed switch. The equivalent circuit of the
input stage is shown in Figure 17.
VCC
50
50
V
C
C
DATAP
DATAN
VCC
05077-017
Figure 17. Equivalent Circuit of the Input Stage
The DATAP and DATAN pins are terminated internally with a
100 Ω differential termination resistor. This minimizes signal
reflections at the input, which could otherwise lead to degradation
in the output eye diagram. It is not recommended to drive the
ADN2525 with single-ended data signal sources.
The ADN2525 input stage must be ac-coupled to the signal
source to eliminate the need for matching between the common-
mode voltages of the data signal source and the input stage of
the driver (see Figure 18). The ac-coupling capacitors should
have an impedance less than 50 Ω over the required frequency
range. Generally, this is achieved using 10 nF to 100 nF capacitors.
ADN2525
DATAP
DATAN
C
C
5050
DATA SIGNAL SOURCE
05077-018
Figure 18. AC-Coupling the Data Source to the ADN2525 Data Inputs
BIAS CURRENT
The bias current is generated internally using a voltage-to-current
converter consisting of an internal operational amplifier and a
transistor, as shown in Figure 19.
GND
200
800
2
RR
VCC
IBMONBSET
I
BMON
ADN2525
I
BIAS
200
IBIAS
0
5077-019
Figure 19. Voltage-to-Current Converter Used to Generate IBIAS
The voltage-to-current conversion factor is set at 100 mA/V by
the internal resistors, and the bias current is monitored using a
current mirror with a gain equal to 1/100. By connecting a 1 kΩ
resistor between IBMON and GND, the bias current can be
monitored as a voltage across the resistor. A low temperature
coefficient precision resistor must be used for the IBMON
resistor (RIBMON). Any error in the value of RIBMON due to
tolerances, or drift in its value over temperature, contributes to
the overall error budget for the IBIAS monitor voltage. If the
IBMON voltage is being connected to an ADC for A/D
conversion, RIBMON should be placed close to the ADC to
minimize errors due to voltage drops on the ground plane.
ADN2525
Rev. A | Page 10 of 16
The equivalent circuits of the BSET, IBIAS, and IBMON pins
are shown in Figure 20, Figure 21, and Figure 22.
V
C
C
BSET
VCC
800
200
05077-020
Figure 20. Equivalent Circuit of the BSET Pin
2
2k
100
IBIAS
VCC
V
CC
0
5077-021
Figure 21. Equivalent Circuit of the IBIAS Pin
VCC
IBMON
V
C
C
100
500
V
C
C
0
5077-022
Figure 22. Equivalent Circuit of the IBMON Pin
The recommended configuration for BSET, IBIAS, and IBMON
is shown in Figure 23.
ADN2525
BSET
V
BSET
GND
IBMON
IBIAS
TO LASER CATHODE
L
R
IBMON
1k
IBIAS
05077-023
Figure 23. Recommended Configuration for the BSET, IBIAS, and IBMON Pins
The circuit used to drive the BSET voltage must be able to drive
the 1 kΩ input resistance of the BSET pin. For proper operation
of the bias current source, the voltage at the IBIAS pin must be
between the compliance voltage specifications for this pin over
supply, temperature, and bias current range (see Table 1). The
maximum compliance voltage is specified for only two bias
current levels (10 mA and 100 mA), but it can be calculated for
any bias current by
VCOMPLIANCE_MAX (V) = VCC (V) − 0.75 − 4.4 × IBIAS (A)
See the Applications Information section for examples of
headroom calculations.
The function of the inductor L is to isolate the capacitance of
the IBIAS output from the high frequency signal path. For
recommended components, see Table 6 .
AUTOMATIC LASER SHUTDOWN (ALS)
The ALS pin is a digital input that enables/disables both the bias
and modulation currents, depending on the logic state applied,
as shown in Table 5 .
Table 5.
ALS Logic State IBIAS and IMOD
High Disabled
Low Enabled
Floating Enabled
The ALS pin is compatible with 3.3 V CMOS and TTL logic
levels. Its equivalent circuit is shown in Figure 24.
V
CC
A
LS
V
CC
100
50k
2k
0
5077-024
Figure 24. Equivalent Circuit of the ALS Pin
MODULATION CURRENT
The modulation current can be controlled by applying a dc
voltage to the MSET pin. This voltage is converted into a dc
current by using a voltage-to-current converter using an
operational amplifier and a bipolar transistor, as shown in
Figure 25.
50
200
800
MSET
GND
IMODP
IMODN
ADN2525
VCC
FROM INPUT STAGE
IMOD
0
5077-025
Figure 25. Generation of Modulation Current on the ADN2525
This dc current is switched by the data signal applied to the
input stage (DATAP and DATAN pins) and gained up by the
output stage to generate the differential modulation current at
the IMODP and IMODN pins.
The output stage also generates the active back-termination,
which provides proper transmission line termination. Active
back-termination uses feedback around an active circuit to
synthesize a broadband termination resistance. This provides
ADN2525
Rev. A | Page 11 of 16
excellent transmission line termination, while dissipating less
power than a traditional resistor passive back-termination. No
portion of the modulation current flows in the active back-
termination resistance. All of the preset modulation current
IMOD, the range specified in Table 1, flows in the external load.
The equivalent circuits for MSET, IMODP, and IMODN are
shown in Figure 26 and Figure 27. The two 25 Ω resistors in
Figure 27 are not real resistors; they represent the active back-
termination resistance.
V
CC
MSET
800
200
V
CC
05077-026
Figure 26. Equivalent Circuit of the MSET Pin
V
CC
V
CC
3.33.3
25
IMODPIMODN
25
05077-027
Figure 27. Equivalent Circuit of the IMODP and IMODN Pins
The recommended configuration of the MSET, IMODP,
and IMODN pins is shown in Figure 28. See Table 6 for
recommended components.
ADN2525
MSET
V
MSET
GND
IMODP
IBIAS
VCC
L
C
TOSA
L
IMODN
Z
0
= 25Z
0
= 25
VCC
VCC
L
C
L
Z
0
= 25Z
0
= 25
05077-028
Figure 28. Recommended Configuration for the MSET, IMODP, and IMODN Pins
The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value, as shown
in Figure 29.
DIFFERENTIAL LOAD RESISTANCE
550 5 10 15 20 25 30 35 40 45 50
I
MOD
/
V
MSET
(mA/V)
210
200
190
180
170
160
150
140
130
120
110
100
90
80
70
60
MINIMUM
TYPICAL
MAXIMUM
05077-029
Figure 29. MSET Voltage-to-Modulation Current Ratio vs.
Differential Load Resistance
Using the resistance of the TOSA, the user can calculate the
voltage range that should be applied to the MSET pin to generate
the required modulation current range (see the example in the
Applications Information section).
The circuit used to drive the MSET voltage must be able to
drive the 1 kΩ resistance of the MSET pin. To be able to drive
80 mA modulation currents through the differential load, the
output stage of the ADN2525 (the IMODP and IMODN pins)
must be ac-coupled to the load. The voltages at these pins have
a dc component equal to VCC and an ac component with
single-ended, peak-to-peak amplitude of IMOD × 25 Ω. This is
the case even if the load impedance is less than 50 Ω differential,
because the transmission line characteristic impedance sets the
peak-to-peak amplitude. For proper operation of the output stage,
the voltages at the IMODP and IMODN pins must be between
the compliance voltage specifications for this pin over supply,
temperature, and modulation current range, as shown in Figure 30.
See the Applications Information section for examples of
headroom calculations.
ADN2525
Rev. A | Page 12 of 16
IMODP, IMODN
VCC
V
CC – 1.1V
V
CC + 1.1V
NORMAL OPERATION REGION
05077-030
Figure 30. Allowable Range for the Voltage at IMODP and IMODN
LOAD MISTERMINATION
Due to its excellent S22 performance, the ADN2525 can drive
differential loads that range from 5 Ω to 50 Ω. In practice, many
TOSAs have differential resistance less than 50 Ω. In this case,
with 50 Ω differential transmission lines connecting the
ADN2525 to the load, the load end of the transmission lines are
misterminated. This mistermination leads to signal reflections
back to the driver. The excellent back-termination in the
ADN2525 absorbs these reflections, preventing their reflection
back to the load. This enables excellent optical eye quality to be
achieved, even when the load end of the transmission lines is
significantly misterminated. The connection between the load
and the ADN2525 must be made with 50 Ω differential (25 Ω
single-ended) transmission lines so that the driver end of the
transmission lines is properly terminated.
POWER CONSUMPTION
The power dissipated by the ADN2525 is given by
IBIASVI
V
VCCP IBIASSUPPLY
MSET ×+
+×= 13.5
where:
VCC is the power supply voltage.
IBIAS is the bias current generated by the ADN2525.
VMSET is the voltage applied to the MSET pin.
ISUPPLY is the sum of the current that flows into the VCC,
IMODP, and IMODN pins of the ADN2525 when
IBIAS = IMOD = 0 expressed in amps (see Tabl e 1).
VIBIAS is the average voltage on the IBIAS pin.
Considering VBSET/IBIAS = 10 as the conversion factor from
VBSET to IBIAS, the dissipated power becomes
IBIAS
BSET
SUPPLY
MSET V
V
I
V
VCCP ×+
+×= 105.13
To ensure long-term reliable operation, the junction tempera-
ture of the ADN2525 must not exceed 125°C, as specified in
Table 2. For improved heat dissipation, the modules case can be
used as heat sink, as shown in Figure 31. A compact optical
module is a complex thermal environment, and calculations of
device junction temperature using the package θJA (junction-to-
ambient thermal resistance) do not yield accurate results.
T
TOP
T
J
TPAD
DIE
PACKAGE
THER
LCOMPOUND MODULE CASE
PCB
VIAS
COPPER PLANE
THERMOCOUPLE
0
5077-031
Figure 31. Typical Optical Module Structure
The following procedure can be used to estimate the IC
junction temperature:
TTOP is the temperature at top of package in °C.
TPAD is the temperature at package exposed paddle in °C.
TJ is the IC junction temperature in °C.
P is the power dissipation in W.
θJ-TOP is the thermal resistance from IC junction to package top.
θJ-PAD is the thermal resistance from IC junction to package
exposed pad.
P
θ
J-TOP
T
PAD
T
TOP
T
TOP
θ
J-PAD
T
PAD
05077-032
Figure 32. Electrical Model for Thermal Calculations
TTOP and TPA D can be determined by measuring the temperature
at points inside the module, as shown in Figure 31. The thermo-
couples should be positioned to obtain an accurate measurement
of the package top and paddle temperatures. Using the model
shown in Figure 32, the junction temperature can be calculated by
(
)
TOPJ
PADJ
TOPJ
PADPADJ
TOPTOPJ
PADJ
J
TTP
T
θ+θ
θ
×
+θ×+
θ
×
θ
×
=
where:
θJ-TOP and θJ-PAD are given in Table 2.
P is the power dissipated by the ADN2525.
ADN2525
Rev. A | Page 13 of 16
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
Figure 33 shows the typical application circuit for the ADN2525.
The dc voltages applied to the BSET and MSET pins control the
bias and modulation currents. The bias current can be monitored
as a voltage drop across the 1 kΩ resistor connected between
the IBMON pin and GND. The ALS pin allows the user to turn
on/off the bias and modulation currents, depending on the logic
level applied to the pin. The data signal source must be connected
to the DATAP and DATAN pins of the ADN2525 using 50 Ω
transmission lines. The modulation current outputs, IMODP
and IMODN, must be connected to the load (TOSA) using 50 Ω
differential (25 Ω single-ended) transmission lines. Table 6
shows recommended components for the ac-coupling interface
between the ADN2525 and TOSA. For up-to-date component
recommendations, contact sales.
Working with a TOSA laser sample, the circuit in Figure 33 delivers
the optical performance shown in Figure 15 and Figure 16. For
additional applications information and optical eye performance of
other laser samples, contact ADI sales or see the ADN2525
application notes at www.analog.com.
Table 6.
Component Value Description
R1, R2 36 Ω 0603 size resistor
R3, R4 200 Ω 0603 size resistor
C3, C4 100 nF 0603 size capacitor,
Phycomp 223878615649
L2, L3, L6, L7 82 nH 0402 size inductor,
Murata LQW15AN82NJ0
L1, L4, L5, L8 10 μH 0603 size inductor,
Murata LQM21FN100M70L
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2525 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. Controlled impedance transmission
lines must be used for the high speed signal paths. The length of
the transmission lines must be kept to a minimum to reduce
losses and pattern-dependent jitter. The PCB layout must be
symmetrical, both on the DATAP and DATAN inputs and on
the IMODP and IMODN outputs, to ensure a balance between
the differential signals. All VCC and GND pins must be connected
to solid copper planes by using low inductance connections.
When the connections are made through vias, multiple vias
can be connected in parallel to reduce the parasitic inductance.
Each GND pin must be locally decoupled with high quality
capacitors. If proper decoupling cannot be achieved using a
single capacitor, the user can use multiple capacitors in parallel
for each GND pin. A 20 μF tantalum capacitor must be used as a
general decoupling capacitor for the entire module. For guidelines
on the surface-mount assembly of the ADN2525, see Amkor
Technology® Application Notes for Surface Mount Assembly of
Amkors MicroLeadFrame® (MLF) Packages.
MSET NC1 ALS GND
BSET IBMON IBIAS GND
VCC
DATAP
DATAN
VCC
VCC
IMODP
IMODN
VCC
DATAP
DATAN
C1
C2
MSET
BSET
R5
1k
ADN2525
Z
0
= 50Z
0
= 25Z
0
= 25
Z
0
= 50
GND
VCC
GND
VCC
TOSA
C4
C7
200µF
L2
L1 R1
3.3V
VCC VCC
VCC
VCC
VCC
TP1 C5
10nF
GND
GND
VCC
C6
10nF
GND
ALS
L7
L8 R4
L6
L5 R3
VCC
L3
L4 R2
VCC
Z
0
= 25Z
0
= 25
C3
GND
05077-033
Figure 33. Typical ADN2525 Application Circuit
ADN2525
Rev. A | Page 14 of 16
DESIGN EXAMPLE
This design example covers:
Headroom calculations for IBIAS, IMODP, and IMODN pins.
Calculation of the typical voltage required at the BSET and
MSET pins to produce the desired bias and modulation currents.
This design example assumes that the resistance of the TOSA is
25 Ω, the forward voltage of the laser at low current is VF = 1 V,
IBIAS = 40 mA, IMOD = 60 mA, and VCC = 3.3 V.
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in Tabl e 1.
Considering the typical application circuit shown in Figure 33,
the voltage at the IBIAS pin can be written as
VIBIAS = VCCVF − (IBIAS × RTOSA) − VLA
where:
VCC is the supply voltage.
VF is the forward voltage across the laser at low current.
RTOSA is the resistance of the TOSA.
VLA is the dc voltage drop across L5, L6, L7, and L8.
VLB is the dc voltage drop across L1, L2, L3, and L4.
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.6 V, as specified by the minimum
IBIAS compliance specification in Tabl e 1.
Assuming that the voltage drop across the 25 Ω transmission
lines is negligible and that VLA = 0 V, VF = 1 V, and IBIAS =
40 mA,
VIBIAS = 3.3 − 1 − (0.04 × 25) = 1.3 V
VIBIAS = 1.3 V > 0.6 V, which satisfies the requirement
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by
VCOMPLIANCE_MAX = VCC − 0.75 − 4.4 × IBIAS (A)
For this example:
VCOMPLIANCE_MAX = VCC – 0.75 − 4.4 × 0.04 = 2.53 V
VIBIAS = 1.3 V < 2.53 V, which satisfies the requirement
To calculate the headroom at the modulation current pins
(IMODP and IMODN), the voltage has a dc component equal
to VCC due to the ac-coupled configuration and a swing equal
to IMOD × 25 Ω. For proper operation of the ADN2525, the
voltage at each modulation output pin should be within the
normal operation region shown in Figure 30.
Assuming VLB = 0 V and IMOD = 60 mA, the minimum voltage
at the modulation output pins is equal to
VCC − (IMOD × 25)/2 = VCC − 0.75
VCC − 0.75 > VCC − 1.1 V, which satisfies the requirement
The maximum voltage at the modulation output pins is equal to
VCC + (IMOD × 25)/2 = VCC + 0.75
VCC + 0.75 < VCC + 1.1 V, which satisfies the requirement
Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to
ensure proper device operation over all operating conditions.
BSET and MSET Pin Voltage Calculation
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2525 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET
voltage to IBIAS gain specified in Table 1. Assuming that
IBIAS = 40 mA and the typical IBIAS/VBSET ratio of 100 mA/V,
the BSET voltage is given by
V4.0
100
40
mA/V100
(mA) === IBIAS
VBSET
The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
IBIAS gain values specified in Table 1.
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
K
IMOD
VMSET =
where K is the MSET voltage to IMOD ratio.
The value of K depends on the actual resistance of the TOSA.
It can be read using the plot shown in Figure 29. For a TOSA
resistance of 25 Ω, the typical value of K = 120 mA/V. Assuming
that IMOD = 60 mA and using the preceding equation, the
MSET voltage is given by
V5.0
120
60
mA/V120
(mA) === IMOD
VMSET
The MSET voltage range can be calculated using the required
IMOD range and the minimum and maximum K values. These
can be obtained from the minimum and maximum curves in
Figure 29.
ADN2525
Rev. A | Page 15 of 16
OUTLINE DIMENSIONS
1
0.50
BSC
0.60 MAX
PIN 1
INDICATO
R
1.50 REF
0.50
0.40
0.30
0.25 MIN
0.45
2.75
BSC SQ
TOP
VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATO
R
0.90
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
3.00
BSC SQ
*1.65
1.50 SQ
1.35
16
5
13
8
9
12
4
EXPOSED
PAD
(BOTTOM VIEW)
*COMPLIANT
TO
JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADN2525ACPZ-WP1−40°C to +85°C 16-Lead LFCSP_VQ, 50-Piece Waffle Pack CP-16-3 F06
ADN2525ACPZ-R21−40°C to +85°C 16-Lead LFCSP_VQ, 250-Piece Reel CP-16-3 F06
ADN2525ACPZ-REEL71−40°C to +85°C 16-Lead LFCSP_VQ, 7” 1,500-Piece Reel CP-16-3 F06
1 Z = Pb-free part.
ADN2525
Rev. A | Page 16 of 16
T
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05077-0-8/06(A)
TTT