EliteMT M11B416256A DRAM 256 K x 16 DRAM EDO PAGE MODE FEATURES ORDERING INFORMATION - PACKAGE X16 organization EDO (Extended Data-Output) access mode 2 CAS Byte/Word Read/Write operation 40-pin 400mil SOJ 44 / 40-pin 400mil TSOP (TypeII) Single 5V ( 10%) power supply TTL-compatible inputs and outputs 512-cycle refresh in 8ms Refresh modes : RAS only, CAS BEFORE RAS (CBR) and HIDDEN JEDEC standard pinout Key AC Parameter tRAC tCAC tRC tPC -25 25 8 43 10 -35 35 10 65 14 PRODUCT NO. PACKING TYPE COMMENTS M11B416256A-25JP SOJ Pb-free M11B416256A-35TG TSOPII Pb-free GENERAL DESCRIPTION The M11B416256A is a randomly accessed solid state memory, organized as 262,144 x 16 bits device. It offers Extended Data-Output , 5V( 10%) single power supply. Access time (-25,-35) and package type (SOJ, TSOP II) are optional features of this family. All these family have CAS - before - RAS , RAS -only refresh and Hidden refresh capabilities. Two access modes are supported by this device : Byte access and Word access. Use only one of the two CAS and leave the other staying high will result in a BYTE access. WORD access happens when two CAS ( CASL , CASH ) are used. CASL transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and CASH transiting low will output or input data into the upper byte (IO8~15). PIN ASSIGNMENT SOJ Top View VCC I/O0 I/O1 I/O2 I/O3 VC C I/O4 I/O5 I/O6 I/O7 NC NC WE RA S NC A0 A1 A2 A3 VC C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Elite Memory Technology Inc 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 TSOP (TypeII) Top View VS S VCC I/O1 5 I/O0 I/O1 4 I/O1 I/O1 3 I/O2 I/O1 2 I/O3 VS S VC C I/O1 1 I/O1 0 I/O9 I/O8 NC CASL CASH OE A8 I/O4 I/O5 I/O6 I/O7 NC NC WE RA S NC A7 A0 A6 A1 A5 A2 A4 A3 VS S VC C 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 VS S 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 NC I/O1 5 I/O1 4 I/O1 3 I/O1 2 VS S I/O1 1 I/O1 0 I/O 9 I/O 8 CASL CASH OE A8 A7 A6 A5 A4 VS S Publication Date : Jun. 2006 Revision : 2.1 1/15 EliteMT M11B416256A FUNCTIONAL BLOCK DIAGRAM WE DATA-IN BUFFER RAS CONTROL LOGIC CASL 16 CASH CLOCK GENERATOR 9 A0 A1 DATA-OUT BUFFER COLUMN ADDRESS BUFFER 9 OE COLUMN DECODER 512 16 16 SENSE AMPLIFIERS I/O GATING 8 REFRESH CONTROLER A2 IO0 : IO15 A3 512 x 16 A4 A5 A6 A7 99 A8 9 ROW. ADDRESS BUFFERS(9) 9 ROW DECODER REFRESH COUNTER 512 x 512 x 16 MEMORY ARRAY 512 VBB GENERATOR VCC VSS PIN DESCRIPTIONS PIN NO. PIN NAME TYPE 16~19,22~26 A0~A8 Input Address Input Row Address : A0~A8 Column Address : A0~A8 14 RAS Input Row Address Strobe 28 CASH Input Column Address Strobe / Upper Byte Control 29 CASL Input Column Address Strobe / Lower Byte Control 13 WE Input Write Enable 27 OE Input Output Enable 2~5,7~10,31~34,36~39 I/O0 ~ I/O15 Input / Output 1,6,20 VCC Supply Power, 5V 21,35,40 VSS Ground Ground 11,12,15,30 NC - Elite Memory Technology Inc DESCRIPTION Data Input / Output No Connect Publication Date : Jun. 2006 Revision : 2.1 2/15 EliteMT M11B416256A ABSOLUTE MAXIMUM RATINGS Voltage on Any pin Relative to Vss ... ......-1V to +7V Operating Temperature, TA (ambient) ....0 C to +70 C Storage Temperature (plastic) ..........-55 C to +150 C Power Dissipation .......................................1.43W Short Circuit Output Current ........................50mA Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation of the device above those conditions indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (0 C TA 70 C ; VCC = 5V 10% unless otherwise noted) PARAMETER CONDITIONS SYMBOL MIN MAX UNITS NOTES Supply Voltage VCC 4.5 5.5 V Supply Voltage VSS 0 0 V Input High Voltage VIH 2.4 VCC +0.3 V 1 Input Low Voltage VIL -0.3 0.8 V 1 Input Leakage Current 0V VIN VIH (max) ILI -10 10 A Output Leakage Current 0V VOUT VCC Output(s) disable ILO -10 10 A Output High Voltage IOH = -5 mA VOH 2.4 - V Output Low Voltage IOL = 4.2 mA VOL - 0.4 V 1 2 Note : 1.All Voltages referenced to VSS 2. 0V VOUT 5.0V, VCC 5.0V PARAMETER CONDITIONS MAX SYMBOL Operating Current RAS , CAS cycling , tRC =min ICC1 Standby Current TTL interface , RAS , CAS = VIH , DOUT =High-Z ICC2 CMOS interface, RAS , CAS VCC-0.2V UNITS NOTES -25 -35 210 150 mA 4 4 mA 2 2 mA 1,2 RAS only refresh Current tRC = min ICC3 210 150 mA 2 EDO Page Mode Current tPC = min ICC4 210 150 mA 1,3 Standby Current RAS =VIH, CAS = VIL ICC5 5 5 mA 1 CAS Before RAS Refresh Current tRC = min ICC6 210 150 mA Note : 1. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS =VIL . 3. Address can be changed once or less while CAS =VIH . Elite Memory Technology Inc Publication Date : Jun. 2006 Revision : 2.1 3/15 EliteMT M11B416256A CAPACITANCE (Ta = 25 C , VCC = 5V 10%) PARAMETER SYMBOL TYP MAX UNIT Input Capacitance (address) CI1 - 5 pF Input Capacitance ( RAS , CASH , CASL , WE , OE ) CI2 - 7 pF CI / O - 10 pF Output capacitance (I/O0~I/O15) AC ELECTRICAL CHARACTERISTICS (Ta = 0 to 70 C , VCC =5V 10%, VSS = 0V) (note 14) Test Conditions Input timing reference levels : 0V, 3V Output reference level : VOL= 0.8V, VOH=2.0V Output Load : 2TTL gate + CL (50pF) Assumed tT = 2ns PARAMETER -25 SYMBOL MIN -35 MAX MIN UNIT Notes MAX tRC 43 65 ns tRWC 65 95 ns tPC 10 14 ns 22 EDO-Page-Mode Read-Write Cycle Time tPCM 32 42 ns 22 Access Time From RAS tRAC 25 35 ns 4 Access Time From CAS tCAC 8 10 ns 5,20 Access Time From OE tOAC 8 10 ns 13,20 Access Time From Column Address tAA 12 18 ns Access Time From CAS Precharge tACP 14 20 ns RAS Pulse Width tRAS 25 10K 35 10K ns RAS Pulse Width (EDO Page Mode) tRASC 25 100K 35 100K ns RAS Hold Time tRSH 8 10 ns RAS Precharge Time tRP 15 25 ns CAS Pulse Width tCAS 4 CAS Hold Time tCSH 21 CAS Precharge Time tCP 4 RAS to CAS Delay Time tRCD 10 CAS to RAS Precharge Time tCRP 5 Read or Write Cycle Time Read Write Cycle Time EDO-Page-Mode Read or Write Cycle Time Row Address Setup Time tASR 0 Row Address Hold Time tRAH 5 RAS to Column Address Delay Time tRAD 8 Column Address Setup Time tASC 0 Column Address Hold Time tCAH Column Address Hold Time (Reference to RAS ) Column Address to RAS Lead Time Elite Memory Technology Inc 10K 17 25 ns 24 30 ns 19 5 ns 6,23 ns 7,18 5 ns 19 0 ns 5 10 10K 25 5 13 20 8 ns 17 ns 8 0 ns 18 5 5 ns 18 tAR 22 30 ns tRAL 12 18 ns Publication Date : Jun. 2006 Revision : 2.1 4/15 EliteMT M11B416256A (Continued) -25 PARAMETER Read Command Setup Time Read Command Hold Time Reference to CAS Read Command Hold Time Reference to RAS CAS to Output in Low-Z Output Buffer Turn-off Delay From CAS or RAS SYMBOL MIN -35 MAX MIN MAX UNIT Notes tRCS 0 0 ns 15,18 tRCH 0 0 ns 9,15,19 tRRH 0 0 ns 9 tCLZ 3 3 ns 20 tOFF1 3 15 ns 10,17,2 0 8 ns 17,26 15 3 Output Buffer Turn-off to OE tOFF2 Write Command Setup Time tWCS 0 0 ns 11,15,1 8 Write Command Hold Time tWCH 5 5 ns 15,25 tWCR 22 30 ns 15 Write Command Pulse Width tWP 5 5 ns 15 Write Command to RAS Lead Time tRWL 7 9 ns 15 Write Command to CAS Lead Time tCWL 5 7 ns 15,19 Data-in Setup Time tDS 0 0 ns 12,20 Data-in Hold Time tDH 5 5 ns 12,20 Data-in Hold Time (Reference to RAS ) tDHR 22 30 ns RAS to WE Delay Time tRWD 34 51 ns 11 Column Address to WE Delay Time tAWD 21 34 ns 11 CAS to WE Delay Time tCWD 17 Transition Time (rise or fall) tT 1.5 Refresh Period (512 cycles) tREF RAS to CAS Precharge Time tRPC 10 10 ns CAS Setup Time(CBR REFRESH) tCSR 5 10 ns 1,18 CAS Hold Time(CBR REFRESH) tCHR 7 10 ns 1,19 OE Hold Time From WE During Read-Mode-Write Cycle tOEH 4 4 ns 16 OE Low to CAS High Setup Time tOES 4 4 ns OE High Hold Time From CAS High tOEHC 2 2 ns OE Precharge Time tOEP 2 2 ns OE Setup Prior to RAS During Hidden Refresh Cycle tORD 0 0 ns Last CAS Going Low to First CAS Returning High tCLCH 4 5 ns Data Output Hold After CAS Returning Low tCOH 3 3 ns Output Disable Delay From WE tWHZ 3 Write Command Hold Time (Reference to RAS ) Elite Memory Technology Inc 6 26 50 2.5 8 7 3 ns 11,18 50 ns 2,3 8 ms 7 21 ns Publication Date : Jun. 2006 Revision : 2.1 5/15 EliteMT M11B416256A Notes : 1. 2. 3. 4. 5. 6. Enables on-chip refresh and address counters. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. Assume that tRCD tRCD (max) If CAS is low at the falling edge of RAS , data-out will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS and back to VIH ) is indeterminate. OE held high and WE taken low after CAS goes low result in a LATE WRITE ( OE -controlled) cycle. 12. Those parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-MODIFY- WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH 14. RAS must be pulsed high. 7. 8. 9. 10. 11. Operation within the tRCD limit ensures that tRCD (max) can be met, tRCD (max) is specified as a reference point only ; if tRCD is greater than the specified tRCD (max) limit, access time is controlled by tCAC. Operation within the tRAD limit ensures that tRAD(max) can be met. tRAD(max) is specified as a reference point only ; if tRAD is greater than the specified tRAD (max) limit, access time is controlled by tAA. Either tRCH or tRRH must be satisfied for a READ cycle. tOFF1(max) defines the time at which the output achieves the open circuit condition ; it is not a reference to VOH or VOL. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS tWCS(min) , the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD tRWD(min) , tAWD tAWD(min) and tCWD tCWD(min) , the cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS 15. 16. 17. 18. before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFY-WRITE operation is not possible. An initial pause of 200s is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. WRITE command is defined as WE going low. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOFF2 and tOEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. The I/Os open during READ cycles once tOFF1 or tOFF2 occur. Referenced to the earlier CAS falling edge. 19. Referenced to the latter CAS rising edge. 20. Output parameter (I/O) is referenced to corresponding CAS input, IO0~7 by CASL and IO8~15 by CASH . 21. Last falling CAS edge to first rising CAS edge. 22. Last rising CAS edge to next cycle's last rising CAS edge. 23. Last rising CAS edge to first falling CAS edge. 24. Each CAS must meet minimum pulse width. 25. Referenced to the latter CAS falling edge. 26. All IOs controlled by OE , regardless CASL and CASH . and RAS or OE go Elite Memory Technology Inc Publication Date : Jun. 2006 Revision : 2.1 6/15 EliteMT M11B416256A TRUTH TABLE FUNCTION RAS CASL CASH WE OE ADDRESSES ROW COL DQS NOTES Standby H H X H X X X X X Read : Word L L L H L ROW COL Data-Out Read : Lower Byte L L H H L ROW COL Lower Byte, Data-Out Read : Upper Byte L H L H L ROW COL Upper Byte, Data-Out Write : Word (Early Write) L L L L X ROW COL Data-In Write : Lower Byte (Early) L L H L X ROW COL Lower Byte, Data-In , Upper Byte, High-Z Write : Upper Byte (Early) L H L L X ROW COL Lower Byte, High-Z , Upper Byte, Data-In Read-Write L L L ROW COL Data-Out, Data-In 1st Cycle EDO-Page-Mode 2nd Cycle Read Any Cycle L H L H L H L ROW COL Data-Out 2 L H L H L H L COL Data-Out 2 L L H L H H L Data-Out 2 EDO-Page-Mode 1st Cycle Write 2nd Cycle L H L H L L X COL Data-In 1 L H L H L L X COL Data-In 1 EDO-Page-Mode 1st Cycle Read-Write 2nd Cycle L H L H L H L L H COL Data-Out, Data-In 1, 2 L H L H L H L L H COL Data-Out, Data-In 1, 2 L H L L L H L ROW COL Data-Out L H H X X ROW H L L L H X X Hidden Refresh RAS -Only Refresh CBR Refresh H L L H ROW ROW High-Z 1, 2 2 High-Z X High-Z 3 *Note : 1. These WRITE cycles may also be BYTE WRITE cycles (either CASL or CASH active). 2. These READ cycles may also be BYTE READ cycles (either CASL or CASH active). 3. Only one CAS must be active ( CASL or CASH ). Elite Memory Technology Inc Publication Date : Jun. 2006 Revision : 2.1 7/15 EliteMT M11B416256A READ CYCLE tRC tRAS tRP VIH RAS VIL tCRP CASL ,CASH tCSH tRSH tCAS tRCD tRRH tCLCH VIH VIL tAR tRAD tRAH tASR ADDR VIH VIL tRAL tCAH tASC ROW ROW COLUMN tRCS WE tRCH VIH VIL tAA tRAC tCAC tCLZ I/O VO H VO L NO TE 1 tOFF1 OPEN VAL ID DATA tO AC OE OPEN tOFF2 VIH VIL EARLY WRITE CYCLE tRC tRAS RAS tCRP CASL ,C ASH tRP VIH VIL tCSH tRSH t CAS tCLCH tRCD VIH VIL tAR tRAD tRAH tASR ADDR VIH VIL tRAL tCAH tASC COLUMN ROW tWCS ROW tCWL tRWL tWCR tWCH tWP WE VIH VIL tDS I/O OE VIH VIL tDHR tDH VAL ID D ATA VIH VIL DON'T CARE UNDEFINED Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. Elite Memory Technology Inc Publication Date : Jun. 2006 Revision : 2.1 8/15 EliteMT M11B416256A READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) tRWC t RAS RAS tCRP CASL,CASH tCSH tRS H t CAS tRCD tAR tRAD tRAH VIH VIL t RAL t CAH tASC ROW COLUMN ROW tCWL tRWL tWP tRWD tCWD tAWD tRCS WE tCLCH VIH VIL tASR ADDR tRP VIH VIL VIH VIL tAA tRAC tCAC I/O VAL ID DO UT OPEN tO AC OE tDH tDS tCLZ VI/O H VI/O L VALI D DIN tOEH tOFF 2 VIH VIL EDO-PAGE-MODE READ CYCLE tRASC RAS tPC tCSH tRCD tCRP CASL ,C AS H tRP VIH VIL tCAS ,t CLCH (NOTE2) tCAS, t CLCH tCP tRSH tCAS, t CLCH tCP tCP VIH VIL tAR t RAD tRAL t AS C tASR tRAH ADDR VIH VIL ROW tCAH COLUMN tASC tASC t CAH tCAH COLUMN COLUMN ROW tRCH tRCS WE VIH VIL tAA t ACP tCAC tAA tRAC tCAC OE VO H VO L tAA tACP tCAC OPEN VAL ID D ATA tO AC tOES NO TE1 tCLZ tCOH tCLZ I/O tRRH VALID DATA tOFF1 VAL ID D ATA tOEHC tO AC OPEN tOFF 2 tOFF 2 tOES VIH VIL tOEP DON'T CARE UNDEFINED *NOTE : 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. 2. tPC can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of CAS to rising edge of CAS . Both measurements must meet the tPC specification. Elite Memory Technology Inc Publication Date : Jun. 2006 Revision : 2.1 9/15 EliteMT M11B416256A EDO-PAGE-MODE EARLY-WRITE CYCLE tRASC RAS tRP VIH VIL tCSH tCRP CASL ,CASH tPC (NOTE1) tCAS,tCLCH tCP tCAS, tCLCH tRCD tRSH tCAS,tCLCH tCP tCP VIH VIL tAR tRAL tCAH tRAD tASR ADDR VIH VIL tRAH tCAH tASC tASC tCAH COLUMN ROW WE COLUMN COLUMN tCWL tWCS tASC tCWL tWCH tWP tWCS tWCH tWP ROW tCWL tWCH tWCS tWP VIH VIL tWCR tDHR tDH tDS I/O VIH VIL OE VIH VIL tRWL tDS VAL ID DATA tDH tDH tDS VAL ID DATA VAL ID DATA EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) tRASC RAS tRP VIH VIL tCSH tCRP CASL ,CASH tCAS, tCLCH tRCD tRSH tCP tPCM tCAS, tCLCH tCP tCAS,tCLCH tASC tCAH tASC tRAL tCAH tAR tRAD tASR ADDR tCP VIH VIL VIH VIL tRAH ROW tASC tCAH COLUMN COLUMN COLUMN ROW tRWD tRCS tRWL tCWL tWP tCWL tWP tAWD tCWD WE VIH VIL tACP tCAC tCLZ VI/O H VI/O L tAA tDH tACP tDH tDS tDS tCAC tCLZ VALI D VALI D DOUT DIN tCAC tCLZ VALI D VALI D DOUT D IN VALID VALI D DOUT DIN tOFF2 tOFF2 tO AC OE tCWD tAA tDH tDS I/O tAWD tAWD tCWD tAA tRAC tO AC tCWL tWP tO AC tOFF2 tOEH VIH VIL DON'T CARE UNDEFINED Note : 1. tPC can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of CAS . Both measurements must meet the tPC specification. Elite Memory Technology Inc Publication Date : Jun. 2006 Revision : 2.1 10/15 EliteMT M11B416256A EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY-WRITE) tRAS C RAS tRP VIH VIL tCSH CAS tCP tPC tCAS tRCD tCRP tCP tRSH tCAS tCP tCAS tCP VIH VIL tAR tRAL tRAD tASC tAS R tRAH ADDR VIH VIL tCAH tASC COLUMN(A) ROW tCAH tRCH VIH VIL OE tWCH tW HZ tACP tCAC VI/OH VI/OL tWCS ROW tAA tAA tRAC I/O tCAH COLUMN(N) COLUMN(B) tRCS WE tASC VAL ID DATA( A) OPE N tDS tCAC tCOH VALID DATA(B ) tDH VALID DATA IN tO AC VIH VIL RAS ONLY REFRESH CYCLE (ADDR = A0~A8 ; OE , WE = DON'T CARE) tRC tRP tRAS RAS VIH VIL CASL ,C AS H VIH VIL tCRP tRPC tASR ADDR I/O VIH VIL VO H VO L tRAH ROW ROW OPE N DON'T CARE UNDEFINED Elite Memory Technology Inc Publication Date : Jun. 2006 Revision : 2.1 11/15 EliteMT M11B416256A CBR REFRESH CYCLE (A0~A8 ; OE = DON'T CARE) tRP RAS tRPC tCP CASL ,C AS H tRAS tRP tCSR tCSR tRPC tCHR tCHR VIH VIL OPEN I/O WE tRAS VIH VIL VIH VIL tRCH HIDDEN REFRESH CYCLE ( WE = HIGH ; OE = LOW) (READ) (REF RESH) tRAS RAS tRCD VIH VIL tRSH tRAH tASR VIH VIL tCHR tAR tRAD ADDR tRAS VIH VIL tCRP CASL ,C AS H tRP tASC ROW tRAL tCAH COLUMN tAA NO TE1 tRAC tOFF1 tCAC tCLZ I/O OE VO H VO L VIH VIL VALID DATA OPEN tO AC tORD OPEN tOFF2 DON'T CARE UNDEFINED Note : 1. tOFF1 is reference from the rising edge of RAS or CAS , whichever occurs last. Elite Memory Technology Inc Publication Date : Jun. 2006 Revision : 2.1 12/15 EliteMT M11B416256A PACKING DIMENSIONS 40-LEAD SOJ(400mil) SECTION I b 2 0.050" Max. D 21 E1 E 40 b Detail "A" 20 e 1 0.024" Min. E 2 1 SECTION Seating Plain R Detail "A" A A1 A2 c 1 II b 2 0.050" Max. D 21 E1 E 40 b Detail "A" 20 A A1 A2 b b2 c e e 1 0.024" Min. E 2 1 Symbol Seating Plain R Detail "A" A A1 A2 c 1 Dimension in mm Min Norm Max 3.250 3.510 3.760 2.080 2.790 REF 0.380 0.460 0.560 0.635 REF Dimension in inch Symbol Dimension in mm Min Norm Max Min Norm Max 0.128 0.138 0.148 E 10.920 11.176 11.430 0.082 E1 10.030 10.160 10.290 0.110 REF E2 9.40 BSC 0.015 0.018 0.022 R1 0.760 0.890 1.020 0.025 REF 1 0 10 Dimension in inch Min Norm Max 0.430 0.440 0.450 0.395 0.400 0.405 0.370 BSC 0.030 0.035 0.040 0.180 0.250 0.360 1.270 BSC 0.007 0.010 0.014 0.050 BSC 1.02 Elite Memory Technology Inc D 25.91 26.040 26.290 0 10 1.025 1.035 Publication Date : Jun. 2006 Revision : 2.1 13/15 EliteMT M11B416256A PACKING DIMENSIONS 40 / 44-LEAD TSOP(II) Symbol DRAM(400mil) Dimension in mm Min Norm Max A Dimension in inch Min Norm 1.20 A1 0.05 A2 0.95 b 0.30 b1 0.30 1.00 0.35 Max 0.047 0.15 0.002 1.05 0.037 0.45 0.012 0.40 0.012 0.006 0.039 0.042 0.018 0.014 0.016 c 0.12 0.21 0.005 0.008 c1 0.10 0.16 0.004 0.006 D 18.28 18.54 0.720 ZD 18.41 0.805 REF 0.725 0.730 0.0317 REF E 11.56 11.76 11.96 0.455 0.463 0.471 E1 10.03 10.16 10.29 0.395 0.400 0.4 L 0.40 0.59 0.69 0.016 0.023 0.027 L1 0.80 REF e 0.80 BSC 0.0315 BSC O ~ 7 REF O ~ 7 REF Elite Memory Technology Inc 0.031 REF Publication Date : Jun. 2006 Revision : 2.1 14/15 EliteMT M11B416256A Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of EliteMT. The contents contained in this document are believed to be accurate at the time of publication. EliteMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by EliteMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of EliteMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. EliteMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Memory Technology Inc Publication Date : Jun. 2006 Revision : 2.1 15/15