LTC2050/LTC2050HV
11
Rev. E
For more information www.analog.com
output multiplied by the closed loop gain of the op amp.
To reduce this form of clock feedthrough, use smaller
valued gain setting resistors and minimize the source
resistance at the input. If the resistance seen at the inputs
is less than 10k, this form of clock feedthrough is less
than 1µVRMS input referred at 7.5kHz, or less than the
amount of residue clock feedthrough from the first form
described above.
Placing a capacitor across the feedback resistor reduces
either form of clock feedthrough by limiting the bandwidth
of the closed loop gain.
Input bias current is defined as the DC current into the
input pins of the op amp. The same current spikes that
cause the second form of clock feedthrough described
above, when averaged, dominate the DC input bias current
of the op amp below 70°C.
At temperatures above 70°C, the leakage of the ESD pro-
tection diodes on the inputs increases the input bias cur-
rents of both inputs in the positive direction, while the
current caused by the charge injection stays relatively
constant. At elevated temperatures (above 85°C) the
leakage current begins to dominate and both the negative
and positive pin’s input bias currents are in the positive
direction (into the pins).
Input Pins, ESD Sensitivity
ESD voltages above 700V on the input pins of the op amp
will cause the input bias currents to increase (more DC
current into the pins). At these voltages, it is possible to
damage the device to a point where the input bias current
exceeds the maximums specified in this data sheet.
Shutdown
The LTC2050 includes a shutdown pin in the 6-lead
SOT-23 and the SO-8 version. When this active low pin
is high or allowed to float, the device operates normally.
When the shutdown pin is pulled low, the device enters
shutdown mode; supply current drops to 3µA, all clock-
ing stops, and both inputs and output assume a high
impedance state.
Clock Feedthrough, Input Bias Current
The LTC2050 uses auto-zeroing circuitry to achieve an
almost zero DC offset over temperature, common mode
voltage, and power supply voltage. The frequency of the
clock used for auto-zeroing is typically 7.5kHz. The term
clock feedthrough is broadly used to indicate visibility of
this clock frequency in the op amp output spectrum. There
are typically two types of clock feedthrough in auto zeroed
op amps like the LTC2050.
The first form of clock feedthrough is caused by the settling
of the internal sampling capacitor and is input referred;
that is, it is multiplied by the closed loop gain of the op
amp. This form of clock feedthrough is independent of the
magnitude of the input source resistance or the magni-
tude of the gain setting resistors. The LTC2050 has a resi-
due clock feedthrough of less then 1µV
RMS
input referred
at 7.5kHz.
The second form of clock feedthrough is caused by the
small amount of charge injection occurring during the
sampling and holding of the op amp’s input offset volt-
age. The current spikes are multiplied by the impedance
seen at the input terminals of the op amp, appearing at the
APPLICATIONS INFORMATION