LM5021NA-1/NOPB - NATIONAL SEMICONDUCTOR

LM5021

LM5021 AC-DC Current Mode PWM Controller

Literature Number: SNVS359C

LM5021

July 10, 2011

AC-DC Current Mode PWM Controller

General Description

The LM5021 off-line pulse width modulation (PWM) controller

contains all of the features needed to implement highly effi-

cient off-line single-ended flyback and forward power con-

verters using current-mode control. The LM5021 features

include an ultra-low (25 µA) start-up current, which minimizes

power losses in the high voltage start-up network. A skip cycle

mode reduces power consumption with light loads for energy

conserving applications (ENERGY STAR®, CECP, etc.). Ad-

ditional features include under-voltage lockout, cycle-by-cy-

cle current limit, hiccup mode overload protection, slope

compensation, soft-start and oscillator synchronization capa-

bility. This high performance 8-pin IC has total propagation

delays less than 100nS and a 1MHz capable oscillator that is

programmed with a single resistor.

Features

■Ultra Low Start-up Current (25 µA maximum)

■Current Mode Control

■Skip Cycle Mode for Low Standby Power

■Single Resistor Programmable Oscillator

■Synchronizable Oscillator

■Adjustable Soft-start

■Integrated 0.7A Peak Gate Driver

■Direct Opto-Coupler Interface

■Maximum Duty Cycle Limiting (80% for LM5021-1 or 50%

for LM5021-2)

■Slope Compensation for (LM5021-1 Only)

■Under Voltage Lockout (UVLO) with Hysteresis

■Cycle-by-Cycle Over-Current Protection

■Hiccup Mode for Continuous Overload Protection

■Leading Edge Blanking of Current Sense Signal

■Packages: MSOP-8 or MDIP-8

Simplified Application Diagram

20144201

LM5021 AC-DC Current Mode PWM Controller

Connection Diagram

Top View

20144202

MSOP-8 and MDIP-8

Ordering Information

Order Number Description Package Type Supplied As

LM5021MM-1 80% Duty Cycle Limit MSOP-8 1000 Units on Tape and Reel

LM5021MMX-1 80% Duty Cycle Limit MSOP-8 3500 Units on Tape and Reel

LM5021NA-1 80% Duty Cycle Limit MDIP-8 40 Units per Rail

LM5021MM-2 50% Duty Cycle Limit MSOP-8 1000 Units on Tape and Reel

LM5021MMX-2 50% Duty Cycle Limit MSOP-8 3500 Units on Tape and Reel

LM5021NA-2 50% Duty Cycle Limit MDIP-8 40 Units per Rail

Pin Descriptions

Pin Name Description Application Information

1 COMP Control input for the Pulse Width Modulator

and Hiccup comparators.

COMP pull-up is provided by an internal 5K resistor which

may be used to bias an opto-coupler transistor.

2 VIN Input voltage. Input to start-up regulator. The VIN pin is clamped at 36V

by an internal zener diode.

3 VCC Output only of a linear bias supply regulator.

Nominally 8.5V.

VCC provides bias to controller and gate drive sections of

the LM5021. An external capacitor must be connected

from this pin to ground.

4 OUT MOSFET gate driver output. High current output to the external MOSFET gate input with

source/sink current capability of 0.3A and 0.7A

respectively.

5 GND Ground return.

6 CS Current Sense input. Current sense input for current mode control and over-

current protection. Current limiting is accomplished using

a dedicated current sense comparator. If the CS

comparator input exceeds 0.5 Volts the OUT pin switches

low for cycle-by-cycle current limit. CS is held low for 90ns

after OUT switches high to blank the leading edge current

spike.

7 RT / SYNC Oscillator timing resistor pin and

synchronization input.

An external resistor connected from RT to GND sets the

oscillator frequency. This pin will also accept

synchronization pulses from an external clock.

8 SS Soft-start / Hiccup time An external capacitor and an internal 22 µA current source

set the soft-start ramp. The soft -start capacitor controls

both the soft-start rate and the hiccup mode period.

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LM5021

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

VIN to GND -0.3V to 30V

VIN Clamp Continuous Current 5mA

CS to GND -0.3V to 1.25V

RT to GND -0.3V to 5.5V

All other pins to GND -0.3V to 7.0V

ESD Rating (Note 2)

Human Body Model 2kV

Storage Temperature -65°C to +150°C

Operating Junction Temperature +150°C

Operating Ratings (Note 1)

VIN Voltage (Note 5) 8V to 30V

Junction Temperature -40°C to +125°C

Electrical Characteristics Specifications in standard type face are for TJ= +25°C and those in boldface type

apply over the full Operating Junction Temperature Range. Unless otherwise specified: VIN = 15V, RT = 44.2KΩ. (Note 3)

Symbol Parameter Conditions Min Typ Max Unit

STARTUP CIRCUIT

Start Up Current Before VCC Enable 18 25 µA

VCC Regulator enable threshold 17 20 23 V

VCC Regulator disable

threshold

7.25 V

VIN ESD Clamp voltage I = 5mA 30 36 40 V

IVIN Operating supply current COMP = 0VDC 2.5 3.75 mA

VCC SUPPLY

Controller enable threshold 6.5 77.5 V

Controller disable threshold 5.3 5.8 6.3 V

VCC regulated output No External Load 88.5 9V

VCC dropout voltage (VIN -

VCC)

I = 5 mA 1.7 V

VCC regulator current limit VCC = 7.5V (Note 4)15 22 mA

SKIP CYCLE MODE COMPARATOR

Skip Cycle mode enable

threshold

⅓ [COMP - 1.25V] 75 125 175 mV

Skip Cycle mode hysteresis 5 mV

CURRENT LIMIT

CS limit to OUT delay CS stepped from 0 to

0.6V, time to OUT

transition low, Cload =

35 ns

CS limit threshold 0.45 0.5 0.55 V

Leading Edge Blanking time 90 ns

CS blanking sinking impedance 35 55 Ω

SOFT-START

VSS-OCV SS pin open-circuit voltage 4.3 5.2 6.1 V

Soft-start Current Source 15 22 30 µA

Soft-start to COMP Offset 0.35 0.55 0.75 V

COMP sinking impedance During SS ramp 60 Ω

OSCILLATOR

Frequency1 (RT = 44.2K) 135 150 165 kHz

Frequency2 (RT = 13.3K) 440 500 560 kHz

Sync threshold 2.4 3.2 3.8 V

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LM5021

Symbol Parameter Conditions Min Typ Max Unit

PWM COMPARATOR

COMP to OUT delay COMP set to 2V

CS stepped 0 to

0.4V, time to OUT

transition low, Cload =

20 ns

Min Duty Cycle COMP = 0V 0%

Max Duty Cycle (-1 Device) 75 80 85 %

Max Duty Cycle (-2 Device) 50 %

COMP to PWM comparator gain 0.33

COMP Open Circuit Voltage 4.2 5.1 6V

COMP at Max Duty Cycle 2.75 V

COMP Short Circuit Current COMP = 0V 0.6 1.1 1.5 mA

SLOPE COMPENSATION

Slope Comp Amplitude

(LM5021-1 only)

CS pin to PWM

Comparator offset at

maximum duty cycle

70 90 110 mV

OUTPUT SECTION

OUT High Saturation IOUT = 50mA, VCC -

OUT

0.6 1.1 V

OUT Low Saturation IOUT = 100mA 0.3 1V

Peak Source Current OUT = VCC/2. 0.3 A

Peak Sink Current OUT = VCC/2. 0.7 A

Rise time Cload = 1nF 25 ns

Fall time Cload = 1nF 10 ns

HICCUP MODE

VOVLD Over load detection threshold COMP pin VSS-OCV – 0.8 VSS-OCV – 0.6 VSS-OCV– 0.4 V

VHIC Hiccup mode threshold SS pin VSS-OCV – 0.8 VSS-OCV – 0.6 VSS-OCV– 0.4 V

VRST Hiccup mode Restart threshold SS pin 0.1 0.3 0.5 V

IDTCS Dead-time current source 0.1 0.25 0.4 µA

IOVCS Overload detection timer current

source

610 14 µA

THERMAL RESISTANCE

θJA MSOP-8 Junction to Ambient 0 LFM 200 °C/W

θJA MDIP-8 Junction to Ambient 0 LFM 107 °C/W

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the

device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.

Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical

Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

Note 4: Device thermal limitations may limit usable range.

Note 5: After initial turn-on at VIN = 20V.

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LM5021

Simplified Block Diagram

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FIGURE 1.

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LM5021

Typical Performance Characteristics Unless otherwise specified: TJ = 25°C.

VIN Start-Up Current

20144204

VIN UVLO

20144205

VIN Current vs OUT Load

20144206

VIN Voltage Falling vs VCC Voltage

20144207

OUT Driver Current vs Temperature

20144208

Hiccup Mode Deadtime vs Softstart Capacitance

20144209

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LM5021

Output Switching Frequency vs RT

20144210

Detailed Operating Description

START UP CIRCUIT

Referring to Figure 2, the input capacitor CVIN is trickle

charged through the start-up resistor Rstart, when the recti-

fied ac input voltage HV is applied. The VIN current consumed

by the LM5021 is only 18 µA (nominal) while the capacitor

CVIN is initially charged to the start-up threshold. When the

input voltage, VIN reaches the upper VIN UVLO threshold of

20V, the internal VCC linear regulator is enabled. The VCC

regulator will remain on until VIN falls to the lower UVLO

threshold of 7.25V (12.5V hysteresis). When the VCC regu-

lator is turned on, the external capacitor at the VCC pin begins

to charge. The PWM controller, soft-start circuit and gate driv-

er are enabled when the VCC voltage reaches the VCC UVLO

upper threshold of 7V. The VCC UVLO has 1.2V hysteresis

between the upper and lower thresholds to avoid chattering

during transients on the VCC pin. When the VCC UVLO en-

ables the switching power supply, energy is transferred from

the primary to the secondary transformer winding(s). A bias

winding, shown in Figure 2, delivers power to the VIN pin to

sustain the VCC regulator. The voltage supplied should be

from 11V (VCC regulated voltage maximum plus VCC regu-

lator dropout voltage) to 30V (maximum operating VIN volt-

age). The bias winding should always be connected to the

VIN pin as shown in Figure 2. Do not connect the bias winding

to the VCC pin. The start-up sequence is completed and nor-

mal operation begins when the voltage from the bias winding

is sufficient to maintain VCC level greater than the VCC UVLO

threshold (5.8V typical).

The LM5021 is designed for ultra-low start-up current into the

VIN pin. To accomplish this very low start-up current, the VCC

regulator of the LM5021 is unique as compared to the VCC

regulator used in other controllers of the LM5xxx family. The

LM5021 is designed specifically for applications with the bias

winding connected to the VIN pin as shown in Figure 2. It is

not recommended that the bias winding be connected to

the VCC pin of the LM5021.

The size of the start-up resistor Rstart not only affects power

supply start-up time, but also power supply efficiency since

the resistor dissipates power in normal operation. The ultra

low start-up current of the LM5021 allows a large value Rstart

resistor (up to 3 MΩ) for improved efficiency with reasonable

start-up time.

20144211

FIGURE 2. Start-Up Circuit Block Diagram

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LM5021

RELATIONSHIP BETWEEN INPUT CAPACITOR CIN &

VCC CAPACITOR CVCC

The internal VCC linear regulator is enabled when VIN reach-

es 20V. The drop in VIN due to charge transfer from CVIN to

CVCC after the regulator is enabled can be calculated from the

following equations where VIN' is the voltage on CVIN imme-

diately after the VCC regulator charges CVCC.

ΔVIN x CVIN = ΔVCC x CVCC

(20V – VIN') CVIN = 8.5V CVCC

Assuming CVIN value as 10 µF, and CVCC of 1µF, then the drop

in VIN will be 0.85V, or the VIN value drops to 19.15V. The

value of the VCC capacitor can be small (less than 1uF) as it

supplies only transient gate drive current of a short duration.

The CVIN capacitor must be sized to supply the gate drive

current and the quiescent current of LM5021until the trans-

former bias winding delivers sufficient voltage to VIN to sus-

tain the VCC voltage.

The CVIN capacitor value can be calculated from the operating

VCC load current after it's output voltage reaches the VCC

UVLO threshold. For example, if the LM5021 is driving an ex-

ternal MOSFET with total gate charge (Qg) of 25nC, the

average gate drive current is Qg x Fsw, where Fsw is the

switching frequency. Assuming a switching frequency of

150KHz, the average gate drive current is 3.75mA. Since the

IC consumes approximately 2.5mA operating current in ad-

dition to the gate current, the total current drawn from CVIN

capacitor is the operating current plus the gate charge cur-

rent, or 6.25mA. The CVIN capacitor must supply this current

for a brief time until the transformer bias winding takes over.

The CVIN voltage must not fall below 8.5V during the start-up

sequence or the cycle will be restarted. The maximum allow-

able start-up time can be calculated using the value of CVIN,

the change in voltage allow at VIN (19.15V – 8.5V) and the

VCC regulator current (6.25mA). Tmax, the maximum time

allowed to energize the bias winding is:

If the calculated value of Tmax is too small, the value of Cin

should be increased further to allow more time before the

transformer bias winding takes over and delivers the operat-

ing current to the VCC regulator. Increasing CVIN will increase

the time from the application of the rectified ac (HV in the

Figure 2) to the time when VIN reaches the 20V start thresh-

old. The initial charging time of CVIN is:

PWM COMPARATOR/SLOPE COMPENSATION

The PWM comparator compares the current sense signal with

the loop error voltage from the COMP pin. The COMP pin

voltage is reduced by 1.25V then attenuated by a 3:1 resistor

divider. The PWM comparator input offset voltage is designed

such that less than 1.25V at the COMP pin will result in a zero

duty cycle at the controller output.

For duty cycles greater than 50 percent, current mode control

circuits are subject to sub-harmonic oscillation. By adding an

additional fixed slope voltage ramp signal (slope compensa-

tion) to the current sense signal, this oscillation can be avoid-

ed. The LM5021-1 integrates this slope compensation by

summing a ramp signal generated by the oscillator with the

current sense signal. The slope compensation is generated

by a current ramp driven through an internal 1.8 kΩ resistor

connected to the CS pin. Additional slope compensation may

be added by increasing the resistance between the current

sense filter capacitor and the CS pin, thereby increasing the

voltage ramp created by the oscillator current ramp. Since the

LM5021-2 is not capable of duty cycles greater than 50%,

there is no slope compensation feature in this device.

CURRENT LIMIT/CURRENT SENSE

The LM5021 provides a cycle-by-cycle over current protec-

tion feature. Current limit is triggered by an internal current

sense comparator threshold which is set at 500mV. If the CS

pin voltage plus the slope compensation voltage exceeds

500mV, the OUT pin output pulse will be immediately termi-

nated.

An RC filter, located near the LM5021, is recommended for

the CS pin to attenuate the noise coupled from the power

FET's gate to source. The CS pin capacitance is discharged

at the end of each PWM clock cycle by an internal switch. The

discharge switch remains on for an additional 90ns leading

edge blanking interval to attenuate the current sense transient

that occurs when the external power FET is turned on. In ad-

dition to providing leading edge blanking, this circuit also

improves dynamic performance by discharging the current

sense filter capacitor at the conclusion of every cycle.

The LM5021 CS comparator is very fast, and may respond to

short duration noise pulses. Layout considerations are critical

for the current sense filter and sense resistor. The capacitor

associated with the CS filter must be placed very close to the

device and connected directly to the pins of the IC (CS and

GND). If a current sense transformer is used, both leads of

the transformer secondary should be routed to the sense re-

sistor, which should also be located close to the IC. If a current

sense resistor located in the power FET's source is used for

current sense, a low inductance resistor is required. In this

case, all of the noise sensitive low current grounds should be

connected in common near the IC and then a single connec-

tion should be made to the power ground (sense resistor

ground point).

OSCILLATOR, SHUTDOWN and SYNC CAPABILITY

A single external resistor connected between RT and GND

pins sets the LM5021 oscillator frequency. The LM5021-2 de-

vice, with 50% maximum duty cycle, includes an internal flip-

flop that divides the oscillator frequency by two. This method

produces a precise 50% maximum duty cycle limit. Because

of this frequency divider, the oscillator frequency of the

LM5021-2 is actually twice the frequency of the gate drive

output (OUT). For the LM5021-1 device, the oscillator fre-

quency and the operational output frequency are the same.

To set a desired output switching frequency (Fsw), the RT

resistor can be calculated from:

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LM5021

LM5021-1:

LM5021-2:

The LM5021 can also be synchronized to an external clock.

The external clock must have a higher frequency than the free

running oscillator frequency set by the RT resistor. The clock

signal should be capacitively coupled into the RT pin with a

100pF capacitor. A peak voltage level greater than 3.8 Volts

at the RT pin is required for detection of the sync pulse. The

dc voltage across the RT resistor is internally regulated at 2

volts. Therefore, the ac pulse superimposed on the RT resis-

tor must have 1.8V or greater amplitude to successfully syn-

chronize the oscillator. The sync pulse width should be set

between 15ns to 150ns by the external components. The RT

resistor is always required, whether the oscillator is free run-

ning or externally synchronized. The RT resistor should be

located very close to the device and connected directly to the

pins of the LM5021 (RT and GND).

GATE DRIVER and MAX DUTY CYCLE LIMIT

The LM5021 provides a gate driver (OUT), which can source

peak current of 0.3A and sink 0.7A. The LM5021 is available

in two duty-cycle limit options. The maximum output duty-cy-

cle is typically 80% for the LM5021-1 option, and precisely

equal to 50% for the LM5021-2 option. The maximum duty

cycle function for the LM5021-2 is accomplished with an in-

ternal toggle flip-flop to ensure an accurate duty cycle limit.

The internal oscillator frequency of the LM5021-2 is therefore

twice the switching frequency of the PWM controller (OUT

pin).

The 80% maximum duty-cycle function for the LM5021-1 is

determined by the internal oscillator. For the LM5021-1 the

internal oscillator frequency and the switching frequency of

the PWM controller are the same.

SOFT-START

The soft-start feature allows the power converter to gradually

reach the initial steady state operating point, thus reducing

start-up stresses and current surges. An internal 22 µA cur-

rent source charges an external capacitor connected to the

SS pin. The capacitor voltage will ramp up slowly, limiting the

COMP pin voltage and the duty cycle of the output pulses.

The soft-start capacitor is also used to generate the hiccup

mode delay time when the output of the switching power sup-

ply is continuously overloaded.

HICCUP MODE OVERLOAD CURRENT LIMITING

Hiccup mode is a method of protecting the power supply from

over-heating and damage during an extended overload con-

dition. When the output fault is removed the power supply will

automatically restart.

Figure 3, Figure 4 and Figure 5 illustrate the equivalent circuit

of the hiccup mode for LM5021 and the relevant waveforms.

During start-up and in normal operation, the external soft-start

capacitor Css is pulled up by a current source that delivers 22

µA to the SS pin capacitor. In normal operation, the soft-start

capacitor continues to charge and eventually reaches the sat-

uration voltage of the current source (VSS_OCV, nominally

5.2V). During start-up the COMP pin voltage follows the SS

capacitor voltage and gradually increases the peak current

delivered by the power supply. When the output of the switch-

ing power supply reaches the desired voltage, the voltage

feedback amplifier takes control of the COMP signal (via the

opto-coupler). In normal operation the COMP level is held at

an intermediate voltage between 1.25V and 2.75V controlled

by the voltage regulation loop. When the COMP pin voltage

is below 1.25V, the duty-cycle is zero. When the COMP level

is above 2.75V, the duty cycle will be limited by the 0.5V

threshold of cycle-by-cycle current limit comparator.

If the output of the power supply is overloaded, the voltage

regulation loop demands more current by increasing the

COMP pin control voltage. When the COMP pin exceeds the

over voltage detection threshold (VOVLD, nominally 4.6V), the

SS capacitor Css will be discharged by a 10 µA overload de-

tection timer current source, IOVCS. If COMP remains above

VOVLD long enough for the SS capacitor to discharge to the

Hiccup mode threshold (VHIC, nominally 4.6V), the controller

enters the hiccup mode. The OUT pin is then latched low and

the SS capacitor discharge current source is reduced from 10

µA to 0.25 µA, the dead-time current source, IDTCS. The SS

pin voltage is slowly reduced until it reaches the Restart

threshold (VRST, nominally 0.3V). Then a new start-up se-

quence commences with 22 µA current source charging the

capacitor CSS. The slow discharge of the SS capacitor from

the Hiccup threshold to the Restart threshold provides an ex-

tended off time that reduces the overheating of components

including diodes and MOSFETs due to the continuous over-

load. The off time during the hiccup mode can be calculated

from the following equation:

Example:

Toff = 808 ms, assuming the CSS capacitor value is 0.047 µF

Short duration intermittent overloads will not trigger the hiccup

mode. The overload duration required to trigger the hiccup

response is set by the capacitor CSS, the 10 µA discharge

current source and voltage difference between the saturation

level of the SS pin and the Hiccup mode threshold.Figure 5

shows the waveform of SS pin with a short duration overload

condition. The overload time required to enter the hiccup

mode can be calculated from the following equation:

Example:

Toverload = 2.82 ms, assuming the CSS capacitor value is

0.047 µF

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LM5021

20144219

FIGURE 3. Hiccup Mode Control

20144220

FIGURE 4. Waveform at SS and COMP Pin due to Continuous Overload

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LM5021

20144221

FIGURE 5. Waveform at SS and COMP Pin due to Brief Overload

SKIP CYCLE OPERATION

During light load conditions, the efficiency of the switching

power supply typically drops as the losses associated with

switching and operating bias currents of the converter be-

come a significant percentage of the power delivered to the

load. The largest component of the power loss is the switching

loss associated with the gate driver and external MOSFET

gate charge. Each PWM cycle consumes a finite amout of

energy as the MOSFET is turned on and then turned off.

These switching losses are proportional to the frequency of

operation. The Skip Cycle function integrated within the

LM5021 controller reduces the average switching frequency

to reduce switching losses and improve efficiency during light

load conditions.

When a light load condition occurs, the COMP pin voltage is

reduced by the voltage feedback loop to reduce the peak cur-

rent delivered by the controller. Referring to Figure 6, the

PWM comparator input tracks the COMP pin voltage through

a 1.25V level shift circuit and a 3:1 resistor divider. As the

COMP pin voltage falls, the input to the PWM comparator falls

proportionately. When the PWM comparator input falls to

125mV, the Skip Cycle comparator detects the light load con-

dition and disables output pulses from the controller. The

controller continues to skip switching cycles until the power

supply output falls and the COMP pin voltage increases to

demand more output current. The number of cycles skipped

will depend on the load and the response time of the frequen-

cy compensation network. Eventually the COMP voltage will

increase when the voltage loop requires more current to sus-

tain the regulated output voltage. When the PWM comparator

input exceeds 130mV (5mV hysteresis), normal fixed fre-

quency switching resumes. Typical power supply designs will

produce a short burst of output pulses followed by a long skip

cycle interval. The average switching frequency in the Skip

Cycle mode can be a small fraction of the normal operating

frequency of the power supply.

The skip cycle mode of operation can be disabled by adding

an offset voltage to the CS pin (refer to Figure 7). A resistive

divider connected to a regulated source, injecting a 125mV

offset (minimum) on the CS pin, will force the voltage at the

PWM Comparator to be greater than 125 mV, disabling the

Skip Cycle Comparator.

20144222

FIGURE 6. Skip Cycle Control

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LM5021

20144224

FIGURE 7. Disabling the Skip Cycle Mode

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LM5021

Typical Application Circuit

20144223

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LM5021

Physical Dimensions inches (millimeters) unless otherwise noted

8 Lead MSOP Package

NS Package Number MUA08A

8 Lead MDIP Package

NS Package Number N08E

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LM5021

Notes

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LM5021

Notes

LM5021 AC-DC Current Mode PWM Controller

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