Atmel M90E25 Single-Phase High-Performance Wide-Span Energy Metering IC PRELIMINARY DATASHEET FEATURES Metering Features * Metering features fully in compliance with the requirements of IEC62052-11 and IEC62053-21; applicable in class 1 or class 2 single-phase watt-hour meter. * Accuracy of 0.1% for active energy over a dynamic range of 5000:1. * Temperature coefficient is 15 ppm/ (typical) for on-chip reference voltage * Single-point calibration over a dynamic range of 5000:1 for active energy. * Energy Meter Constant doubling at low current to save verification time. * Electrical parameters measurement: less than 0.5% fiducial error for Vrms, Irms, mean active/ apparent power, frequency, power factor and phase angle. * Forward/ reverse active energy with independent energy registers. Active energy can be output by pulse or read through energy registers to adapt to different applications. * Programmable startup and no-load power threshold. * Dedicated ADC and different gains for L line and N line current sampling circuits. Current sampled over shunt resistor or current transformer (CT); voltage sampled over resistor divider network or potential transformer (PT). * Programmable L line and N line metering modes: anti-tampering mode (larger power), L line mode (fixed L line), L+N mode (applicable for single-phase three-wire system) and flexible mode (configure through register). * Programmable L line and N line power difference threshold in anti-tampering mode. Other Features * 3.3V single power supply. Operating voltage range: 2.8~3.6V. Metering accuracy guaranteed within 3.0V~3.6V. 5V compatible for digital input. * Built-in hysteresis for power-on reset. * Four-wire SPI interface or simplified three-wire SPI interface with fixed 24 cycles for all registers operation * Parameter diagnosis function and programmable interrupt output of the IRQ interrupt signal and the WarnOut signal. * Programmable voltage sag detection and zero-crossing output. * Channel input range - Voltage channel (when gain is '1'): 120Vrms~600mVrms. - L line current channel (when gain is '24'): 5Vrms~25mVrms. - N line current channel (when gain is '1'): 120Vrms~600mVrms. * Programmable L line current gain: 1, 4, 8, 16, 24; Programmable N line gain: 1, 2, 4. * Support L line and N line offset compensation. * CF1 outputs active energy pulses which can be used for calibration or energy accumulation. * Crystal oscillator frequency: 8.192 MHz. On-chip 10pF capacitors and no need of external capacitors. * Green SSOP28 package. * Operating temperature: -40 ~ +85 . Atmel-46001A-SE-M90E25-Datasheet_041814 APPLICATION * The M90E25 is used for active energy metering for single-phase two-wire (1P2W), single-phase three-wire (1P3W) or anti-tampering energy meters. With the measurement function, the M90E25 can also be used in power instruments which need to measure voltage, current, etc. DESCRIPTION The M90E25 is high-performance wide-span energy metering chips. The ADC and DSP technology ensure the chips' long-term stability over variations in grid and ambient environmental conditions. BLOCK DIAGRAM MMD1 I1P I1N VP VN I2P I2N Vref PGA X1/X4/X8/ X16/X24 DSP Module ADC PGA X1 ADC PGA X1/X2/X4 ADC HPF1 HPF0 L Line Forward/Reverse Active Power L Line Apparent Power L Line Irms HPF1 HPF0 Vrms HPF1 HPF0 N Line Forward/Reverse Active Power N Line Apparent Power N Line Irms Reference Voltage Crystal Oscillator RESET MMD0 3-wire or 4-wire SPI Active Energy Pulse Output WarnOut/IRQ/ZX Power Factor/ Angle/Frequency Power On Reset OSCI OSCO CS SCLK SDO SDI CF1 WarnOut IRQ ZX Figure-1 Block Diagram M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 2 Ta bl e o f C o n t en ts FEATURES .......................................................................................................................................... 1 APPLICATION ..................................................................................................................................... 2 DESCRIPTION ..................................................................................................................................... 2 BLOCK DIAGRAM............................................................................................................................... 2 1 PIN ASSIGNMENT .......................................................................................................................... 7 2 PIN DESCRIPTION .......................................................................................................................... 8 3 FUNCTIONAL DESCRIPTION ...................................................................................................... 10 3.1 DYNAMIC METERING RANGE .............................................................................................................................10 3.2 STARTUP AND NO-LOAD POWER .....................................................................................................................10 3.3 ENERGY REGISTERS ...........................................................................................................................................10 3.4 N LINE METERING AND ANTI-TAMPERING .......................................................................................................11 3.4.1 Metering Mode and L/N Line Current Sampling Gain Configuration ................................................... 11 3.4.2 Anti-Tampering Mode ............................................................................................................................... 11 3.5 MEASUREMENT AND ZERO-CROSSING ...........................................................................................................12 3.5.1 Measurement ............................................................................................................................................. 12 3.5.2 Zero-Crossing ............................................................................................................................................ 12 3.6 CALIBRATION .......................................................................................................................................................13 3.7 RESET ....................................................................................................................................................................14 4 INTERFACE ................................................................................................................................... 15 4.1 SERIAL PERIPHERAL INTERFACE (SPI) ...........................................................................................................15 4.1.1 Four-Wire Mode ......................................................................................................................................... 15 4.1.2 Three-Wire Mode ....................................................................................................................................... 16 4.1.3 Timeout and Protection ............................................................................................................................ 17 4.2 WARNOUT PIN FOR FATAL ERROR WARNING ................................................................................................18 4.3 LOW COST IMPLEMENTATION IN ISOLATION WITH MCU ..............................................................................18 5 REGISTER ..................................................................................................................................... 19 5.1 REGISTER LIST ....................................................................................................................................................19 5.2 STATUS AND SPECIAL REGISTER ....................................................................................................................21 5.3 METERING/ MEASUREMENT CALIBRATION AND CONFIGURATION ............................................................25 5.3.1 Metering Calibration and Configuration Register .................................................................................. 25 5.3.2 Measurement Calibration Register .......................................................................................................... 32 5.4 ENERGY REGISTER .............................................................................................................................................37 5.5 MEASUREMENT REGISTER ................................................................................................................................40 6 ELECTRICAL SPECIFICATION .................................................................................................... 46 6.1 ELECTRICAL SPECIFICATION ............................................................................................................................46 6.2 SPI INTERFACE TIMING .......................................................................................................................................48 6.3 POWER ON RESET TIMING .................................................................................................................................50 6.4 ZERO-CROSSING TIMING ....................................................................................................................................51 M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 3 6.5 VOLTAGE SAG TIMING ........................................................................................................................................52 6.6 PULSE OUTPUT ....................................................................................................................................................53 6.7 ABSOLUTE MAXIMUM RATING ..........................................................................................................................53 ORDERING INFORMATION .............................................................................................................. 54 PACKAGE DIMENSIONS .................................................................................................................. 55 REVISION HISTORY ......................................................................................................................... 56 M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 4 List of Tables Table-1 Pin Description ....................................................................................................................................................... 8 Table-2 Active Energy Metering Error ............................................................................................................................... 10 Table-3 Threshold Configuration for Startup and No-Load Power .................................................................................... 10 Table-4 Energy Registers .................................................................................................................................................. 10 Table-5 Metering Mode ..................................................................................................................................................... 11 Table-6 The Measurement Format .................................................................................................................................... 12 Table-7 Read / Write Result in Four-Wire Mode ............................................................................................................... 17 Table-8 Read / Write Result in Three-Wire Mode ............................................................................................................. 17 Table-9 Register List ......................................................................................................................................................... 19 Table-10 SPI Timing Specification .................................................................................................................................... 49 Table-11 Power On Reset Specification ............................................................................................................................ 50 Table-12 Zero-Crossing Specification ............................................................................................................................... 51 Table-13 Voltage Sag Specification .................................................................................................................................. 52 M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 5 List of Figures Figure-1 Block Diagram ...................................................................................................................................................... 2 Figure-2 Pin Assignment (Top View) ................................................................................................................................... 7 Figure-3 Read Sequence in Four-Wire Mode .................................................................................................................... 15 Figure-4 Write Sequence in Four-Wire Mode .................................................................................................................... 15 Figure-5 Read Sequence in Three-Wire Mode .................................................................................................................. 16 Figure-6 Write Sequence in Three-Wire Mode .................................................................................................................. 16 Figure-7 4-Wire SPI Timing Diagram ................................................................................................................................ 48 Figure-8 3-Wire SPI Timing Diagram ................................................................................................................................ 48 Figure-9 Power On Reset Timing Diagram ....................................................................................................................... 50 Figure-10 Zero-Crossing Timing Diagram ......................................................................................................................... 51 Figure-11 Voltage Sag Timing Diagram ............................................................................................................................ 52 Figure-12 Output Pulse Width ........................................................................................................................................... 53 M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 6 1 PIN ASSIGNMENT MMD1 1 28 MMD0 DGND 2 27 SDI DVDD 3 26 SDO Reset 4 25 SCLK AVDD 5 24 CS AGND 6 23 OSCO I2P 7 22 OSCI I2N 8 21 ZX NC 9 20 IRQ I1P 10 19 NC I1N 11 18 CF1 NC 12 17 WarnOut Vref 13 16 VP AGND 14 15 VN Figure-2 Pin Assignment (Top View) 7 M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 2 PIN DESCRIPTION Table-1 Pin Description Name Pin No. I/O note 1 Type Reset 4 I LVTTL DVDD 3 I Power DGND 2 I Power AVDD 5 I Power Vref 13 O Analog AGND 6, 14 I Power I1P I1N 10 11 I Analog I2P I2N 7 8 VP VN 16 15 NC 9, 12, 19 I I Description Reset: Reset Pin (active low) This pin should connect to ground through a 0.1F filter capacitor. In application it can also directly connect to one output pin from microcontroller (MCU). DVDD: Digital Power Supply This pin provides power supply to the digital part. It should be decoupled with a 10F electrolytic capacitor and a 0.1F capacitor. DGND: Digital Ground AVDD: Analog Power Supply This pin provides power supply to the analog part. This pin should connect to DVDD through a 10 resistor and be decoupled with a 0.1F capacitor. Vref: Output Pin for Reference Voltage This pin should be decoupled with a 1F capacitor and a 1nF capacitor. AGND: Analog Ground I1P: Positive Input for L Line Current I1N: Negative Input for L Line Current These pins are differential inputs for L line current. Input range is 5Vrms~25mVrms when gain is '24'. Analog I2P: Positive Input for N Line Current I2N: Negative Input for N Line Current These pins are differential inputs for N line current. Input range is 120Vrms~600mVrms when gain is '1'. Analog VP: Positive Input for Voltage VN: Negative Input for Voltage These pins are differential inputs 120Vrms~600mVrms. for voltage. Input range is NC: These pins could be left open or connect to ground. CS 24 I LVTTL SCLK 25 I LVTTL SDO 26 OZ LVTTL SDI 27 I LVTTL MMD1 MMD0 1 28 I LVTTL OSCI 22 I LVTTL CS: Chip Select (Active Low) In 4-wire SPI mode, this pin must be driven from high to low for each read/ write operation, and maintain low for the entire operation. In 3-wire SPI mode, this pin must be low all the time. Refer to section 4.1. SCLK: Serial Clock This pin is used as the clock for the SPI interface. Data on SDI is shifted into the chip on the rising edge of SCLK while data on SDO is shifted out of the chip on the falling edge of SCLK. SDO: Serial Data Output This pin is used as the data output for the SPI interface. Data on this pin is shifted out of the chip on the falling edge of SCLK. SDI: Serial Data Input This pin is used as the data input for the SPI interface. Address and data on this pin is shifted into the chip on the rising edge of SCLK. MMD1/0: Metering Mode Configuration 00: anti-tampering mode (larger power); 01: L line mode (fixed L line); 10: L+N mode (applicable for single-phase three-wire system); 11: flexible mode (line specified by the LNSel bit (MMode, 2BH)) OSCI: External Crystal Input An 8.192 MHz crystal is connected between OSCI and OSCO. There is an on-chip 10pF capacitor, therefore no need of external capacitors. M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 8 Table-1 Pin Description (Continued) Name Pin No. OSCO 23 CF1 18 I/O note 1 Type O LVTTL O LVTTL Description OSCO: External Crystal Output An 8.192 MHz crystal is connected between OSCI and OSCO. There is an on-chip 10pF capacitor, therefore no need of external capacitors. CF1: Active Energy Pulse Output This pin outputs active energy pulses. ZX: Voltage Zero-Crossing Output This pin is asserted when voltage crosses zero. Zero-crossing mode can be ZX 21 O LVTTL configured to positive zero-crossing, negative zero-crossing or all zerocrossing by the Zxcon[1:0] bits (MMode, 2BH). IRQ: Interrupt Output This pin is asserted when one or more events in the SysStatus register IRQ 20 O LVTTL (01H) occur. It is deasserted when there is no bit set in the SysStatus register (01H). WarnOut: Fatal Error Warning WarnOut 17 O LVTTL This pin is asserted when there is metering parameter calibration error or voltage sag. Refer to section 4.2. Note 1: All digital inputs are 5V tolerant except for the OSCI pin. 9 M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 3 FUNCTIONAL DESCRIPTION 3.1 DYNAMIC METERING RANGE Accuracy is 0.1% for active energy metering over a dynamic range of 5000:1 (typical). Refer to Table-2. Table-2 Active Energy Metering Error Current Power Factor 20mA I 50mA 50mA I 100A Error(%) 0.2 1.0 0.1 50mA I 100mA 0.2 0.5 (Inductive) 100mA I 100A 0.8 (Capacitive) 0.1 Note: Shunt resistor is 250 or CT ratio is 1000:1 and load resistor is 6. 3.2 STARTUP AND NO-LOAD POWER Startup and no-load power thresholds are programmable. The related registers are listed in Table-3. Table-3 Threshold Configuration for Startup and No-Load Power Threshold Register Threshold for Active Startup Power Threshold for Active No-load Power PStartTh, 27H PNolTh, 28H The chip will start within 1.2 times of the theoretical startup time of the configured startup power, if startup power is less than the corresponding power of 20mA when power factor or sin is 1.0. The chip has no-load status bits, the Pnoload bit (EnStatus, 46H). The chip will not output any active pulse (CF1) in active no-load state. 3.3 ENERGY REGISTERS The M90E25 provides energy pulse output CF1 which is proportionate to active energy. Energy is usually accumulated by adding the CF1 pulses in system applications. Alternatively, the M90E25 provides energy registers. There are forward (inductive), reverse (capacitive) and absolute energy registers. Refer to Table-4. Table-4 Energy Registers Energy Register Forward Active Energy Reverse Active Energy Absolute Active Energy APenergy, 40H ANenergy, 41H ATenergy, 42H Each energy register is cleared after read. The resolution of energy registers is 0.1CF, i.e. one LSB represents 0.1 energy pulse. M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 10 3.4 N LINE METERING AND ANTI-TAMPERING 3.4.1 METERING MODE AND L/N LINE CURRENT SAMPLING GAIN CONFIGURATION The M90E25 has two current sampling circuits with N line metering and anti-tampering functions. The MMD1 and MMD0 pins are used to configure the metering mode. Refer to Table-5. Table-5 Metering Mode MMD1 MMD0 0 0 0 1 1 0 1 1 Metering Mode Anti-tampering Mode (larger power) L Line Mode (fixed L line) L+N Mode (applicable for single-phase threewire system) Flexible Mode (line specified by the LNSel bit (MMode, 2BH)) CF1 Output CF1 represents the larger energy line. Refer to section 3.4.2. CF1 represents L line energy all the time. CF1 represents the arithmetic sum of L line and N line energy CF1 represents energy of the specified line. The M90E25 has two current sampling circuits with different gain configurations. L line gain can be 1, 4, 8, 16 and 24, and N line gain can be 1, 2 and 4. The configuration is made by the MMode register (2BH). Generally L line can be sampled over shunt resistor or CT. N line can be sampled over CT for isolation consideration. Note that Rogowski coil is not supported. 3.4.2 ANTI-TAMPERING MODE Threshold In anti-tampering mode, the power difference threshold between L line and N line can be: 1%, 2%,... 12%, 12.5%, 6.25%, 3.125% and 1.5625%, altogether 16 choices. The configuration is made by the Pthresh[3:0] bits (MMode, 2BH) and the default value is 3.125%. Compare Method In anti-tampering mode, the compare method is as follows: If current metering line is L line and N Line Active Power - L Line Active Power * 100% > Threshold L Line Active Power N line is switched as the metering line, otherwise L line keeps as the metering line. If current metering line is N line and L Line Active Power - N Line Active Power * 100% > Threshold N Line Active Power L line is switched as the metering line, otherwise N line keeps as the metering line. This method can achieve hysteresis around the threshold automatically. L line is employed after reset by default. Special Treatment at Low Power When power is low, general factors such as the quantization error or calibration difference between L line and N line might cause the power difference to be exceeded. To ensure L line and N line to start up normally, special treatment as follows is adopted: The line with higher power is selected as the metering line when both L line and N line power are lower than 8 times of the startup power but higher than the startup power. 11 M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 3.5 MEASUREMENT AND ZERO-CROSSING 3.5.1 MEASUREMENT The M90E25 has the following measurements: * voltage rms * current rms (L line/N line) * mean active power (L line/N line) * voltage frequency * power factor (L line/N line) * phase angle between voltage and current (L line/N line) * mean apparent power (L line/N line) The above measurements are all calculated with fiducial error except for frequency. The frequency accuracy is 0.01Hz, and the other measurement accuracy is 0.5%. Fiducial error is calculated as follow: Fiducial_E rror = U mea - U real * 100% U FV Where Umea is the measured voltage, Ureal is the actual voltage and UFV is the fiducial value. Table-6 The Measurement Format Measurement Voltage rms note 1, note 2 Current rms Active Power note 1 Apparent Power Frequency Fiducial Value (FV) M90E25 Defined Format Range Un Imax as 4Ib maximum power as Un*4Ib XXX.XX 0~655.35V XX.XXX 0~65.535A XX.XXX -32.768~+32.767 kW Complement, MSB as the sign bit Un*4Ib XX.XXX 0~+32.767 kVA Complement, MSB always '0' fn XX.XX 45.00~65.00 Hz 1.000 X.XXX -1.000~+1.000 note 1 note 3 Power Factor Comment Signed, MSB as the sign bit note 4 180 XXX.X -180~+180 Signed, MSB as the sign bit Phase Angle Note 1: All registers are of 16 bits. For cases when the current and active/apparent power goes beyond the above range, it is suggested to be handled by microcontroller (MCU) in application. For example, register value can be calibrated to 1/2 of the actual value during calibration, then multiply 2 in application. Note that if the actual current is twice of that of the M90E25, the actual active/apparent power is also twice of that of the chip. Note 2: The accuracy is not guaranteed when the current is lower than 15mA. Note that the tolerance is 25 mA at IFV of 5A and fiducial accuracy of 0.5%. Note 3: Power factor is obtained by active power dividing apparent power Note 4: Phase angle is obtained when voltage/current crosses zero at the frequency of 256kHz. Precision is not guaranteed at small current. 3.5.2 ZERO-CROSSING The ZX pin is asserted when the sampling voltage crosses zero. Zero-crossing mode can be configured to positive zerocrossing, negative zero-crossing and all zero-crossing by the Zxcon[1:0] bits (MMode, 2BH). Refer to section 6.4. The zero-crossing signal can facilitate operations such as relay operation and power line carrier transmission in typical smart meter applications. M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 12 3.6 CALIBRATION Calibration includes metering and measurement calibration. Metering Calibration The M90E25 design methodology guarantees the accuracy over the entire dynamic range, after metering calibration at one specific current, i.e. the basic current of Ib. The calibration procedure includes the following steps: 1. Calibrate gain at unity power factor; 2. Calibrate phase angle compensation at 0.5 inductive power factor. Generally, line current sampling is susceptible to the circuits around the sensor when shunt resistor is employed as the current sensor in L line. For example, the transformer in the energy meter's power supply may conduct interference to the shunt resistor. Such interference will cause perceptible metering error, especially at low current conditions. The total interfere is at a statistically constant level. In this case, the M90E25 provides the power offset compensation feature to improve metering performance. L line and N line need to be calibrated sequentially. Measurement Calibration Measurement calibration includes gain calibration for voltage rms and current rms. Considering the possible nonlinearity around zero caused by external components, the M90E25 also provides offset compensation for voltage rms, current rms and mean active power. The M90E25 design methodology guarantees automatic calibration for frequency, phase angle and power factor measurement. 13 M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 3.7 RESET The M90E25 has an on-chip power supply monitor circuit with built-in hysteresis. The M90E25 only works within the voltage range. The M90E25 has three means of reset: power-on reset, hardware reset and software reset. All registers resume to their default value after reset. Power-on Reset: Power-on reset is initiated during power-up. Refer to section 6.3. Hardware Reset: Hardware Reset is initiated when the reset pin is pulled low. The width of the reset signal should be over 200s. Software Reset: Software Reset is initiated when `789AH' is written to the software reset register (SoftReset, 00H). M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 14 4 INTERFACE 4.1 SERIAL PERIPHERAL INTERFACE (SPI) SPI is a full-duplex, synchronous channel. There are two SPI modes: four-wire mode and three-wire mode. In four-wire mode, four pins are used: CS, SCLK, SDI and SDO. In three-wire mode, three pins are used: SCLK, SDI and SDO. Data on SDI is shifted into the chip on the rising edge of SCLK while data on SDO is shifted out of the chip on the falling edge of SCLK. The LastSPIData register (06H) stores the 16-bit data that is just read or written. 4.1.1 FOUR-WIRE MODE In four-wire mode, the CS pin must be driven low for the entire read or write operation. The first bit on SDI defines the access type and the lower 7-bit is decoded as address. Read Sequence As shown in Figure-3, a read operation is initiated by a high on SDI followed by a 7-bit register address. A 16-bit data in this register is then shifted out of the chip on SDO. A complete read operation contains 24 cycles. CS 1 2 3 4 5 6 7 8 A1 A0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK Register Address SDI A6 A5 A4 A3 A2 16-bit data High Impedance SDO Don't care D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure-3 Read Sequence in Four-Wire Mode Write Sequence As shown in Figure-4, a write operation is initiated by a low on SDI followed by a 7-bit register address. A 16-bit data is then shifted into the chip on SDI. A complete write operation contains 24 cycles. CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK Register Address SDI A6 A5 A4 A3 SDO A2 A1 16-bit data A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 High Impedance Figure-4 Write Sequence in Four-Wire Mode 15 M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 D5 D4 D3 D2 D1 D0 4.1.2 THREE-WIRE MODE In three-wire mode, CS is always at low level. When there is no operation, SCLK keeps at high level. The start of a read or write operation is triggered if SCLK is consistently low for at least 400s. The subsequent read or write operation is similar to that in four-wire mode. Refer to Figure-5 and Figure-6. CS Drive Low 1 SCLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 Low 400s Low 400s Register address SDI Don't care A6 A5 A4 A3 A2 A1 Don't care A0 16-bit data Hign Impedance SDO A6 D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 23 24 A5 A4 3 4 High Impedance Figure-5 Read Sequence in Three-Wire Mode CS Drive low 1 SCLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SDO 17 18 19 20 21 22 Don't care 1 2 Low 400s Register Address SDI 16 Low 400s A6 A5 A4 A3 A2 A1 16-bit data A0 D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Don't care A6 A5 A4 High Impedance Figure-6 Write Sequence in Three-Wire Mode M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 16 4.1.3 TIMEOUT AND PROTECTION Timeout occurs if SCLK does not toggle for 6ms in both four-wire and three-wire modes. When timeout, the read or write operation is aborted. If there are more than 24 SCLK cycles when CS is driven low in four-wire mode or between two starts in three-wire mode, writing operation is prohibited while normal reading operation can be completed by taking the first 24 SCLK cycles as the valid ones. However, the reading result might not be the intended one. A read access to an invalid address returns all zero. A write access to an invalid address is discarded. Table-7 and Table-8 list the read or write result in different conditions. Table-7 Read / Write Result in Four-Wire Mode Condition Operation Timeout Read Write Result note 1 SCLK Cycles Read/Write Status LastSPIData Register Update Normal Read Yes - note 2 - note 2 <24 Partial Read No No =24 Normal Write Yes No !=24 No Write No Yes - No Write No >=24 Note 1: The number of SCLK cycles when CS is driven low or the number of SCLK cycles before timeout if any. Note 2: '-' stands for Don't Care. Table-8 Read / Write Result in Three-Wire Mode Condition Operation Read Result note 1 Timeout SCLK Cycles No >=24 note 2 Read/Write Status LastSPIData Register Update Normal Read Yes Timeout after 24 cycles >24 Normal Read Yes Timeout before 24 cycles note 3 Partial Read No Timeout at 24 cycles =24 Normal Read Yes No =24 Normal Write Yes No !=24 No Write No Yes - No Write No Write - Note 1: The number of SCLK cycles between 2 starts or the number of SCLK cycles before timeout if any. Note 2: There is no such case of less than 24 SCLK cycles when there is no timeout in three-wire mode, because the first few SCLK cycles in the next operation is counted into this operation. In this case, data is corrupted. Note 3: '-' stands for Don't Care. 17 M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 4.2 WARNOUT PIN FOR FATAL ERROR WARNING Fatal error warning is raised through the WarnOut pin in two cases: checksum calibration error and voltage sag. Calibration Error The M90E25 performs diagnosis on a regular basis for important parameters such as calibration parameters and metering configuration. When checksum is not correct, the CalErr[1:0] bits (SysStatus, 01H) are set, and both the WarnOut pin and the IRQ pin are asserted. When checksum is not correct, the metering part does not work to prevent a large number of pulses during power-on or any abnormal situation upon incorrect parameters. Voltage Sag Voltage sag is detected when voltage is continuously below the voltage sag threshold for one cycle which starts from any zero-crossing point. Voltage threshold is configured by the SagTh register (03H). Refer to section 6.5. When voltage sag occurs, the SagWarn bit (SysStatus, 01H) is set and the WarnOut pin is asserted if the FuncEn register (02H) enables voltage sag warning through the WarnOut pin. This function helps reduce power-down detection circuit in system design. In addition, the method of judging voltage sag by detecting AC side voltage eliminates the influence of large capacitor in traditional rectifier circuit, and can detect voltage sag earlier. 4.3 LOW COST IMPLEMENTATION IN ISOLATION WITH MCU The following functions can be achieved at low cost when the M90E25 is isolated from the MCU: SPI: MCU can perform read and write operations through low speed optocoupler (e.g. PS2501) when the M90E25 is isolated from the MCU. The SPI interface can be of 3-wire or 4-wire. Energy Pulses CF1: Energy can be accumulated by reading values in corresponding energy registers. CF1 can also connect to the optocoupler and the energy pulse light can be turned on by CF1. Fatal Error WarnOut: Fatal error can be acquired by reading the CalErr[1:0] bits (SysStatus, 01H). IRQ: IRQ interrupt can be acquired by reading the SysStatus register (01H). Reset: The M90E25 is reset when `789AH' is written to the software reset register (SoftReset, 00H). M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 18 5 REGISTER 5.1 REGISTER LIST Table-9 Register List Register Address Register Name Read/Write Type Functional Description Page Status and Special Register 00H SoftReset W Software Reset P 21 01H SysStatus R/C System Status P 22 02H FuncEn R/W Function Enable P 23 03H SagTh R/W Voltage Sag Threshold P 23 04H SmallPMod R/W Small-Power Mode P 24 06H LastSPIData R Last Read/Write SPI Value P 24 20H CalStart R/W Calibration Start Command P 25 21H PLconstH R/W High Word of PL_Constant P 25 22H PLconstL R/W Low Word of PL_Constant P 26 23H Lgain R/W L Line Calibration Gain P 26 24H Lphi R/W L Line Calibration Angle P 26 25H Ngain R/W N Line Calibration Gain P 27 26H Nphi R/W N Line Calibration Angle P 27 Metering Calibration and Configuration Register 27H PStartTh R/W Active Startup Power Threshold P 27 28H PNolTh R/W Active No-Load Power Threshold P 28 2BH MMode R/W Metering Mode Configuration P 29 2CH CS1 R/W Checksum 1 P 31 30H AdjStart R/W Measurement Calibration Start Command P 32 31H Ugain R/W Voltage rms Gain P 32 32H IgainL R/W L Line Current rms Gain P 33 Measurement Calibration Register 33H IgainN R/W N Line Current rms Gain P 33 34H Uoffset R/W Voltage Offset P 33 35H IoffsetL R/W L Line Current Offset P 34 36H IoffsetN R/W N Line Current Offset P 34 37H PoffsetL R/W L Line Active Power Offset P 34 39H PoffsetN R/W N Line Active Power Offset P 35 3BH CS2 R/W Checksum 2 P 36 Energy Register 40H APenergy R/C Forward Active Energy P 37 41H ANenergy R/C Reverse Active Energy P 38 42H ATenergy R/C Absolute Active Energy P 38 46H EnStatus R Metering Status P 39 48H Irms R L Line Current rms P 40 Measurement Register 19 49H Urms R Voltage rms P 40 4AH Pmean R L Line Mean Active Power P 41 4CH Freq R Voltage Frequency P 41 M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 Table-9 Register List (Continued) Register Address Register Name Read/Write Type Functional Description Page 4DH PowerF R L Line Power Factor P 42 4EH Pangle R Phase Angle between Voltage and L Line Current P 42 4FH Smean R L Line Mean Apparent Power P 43 68H Irms2 R N Line Current rms P 43 6AH Pmean2 R N Line Mean Active Power P 44 6DH PowerF2 R N Line Power Factor P 44 6EH Pangle2 R Phase Angle between Voltage and N Line Current P 45 6FH Smean2 R N Line Mean Apparent Power P 45 M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 20 5.2 STATUS AND SPECIAL REGISTER SoftReset Software Reset Address: 00H Type: Write Default Value: 0000H 15 14 13 12 11 10 9 8 SoftReset15 SoftReset14 SoftReset13 SoftReset12 SoftReset11 SoftReset10 SoftReset9 SoftReset8 7 6 5 4 3 2 1 0 SoftReset7 SoftReset6 SoftReset5 SoftReset4 SoftReset3 SoftReset2 SoftReset1 SoftReset0 Bit 15 - 0 21 Name SoftReset[15:0] Description Software reset register. The XXXXXX resets if only 789AH is written to this register. M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 SysStatus System Status Address: 01H Type: Read/Clear Default Value: 0000H 15 14 13 12 11 10 9 8 CalErr1 CalErr0 AdjErr1 AdjErr0 - - - - 7 6 5 4 3 2 1 0 LNchange - RevPchg - - - SagWarn - Bit Name Description 15 - 14 CalErr[1:0] These bits indicate CS1 checksum status. 00: CS1 checksum correct (default) 11: CS1 checksum error. At the same time, the WarnOut pin is asserted. 13 - 12 AdjErr[1:0] These bits indicate CS2 checksum status. 00: CS2 checksum correct (default) 11: CS2 checksum error. 11 - 8 - 7 LNchange 6 - 5 RevPchg 4-2 - 1 SagWarn 0 - Reserved. This bit indicates whether there is any change of the metering line (L line and N line). 0: metering line no change (default) 1: metering line changed Reserved. This bit indicates whether there is any change with the direction of active energy. 0: direction of active energy no change (default) 1: direction of active energy changed This status is enabled by the RevPEn bit (FuncEn, 02H). Reserved. This bit indicates the voltage sag status. 0: no voltage sag (default) 1: voltage sag Voltage sag is enabled by the SagEn bit (FuncEn, 02H). Voltage sag status can also be reported by the WarnOut pin. It is enabled by the SagWo bit(FuncEn, 02H). Reserved. Note: Any of the above events will prompt the IRQ pin to be asserted, which can be supplied to external MCU as an interrupt. M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 22 FuncEn Function Enable Address: 02H Type: Read/Write Default Value: 000CH 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - SagEn SagWo - RevPEn - - Bit 15 - 6 Name - Description 5 SagEn This bit determines whether to enable the voltage sag interrupt. 0: disable (default) 1: enable 4 SagWo This bit determines whether to enable voltage sag to be reported by the WarnOut pin. 0: disable (default) 1: enable 3 - 2 RevPEn 1-0 - Reserved. Reserved. This bit determines whether to enable the direction change interrupt of active energy. 0: disable 1: enable (default) Reserved. SagTh Voltage Sag Threshold Address: 03H Type: Read/Write Default Value: 1D6AH 15 14 13 12 11 10 9 8 SagTh15 SagTh14 SagTh13 SagTh12 SagTh11 SagTh10 SagTh9 SagTh8 7 6 5 4 3 2 1 0 SagTh7 SagTh6 SagTh5 SagTh4 SagTh3 SagTh2 SagTh1 SagTh0 Bit 15 - 0 23 Name Description Voltage sag threshold configuration. Data format is XXX.XX. Unit is V. SagTh[15:0] The power-on value of SagTh is 1D6AH, which is calculated by 22000*sqrt(2)*0.78/(4*Ugain/32768) For details, please refer to application note 46101. M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 SmallPMod Small-Power Mode Address: 04H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 SmallPMod1 5 SmallPMod1 4 SmallPMod1 3 SmallPMod1 2 SmallPMod1 1 SmallPMod1 0 SmallPMod9 SmallPMod8 7 6 5 4 3 2 1 0 SmallPMod7 SmallPMod6 SmallPMod5 SmallPMod4 SmallPMod3 SmallPMod2 SmallPMod1 SmallPMod0 Bit 15 - 0 Name Description SmallPMod[15:0] Small-power mode command. A987H: small-power mode. The relationship between the register value of L line and N line active power in small-power mode and normal mode is: power in normal mode = power in small-power mode *10*Igain*Ugain /2^42 Others: Normal mode. Small-power mode is mainly used in the power offset calibration. LastSPIData Last Read/Write SPI Value Address: 06H Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 LastSPIData1 5 LastSPIData1 4 LastSPIData1 3 LastSPIData1 2 LastSPIData1 1 LastSPIData1 0 LastSPIData9 LastSPIData8 7 6 5 4 3 2 1 0 LastSPIData7 LastSPIData6 LastSPIData5 LastSPIData4 LastSPIData3 LastSPIData2 LastSPIData1 LastSPIData0 Bit 15 - 0 Name LastSPIData[15:0] Description This register stores the data that is just read or written through the SPI interface. Refer to Table-7 and Table-8. M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 24 5.3 METERING/ MEASUREMENT CALIBRATION AND CONFIGURATION 5.3.1 METERING CALIBRATION AND CONFIGURATION REGISTER CalStart Calibration Start Command Address: 20H Type: Read/Write Default Value: 6886H 15 14 13 12 11 10 9 8 CalStart15 CalStart14 CalStart13 CalStart12 CalStart11 CalStart10 CalStart9 CalStart8 7 6 5 4 3 2 1 0 CalStart7 CalStart6 CalStart5 CalStart4 CalStart3 CalStart2 CalStart1 CalStart0 Bit Name 15 - 0 Description Metering calibration start command: 6886H: Power-on value. Metering function is disabled. 5678H: Metering calibration startup command. After 5678H is written to this register, registers 21H-2BH resume to their power-on values. The M90E25 starts to meter and output energy pulses regardless of the correctness of diagnosis. The CalErr[1:0] bits (SysStatus, 01H) are not set and the WarnOut/ CalStart[15:0] IRQ pins do not report any warning/interrupt. 8765H: Check the correctness of the 21H-2BH registers. If correct, normal metering. If not correct, metering function is disabled, the CalErr[1:0] bits (SysStatus, 01H) are set and the WarnOut/IRQ pins report warning/interrupt. Others: Metering function is disabled. The CalErr[1:0] bits (SysStatus, 01H) are set and the WarnOut/IRQ pins report warning/interrupt. PLconstH High Word of PL_Constant Address: 21H Type: Read/Write Default Value: 0015H 15 14 13 12 11 10 9 8 PLconstH15 PLconstH14 PLconstH13 PLconstH12 PLconstH11 PLconstH10 PLconstH9 PLconstH8 7 6 5 4 3 2 1 0 PLconstH7 PLconstH6 PLconstH5 PLconstH4 PLconstH3 PLconstH2 PLconstH1 PLconstH0 Bit 15 - 0 25 Name Description PLconstH[15:0] The PLconstH[15:0] and PLconstL[15:0] bits are high word and low word of PL_Constant respectively. PL_Constant is a constant which is proportional to the sampling ratios of voltage and current, and inversely proportional to the Meter Constant. PL_Constant is a threshold for energy calculated inside the chip, i.e., energy larger than PL_Constant will be accumulated in the corresponding energy registers and then output on CF1. It is suggested to set PL_constant as a multiple of 4 so as to double or redouble Meter Constant in low current state to save verification time. Note: PLconstH takes effect after PLconstL are configured. For details, please refer to application note 46101. M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 PLconstL Low Word of PL_Constant Address: 22H Type: Read/Write Default Value: D174H 15 14 13 12 11 10 9 8 PLconstL15 PLconstL14 PLconstL13 PLconstL12 PLconstL11 PLconstL10 PLconstL9 PLconstL8 7 6 5 4 3 2 1 0 PLconstL7 PLconstL6 PLconstL5 PLconstL4 PLconstL3 PLconstL2 PLconstL1 PLconstL0 Bit 15 - 0 Name PLconstL[15:0] Description The PLconstH[15:0] and PLconstL[15:0] bits are high word and low word of PL_Constant respectively. It is suggested to set PL_constant as a multiple of 4. For details, please refer to application note 46101. Lgain L Line Calibration Gain Address: 23H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 Lgain15 Lgain14 Lgain13 Lgain12 Lgain11 Lgain10 Lgain9 Lgain8 7 6 5 4 3 2 1 0 Lgain7 Lgain6 Lgain5 Lgain4 Lgain3 Lgain2 Lgain1 Lgain0 Bit 15 - 0 Name Lgain[15:0] Description L line calibration gain. For details, please refer to application note 46101. Lphi L Line Calibration Angle Address: 24H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 Lphi15 - - - - - Lphi9 Lphi8 7 6 5 4 3 2 1 0 Lphi7 Lphi6 Lphi5 Lphi4 Lphi3 Lphi2 Lphi1 Lphi0 Bit 15 - 0 Name Lphi[15:0] Description L line calibration phase angle. For details, please refer to application note 46101. M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 26 Ngain N Line Calibration Gain Address: 25H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 Ngain15 Ngain14 Ngain13 Ngain12 Ngain11 Ngain10 Ngain9 Ngain8 7 6 5 4 3 2 1 0 Ngain7 Ngain6 Ngain5 Ngain4 Ngain3 Ngain2 Ngain1 Ngain0 Bit 15 - 0 Name Ngain[15:0] Description N line calibration gain. For details, please refer to application note 46101. Nphi N Line Calibration Angle Address: 26H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 Nphi15 - - - - - Nphi9 Nphi8 7 6 5 4 3 2 1 0 Nphi7 Nphi6 Nphi5 Nphi4 Nphi3 Nphi2 Nphi1 Nphi0 Bit 15 - 0 Name Nphi[15:0] Description N line calibration phase angle. For details, please refer to application note 46101. PStartTh Active Startup Power Threshold Address: 27H Type: Read/Write Default Value: 08BDH 15 14 13 12 11 10 9 8 PStartTh15 PStartTh14 PStartTh13 PStartTh12 PStartTh11 PStartTh10 PStartTh9 PStartTh8 7 6 5 4 3 2 1 0 PStartTh7 PStartTh6 PStartTh5 PStartTh4 PStartTh3 PStartTh2 PStartTh1 PStartTh0 Bit 15 - 0 27 Name Description PStartTh[15:0 ] Active startup power threshold. For details, please refer to application note 46101. M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 PNolTh Active No-Load Power Threshold Address: 28H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 PNolTh15 PNolTh14 PNolTh13 PNolTh12 PNolTh11 PNolTh10 PNolTh9 PNolTh8 7 6 5 4 3 2 1 0 PNolTh7 PNolTh6 PNolTh5 PNolTh4 PNolTh3 PNolTh2 PNolTh1 PNolTh0 Bit 15 - 0 Name Description PNolTh[15:0] Active no-load power threshold. For details, please refer to application note 46101. M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 28 MMode Metering Mode Configuration Address: 2BH Type: Read/Write Default Value: 9422H 15 14 13 12 11 10 9 8 Lgain2 Lgain1 Lgain0 Ngain1 Ngain0 LNSel DisHPF1 DisHPF0 7 6 5 4 3 2 1 0 Amod - ZXCon1 ZXCon0 Pthresh3 Pthresh2 Pthresh1 Pthresh0 Bit Name Description L line current gain, default value is `100'. 15 - 13 12 - 11 10 Lgain2 1 0 0 0 0 Lgain[2:0] Ngain[1:0] LNSel Lgain1 X 0 0 1 1 Lgain0 X 0 1 0 1 Current Channel Gain 1 4 8 16 24 N line current gain 00: 2 01: 4 10: 1 (default) 11: 1 This bit specifies metering as L line or N line when metering mode is set to flexible mode by MMD1 and MMD0 pins. 0: N line 1: L line (default) These bits configure the High Filter Pass (HPF) after ADC. There are two first-order HPF in serial: HPF1 and HPF0. The configuration are applicable to all channels: 9-8 29 DisHPF[1:0] 7 Amod 6 - DisHPF1 DisHPF 0 0 0 1 1 0 1 0 1 CF1 output for active power: 0: forward or reverse energy pulse output (default) 1: absolute energy pulse output Reserved. M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 HPF Configuration enable HPF1 and HPF0 (default) enable HPF1, disable HPF0; disable HPF1, enable HPF0; disable HPF1 and HPF0 5-4 Zxcon[1:0] These bits configure zero-crossing mode. The ZX pin outputs 5ms-width high level when voltage crosses zero. 00: positive zero-crossing 01: negative zero-crossing 10: all zero-crossing: both positive and negative zero-crossing (default) 11: no zero-crossing output These bits configure the L line and N line power difference threshold in anti-tampering mode. 3-0 Pthresh[3:0] Pthresh 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Pthresh 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Pthresh 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Pthresh0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Threshold 12.5% 6.25% 3.125% (default) 1.5625% 1% 2% 3% 4% 5% 6% 7% 8% 9% 10% 11% 12% M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 30 CS1 Checksum 1 Address: 2CH Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 CS1_15 CS1_14 CS1_13 CS1_12 CS1_11 CS1_10 CS1_9 CS1_8 7 6 5 4 3 2 1 0 CS1_7 CS1_6 CS1_5 CS1_4 CS1_3 CS1_2 CS1_1 CS1_0 Bit Name Description The CS1 register should be written after the 21H-2BH registers are written. Suppose the high byte and the low byte of the 21H-2BH registers are shown in below table. 15 - 0 Register Address 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH CS1[15:0] High Byte H21 H22 H23 H24 H25 H26 H27 H28 H29 H2A H2B Low Byte L21 L22 L23 L24 L25 L26 L27 L28 L29 L2A L2B The calculation of the CS1 register is as follows: The low byte of 2CH register is: L2C=MOD(H21+H22+...+H2B+L21+L22+...+L2B, 2^8) The high byte of 2CH register is: H2C=H21 XOR H22 XOR ... XOR H2B XOR L21 XOR L22 XOR ... XOR L2B A part of registers are not used. These registers can be dealed as 0000H in CS calculation. The M90E25 calculates CS1 regularly. If the value of the CS1 register and the calculation by the M90E25 is different when CalStart=8765H, the CalErr[1:0] bits (SysStatus, 01H) are set and the WarnOut and IRQ pins are asserted. Note: The readout value of the CS1 register is the calculation by the M90E25, which is different from what is written. 31 M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 5.3.2 MEASUREMENT CALIBRATION REGISTER AdjStart Measurement Calibration Start Command Address: 30H Type: Read/Write Default Value: 6886H 15 14 13 12 11 10 9 8 AdjStart15 AdjStart14 AdjStart13 AdjStart12 AdjStart11 AdjStart10 AdjStart9 AdjStart8 7 6 5 4 3 2 1 0 AdjStart7 AdjStart6 AdjStart5 AdjStart4 AdjStart3 AdjStart2 AdjStart1 AdjStart0 Bit Name 15 - 0 Description Measurement Calibration Start Command 6886H: Power-on value. No measurement. 5678H: Measurement calibration startup command. After 5678H is written to this register, registers 31H3AH resume to their power-on values. The M90E25 starts to measure regardless of the correctness of diagnosis. The AdjErr[1:0] bits (SysStatus, 01H) are not set and the IRQ pin does not AdjStart[15:0] report any interrupt. 8765H: Check the correctness of the 31H-3AH registers. If correct, normal measurement. If not correct, measurement function is disabled, the AdjErr[1:0] bits (SysStatus, 01H) are set and the IRQ pin reports interrupt. Others: No measurement. The AdjErr[1:0] bits (SysStatus, 01H) are set and the IRQ pin reports interrupt. Ugain Voltage rms Gain Address: 31H Type: Read/Write Default Value: 6720H 15 14 13 12 11 10 9 8 Ugain15 Ugain14 Ugain13 Ugain12 Ugain11 Ugain10 Ugain9 Ugain8 7 6 5 4 3 2 1 0 Ugain7 Ugain6 Ugain5 Ugain4 Ugain3 Ugain2 Ugain1 Ugain0 Bit Name 15 - 0 Ugain[15:0] Description Voltage rms Gain. For details, please refer to application note 46101. Note: the Ugain15 bit should only be '0' M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 32 IgainL L Line Current rms Gain Address: 32H Type: Read/Write Default Value: 7A13H 15 14 13 12 11 10 9 8 IgainL15 IgainL14 IgainL13 IgainL12 IgainL11 IgainL10 IgainL9 IgainL8 7 6 5 4 3 2 1 0 IgainL7 IgainL6 IgainL5 IgainL4 IgainL3 IgainL2 IgainL1 IgainL0 Bit 15 - 0 Name IgainL[15:0] Description L Line Current rms Gain, For details, please refer to application note 46101. IgainN N Line Current rms Gain Address: 33H Type: Read/Write Default Value: 7530H 15 14 13 12 11 10 9 8 IgainN15 IgainN14 IgainN13 IgainN12 IgainN11 IgainN10 IgainN9 IgainN8 7 6 5 4 3 2 1 0 IgainN7 IgainN6 IgainN5 IgainN4 IgainN3 IgainN2 IgainN1 IgainN0 Bit 15 - 0 Name Description IgainN[15:0] N Line Current rms Gain. For details, please refer to application note 46101. Uoffset Voltage Offset Address: 34H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 Uoffset15 Uoffset14 Uoffset13 Uoffset12 Uoffset11 Uoffset10 Uoffset9 Uoffset8 7 6 5 4 3 2 1 0 Uoffset7 Uoffset6 Uoffset5 Uoffset4 Uoffset3 Uoffset2 Uoffset1 Uoffset0 Bit 15 - 0 33 Name Description Uoffset[15:0] Voltage offset. For calculation method, please refer to application note 46101. M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 IoffsetL L Line Current Offset Address: 35H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 IoffsetL15 IoffsetL14 IoffsetL13 IoffsetL12 IoffsetL11 IoffsetL10 IoffsetL9 IoffsetL8 7 6 5 4 3 2 1 0 IoffsetL7 IoffsetL6 IoffsetL5 IoffsetL4 IoffsetL3 IoffsetL2 IoffsetL1 IoffsetL0 Bit 15 - 0 Name Description IoffsetL[15:0] L line current offset. For calculation method, please refer to application note 46101. IoffsetN N Line Current Offset Address: 36H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 IoffsetN15 IoffsetN14 IoffsetN13 IoffsetN12 IoffsetN11 IoffsetN10 IoffsetN9 IoffsetN8 7 6 5 4 3 2 1 0 IoffsetN7 IoffsetN6 IoffsetN5 IoffsetN4 IoffsetN3 IoffsetN2 IoffsetN1 IoffsetN0 Bit 15 - 0 Name Description IoffsetN[15:0] N line current offset. For calculation method, please refer to application note 46101. PoffsetL L Line Active Power Offset Address: 37H Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 PoffsetL15 PoffsetL14 PoffsetL13 PoffsetL12 PoffsetL11 PoffsetL10 PoffsetL9 PoffsetL8 7 6 5 4 3 2 1 0 PoffsetL7 PoffsetL6 PoffsetL5 PoffsetL4 PoffsetL3 PoffsetL2 PoffsetL1 PoffsetL0 Bit Name 15 - 0 PoffsetL[15:0] Description L line active power offset. Complement, MSB is the sign bit. For calculation method, please refer to application note 46101. M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 34 PoffsetN N Line Active Power Offset Address: 39H Type: Read/Write Default Value: 0000H 35 15 14 13 12 11 10 9 8 PoffsetN15 PoffsetN14 PoffsetN13 PoffsetN12 PoffsetN11 PoffsetN10 PoffsetN9 PoffsetN8 7 6 5 4 3 2 1 0 PoffsetN7 PoffsetN6 PoffsetN5 PoffsetN4 PoffsetN3 PoffsetN2 PoffsetN1 PoffsetN0 Bit Name 15 - 0 PoffsetN[15:0] Description N line active power offset. Complement, MSB is the sign bit. For calculation method, please refer to application note 46101. M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 CS2 Checksum 2 Address: 3BH Type: Read/Write Default Value: 0000H 15 14 13 12 11 10 9 8 CS2_15 CS2_14 CS2_13 CS2_12 CS2_11 CS2_10 CS2_9 CS2_8 7 6 5 4 3 2 1 0 CS2_7 CS2_6 CS2_5 CS2_4 CS2_3 CS2_2 CS2_1 CS2_0 Bit Name Description The CS2 register should be written after the 31H-3AH registers are written. Suppose the high byte and the low byte of the 31H-3AH registers are shown in below table. 15 - 0 CS2[15:0] Register Address 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH High Byte H31 H32 H33 H34 H35 H36 H37 H38 H39 H3A Low Byte L31 L32 L33 L34 L35 L36 L37 L38 L39 L3A The calculatiion of the CS2 register is as follows: The low byte of 3BH register is: L3B=MOD(H31+H32+...+H3A+L31+L32+...+L3A, 2^8) The high byte of 3BH register is: H3B=H31 XOR H32 XOR ... XOR H3A XOR L31 XOR L32 XOR ... XOR L3A The M90E25 calculates CS2 regularly. If the value of the CS2 register and the calculation by the M90E25 is different when AdjStart=8765H, the AdjErr[1:0] bits (SysStatus, 01H) are set. Note: The readout value of the CS2 register is the calculation by the XXXXXX, which is different from what is written. M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 36 5.4 ENERGY REGISTER Theory of Energy Registers The internal energy resolution is 0.01 pulse. Within 0.01 pulse, forward and reverse energy are counteracted. When energy exceeds 0.01 pulse, the respective forward/reserve energy is increased. The forward and reverse energy are not counteracted in absolute energy registers. Take the example of active energy, suppose: T0: Forward energy is 12.34 pulses and reverse energy is 1.23 pulses; From T0 to T1: 0.005 forward pulse appeared From T1 to T2: 0.004 reverse pulse appeared From T2 to T3: 0.003 reverse pulse appeared T0 T1 T2 T3 Forward Active Pulse 12.34 12.345 12.341 12.34 Reserve Active Pulse 1.23 1.23 1.23 1.232 Absolute Active Pulse 13.57 13.575 13.579 13.582 When forward/reverse energy or absolute energy reaches 0.1 pulse, the respective register is updated. When forward/reverse energy or absolute energy reaches 1 pulse, the CF1 pins outputs pulse and the REVP/REVQ bits (EnStatus, 46H) are updated. Absolute energy might be more than the sum of forward and reverse energies. If "consistency" is required between absolute energy and forward/reverse energy in system application, absolute energy can be obtained by calculating the readout of the forward and reverse energy registers. APenergy Forward Active Energy Address: 40H Type: Read/Clear Default Value: 0000H 15 14 13 12 11 10 9 8 APenergy15 APenergy14 APenergy13 APenergy12 APenergy11 APenergy10 APenergy9 APenergy8 7 6 5 4 3 2 1 0 APenergy7 APenergy6 APenergy5 APenergy4 APenergy3 APenergy2 APenergy1 APenergy0 Bit 15 - 0 37 Name Description APenergy[15:0] Forward active energy; cleared after read. Data format is XXXX.X pulses. Resolution is 0.1 pulse. Maximum is 6553.5 pulses. When the accumulation of this register has achieved FFFFH, the continuation accumulation will return to 0000H. M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 ANenergy Reverse Active Energy Address: 41H Type: Read/Clear Default Value: 0000H 15 14 13 12 11 10 9 8 ANenergy15 ANenergy14 ANenergy13 ANenergy12 ANenergy11 ANenergy10 ANenergy9 ANenergy8 7 6 5 4 3 2 1 0 ANenergy7 ANenergy6 ANenergy5 ANenergy4 ANenergy3 ANenergy2 ANenergy1 ANenergy0 Bit 15 - 0 Name Description ANenergy[15:0] Reverse active energy, cleared after read. Data format is XXXX.X pulses. Resolution is 0.1 pulse. Maximum is 6553.5 pulses. When the accumulation of this register has achieved FFFFH, the continuation accumulation will return to 0000H. ATenergy Absolute Active Energy Address: 42H Type: Read/Clear Default Value: 0000H 15 14 13 12 11 10 9 8 ATenergy15 ATenergy14 ATenergy13 ATenergy12 ATenergy11 ATenergy10 ATenergy9 ATenergy8 7 6 5 4 3 2 1 0 ATenergy7 ATenergy6 ATenergy5 ATenergy4 ATenergy3 ATenergy2 ATenergy1 ATenergy0 Bit Name Description 15 - 0 ATenergy[15:0] Absolute active energy, cleared after read. Data format is XXXX.X pulses. Resolution is 0.1 pulse. Maximum is 6553.5 pulses. When the accumulation of this register has achieved FFFFH, the continuation accumulation will return to 0000H. M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 38 EnStatus Metering Status Address: 46H Type: Read Default Value After Power On: C800H 15 14 13 12 11 10 9 8 - Pnoload - RevP Lline - - - 7 6 5 4 3 2 1 0 - - - - - - LNMode1 LNMode0 Bit 15 Name - 14 Pnoload 13 - Description Reserved. This bit indicates whether the M90E25 is in active no-load status. 0: not active no-load state 1: active no-load state Reserved. 12 RevP This bit indicates the direction of the last CF1 (active output). 0: active forward 1: active reverse Note: This bit is always '0' when the CF1 output is configured to be absolute energy. 11 Lline This bit indicates the current metering line in anti-tampering mode. 0: N line 1: L line 10 - 2 - Reserved. These bits indicate the configuration of MMD1 and MMD0 pins. Their relationship is as follows: 1-0 39 LNMode[1:0] MMD 1 0 0 MMD 0 0 1 LNmo d1 0 0 LNmo d0 0 1 1 0 1 0 1 1 1 1 M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 L/N Metering Mode anti-tampering mode (larger power) L line mode (fixed L line) L+N mode (applicable for single-phase three-wire system) Flexible mode (Line specified by the LNSel bit (MMode, 2BH)) 5.5 MEASUREMENT REGISTER Irms L Line Current rms Address: 48H Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Irms15 Irms14 Irms13 Irms12 Irms11 Irms10 Irms9 Irms8 7 6 5 4 3 2 1 0 Irms7 Irms6 Irms5 Irms4 Irms3 Irms2 Irms1 Irms0 Bit 15 - 0 Name Description Irms[15:0] L line current rms. Data format is XX.XXX, which corresponds to 0 ~ 65.535A. For cases when the current exceeds 65.535A, it is suggested to be handled by MCU in application. For example, the register value can be calibrated to 1/2 of the actual value during calibration, then multiplied by 2 in application. Urms Voltage rms Address: 49H Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Urms15 Urms14 Urms13 Urms12 Urms11 Urms10 Urms9 Urms8 7 6 5 4 3 2 1 0 Urms7 Urms6 Urms5 Urms4 Urms3 Urms2 Urms1 Urms0 Bit Name 15 - 0 Urms[15:0] Description Voltage rms. Data format is XXX.XX, which corresponds to 0 ~ 655.35V. M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 40 Pmean L Line Mean Active Power Address: 4AH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Pmean15 Pmean14 Pmean13 Pmean12 Pmean11 Pmean10 Pmean9 Pmean8 7 6 5 4 3 2 1 0 Pmean7 Pmean6 Pmean5 Pmean4 Pmean3 Pmean2 Pmean1 Pmean0 Bit Name 15 - 0 Description L line mean active power. Complement, MSB is the sign bit. Data format is XX.XXX, which corresponds to -32.768~+32.768kW. Pmean[15:0] If current is specially handle by MCU, the power of the M90E25 and the actual power have the same multiple relationship as the current. Freq Voltage Frequency Address: 4CH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Freq15 Freq14 Freq13 Freq12 Freq11 Freq10 Freq9 Freq8 7 6 5 4 3 2 1 0 Freq7 Freq6 Freq5 Freq4 Freq3 Freq2 Freq1 Freq0 Bit 15 - 0 41 Name Description Freq[15:0] Voltage frequency. Data format is XX.XX. Frequency measurement range is 45.00~65.00Hz. For example, 1388H corresponds to 50.00Hz. M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 PowerF L Line Power Factor Address: 4DH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 PowerF15 PowerF14 PowerF13 PowerF12 PowerF11 PowerF10 PowerF9 PowerF8 7 6 5 4 3 2 1 0 PowerF7 PowerF6 PowerF5 PowerF4 PowerF3 PowerF2 PowerF1 PowerF0 Bit Name 15 - 0 Description L line power factor. PowerF[15:0] Signed, MSB is the sign bit. Data format is X.XXX. Power factor range: -1.000~+1.000. For example, 03E 8H corresponds to the power factor of 1.000, and 83E8H corresponds to the power factor of -1.000. Pangle Phase Angle between Voltage and L Line Current Address: 4EH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Pangle15 Pangle14 Pangle13 Pangle12 Pangle11 Pangle10 Pangle9 Pangle8 7 6 5 4 3 2 1 0 Pangle7 Pangle6 Pangle5 Pangle4 Pangle3 Pangle2 Pangle1 Pangle0 Bit Name 15 - 0 Pangle[15:0] Description L line voltage current angle. Signed, MSB is the sign bit. Data format is XXX.X. Angle range: -180.0~+180.0 degree. M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 42 Smean L Line Mean Apparent Power Address: 4FH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Smean15 Smean14 Smean13 Smean12 Smean11 Smean10 Smean9 Smean8 7 6 5 4 3 2 1 0 Smean7 Smean6 Smean5 Smean4 Smean3 Smean2 Smean1 Smean0 Bit Name 15 - 0 Description L line mean apparent power. Complement, MSB is always '0'. Data format is XX.XXX, which corresponds to 0~+32.767kVA. Smean[15:0] If current is specially handled by MCU, the power of the M90E25 and the actual power have the same multiple relationship as the current. Irms2 N Line Current rms Address: 68H Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Irms2_15 Irms2_14 Irms2_13 Irms2_12 Irms2_11 Irms2_10 Irms2_9 Irms2_8 7 6 5 4 3 2 1 0 Irms2_7 Irms2_6 Irms2_5 Irms2_4 Irms2_3 Irms2_2 Irms2_1 Irms2_0 Bit 15 - 0 43 Name Description Irms2[15:0] N line current rms. Data format is XX.XXX, which corresponds to 65.535A. For cases when the current exceeds 65.535A, it is suggested to be handled by MCU in application. For example, the register value can be calibrated to 1/2 of the actual value during calibration, then multiplied by 2 in application. M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 Pmean2 N Line Mean Active Power Address: 6AH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Pmean2_15 Pmean2_14 Pmean2_13 Pmean2_12 Pmean2_11 Pmean2_10 Pmean2_9 Pmean2_8 7 6 5 4 3 2 1 0 Pmean2_7 Pmean2_6 Pmean2_5 Pmean2_4 Pmean2_3 Pmean2_2 Pmean2_1 Pmean2_0 Bit Name 15 - 0 Description N line mean active power. Complement, MSB is the sign bit. Data format is XX.XXX, which corresponds to -32.768~+32.767kW. Pmean2[15:0] If current is specially handled by MCU, the power of the M90E25 and the actual power have the same multiple relationship as the current. PowerF2 N Line Power Factor Address: 6DH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 PowerF2_15 PowerF2_14 PowerF2_13 PowerF2_12 PowerF2_11 PowerF2_10 PowerF2_9 PowerF2_8 7 6 5 4 3 2 1 0 PowerF2_7 PowerF2_6 PowerF2_5 PowerF2_4 PowerF2_3 PowerF2_2 PowerF2_1 PowerF2_0 Bit 15 - 0 Name Description N line power factor. PowerF2[15:0 Signed, MSB is the sign bit. Data format is X.XXX. Power factor range: -1.000~+1.000. For example, 03E ] 8H corresponds to the power factor of 1.000, and 83E8H corresponds to the power factor of -1.000. M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 44 Pangle2 Phase Angle between Voltage and N Line Current Address: 6EH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Pangle2_15 Pangle2_14 Pangle2_13 Pangle2_12 Pangle2_11 Pangle2_10 Pangle2_9 Pangle2_8 7 6 5 4 3 2 1 0 Pangle2_7 Pangle2_6 Pangle2_5 Pangle2_4 Pangle2_3 Pangle2_2 Pangle2_1 Pangle2_0 Bit Name 15 - 0 Description N line voltage current angle Pangle2[15:0] Signed, MSB is the sign bit. Data format is XXX.X. Angle range: -180.0~+180.0 degree. Smean2 N Line Mean Apparent Power Address: 6FH Type: Read Default Value: 0000H 15 14 13 12 11 10 9 8 Smean2_15 Smean2_14 Smean2_13 Smean2_12 Smean2_11 Smean2_10 Smean2_9 Smean2_8 7 6 5 4 3 2 1 0 Smean2_7 Smean2_6 Smean2_5 Smean2_4 Smean2_3 Smean2_2 Smean2_1 Smean2_0 Bit 15 - 0 45 Name Description N line mean apparent power Complement, MSB is always '0'. Data format is XX.XXX, which corresponds to 0~+32.767kVA. Smean2[15:0] If current is specially handled by MCU, the power of M90E25 and the actual power have the same multiple relationship as the current. M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 6 ELECTRICAL SPECIFICATION 6.1 ELECTRICAL SPECIFICATION Parameters and Description Min. Typical Max. Unit Test Conditions and Comments % VDD=3.3V0.3V, 100Hz, I=5A, V=220V, L line shunt resistor 150, N line CT 1000:1, sampling resistor 4.8 Accuracy DC Power Supply Rejection Ratio (PSRR) 0.1 AC Power Supply Rejection Ratio (PSRR) 0.1 % VDD=3.3V superimposes 400mVrms, 100Hz Sinusoidal signal, I=5A, V=220V, L line shunt resistor 150, N line CT 1000:1, sampling resistor 4.8 Active Energy Error (Dynamic Range 5000:1) 0.1 % L line current gain is `24'; N line current gain is `1' Channel Characteristics Sampling Frequency 8 kHz L Line Current Channel Equivalent Input Noise 19.1 nV/ Hz Single side band noise (measured at 50Hz, and PGA gain is `24') N Line Current Channel Equivalent Input Noise 458.4 nV/ Hz Single side band noise (measured at 50Hz, and PGA gain is `1') Voltage Channel Equivalent Input Noise 458.4 nV/ Hz Single side band noise (measured at 50Hz, and PGA gain is `1') Total Harmonic Distortion for Each Channel 80 dB Active Energy Metering Bandwidth 4 kHz Irms and Vrms Measurement Bandwidth 4 kHz Measurement Error 0.5 25C, PGA gain is `1', 500mVrms input % Analog Input L Line Current Channel Differential Input 5 25m PGA gain is `24' 7.5 37.5m PGA gain is `16' 15 75m PGA gain is `8' 30 150m PGA gain is `4' 120 600m 30 150m Vrms PGA gain is `1' PGA gain is `4' 60 300m N Line Current Channel Differential Input 120 600m Vrms PGA gain is `1' Voltage Channel Differential Input 120 600m Vrms PGA gain is `1' L Line Current Channel Input Impedance 1 PGA gain is `2' K N Line Current Channel Input Impedance 50 K Voltage Channel Input Impedance 50 K L Line Current Channel DC Offset 10 mV PGA gain is `24' N Line Current Channel DC Offset 10 mV PGA gain is `1' 10 mV PGA gain is `1' Voltage Channel DC Offset Reference On-Chip Reference Reference Voltage Temperature Coefficient 1.398 1.417 15 1.440 V 40 ppm/C Reference voltage test mode Clock Crystal or External Clock 8.192 MHz The Accuracy of crystal or external clock is 100 ppm M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 46 SPI Interface SPI Interface Bit Rate 200 160k bps Pulse Width CF1 Pulse Width 80 ms If T 160 ms, width=80ms; if T<160 ms, width = 0.5T. Refer to Section 6.6 ESD Machine Model (MM) 400 V JESD22-A115 Charged Device Model (CDM) 1000 V JESD22-C101 Human Body Model (HBM) 4000 V JESD22-A114 Latch Up 100 mA JESD78A Latch Up 4.95 V JESD78A Operating Conditions within 2.8 3.3 3.6 V Metering precision 3.0V~3.6V. guaranteed AVDD, Analog Power Supply within 2.8 3.3 3.6 V Metering precision 3.0V~3.6V. guaranteed DVDD, Digital Power Supply IAVDD, Analog Current 3.75 mA L line/ N line current channel and voltage channel are open IDVDD, Digital Current 2.75 mA VDD=3.3V DC Characteristics Digital Input High Level (all digital pins except OSCI) 2.0 VDD+2.6 V VDD=3.3V10%, Digital Input High Level (OSCI) 2.0 VDD+0.3 V VDD=3.3V10% VDD=3.3V10% Digital Input Low Level 0.8 V Digital Input Leakage Current 1 A Digital Output Low Level (CF1) 0.4 V VDD=3.3V, IOL=10mA Digital Output Low Level (IRQ, WarnOut, ZX, SDO) 0.4 V VDD=3.3V, IOL=5mA Digital Output High Level (CF1) 2.4 V VDD=3.3V, IOH=-10mA Digital Output High Level (IRQ, WarnOut, ZX, SDO) 2.4 V VDD=3.3V, IOH=-5mA V VDD=3.3V, IOL=1mA V VDD=3.3V, IOH=-1mA Digital Output Low Level (OSCO) Digital Output High Level (OSCO) 47 VDD=3.6V, VI=VDD or GND M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 0.4 2.4 6.2 SPI INTERFACE TIMING The SPI interface timing is as shown in Figure-7, Figure-8 and Table-10. tCSH CS t t CSS t CLH t CLL t CSD CLD SCLK tDIS SDI t DIH Valid Input tDW t SDO t PD DF High Impedance High Impedance Valid Output Figure-7 4-Wire SPI Timing Diagram t t CLH CLL SCLK t SDI DIS t DIH Valid Input tDW t SDO PD High Impedance High Impedance Valid Output Figure-8 3-Wire SPI Timing Diagram M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 48 Table-10 SPI Timing Specification Symbol tCSH note 1 Description Min. Minimum CS High Level Time note 2 ns CS Setup Time 3T+10 ns CS Hold Time 30T+10 ns note 1 tCSS tCSD note 1 note 1 tCLD Max. +10 Unit Clock Disable Time 1T ns tCLH Clock High Level Time 30T+10 ns tCLL Clock Low Level Time 16T+10 ns tDIS Data Setup Time 3T+10 ns tDIH Data Hold Time 22T+10 ns tDW Minimum Data Width 30T+10 ns tPD Output Delay 14T note 1 tDF Output Disable Time Note: 1. Not applicable for three-wire SPI. 2. T means SCLK cycle. T=122ns. (Typical value for four-wire SPI) 49 30T Typical M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 15T+20 ns 16T+20 ns 6.3 POWER ON RESET TIMING VH VL DVDD T2 T1 RESET Figure-9 Power On Reset Timing Diagram Table-11 Power On Reset Specification Symbol Description Min. Typical Max. Unit VH Power On Trigger Voltage 2.47 2.6 2.73 V VL Power Off Trigger Voltage 2.185 2.3 2.415 V Hysteretic Voltage Difference 0.285 0.3 0.315 V VH-VL T1 Delay Time After Power On 5 ms T2 Delay Time After Power Off 10 s M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 50 6.4 ZERO-CROSSING TIMING V TZX ZX (Positive zero-crossing) TD ZX (Negative zero-crossing) ZX (All zero-crossing) Figure-10 Zero-Crossing Timing Diagram Table-12 Zero-Crossing Specification Symbol 51 Description TZX High Level Width TD Delay Time M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 Min. Typical Max. 5 Unit ms 0.5 ms 6.5 VOLTAGE SAG TIMING Voltage Sag Threshold V Voltage Sag Threshold TD WarnOut IRQ Figure-11 Voltage Sag Timing Diagram Table-13 Voltage Sag Specification Symbol TD Description Delay Time Min. Typical Max. Unit 0.5 ms M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 52 6.6 PULSE OUTPUT Tp=80ms Tp=0.5T Tp=5ms CFx T160ms if T<10ms, force T=10ms 10msT<160ms Figure-12 Output Pulse Width 6.7 ABSOLUTE MAXIMUM RATING Parameter Maximum Limit Relative Voltage Between AVDD and AGND -0.3V~3.7V Relative Voltage Between DVDD and DGND -0.3V~3.7V Analog Input Voltage (I1P, I1N, I2P, I2N, VP, VN) -1V~VDD Digital Input Voltage -0.3V~VDD+2.6V Operating Temperature Range -40~85 C Maximum Junction Temperature 53 150 C Package Type Thermal Resistance JA Unit Condition Green SSOP28 63.2 C/W No Airflow M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 ORDERING INFORMATION Atmel Ordering Code Package Carrier Temperature Range ATM90E25-YU-R SSOP28 Tape&Reel Industry (-40C to +85C) ATM90E25-YU-B SSOP28 Tube Industry (-40C to +85C) M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 54 PACKAGE DIMENSIONS (1'9,(: 7239,(: & ' '(7$,/$ % 5 + 5 a ( ( &/ JDXJHSODQH VHDWLQJSODQH / 5() & $ % ;7,36 H $ ' $ 6(('(7$,/$ $ & & ;E & $ % $ &20021',0(16,216 8QLWRI0HDVXUH PP 6($7,1* 3/$1( 6,'(9,(: 127( 5HIHUWR-('(&GUDZLQJ029DULDWLRQ$+ 'DQG(GLPHQVLRQVGRQRWLQFOXGHPROGIODVKRU SURWUXVLRQVEXWGRLQFOXGHPROGPLVPDWFKDQGDUH PHDVXUHGDWGDWXPSODQH+0ROGIODVKRUSURWUXVLRQ VKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQEGRHVQRWLQFOXGHGDPEDUSURWUXVWLRQ LQWUXVLRQ$OORZDEOHGDPEDUSURWUXVLRQVKDOOEHPP WRWDOLQH[FHVVRIEGLPHVQLRQDWPD[LPXPPDWHULDO FRQGLWLRQ'DPEDULQWUXVLRQVKDOOQRWUHGXFHGLPHQVLRQE E\PRUHWKDQPPDWOHDVWPDWHULDOFRQGLWLRQ 6<0%2/ 0,1 $ $ $ E 0$; 7<3 127( F ' ( ( H %6& / 5 5 7,7/( 3DFNDJH'UDZLQJ&RQWDFW SDFNDJHGUDZLQJV#DWPHOFRP 55 M90E25 [Preliminary Datasheet] Atmel-46001A-SE-M90E25-Datasheet_041814 <OHDGPP%RG\:LGWKPPSLWFKPP OHDGOHQJWK3ODVWLF6KULQN6PDOO2XWOLQH3DFNDJH 6623 *3& '5$:,1*12 5(9 7%) < % REVISION HISTORY Doc. Rev. Date 46001A 04/18/2014 Comments Initial document release in Atmel. M90E25 [PRELIMINARY DATASHEET] Atmel-46001A-SE-M90E25-Datasheet_041814 56 X X X X Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com (c) 2014 Atmel Corporation. All rights reserved. / Rev.: Atmel-46001A-SE-M90E25-Datasheet_041814. Atmel(R), Atmel logo and combinations thereof, Enabling Unlimited Possibilities(R), and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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