1
®
FN8170.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9260
Dual Supply/Low Power/256-Tap/SPI bus
Dual Digitally-Controlled (XDCP™)
Potentiometers
FEATURES
• Dual–Two Separate Potentiometers
• 256 resistor taps/pot–0.4% resolution
• SPI Serial Interface for write, read, and transfer
operations of the pot entiometer
•Wiper Resistance, 100Ω ty pica l @ V+ = 5V,
V- = -5V
• 4 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position
on Power-up.
• Standby Current < 5µA Max
•V
CC: 2.7V to 5.5V Operation
•50kΩ, 100kΩ versions of End to End Resistanc e
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 24-Lead SOIC, 24-Lead XBGA
• Low Power CMOS
• Power Supply VCC = 2.7V to 5.5V
V+ = 2.7V to 5.5V
V- = -2.7V to -5.5V
DESCRIPTION
The X9260 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points conne cted to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Regis ter (WCR) and a
four nononvolatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the
contents of the default Data Register (DR0) to the
WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
RH0
RL0
Bus
RW0
Interface
and Control
VCC
VSS
SPI
Bus
Address
Data
Status
Write
Read
Transfer
50kΩ or 100kΩ versions
Inc/Dec
RH1
RL1
RW1
Power-on Recall
Wiper Counter
Registers (WCR)
Data Registers
(DR0-DR3)
Interface
Control
V+
V-
Data Sheet February 28, 2005
2FN8170.0
February 28, 2005
DETAILED FUNCTIONAL DIAGRAM
CIRCUIT LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage
amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF
wireless systems
• Set the operating points in temper ature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
R
0
R
1
R
2
R
3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
R
H1
R
L1
R
0
R
1
R
2
R
3
Wiper
Counter
Register
(WCR)
R
H0
R
L0
Data
8
R
W0
R
W1
Pot 0
INTERFACE
AND
CONTROL
CIRCUITRY
V
CC
V
SS
256-taps
50K
Ω
and 100K
Ω
CS
SCK
A0
SO
SI
HOLD
WP
A1
Power-on
Recall
Power-on
Recall
V+
V-
X9260
3FN8170.0
February 28, 2005
PIN CONFIGURATION
PIN ASSIGNMENTS
Pin
(SOIC) Pin
(XBGA) Symbol Function
1 SO Serial Data Output for SPI bus
2 A0 Device Address for SPI bus.
3 NC No Connect.
4 NC No Connect.
5 NC No Connect.
6 V+ Analog Supply Voltage (Positive)
7V
CC System Supply Voltage
8R
L0 Low Terminal for Potentiometer 0.
9R
H0 High Terminal for Potentiometer 0.
10 RW0 Wiper Terminal for Potentiometer 0.
11 CS Device Address for SPI bus.
12 WP Hardware Write Protect
13 SI Serial Data Input for SPI bus
14 A1 Device Address for SPI bus.
15 RL1 Low Terminal for Potentiometer 1.
16 RH1 High Terminal for Potentiometer 1.
17 RW1 Wiper Terminal for Potentiometer 1.
18 VSS System Ground
19 V- Analog Supply Voltage (Negative)
20 NC No Connect
21 NC No Connect
22 NC No Connect
23 SCK Serial Clock for SPI bus
24 HOLD Device select. Pause the SPI serial bus.
2 3 4
A
B
C
D
E
F
Top View - Bumps Down
1 XBGA
SO
A0
NC
V+
VCC
RL0
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
HOLD
SCK
NC
NC
NC
V-
VSS
RW1
RH1
RL1
SOIC
X9260
NC
14
13
11
12
NC
RH0
RW0
CS A1
SI
WP
Not Available
X9260
4FN8170.0
February 28, 2005
PIN DESCRIPTIONS
Bus Interface Pins
SERIAL OUTPUT (SO)
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
SERIAL INPUT
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out o f the
X9260.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
DEVICE ADDRESS (A1 - A0)
The address inputs are used to set the 4-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order
to initiate communication with the X9260.
CHIP SELECT (CS)
When CS is HIGH, the X9260 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9260, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Potentiometer Pins
RH, RL
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2 sets of RH and
RL such that RH0 and RL0 are the term inals of POT 0
and so on.
RW
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 2
potentiometers, there are 2 sets of RW such that RW0
is the terminals of POT 0 and so on.
Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
The VCC pin is the system supply voltage. The VSS
pin is the system ground.
Analog Supply Voltages (V+ and V-)
These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper
switches while the V- supply is used to bias the
switches and the internal P+ substrate of the
integrated circuit. Both of these supplies set the
voltage limits of the potentiometer.
Other Pins
NO CONNECT
No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
X9260
5FN8170.0
February 28, 2005
PRINCIPLES OF OPERATION
Serial Interface
The X9260 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the e ntire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9260 is comprised of a resistor array (See
Figure 1). The array contains the equivalent of 255
discrete resistive segments that are connected in
series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer
(RH and RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1) .
Power-up and Down Requirements.
At all times, the voltages on the potentiometer pins
must be less than V+ and more than V-. During power-
up and power-down, VCC, V+, and V- must reach their
final values within 1msecs of each other. The VCC
ramp rate spec is always in effect.
Figure 1. .Detailed Potentiometer Block Diagram
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY REGISTER 0 REGISTER 1
REGISTER 2 REGISTER 3
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
RH
RL
RW
8 8
C
O
U
N
T
E
R
D
E
C
O
D
E
IF WCR = 00[H] THEN RW = RL
IF WCR = FF[H] THEN RW = RH
WIPER
(WCR)
One of Two Potentiometers
(DR0) (DR1)
(DR2) (DR3)
X9260
6FN8170.0
February 28, 2005
DEVICE DESCRIPTION
Wiper Counter Register (WCR)
The X9260 contains two Wiper Cou nter Registers, one
for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written ind irectly by transfe rring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9260 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR.
Data Registers (DR)
Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper
positions or data (0~255).
Status Register (SR)
This 1-bit Status Register is used to store the system
status.
WIP: Write In Progress status bit, read only.
– When WIP = 1, indicates that high-voltage write
cycle is in progress.
– When WIP = 0, indicates that no high-voltage write
cycle is in progress.
Table 5. Wiper Counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
VVVVVVVV
(MSB) (LSB)
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
NV NV NV NV NV NV NV NV
MSB LSB
X9260
7FN8170.0
February 28, 2005
DEVICE DESCRIPTION
Instructions
IDENTIFICATION BYTE ( ID AND A )
The first byte sent to the X9260 from the host,
following a CS going HIGH to LOW, is called the
Identification Byte. The most signific ant four bits of the
slave address are a device type identifier. The ID[3:0]
bits is the device id for the X9260; this is fixed as
0101[B] (refer to Table 3) .
The AD[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3 - A0 input pins. The slave address
is externally specified by the user. The X9260
compares the serial data stream with the address
input state; a successful compare of both address bits
is required for the X9260 to successfully continue the
command sequence. Only the device which slave
address matches the incoming device address sent
by the master executes the instruction. The A3 - A0
inputs can be actively driven by CMOS input signals
or tied to VCC or VSS.
INSTRUCTION BYTE ( I[3:0] )
The next byte sent to the X9260 contains the instruction
and register pointer information. The three most
significant bits are used provide the instruction opcode
(I[3:0]). The RB and RA bits point to one of the four
Data Registers of each associated XDCP. The least
significant bit points to one of two Wiper Counter
Registers or Pots.The format is shown below in Table 4.
Table 3. Identification Byte Format
Table 4. Instruction Byte Format
ID3 ID2 ID1 ID0 A3 A2 A1 A0
0101
(MSB) (LSB)
Device Type
Identifier Slave Address
I3 I2 I1 I0 RB RA 0 P0
(MSB) (LSB)
Instruction Data Pot Selection
Opcode Selection (WCR Selection)
Register
X9260
8FN8170.0
February 28, 2005
DEVICE DESCRIPTION
Instructions
Four of the ten instructions are three bytes in length.
These instructions are:
–Read Wiper Counter Register – read the current
wiper position of the selected potentiometer,
–Write Wiper Counter Register – change current
wiper position of the selected potentiometer,
–Read Data Register – read the contents of the
selected Data Register;
–Write Data Register – write a new value to the
selected Data Register.
–Read Status - This comma nd ret ur ns the co nt en ts
of the WIP bit which indicates if the internal write
cycle is in progress.
The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer fr om a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the two potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and
one associated register. The Read Status Register
instruction is the only unique format (See Figure 5).
Four instructions require a two-byte sequence to
complete. These instructions transfer data between
the host and the X9260; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are:
–XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.
–XFR Wiper Counter Register to Data Register –
This transfers the contents of the specified Wiper
Counter Register to the specifie d associated Data
Register.
–Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all speci-
fied Data Registers to the associated Wiper Counter
Registers.
–Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (See
Figures 6 and 7). T he Incre ment/Decrement comm and
is different from the other commands. Once the
command is issued and the X9260 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (tHIGH) while SI is HIGH,
the selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCL clock
pulse while SI is LOW, the selected wiper will move
one resistor segment towards the RL terminal. A
detailed illustration of the sequence and timing for this
operation are shown. See Instruction format for more
details.
X9260
9FN8170.0
February 28, 2005
Figure 2. Two-Byte Instr uction Sequence
Figure 3. Three-Byte Instruction Sequence (Write)
Figure 4. Three-Byte Instruction Sequence (Read)
ID3 ID2 ID1 ID0 0 A1 A0 I3 I2 I1 RB RA P0
SCK
SI
CS
0101
Device ID Internal Instruction
Opcode
Address Register
0
I0
Address Pot/WCR
Address
0
00
0101
A1 A0 I3 I2 I1 I0 RB RA P0
SCL
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
ID3 ID2 ID1 ID0
Device ID Internal Instruction
Opcode
Address Register
Address Pot/WCR
Address
00
WCR[7:0]
or
Data Register Bit [7:0]
0
0101
A1 A0 I3 I2 I1 I0 RB RA P0
SCL
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
ID3 ID2 ID1 ID0
Device ID Internal Instruction
Opcode
Address Register
Address Pot/WCR
Address
00
WCR[7:0]
S0
XXXXX
XXX
Don’t Care
or
Data Register Bit [7:0]
0
X9260
10 FN8170.0
February 28, 2005
Figure 5. Three-Byte Instruction Sequence (Read Status Register)
Figure 6. Increment/Decrement Instruction Sequence
Figure 7. Increment/Decrement Timing Limits
WIP
Status
Bit
0101
A1 A0 I3 I2 I1 I0 RB RA P0
SCL
SI
CS
00
ID3 ID2 ID1 ID0
Device ID Internal Instruction
Opcode
Address Register
Address Pot/WCR
Address
00 00000
00
10110
0101
A1 A0 I3I2 I1 I0 RB RA P0
SCL
SI
CS
00
ID3 ID2 ID1 ID0
Device ID Internal Instruction
Opcode
Address Register
Address Pot/WCR
Address
00
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
0
SCK
SI
R
W
INC/DEC CMD ISSUED
tWRID
VOLTAGE OUT
X9260
11 FN8170.0
February 28, 2005
Table 5. Instruction Set
Note: 1/0 = data is one or zero
Instruction Instruction Set OperationI3 I2 I1 I0 RB RA 0 P0
Read Wiper Counter
Register 1 0 0 1 0 0 0 1/0 Read the contents of the Wiper Counter
Register pointed to by P0
Write Wiper Counter
Register 1 0 1 0 0 0 0 1/0 Write new value to the Wiper Counter
Register pointed to by P0
Read Data Register 1 0 1 1 1/0 1/0 0 1/0 Read the contents of the Data Register
pointed to by P0 and RB - RA
Write Data Register 1 1 0 0 1/0 1/0 0 1/0 Write new value to the Data Register
pointed to by P0 and RB - RA
XFR Data Register to
Wiper Counter Register 1 1 0 1 1/0 1/0 0 1/0 Transfer the contents of the Data Register
pointed to by P0 and RB - RA to its
associated Wiper Counter Register
XFR Wiper Counter
Register to Data Register 1 1 1 0 1/0 1/0 0 1/0 Transfer the contents of the Wiper Counter
Register pointed to by P0 to the Data
Register pointed to by RB - RA
Global XFR Data Registers
to Wiper Counter Registers 0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers
pointed to by RB - RA of all four pots to their
respective Wiper Counter Registers
Global XFR Wiper Counter
Registers to Data Register 1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Co unter
Registers to their respective data Registers
pointed to by RB - RA of all four pots
Increment/Decrement
Wiper Counter Register 0 0 1 0 0 0 0 1/0 Enable Increment/decrement of the Control
Latch pointed to by P0
X9260
12 FN8170.0
February 28, 2005
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode WCR
Addresses Wiper Position
(Sent by X9260 on SO) CS
Rising
Edge
010100A1A01001000P0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode WCR
Addresses Data Byte
(Sent by Host on SI) CS
Rising
Edge
010100A1A01010000P0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR and WCR
Addresses Data Byte
(Sent by X9271 on SO) CS
Rising
Edge
010100A1A01011RBRA0 P0
D
7D
6D
5D
4D
3D
2D
1D
0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR and WCR
Addresses Data Byte
(Sent by Host on SI) CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A1A01100RBRA0 P0
D
7D
6D
5D
4D
3D
2D
1D
0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR
Addresses CS
Rising
Edge
010100A1A00001RBRA00
X9260
13 FN8170.0
February 28, 2005
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data
Register (DR)
Transfer Data Register (D R) to Wiper Counter Reg-
ister (WCR)
Increment/Decrement Wiper Counter Register
(WCR)
Read Status Regist er (SR)
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR
Addresses CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A1A01000RBRA00
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR and WCR
Addresses CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A1A01110RBRA0P0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR and WCR
Addresses CS
Rising
Edge
010100A1A01101RBRA0P0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode WCR
Addresses Increment/Decrement
(Sent by Master on SDA) CS
Rising
Edge
0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 P0 I/D I/D . . . . I/D I/D
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode WCR
Addresses Data Byte
(Sent by X9260 on SO) CS
Rising
Edge
010100A1A0010100010000000WIP
X9260
14 FN8170.0
February 28, 2005
ABSOLUTE MAXIMUM RATINGS
Temperature under bias........................-65 to +135°C
Storage temperature ............................. -65 to +150°C
Voltage on SCK, SCL or any address inpu t
with respect to VSS ................................. -1V to +7V
Voltage on V+ (reference d to VSS)........................10V
Voltage on V- ( referenced to VSS)........................-10V
(V+) - (V-) ..............................................................12V
Any VH/RH..............................................................V+
Any VL/RL.................................................................V-
Lead temperature ( soldering, 10 seconds)........300°C
IW (10 seconds)..................................................±6mA
COMMENT
Stresses above those listed under “Absolute Maximu m
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp Min. Max.
Commercial 0°C+70°C
Industrial -40°C+85°C
Device Supply Voltage (VCC)(4) Limits
X9260 5V ± 10%
X9260-2.7 2.7V to 5.5V
V+ 2.7V to 5.5V
V- -2.5V to -5.5V
X9260
15 FN8170.0
February 28, 2005
POTENTIOMETER CHARAC TERISTICS
(Over recommended operating conditions unless otherwise stated.)
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (RH - RL) / 255, single pot
(4) During power-up VCC > VH, VL, and VW.
(5) n = 0, 1, 2, …,255; m =0, 1, 2, …, 254.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Unit
End to end resistance ±20 %
Power rating 50 mW 25°C, each pot
IW Wiper current ±3 mA
RWWiper resistance 250 ΩWiper current = ± 1mA,
V+ = 3V; V- = -3V
RWWiper resistance 150 ΩWiper current = ± 1mA,
V+ = 3V; V- = -3V
Vv+ Voltage on V+ pin X9260 +4.5 +5.5 V
X9260-2.7 +2.7 +5.5
Vv- Voltage on V- pin X9260 -5.5 -4.5 V
X9260-2.7 -5.5 -2.7
VTERM Voltage on any VH/RH or VL/RL
pin V- V+ V
Noise -120 dBV Ref: 1kHz
Resolution (4) 0.4 %
Absolute linearity (1) ±1MI
(3) Vw(n)(actual) - Vw(n)(expected)
Relative linearity (2) ±0.6 MI(3) Vw(n + 1) - [Vw(n) + MI]
Temperature coefficient ±300 ppm/°C
Ratiometric Temperature
Coefficient ±20 ppm/°C
CH/CL/CWPotentiometer Capacitances 10/10/25 pF See Circuit #3
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February 28, 2005
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
POWER-UP AND DOWN REQUIREMENTS
The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach
their final values within 1msec of each other. At all times, the voltages on the potentiometer p ins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The VCC ramp ra te spec is always in effect.
A.C. TEST CONDITIONS
Notes: (6) This parameter is not 100% tested
(7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued.
These parameters are not 100% tested.
Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units
ICC1 VCC supply current
(active) 400 µAf
SCK = 2.5 MHz, SO = Open, VCC = 6V
Other Inputs = VSS
ICC2 VCC supply current
(nonvolatile write) 15mAf
SCK = 2.5MHz, SO = Open, VCC = 6V
Other Inputs = VSS
ISB VCC current (standby) 5 µASCK = SI = V
SS, Addr. = VSS,
CS = VCC = 6V
ILI Input leakage current 10 µAV
IN = VSS to VCC
ILO Output leakage current 10 µAV
OUT = VSS to VCC
VIH Input HIGH voltage VCC x 0.7 VCC + 1 V
VIL Input LOW voltage -1 VCC x 0.3 V
VOL Output LOW voltage 0.4 V IOL = 3mA
VOH Output HIGH voltage VCC - 0.8 V IOH = -1mA, VCC ≥ +3V
VOH Output HIGH voltage VCC - 0.4 V IOH = -0.4mA, VCC ≤ +3V
Parameter Min. Units
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 years
Symbol Test Max. Units Test Conditions
COUT(6) Output capacitance (SO) 8 pF VOUT = 0V
CIN(6) Input capacitance (A0, A1, SI, CS, WP, HOLD, and SCK) 6 pF VIN = 0V
Symbol Parameter Min. Max. Units
tr VCC(6) VCC Power-up rate 0.2 50 V/ms
tPUR(7) Power-up to initiation of read operation 1 ms
Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
X9260
17 FN8170.0
February 28, 2005
EQUIVALENT A.C. LOAD CIRCUIT
AC TIMING
RH
10pF
CLCL
RW
RTOTAL
CW
25pF 10pF
RL
SPICE Macromodel
5V
1462Ω
100pF
SO pin
2714Ω
3V
1382Ω
100pF
SO pin
1217Ω
Symbol Parameter Min. Max. Units
fSCK SSI/SPI clock frequency 2 MHz
tCYC SSI/SPI clock cycle rime 500 ns
tWH SSI/SPI clock high rime 200 ns
tWL SSI/SPI clock low time 200 ns
tLEAD Lead time 250 ns
tLAG Lag time 250 ns
tSU SI, SCK, HOLD and CS input setup time 50 ns
tHSI, SCK, HOLD and CS input hold time 50 ns
tRI SI, SCK, HOLD and CS input rise time 2 µs
tFI SI, SCK, HOLD and CS input fall time 2 µs
tDIS SO output disable time 0 250 ns
tVSO output valid time 200 ns
tHO SO output hold time 0 ns
tRO SO output rise time 100 ns
tFO SO output fall time 100 ns
tHOLD HOLD time 400 ns
tHSU HOLD setup time 100 ns
tHH HOLD hold time 100 ns
tHZ HOLD low to output in high Z 100 ns
tLZ HOLD high to output in low Z 100 ns
TINoise suppression time constant at SI, SCK, HOLD and CS inputs 10 ns
tCS CS deselect time 2 µs
tWPASU WP, A0 setup time 0 ns
tWPAH WP, A0 hold time 0 ns
X9260
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February 28, 2005
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
SYMBOL TABLE
Symbol Parameter Typ. Max. Units
tWR High-voltage write cycle time (store instructions) 5 10 ms
Symbol Parameter Min. Max. Units
tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs
tWRL Wiper response time after instruction issued (all load instructions) 5 10 µs
WAVEFORM INPUTS OUTPUTS
Must be
steady Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X9260
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February 28, 2005
TIMING DIAGRAMS
Input Timing
Output Timing
Hold Timing
...
CS
SCK
SI
SO
MSB LSB
High Impedance
tLEAD
tH
tSU tFI
tCS
tLAG
tCYC
tWL
...
tRI
tWH
...
CS
SCK
SO
SI ADDR
MSB LSB
tDIS
tHO
tV
...
...
CS
SCK
SO
SI
HOLD
tHSU tHH
tLZ
tHZ
tHOLD
tRO tFO
X9260
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February 28, 2005
XDCP Timing (for All Load Instructions)
Write Protect and Device Address Pins Timing
...
CS
SCK
SI MSB LSB
VWx
tWRL
...
SO High Impedance
CS
WP
A0
A1
tWPASU tWPAH
(Any Instruction)
X9260
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February 28, 2005
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
Application Circuits
VR
RW
+VR
I
Three terminal Potentiometer;
Variable voltage divider Two terminal Variable Resistor;
Variable current
Noninverting Amplifier Voltage Regulator
Offset Voltage Adjustment Comparator with Hysterisis
+
–
VSVO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
100kΩ
10kΩ10kΩ
10kΩ
-12V+12V
TL072
+
–
VSVO
R2
R1
}
}
X9260
22 FN8170.0
February 28, 2005
Application Circuits (continued)
Attenuator Filter
Inverting Amplifier Equivalent L-R Circuit
+
–
VSVO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1
fc = 1/(2πRC)
+
–
VS
VO
R2
R1
ZIN = R2 + s R 2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
Function Generator
R2
R4R1 = R2 = R3 = R4 = 10kΩ
+
–
VS
R2
R1
R
C
}
}
VO = G VS
G = - R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
C
VO
X9260
23 FN8170.0
February 28, 2005
PACKAGING INFORMATION
a
B
A
D
C
F
E
1234
B
A
D
C
F
E
1234
b
Top View (Bump Side Down)
Side View (Bump Side Down)
Bottom View (Bump Side U p)
c
d
e
f
k
aj
b
Note:
Drawing not to scale
= Die Orientation mark
Symbol
Millimeters Inches
Min Nom. Max Min Nom. Max
Package Body Dimension X a 2.753 2.783 2.813 0.10838 0.10956 0.11074
Package Body Dimension Y b 4.531 4.561 4.591 0.17838 0.17956 0.18074
Package Height c 0.697 0.730 0.763 0.02744 0.02874 0.03004
Package Body Thickness d 0.444 0.457 0.470 0.01748 0.01799 0.01850
Ball Height e 0.253 0.273 0.293 0.00996 0.01075 0.01154
Ball Diameter f 0.360 0.374 0.388 0.01417 0.01472 0.01528
Total Ball Count g 24
Ball Count X Axis h 4
Ball Count Y Axis i 6
Pins Pitch X Axis j 0.5
Pins Pitch Y Axis k 0.5
Edge to Ball Center (Corner)
Distance Along X l 0.611 0.641 0.671 0.02407 0.02525 0.02643
Edge to Ball Center (Corner)
Distance Along Y m 1.000 1.030 1.060 0.03939 0.04057 0.04175
l
m
24-Ball BGA (X9260TA/X9260UA)
X9260
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February 28, 2005
PACKAGING INFORMATION
0.290 (7.37)
0.299 (7.60) 0.393 (10.00)
0.420 (10.65)
0.014 (0.35)
0.020 (0.50)
Pin 1
Pin 1 Index
0.050 (1.27)
0.598 (15.20)
0.610 (15.49)
0.003 (0.10)
0.012 (0.30)
0.092 (2.35)
0.105 (2.65)
(4X) 7°
24-Lead Plastic Small Outline Gull Wing Package Type S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.420"
0.050" Typical
0.050"
Typical
0.030" Typical
24 Places
FOOTPRINT
0.010 (0.25)
0.020 (0.50)
0.015 (0.40)
0.050 (1.27)
0.009 (0.22)
0.013 (0.33)
0° - 8°
X 45°
X9260
25
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8170.0
February 28, 2005
ORDERING INFORMATION
Device VCC Limits
Blank = 5V ± 10%
- 2.7 = 2.7 to 5.5V
Temperatur e Range
Blank = Commercial = 0°C to +70°C
I = Industrial = - 40°C to +85°C
Package
S24 = 24-Lead SOIC
xxx = xxx-Lead XBGA
Potentiomete r Organization
Pot
U = 50kΩ
T = 100kΩ
X9260 P T V
Y
PART MARK CONVENTION
xx Lead XBGA Top Mark
X9260xxxx-2.7
X9260xxxx xx
X9260 xxxx
X9260xxxxx I-2.7
X9260xxxx-2.7
X9260xxxx xx
X9260 xxxx
X9260xxxxx I-2.7
X9260
