UPD78F9418AGC-8BT-A - NEC - Product.Network

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User’s Manual

PD789405A

PD789406A

PD789407A

PD789407A, 789417A

Subseries

8-Bit Single-Chip Microcontrollers

Printed in Japan

Document No. U13952EJ3V1UD00 (3rd edition)

Date Published October 2005 N CP(K)

PD789415A

PD789416A

PD789417A

PD78F9418A

1999, 2003

2 User’s Manual U13952EJ3V1UD

[MEMO]

User’s Manual U13952EJ3V1UD 3

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V

(MAX) and V

(MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is

fixed, and also in the transition period when the input level passes through the area between V

(MAX)

and V

(MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V

GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins

must be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

NOTES FOR CMOS DEVICES

4 User’s Manual U13952EJ3V1UD

EEPROM and FIP are trademarks of NEC Electronics Corporation.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the

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PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

These commodities, technology or software, must be exported in accordance

with the export administration regulations of the exporting country.

Diversion contrary to the law of that country is prohibited.

The information in this document is current as of August, 2005. The information is subject to

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NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

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or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

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determine NEC Electronics' willingness to support a given application.

(Note)

•

M8E 02. 11-1

(1)

(2)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

"Standard":

"Special":

"Specific":

User’s Manual U13952EJ3V1UD 5

Regional Information

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

[GLOBAL SUPPORT]

http://www.necel.com/en/support/support.html

NEC Electronics America, Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-558-3737

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Tel: 02-2719-2377

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Novena Square, Singapore

Tel: 6253-8311

J05.6

EC Electronics (Europe) GmbH

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Tel: 01908-691-133

Some information contained in this document may vary from country to country. Before using any NEC

Electronics product in your application, pIease contact the NEC Electronics office in your country to

obtain a list of authorized representatives and distributors. They will verify:

6 User’s Manual U13952EJ3V1UD

Major Revisions in This Edition

Page Description

U13952EJ2V0UD00 → U13952EJ3V0UD00

pp.38, 39, 41 Modification of pin handling of AVREF pin and VPP pin in CHAPTER 2 PIN FUNCTIONS

p.92 Addition of Note related to feedback resistor in Figure 5-3 Format of Suboscillation Mode Register

pp.112, 113 Addition of 6.5 Cautions on Using 16-Bit Timer 50

pp.151, 164 Addition of (8) Input impedance of ANI0 to ANI6 pins in 10.5 Cautions on Using 8-Bit A/D Converter and

11.5 Cautions on Using 10-Bit A/D Converter

p.154 Modification of description of (2) A/D conversion result register 0 (ADCR0) in 11.2 Configuration of 10-Bit

A/D Converter

p.196 Addition of description on reading receive data of UART in 13.4.2 Asynchronous serial interface (UART)

mode

p.232 Addition of Caution in Figure 15-2 Format of Interrupt Request Flag Register

p.237 Addition of Caution in Figure 15-7 Format of Key Return Mode Register 00

p.256 Addition of description on pull-up resistor and divider resistor for LCD driving in Table 18-1 Differences

Between

PD78F9418A and Mask ROM Versions

pp.257 to 266 Overall revision of contents related to flash memory programming as 18.1 Flash Memory Characteristics

pp.278 to 292 Addition of CHAPTER 21 ELECTRICAL SPECIFICATIONS

pp.293 to 295 Addition of CHAPTER 22 CHARACTERISTICS CURVES (REFERENCE VALUES)

pp.296, 297 Addition of CHAPTER 23 PACKAGE DRAWINGS

pp.298, 299 Addition of CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS

pp.301 to 310 Overall revision of contents of APPENDIX A DEVELOPMENT TOOLS

Deletion of embedded software

pp.311 to 314 Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN

U13952EJ3V0UD00 → U13952EJ3V1UD00

p. 24 Modification of 1.3 Ordering Information

p. 300 Addition of Table 24-1. Surface Mounting Type Soldering Conditions (3/3)

The mark shows major revised points.

User’s Manual U13952EJ3V1UD 7

INTRODUCTION

Target Readers This manual is intended for users who wish to understand the functions of the

PD789407A and

PD789417A Subseries and to design and develop application

systems and programs using these microcontrollers.

Target products:

•

PD789407A Subseries:

PD789405A,

PD789406A, and

PD789407A

•

PD789417A Subseries:

PD789415A,

PD789416A,

PD789417A, and

PD78F9418A

Purpose This manual is intended to give users an understanding of the functions described in

the Organization below.

Organization The

PD789407A and

PD789417A Subseries User’s Manual is divided into two

parts: this manual and instructions (common to the 78K/0S Series).

PD789407A and

PD789417A

Subseries

User’s Manual

78K/0S Series

User’s Manual

Instructions

• Pin functions

• Internal block functions

• Interrupt functions

• Other on-chip peripheral functions

• Electrical specifications

• CPU function

• Instruction set

• Explanation of each

instruction

How to Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of

electrical engineering, logic circuits, and microcontrollers.

• To understand the functions in general:

→ Read this manual in the order of the CONTENTS.

• How to interpret the register formats:

→ The name of a bit whose number is enclosed in brackets is reserved for the

assembler and is defined for the C compiler by the header file sfrbit.h.

• When you know a register name and want to confirm its details:

→ Read APPENDIX C REGISTER INDEX.

• To know the 78K/0S Series instructions functions in detail:

→ Refer to 78K/0S Series Instructions User’s Manual (U11047E).

• To learn the electrical specifications of the

PD789407A and

PD789417A

Subseries

→ Refer to CHAPTER 21 ELECTRICAL SPECIFICATIONS.

8 User’s Manual U13952EJ3V1UD

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representation: xxx (overscore over pin or signal name)

Note: Footnote for item marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information

Numerical representation: Binary ... xxxx or xxxxB

Decimal ... xxxx

Hexadecimal ... xxxxH

Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents Related to Devices

Document Name Document No.

PD789407A, 789417A Subseries User’s Manual This manual

78K/0S Series Instructions User’s Manual U11047E

Documents Related to Development Software Tools (User’s Manuals)

Document Name Document No.

Operation U14876E

Language U14877E

RA78K0S Assembler Package

Structured Assembly Language U11623E

Operation U14871E CC78K0S C Compiler

Language U14872E

Operation (WindowsTM Based) U15373E SM78K Series System Simulator Ver. 2.30 or Later

External Part User Open Interface Specifications U15802E

ID78K Series Integrated Debugger Ver. 2.30 or Later Operation (Windows Based) U15185E

Project Manager Ver. 3.12 or Later (Windows Based) U14610E

Documents Related to Development Hardware Tools (User’s Manuals)

Document Name Document No.

IE-78K0S-NS In-Circuit Emulator U13549E

IE-78K0S-NS-A In-Circuit Emulator U15207E

IE-789418-NS-EM1 Emulation Board U14364E

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

User’s Manual U13952EJ3V1UD 9

Documents Related to Flash Memory Writing

Document Name Document No.

PG-FP3 Flash Memory Programmer User’s Manual U13502E

PG-FP4 Flash Memory Programmer User’s Manual U15260E

Other Related Documents

Document Name Document No.

SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X

Semiconductor Device Mount Manual Note

Quality Grades on NEC Semiconductor Devices C11531E

NEC Semiconductor Device Reliability/Quality Control System C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E

Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html)

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

10 User’s Manual U13952EJ3V1UD

CONTENTS

CHAPTER 1 GENERAL...........................................................................................................................23

1.1 Features.........................................................................................................................................23

1.2 Applications ..................................................................................................................................23

1.3 Ordering Information....................................................................................................................24

1.4 Pin Configuration (Top View) ......................................................................................................25

1.5 78K/0S Series Lineup ...................................................................................................................27

1.6 Block Diagram...............................................................................................................................30

1.7 Overview of Functions .................................................................................................................31

CHAPTER 2 PIN FUNCTIONS ...............................................................................................................33

2.1 List of Pin Functions ....................................................................................................................33

2.2 Description of Pin Functions.......................................................................................................36

2.2.1 P00 to P03 (Port 0)............................................................................................................................36

2.2.2 P20 to P27 (Port 2)............................................................................................................................36

2.2.3 P40 to P47 (Port 4)............................................................................................................................37

2.2.4 P50 to P53 (Port 5)............................................................................................................................37

2.2.5 P60 to P66 (Port 6)............................................................................................................................37

2.2.6 P80 to P87 (Port 8)............................................................................................................................38

2.2.7 P90 to P93 (Port 9)............................................................................................................................38

2.2.8 S0 to S15 ..........................................................................................................................................38

2.2.9 COM0 to COM3 ................................................................................................................................38

2.2.10 VLC0 to VLC2 .....................................................................................................................................38

2.2.11 BIAS................................................................................................................................................ 38

2.2.12 AVREF ..............................................................................................................................................38

2.2.13 AVDD ...............................................................................................................................................38

2.2.14 AVSS ...............................................................................................................................................39

2.2.15 RESET ............................................................................................................................................39

2.2.16 X1, X2 .............................................................................................................................................39

2.2.17 XT1, XT2 ......................................................................................................................................... 39

2.2.18 VDD0, VDD1 ....................................................................................................................................... 39

2.2.19 VSS0, VSS1 .......................................................................................................................................39

2.2.20 VPP (

PD78F9418A only) ................................................................................................................39

2.2.21 IC (mask ROM version only) ...........................................................................................................40

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ...........................................41

CHAPTER 3 CPU ARCHITECTURE......................................................................................................44

3.1 Memory Space ..............................................................................................................................44

3.1.1 Internal program memory space........................................................................................................48

3.1.2 Internal data memory space.............................................................................................................. 49

3.1.3 Special function register (SFR) area .................................................................................................49

3.1.4 Data memory addressing ..................................................................................................................50

3.2 Processor Registers.....................................................................................................................54

3.2.1 Control registers................................................................................................................................54

User’s Manual U13952EJ3V1UD 11

3.2.2 General-purpose registers................................................................................................................. 57

3.2.3 Special function registers (SFR)........................................................................................................ 58

3.3 Instruction Address Addressing.................................................................................................61

3.3.1 Relative addressing........................................................................................................................... 61

3.3.2 Immediate addressing....................................................................................................................... 62

3.3.3 Table indirect addressing .................................................................................................................. 63

3.3.4 Register addressing .......................................................................................................................... 63

3.4 Operand Address Addressing ....................................................................................................64

3.4.1 Direct addressing .............................................................................................................................. 64

3.4.2 Short direct addressing ..................................................................................................................... 65

3.4.3 Special function register (SFR) addressing ....................................................................................... 66

3.4.4 Register addressing .......................................................................................................................... 67

3.4.5 Register indirect addressing.............................................................................................................. 68

3.4.6 Based addressing ............................................................................................................................. 69

3.4.7 Stack addressing............................................................................................................................... 69

CHAPTER 4 PORT FUNCTIONS........................................................................................................... 70

4.1 Function of Port............................................................................................................................70

4.2 Configuration of Ports .................................................................................................................72

4.2.1 Port 0 ................................................................................................................................................ 72

4.2.2 Port 2 ................................................................................................................................................ 73

4.2.3 Port 4 ................................................................................................................................................ 78

4.2.4 Port 5 ................................................................................................................................................ 80

4.2.5 Port 6 ................................................................................................................................................ 81

4.2.6 Port 8 ................................................................................................................................................ 83

4.2.7 Port 9 ................................................................................................................................................ 84

4.3 Registers Controlling Ports.........................................................................................................85

4.4 Operation of Ports ........................................................................................................................88

4.4.1 Writing to I/O port.............................................................................................................................. 88

4.4.2 Reading from I/O port........................................................................................................................ 88

4.4.3 Arithmetic operation of I/O port ......................................................................................................... 88

CHAPTER 5 CLOCK GENERATOR ......................................................................................................89

5.1 Functions of Clock Generator.....................................................................................................89

5.2 Configuration of Clock Generator ..............................................................................................89

5.3 Registers Controlling Clock Generator...................................................................................... 91

5.4 System Clock Oscillators ............................................................................................................ 94

5.4.1 Main system clock oscillator.............................................................................................................. 94

5.4.2 Subsystem clock oscillator ................................................................................................................ 95

5.4.3 Examples of incorrect resonator connection ..................................................................................... 96

5.4.4 Divider............................................................................................................................................... 97

5.4.5 When no subsystem clock is used .................................................................................................... 97

5.5 Operation of Clock Generator ..................................................................................................... 98

5.6 Changing Setting of System Clock and CPU Clock..................................................................99

5.6.1 Time required for switching between system clock and CPU clock................................................... 99

5.6.2 Switching between system clock and CPU clock ............................................................................ 100

12 User’s Manual U13952EJ3V1UD

CHAPTER 6 16-BIT TIMER 50.............................................................................................................101

6.1 Function of 16-Bit Timer 50 .......................................................................................................101

6.2 Configuration of 16-Bit Timer 50...............................................................................................102

6.3 Registers Controlling 16-Bit Timer 50 ......................................................................................104

6.4 Operation of 16-Bit Timer 50 .....................................................................................................107

6.4.1 Operation as timer interrupt............................................................................................................. 107

6.4.2 Operation as timer output................................................................................................................ 109

6.4.3 Capture operation............................................................................................................................ 110

6.4.4 16-bit timer counter 50 readout .......................................................................................................111

6.5 Cautions on Using 16-Bit Timer 50 ...........................................................................................112

6.5.1 Restrictions when rewriting 16-bit compare register 50................................................................... 112

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02 .............................................................114

7.1 Function of 8-Bit Timer/Event Counters 00 to 02....................................................................114

7.2 Configuration of 8-Bit Timer/Event Counters 00 to 02 ...........................................................115

7.3 Registers Controlling 8-Bit Timer/Event Counters 00 to 02...................................................118

7.4 Operation of 8-Bit Timer/Event Counters 00 to 02 ..................................................................122

7.4.1 Operation as interval timer .............................................................................................................. 122

7.4.2 Operation as external event counter (timer 00 and timer 01 only)...................................................125

7.4.3 Operation as square-wave output (timer 02 only)............................................................................ 126

7.5 Cautions on Using 8-Bit Timer/Event Counters 00 to 02........................................................128

CHAPTER 8 WATCH TIMER ...............................................................................................................129

8.1 Functions of Watch Timer .........................................................................................................129

8.2 Configuration of Watch Timer ...................................................................................................130

8.3 Register Controlling Watch Timer ............................................................................................131

8.4 Operation of Watch Timer..........................................................................................................132

8.4.1 Operation as watch timer ................................................................................................................ 132

8.4.2 Operation as interval timer .............................................................................................................. 132

CHAPTER 9 WATCHDOG TIMER .......................................................................................................134

9.1 Functions of Watchdog Timer...................................................................................................134

9.2 Configuration of Watchdog Timer ............................................................................................135

9.3 Registers Controlling Watchdog Timer....................................................................................136

9.4 Operation of Watchdog Timer ...................................................................................................138

9.4.1 Operation as watchdog timer...........................................................................................................138

9.4.2 Operation as interval timer .............................................................................................................. 139

CHAPTER 10 8-BIT A/D CONVERTER (

PD789407A SUBSERIES).............................................140

10.1 Function of 8-Bit A/D Converter..............................................................................................140

10.2 Configuration of 8-Bit A/D Converter .....................................................................................140

10.3 Registers Controlling 8-Bit A/D Converter.............................................................................143

10.4 Operation of 8-Bit A/D Converter............................................................................................145

10.4.1 Basic operation of 8-bit A/D converter........................................................................................... 145

10.4.2 Input voltage and conversion result............................................................................................... 146

10.4.3 Operation mode of 8-bit A/D converter.......................................................................................... 148

User’s Manual U13952EJ3V1UD 13

10.5 Cautions on Using 8-Bit A/D Converter ................................................................................. 149

CHAPTER 11 10-BIT A/D CONVERTER (

PD789417A SUBSERIES)...........................................153

11.1 Function of 10-Bit A/D Converter ...........................................................................................153

11.2 Configuration of 10-Bit A/D Converter ...................................................................................153

11.3 Registers Controlling 10-Bit A/D Converter ..........................................................................156

11.4 Operation of 10-Bit A/D Converter..........................................................................................158

11.4.1 Basic operation of 10-bit A/D converter......................................................................................... 158

11.4.2 Input voltage and conversion result............................................................................................... 160

11.4.3 Operation mode of 10-bit A/D converter........................................................................................ 161

11.5 Cautions on Using 10-Bit A/D Converter ...............................................................................162

CHAPTER 12 COMPARATOR..............................................................................................................166

12.1 Functions of Comparator ........................................................................................................166

12.2 Configuration of Comparator ..................................................................................................167

12.3 Register Controlling Comparator ...........................................................................................168

12.4 Operation of Comparator.........................................................................................................169

CHAPTER 13 SERIAL INTERFACE 00 ..............................................................................................171

13.1 Functions of Serial Interface 00 ..............................................................................................171

13.2 Configuration of Serial Interface 00 .......................................................................................172

13.3 Registers Controlling Serial Interface 00...............................................................................176

13.4 Operation of Serial Interface 00 .............................................................................................. 183

13.4.1 Operation stopped mode............................................................................................................... 183

13.4.2 Asynchronous serial interface (UART) mode ................................................................................ 185

13.4.3 3-wire serial I/O mode ................................................................................................................... 198

CHAPTER 14 LCD CONTROLLER/DRIVER.......................................................................................202

14.1 Functions of LCD Controller/Driver........................................................................................202

14.2 Configuration of LCD Controller/Driver .................................................................................203

14.3 Registers Controlling LCD Controller/Driver.........................................................................205

14.4 Setting LCD Controller/Driver .................................................................................................208

14.5 LCD Display Data Memory.......................................................................................................208

14.6 Common and Segment Signals ..............................................................................................209

14.7 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2 .............................................................213

14.8 Display Modes .......................................................................................................................... 215

14.8.1 Static display example................................................................................................................... 215

14.8.2 Two-time-slice display example .................................................................................................... 218

14.8.3 Three-time-slice display example.................................................................................................. 221

14.8.4 Four-time-slice display example.................................................................................................... 225

CHAPTER 15 INTERRUPT FUNCTIONS ............................................................................................228

15.1 Interrupt Function Types .........................................................................................................228

15.2 Interrupt Sources and Configuration .....................................................................................228

15.3 Registers Controlling Interrupt Function...............................................................................231

15.4 Operation of Interrupt Servicing .............................................................................................238

15.4.1 Non-maskable interrupt acknowledgment operation ..................................................................... 238

14 User’s Manual U13952EJ3V1UD

15.4.2 Maskable interrupt acknowledgment operation ............................................................................. 240

15.4.3 Multiple interrupt servicing............................................................................................................. 241

15.4.4 Putting interrupt requests on hold.................................................................................................. 243

CHAPTER 16 STANDBY FUNCTION ..................................................................................................244

16.1 Standby Function and Configuration .....................................................................................244

16.1.1 Standby function............................................................................................................................ 244

16.1.2 Standby function control register ................................................................................................... 245

16.2 Operation of Standby Function...............................................................................................246

16.2.1 HALT mode ................................................................................................................................... 246

16.2.2 STOP mode .................................................................................................................................. 249

CHAPTER 17 RESET FUNCTION .......................................................................................................252

CHAPTER 18

PD78F9418A ................................................................................................................256

18.1 Flash Memory Characteristics ................................................................................................257

18.1.1 Programming environment ............................................................................................................ 257

18.1.2 Communication mode ................................................................................................................... 258

18.1.3 On-board pin connections ............................................................................................................. 261

18.1.4 Connection when using flash memory writing adapter .................................................................. 264

CHAPTER 19 MASK OPTIONS ...........................................................................................................267

19.1 Mask Option for Pins................................................................................................................267

19.2 Mask Option for Voltage Division Resistor for LCD Driver..................................................267

CHAPTER 20 INSTRUCTION SET ......................................................................................................268

20.1 Operation...................................................................................................................................268

20.1.1 Operand identifiers and description methods ................................................................................ 268

20.1.2 Description of “Operation” column................................................................................................. 269

20.1.3 Description of “Flag” column.......................................................................................................... 269

20.2 Operation List ...........................................................................................................................270

20.3 Instructions Listed by Addressing Type................................................................................275

CHAPTER 21 ELECTRICAL SPECIFICATIONS.................................................................................278

CHAPTER 22 CHARACTERISTICS CURVES (REFERENCE VALUES).........................................293

22.1 Characteristics Curves for Mask ROM Versions...................................................................293

22.2 Characteristics Curves for

PD78F9418A .............................................................................295

CHAPTER 23 PACKAGE DRAWINGS................................................................................................296

CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS...........................................................298

APPENDIX A DEVELOPMENT TOOLS...............................................................................................301

A.1 Software Package ......................................................................................................................303

A.2 Language Processing Software ...............................................................................................303

A.3 Control Software ........................................................................................................................304

User’s Manual U13952EJ3V1UD 15

A.4 Flash Memory Writing Tools.....................................................................................................304

A.5 Debugging Tools (Hardware).................................................................................................... 305

A.6 Debugging Tools (Software).....................................................................................................306

A.7 Package Drawings of Conversion Socket and Conversion Adapter....................................307

A.7.1 Package drawing and recommended footprint of conversion socket (EV-9200GC-80) .................. 307

A.7.2 Package drawing of conversion adapter (TGK-080SDW)............................................................... 309

A.7.3 Package drawing of conversion adapter (TGC-080SBP)................................................................ 310

APPENDIX B NOTES ON TARGET SYSTEM DESIGN...................................................................311

APPENDIX C REGISTER INDEX.........................................................................................................315

C.1 Register Index (Alphabetic Order of Register Name) ............................................................315

C.2 Register Index (Alphabetic Order of Register Symbol) ......................................................... 317

APPENDIX D REVISION HISTORY .....................................................................................................319

16 User’s Manual U13952EJ3V1UD

LIST OF FIGURES (1/5)

Figure No. Title Page

2-1 Pin I/O Circuits .............................................................................................................................................42

3-1 Memory Map (

PD789405A and

PD789415A)...........................................................................................44

3-2 Memory Map (

PD789406A and

PD789416A)...........................................................................................45

3-3 Memory Map (

PD789407A and

PD789417A)...........................................................................................46

3-4 Memory Map (

PD78F9418A)......................................................................................................................47

3-5 Data Memory Addressing (

PD789405A and

PD789415A) .......................................................................50

3-6 Data Memory Addressing (

PD789406A and

PD789416A) .......................................................................51

3-7 Data Memory Addressing (

PD789407A and

PD789417A) .......................................................................52

3-8 Data Memory Addressing (

PD78F9418A) ..................................................................................................53

3-9 Program Counter Configuration....................................................................................................................54

3-10 Program Status Word Configuration.............................................................................................................54

3-11 Stack Pointer Configuration..........................................................................................................................56

3-12 Data Saved to Stack Memory.......................................................................................................................56

3-13 Data Restored from Stack Memory ..............................................................................................................56

3-14 General-Purpose Register Configuration......................................................................................................57

4-1 Port Types ....................................................................................................................................................70

4-2 Block Diagram of P00 to P03 .......................................................................................................................72

4-3 Block Diagram of P20...................................................................................................................................73

4-4 Block Diagram of P21...................................................................................................................................74

4-5 Block Diagram of P22 and P24 ....................................................................................................................75

4-6 Block Diagram of P23...................................................................................................................................76

4-7 Block Diagram of P25 to P27 .......................................................................................................................77

4-8 Block Diagram of P40 to P45 .......................................................................................................................78

4-9 Block Diagram of P46 and P47 ....................................................................................................................79

4-10 Block Diagram of P50 to P53 .......................................................................................................................80

4-11 Block Diagram of P60 and P61 ....................................................................................................................81

4-12 Block Diagram of P62 to P66 .......................................................................................................................82

4-13 Block Diagram of P80 to P87 .......................................................................................................................83

4-14 Block Diagram of P90 to P93 .......................................................................................................................84

4-15 Format of Port Mode Register ......................................................................................................................86

4-16 Format of Pull-Up Resistor Option Register 0 ..............................................................................................86

4-17 Format of Pull-Up Resistor Option Register 1 ..............................................................................................87

4-18 Format of Pull-Up Resistor Option Register 2 ..............................................................................................87

5-1 Block Diagram of Clock Generator ...............................................................................................................90

5-2 Format of Processor Clock Control Register ................................................................................................91

5-3 Format of Suboscillation Mode Register.......................................................................................................92

5-4 Format of Subclock Control Register............................................................................................................93

5-5 External Circuit of Main System Clock Oscillator..........................................................................................94

5-6 External Circuit of Subsystem Clock Oscillator.............................................................................................95

5-7 Examples of Incorrect Resonator Connection ..............................................................................................96

5-8 Switching Between System Clock and CPU Clock .....................................................................................100

User’s Manual U13952EJ3V1UD 17

LIST OF FIGURES (2/5)

Figure No. Title Page

6-1 Block Diagram of 16-Bit Timer 50...............................................................................................................102

6-2 Format of 16-Bit Timer Mode Control Register 50......................................................................................105

6-3 Format of Port Mode Register 2 .................................................................................................................106

6-4 Settings of 16-Bit Timer Mode Control Register 50 for Timer Interrupt Operation ......................................107

6-5 Timing of Timer Interrupt Operation ...........................................................................................................108

6-6 Settings of 16-Bit Timer Mode Control Register 50 for Timer Output Operation.........................................109

6-7 Timer Output Timing...................................................................................................................................109

6-8 Settings of 16-Bit Timer Mode Control Register 50 for Capture Operation.................................................110

6-9 Capture Operation Timing (Both Edges of CPT5 Pin Are Specified)..........................................................110

6-10 Readout Timing of 16-Bit Timer Counter 50...............................................................................................111

7-1 Block Diagram of 8-Bit Timer/Event Counter 00.........................................................................................116

7-2 Block Diagram of 8-Bit Timer/Event Counter 01.........................................................................................116

7-3 Block Diagram of 8-Bit Timer 02.................................................................................................................117

7-4 Format of 8-Bit Timer Mode Control Register 00........................................................................................118

7-5 Format of 8-Bit Timer Mode Control Register 01........................................................................................119

7-6 Format of 8-Bit Timer Mode Control Register 02........................................................................................120

7-7 Format of Port Mode Register 2 .................................................................................................................121

7-8 Interval Timer Operation Timing of Timer 00 and Timer 01........................................................................123

7-9 Interval Timer Operation Timing of Timer 02..............................................................................................124

7-10 External Event Counter Operation Timing (with Rising Edge Specified) ....................................................125

7-11 Square-Wave Output Timing......................................................................................................................127

7-12 Start Timing of 8-Bit Timer Counters 00, 01, and 02 ..................................................................................128

7-13 External Event Counter Operation Timing..................................................................................................128

8-1 Block Diagram of Watch Timer...................................................................................................................129

8-2 Format of Watch Timer Mode Control Register..........................................................................................131

8-3 Watch Timer/Interval Timer Operation Timing............................................................................................133

9-1 Block Diagram of Watchdog Timer.............................................................................................................135

9-2 Format of Timer Clock Selection Register 2...............................................................................................136

9-3 Format of Watchdog Timer Mode Register ................................................................................................137

10-1 Block Diagram of 8-Bit A/D Converter ........................................................................................................141

10-2 Format of A/D Converter Mode Register 0 .................................................................................................143

10-3 Format of A/D Input Selection Register 0 ...................................................................................................144

10-4 Basic Operation of 8-Bit A/D Converter......................................................................................................146

10-5 Relationship Between Analog Input Voltage and A/D Conversion Result...................................................147

10-6 Software-Started A/D Conversion ..............................................................................................................148

10-7 How to Reduce Current Consumption in Standby Mode ............................................................................149

10-8 Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ..................................150

10-9 Conversion Result Readout Timing (When Conversion Result Is Normal Value).......................................150

10-10 Analog Input Pin Processing ......................................................................................................................151

10-11 A/D Conversion End Interrupt Request Generation Timing........................................................................152

18 User’s Manual U13952EJ3V1UD

LIST OF FIGURES (3/5)

Figure No. Title Page

10-12 AVDD Pin Processing ..................................................................................................................................152

11-1 Block Diagram of 10-Bit A/D Converter ......................................................................................................154

11-2 Format of A/D Converter Mode Register 0 .................................................................................................156

11-3 Format of A/D Input Selection Register 0 ...................................................................................................157

11-4 Basic Operation of 10-Bit A/D Converter ....................................................................................................159

11-5 Relationship Between Analog Input Voltage and A/D Conversion Result...................................................160

11-6 Software-Started A/D Conversion...............................................................................................................161

11-7 How to Reduce Current Consumption in Standby Mode ............................................................................162

11-8 Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ..................................163

11-9 Conversion Result Readout Timing (When Conversion Result Is Normal Value).......................................163

11-10 Analog Input Pin Processing ......................................................................................................................164

11-11 A/D Conversion End Interrupt Request Generation Timing ........................................................................165

11-12 AVDD Pin Processing ..................................................................................................................................165

12-1 Block Diagram of Comparator ....................................................................................................................167

12-2 Format of Comparator Mode Register 0 .....................................................................................................168

12-3 Settings of Comparator Mode Register 0 for Comparator Operation..........................................................169

12-4 Settings of External Interrupt Mode Register 1 at INTCMP0 Occurrence...................................................169

12-5 Comparator Operation Timing ....................................................................................................................170

13-1 Block Diagram of Serial Interface 00 ..........................................................................................................173

13-2 Block Diagram of Baud Rate Generator .....................................................................................................174

13-3 Format of Serial Operation Mode Register 00 ............................................................................................176

13-4 Format of Asynchronous Serial Interface Mode Register 00 ......................................................................177

13-5 Format of Asynchronous Serial Interface Status Register 00 .....................................................................179

13-6 Format of Baud Rate Generator Control Register 00 .................................................................................180

13-7 Format of Asynchronous Serial Interface Transmit/Receive Data ..............................................................191

13-8 Asynchronous Serial Interface Transmission Completion Interrupt Timing.................................................193

13-9 Asynchronous Serial Interface Reception Completion Interrupt Timing......................................................194

13-10 Receive Error Timing..................................................................................................................................195

13-11 3-Wire Serial I/O Mode Timing ...................................................................................................................201

14-1 Block Diagram of LCD Controller/Driver .....................................................................................................204

14-2 Format of LCD Display Mode Register 0 ....................................................................................................205

14-3 Format of LCD Port Selector 0 ...................................................................................................................206

14-4 Format of LCD Clock Control Register 0 ....................................................................................................207

14-5 Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs ...................208

14-6 Common Signal Waveforms.......................................................................................................................211

14-7 Voltages and Phases of Common and Segment Signals ...........................................................................212

14-8 Examples of LCD Drive Power Connections (with On-Chip Voltage Divider Resistors) .............................214

14-9 Static LCD Display Pattern and Electrode Connections .............................................................................215

14-10 Example of Connecting Static LCD Panel ..................................................................................................216

14-11 Static LCD Drive Waveform Examples .......................................................................................................217

User’s Manual U13952EJ3V1UD 19

LIST OF FIGURES (4/5)

Figure No. Title Page

14-12 Two-Time-Slice LCD Display Pattern and Electrode Connections .............................................................218

14-13 Example of Connecting Two-Time-Slice LCD Panel ..................................................................................219

14-14 Two-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method)..........................................................220

14-15 Three-Time-Slice LCD Display Pattern and Electrode Connections...........................................................221

14-16 Example of Connecting Three-Time-Slice LCD Panel................................................................................222

14-17 Three-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method) .......................................................223

14-18 Three-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method) .......................................................224

14-19 Four-Time-Slice LCD Display Pattern and Electrode Connections.............................................................225

14-20 Example of Connecting Four-Time-Slice LCD Panel..................................................................................226

14-21 Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method) .........................................................227

15-1 Basic Configuration of Interrupt Function ...................................................................................................230

15-2 Format of Interrupt Request Flag Register .................................................................................................232

15-3 Format of Interrupt Mask Flag Register......................................................................................................233

15-4 Format of External Interrupt Mode Register 0 ............................................................................................234

15-5 Format of External Interrupt Mode Register 1 ............................................................................................235

15-6 Configuration of Program Status Word.......................................................................................................236

15-7 Format of Key Return Mode Register 00....................................................................................................237

15-8 Block Diagram of Falling Edge Detector.....................................................................................................237

15-9 Flowchart of Non-Maskable Interrupt Request Acknowledgment ...............................................................239

15-10 Timing of Non-Maskable Interrupt Request Acknowledgment....................................................................239

15-11 Non-Maskable Interrupt Request Acknowledgment ...................................................................................239

15-12 Interrupt Acknowledgment Program Algorithm ...........................................................................................240

15-13 Interrupt Request Acknowledgment Timing (Example: MOV A, r)..............................................................241

15-14 Interrupt Request Acknowledgment Timing (When Interrupt Request Flag

Is Generated in Final Clock Under Execution)............................................................................................241

15-15 Example of Multiple Interrupt......................................................................................................................242

16-1 Format of Oscillation Stabilization Time Selection Register .......................................................................245

16-2 Releasing HALT Mode by Interrupt ............................................................................................................247

16-3 Releasing HALT Mode by RESET Input.....................................................................................................248

16-4 Releasing STOP Mode by Interrupt............................................................................................................250

16-5 Releasing STOP Mode by RESET Input ....................................................................................................251

17-1 Block Diagram of Reset Function...............................................................................................................252

17-2 Reset Timing by RESET Input ...................................................................................................................253

17-3 Reset Timing by Overflow in Watchdog Timer ...........................................................................................253

17-4 Reset Timing by RESET Input in STOP Mode ...........................................................................................253

18-1 Environment for Writing Program to Flash Memory....................................................................................257

18-2 Communication Mode Selection Format ....................................................................................................258

18-3 Example of Connection with Dedicated Flash Programmer .......................................................................259

18-4 VPP Pin Connection Example......................................................................................................................261

18-5 Signal Conflict (Serial Interface Input Pin)..................................................................................................262

20 User’s Manual U13952EJ3V1UD

LIST OF FIGURES (5/5)

Figure No. Title Page

18-6 Malfunction of Another Device....................................................................................................................262

18-7 Signal Conflict (RESET Pin) .......................................................................................................................263

18-8 Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode....................264

18-9 Example of Flash Memory Writing Adapter Connection When Using UART Mode ....................................265

18-10 Example of Flash Memory Writing Adapter Connection When Using Pseudo 3-Wire Mode

(When P0 Is Used) .....................................................................................................................................266

A-1 Development Tools.....................................................................................................................................302

A-2 Package Drawing of EV-9200GC-80 (for Reference) .................................................................................307

A-3 Recommended Footprint of EV-9200GC-80 (for Reference)......................................................................308

A-4 Package Drawing of TGK-080SDW (for Reference)...................................................................................309

A-5 Package Drawing of TGC-080SBP (for Reference)....................................................................................310

B-1 Distance Between In-Circuit Emulator and Conversion Socket (80GC) .....................................................311

B-2 Connection Condition of Target System (NP-80GC-TQ) ............................................................................312

B-3 Distance Between In-Circuit Emulator and Conversion Adapter (80GK) ....................................................313

B-4 Connection Condition of Target System (NP-80GK) ..................................................................................314

User’s Manual U13952EJ3V1UD 21

LIST OF TABLES (1/2)

Table No. Title Page

2-1 Types of Pin I/O Circuits...............................................................................................................................41

3-1 Internal ROM Capacity .................................................................................................................................48

3-2 Vector Table.................................................................................................................................................48

3-3 Special Function Register List......................................................................................................................59

4-1 Port Functions ..............................................................................................................................................71

4-2 Configuration of Port ....................................................................................................................................72

4-3 Port Mode Register and Output Latch Settings When Using Alternate Functions ........................................85

5-1 Configuration of Clock Generator .................................................................................................................89

5-2 Maximum Time Required for Switching CPU Clock .....................................................................................99

6-1 Configuration of 16-Bit Timer 50.................................................................................................................102

6-2 Interval Time of 16-Bit Timer 50 .................................................................................................................107

6-3 Settings of Capture Edge ...........................................................................................................................110

7-1 Interval Time of 8-Bit Timer/Event Counter 00 ...........................................................................................114

7-2 Interval Time of 8-Bit Timer/Event Counter 01 ...........................................................................................114

7-3 Interval Time of 8-Bit Timer 02 ...................................................................................................................114

7-4 Square-Wave Output Range of 8-Bit Timer 02...........................................................................................115

7-5 Configuration of 8-Bit Timer/Event Counters 00 to 02 ................................................................................115

7-6 Interval Time of 8-Bit Timer/Event Counter 00 ...........................................................................................122

7-7 Interval Time of 8-Bit Timer/Event Counter 01 ...........................................................................................122

7-8 Interval Time of 8-Bit Timer 02 ...................................................................................................................123

7-9 Square-Wave Output Range of 8-Bit Timer 02...........................................................................................126

8-1 Interval Time of Interval Timer....................................................................................................................130

8-2 Configuration of Watch Timer.....................................................................................................................130

8-3 Interval Time of Interval Timer....................................................................................................................132

9-1 Program Loop Detection Time of Watchdog Timer ....................................................................................134

9-2 Interval Time ..............................................................................................................................................134

9-3 Configuration of Watchdog Timer...............................................................................................................135

9-4 Program Loop Detection Time of Watchdog Timer ....................................................................................138

9-5 Interval Time of Interval Timer....................................................................................................................139

10-1 Configuration of 8-Bit A/D Converter ..........................................................................................................140

11-1 Configuration of 10-Bit A/D Converter ........................................................................................................153

12-1 INTCMP0 Valid Edges ...............................................................................................................................169

13-1 Configuration of Serial Interface 00 ............................................................................................................172

22 User’s Manual U13952EJ3V1UD

LIST OF TABLES (2/2)

Table No. Title Page

13-2 Operation Mode Settings of Serial Interface 00..........................................................................................178

13-3 Example of Relationship Between Main System Clock and Baud Rate......................................................181

13-4 Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC00 Is Set to 80H)...........182

13-5 Example of Relationship Between Main System Clock and Baud Rate......................................................189

13-6 Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC00 Is Set to 80H)...........190

13-7 Receive Error Causes ................................................................................................................................195

14-1 Maximum Number of Pixels........................................................................................................................202

14-2 Configuration of LCD Controller/Driver .......................................................................................................203

14-3 Frame Frequencies (Hz).............................................................................................................................207

14-4 COM Signals ..............................................................................................................................................209

14-5 LCD Drive Voltage......................................................................................................................................210

14-6 LCD Drive Voltages (with On-Chip Voltage Divider Resistors) ...................................................................213

14-7 Select and Deselect Voltages (COM0) .......................................................................................................215

14-8 Select and Deselect Voltages (COM0 and COM1).....................................................................................218

14-9 Select and Deselect Voltages (COM0 to COM2)........................................................................................221

14-10 Select and Deselect Voltages (COM0 to COM3)........................................................................................225

15-1 Interrupt Source List ...................................................................................................................................229

15-2 Flags Corresponding to Interrupt Request Signal Name ............................................................................231

15-3 Time from Generation of Maskable Interrupt Request to Servicing ............................................................240

16-1 HALT Mode Operating Status ....................................................................................................................246

16-2 Operation After Release of HALT Mode .....................................................................................................248

16-3 STOP Mode Operating Status....................................................................................................................249

16-4 Operation After Release of STOP Mode ....................................................................................................251

17-1 Hardware Status After Reset......................................................................................................................254

18-1 Differences Between

PD78F9418A and Mask ROM Versions .................................................................256

18-2 Communication Mode List ..........................................................................................................................258

18-3 Pin Connection List.....................................................................................................................................260

19-1 Selection of Mask Option for Pins ..............................................................................................................267

19-2 Combination of Selectable Voltage Division Resistor .................................................................................267

20-1 Operand Identifiers and Description Methods.............................................................................................268

24-1 Surface Mounting Type Soldering Conditions.............................................................................................298

User’s Manual U13952EJ3V1UD 23

CHAPTER 1 GENERAL

1.1 Features

• ROM and RAM capacities

Item Program Memory Data Memory

Part Number

Internal High-Speed

RAM

LCD Data RAM

PD789405A, 789415A ROM 12 KB 512 bytes 28 × 4 bits

PD789406A, 789416A 16 KB

PD789407A, 789417A 24 KB

PD78F9418A Flash memory 32 KB

• Minimum instruction execution time can be changed from high speed (0.4

s: @ 5.0 MHz operation with main

system clock) to ultra low speed (122

s: @ 32.768 kHz operation with subsystem clock)

• 43 I/O ports

• Serial interface channel: Switchable between 3-wire serial I/O and UART modes

• LCD controller/driver:

• Up to 28 segment signal outputs

• Up to 4 common signal outputs

• Bias switchable between 1/2 and 1/3

• Seven A/D converters with an 8-bit resolution (for

PD789407A Subseries only)

• Seven A/D converters with a 10-bit resolution (for

PD789417A Subseries only)

• Six timers:

• 16-bit timer

• Two 8-bit timer/event counters

• 8-bit timer

• Watch timer

• Watchdog timer

• 17 vectored interrupt sources

• Power supply voltage: VDD = 1.8 to 5.5 V

• Operating ambient temperature: TA = –40 to +85°C

1.2 Applications

APS compact cameras, manometers, rice cookers, etc.

CHAPTER 1 GENERAL

24 User’s Manual U13952EJ3V1UD

1.3 Ordering Information

Part Number Package Internal ROM

PD789405AGC-xxx-8BT 80-pin plastic QFP (14 x 14) Mask ROM

PD789405AGK-xxx-9EU 80-pin plastic TQFP (fine pitch) (12 x 12) Mask ROM

PD789406AGC-xxx-8BT 80-pin plastic QFP (14 x 14) Mask ROM

PD789406AGK-xxx-9EU 80-pin plastic TQFP (fine pitch) (12 x 12) Mask ROM

PD789407AGC-xxx-8BT 80-pin plastic QFP (14 x 14) Mask ROM

PD789407AGK-xxx-9EU 80-pin plastic TQFP (fine pitch) (12 x 12) Mask ROM

PD789415AGC-xxx-8BT 80-pin plastic QFP (14 x 14) Mask ROM

PD789415AGK-xxx-9EU 80-pin plastic TQFP (fine pitch) (12 x 12) Mask ROM

PD789416AGC-xxx-8BT 80-pin plastic QFP (14 x 14) Mask ROM

PD789416AGK-xxx-9EU 80-pin plastic TQFP (fine pitch) (12 x 12) Mask ROM

PD789417AGC-xxx-8BT 80-pin plastic QFP (14 x 14) Mask ROM

PD789417AGK-xxx-9EU 80-pin plastic TQFP (fine pitch) (12 x 12) Mask ROM

PD78F9418AGC-8BT 80-pin plastic QFP (14 x 14) Flash memory

PD78F9418AGK-9EU 80-pin plastic TQFP (fine pitch) (12 x 12) Flash memory

PD789405AGC-xxx-8BT-A 80-pin plastic QFP (14 x 14) Mask ROM

PD789405AGK-xxx-9EU-A 80-pin plastic TQFP (fine pitch) (12 x 12) Mask ROM

PD789406AGC-xxx-8BT-A 80-pin plastic QFP (14 x 14) Mask ROM

PD789406AGK-xxx-9EU-A 80-pin plastic TQFP (fine pitch) (12 x 12) Mask ROM

PD789407AGC-xxx-8BT-A 80-pin plastic QFP (14 x 14) Mask ROM

PD789407AGK-xxx-9EU-A 80-pin plastic TQFP (fine pitch) (12 x 12) Mask ROM

PD789415AGC-xxx-8BT-A 80-pin plastic QFP (14 x 14) Mask ROM

PD789415AGK-xxx-9EU-A 80-pin plastic TQFP (fine pitch) (12 x 12) Mask ROM

PD789416AGC-xxx-8BT-A 80-pin plastic QFP (14 x 14) Mask ROM

PD789416AGK-xxx-9EU-A 80-pin plastic TQFP (fine pitch) (12 x 12) Mask ROM

PD789417AGC-xxx-8BT-A 80-pin plastic QFP (14 x 14) Mask ROM

PD789417AGK-xxx-9EU-A 80-pin plastic TQFP (fine pitch) (12 x 12) Mask ROM

PD78F9418AGC-8BT-A 80-pin plastic QFP (14 x 14) Flash memory

PD78F9418AGK-9EU-A 80-pin plastic TQFP (fine pitch) (12 x 12) Flash memory

Remarks 1. xxx indicates ROM code suffix.

2. Products that have the part numbers suffixed by "-A" are lead-free products.

CHAPTER 1 GENERAL

User’s Manual U13952EJ3V1UD 25

1.4 Pin Configuration (Top View)

• 80-pin plastic QFP (14 x 14)

• 80-pin plastic TQFP (fine pitch) (12 x 12)

DD1

BIAS

LC0

LC1

LC2

SS1

COM0

COM1

COM2

COM3

P50

P51

P52

P53

P20/SCK/ASCK

P21/SO/TxD

P22/SI/RxD

P23/CMPTOUT0/TO2

P24/INTP0/TI0

P25/INTP1/TI1

P26/INTP2/TO5

P27/INTP3/CPT5

P60/ANI0/CMPIN0

P61/ANI1/CMPREF0

P62/ANI2

P63/ANI3

P64/ANI4

P65/ANI5

P66/ANI6

S10

S11

S12

S13

S14

S15

P93/S16

P92/S17

P91/S18

P90/S19

P87/S20

P86/S21

P85/S22

P84/S23

P83/S24

P82/S25

P81/S26

P80/S27

REF

P40/KR0

P41/KR1

P42/KR2

P43/KR3

P44/KR4

P45/KR5

IC (V

)

XT1

XT2

DD0

SS0

RESET

P46

P47

P00

P01

P02

P03

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.

2. Connect the AVDD pin to VDD0.

3. Connect the AVSS pin to VSS0.

Remark The parenthesized values apply to the

PD78F9418A.

CHAPTER 1 GENERAL

26 User’s Manual U13952EJ3V1UD

ANI0 to ANI6: Analog input P60 to P66: Port 6

ASCK: Asynchronous serial input P80 to P87: Port 8

AVDD: Analog power supply P90 to P93: Port 9

AVREF: Analog reference voltage RESET: Reset

AVSS: Analog ground RxD: Receive data

BIAS: LCD power supply bias control S0 to S27: Segment output

CMPIN0: Comparator input SCK: Serial clock

CMPREF0: Comparator reference SI: Serial input

CMPTOUT0: Comparator output SO: Serial output

COM0 to COM3: Common output TI0, TI1: Timer input

CPT5: Capture trigger input TO2, TO5: Timer output

IC: Internally connected TxD: Transmit data

INTP0 to INTP3: Interrupt from peripherals VDD0, VDD1: Power supply

KR0 to KR5: Key return VLC0 to VLC2: LCD power supply

P00 to P03: Port 0 VPP: Programming power supply

P20 to P27: Port 2 VSS0, VSS1: Ground

P40 to P47: Port 4 X1, X2: Crystal (main system clock)

P50 to P53: Port 5 XT1, XT2: Crystal (subsystem clock)

CHAPTER 1 GENERAL

User’s Manual U13952EJ3V1UD 27

1.5 78K/0S Series Lineup

The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.

52-pin SIO + resistance division method LCD (24 × 4)

8-bit A/D + internal voltage boosting method LCD (23 × 4)

PD789327

LCD drive

80-pin

PD789436

PD789446

PD789426

PD789456

PD789417A

PD789407A

PD789316

PD789467

PD789306

PD789426 with 10-bit A/D

PD789860 with enhanced timer function, SIO, and expanded ROM and RAM

PD789446 with 10-bit A/D

SIO + 8-bit A/D + resistance division method LCD (28 × 4)

SIO + 8-bit A/D + internal voltage boosting method LCD (15 × 4)

PD789407A with 10-bit A/D

SIO + 8-bit A/D + internal voltage boosting method LCD (5 × 4)

RC oscillation version of PD789306

SIO + internal voltage boosting method LCD (24 × 4)

64-pin

52-pin

64-pin

SIO + 10-bit A/D + internal voltage boosting method LCD (28 × 4)

80-pin

SIO + 8-bit A/D + resistance division method LCD (28 × 4)

80-pin PD789479

PD789489

64-pin

Products under

development

Products in mass

production

Small-scale package, general-purpose applications

78K/0S

Series

28-pin

PD789014 with enhanced timer function and expanded ROM and RAM

On-chip UART and capable of low-voltage (1.8 V) operation

PD789074 with subsystem clock added

Inverter control

44-pin PD789842 On-chip inverter controller and UART

PD789146

PD789156

44-pin

Small-scale package, general-purpose applications and A/D function

44-pin

30-pin

PD789124A

PD789134A

PD789177

PD789167

30-pin

PD789104A

PD789114A

PD789167 with 10-bit A/D

PD789104A with enhanced timer function

PD789124A with 10-bit A/D

RC oscillation version of PD789104A

PD789104A with 10-bit A/D

PD789026 with 8-bit A/D and multiplier added

PD789104A with EEPROM

added

PD789146 with 10-bit A/D

PD789177Y

PD789167Y

Y subseries supports SMB.

USB

88-pin PD789830

PD789835

144-pin

UART + dot LCD (40 × 16)

UART + 8-bit A/D + dot LCD (total display outputs: 96)

42-/44-pin

44-pin

30-pin

20-pin

PD789026 with enhanced timer function

RC oscillation version of PD789052

VFD drive

52-pin

64-pin

PD789871 On-chip VFD controller (total display outputs: 25)

Meter control

PD789881 UART + resistance division method LCD (26 × 4)

30-pin PD789074 with enhanced timer function and expanded ROM and RAM

44-pin PD789800 For PC keyboard. On-chip USB function

Keyless entry

20-pin

30-pin

On-chip POC and key return circuit

RC oscillation version of PD789860

On-chip bus controller

30-pin PD789850 On-chip CAN controller

µµ

PD789074

PD789088

PD789062

PD789014

PD789046

PD789026

PD789052

PD789860

PD789861

PD789862

PD789860 without EEPROM

, POC, and LVI

µµ

Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some

documents, but the functions of the two are the same.

CHAPTER 1 GENERAL

28 User’s Manual U13952EJ3V1UD

The major functional differences between the subseries are listed below.

Series for general-purpose applications and LCD drive

Timer VDD Function

Subseries

ROM

Capacity

(Bytes) 8-Bit 16-Bit Watch WDT

8-Bit

A/D

10-Bit

A/D

Serial Interface I/O

MIN.Value

Remarks

PD789046 16 K 1 ch

PD789026 4 K to 16 K

1 ch 34

PD789088

16 K to 32 K

3 ch

PD789074 2 K to 8 K 1 ch

1 ch

PD789014 2 K to 4 K 2 ch −

−

1 ch − − 1 ch (UART: 1 ch)

1.8 V −

PD789062 4 K − 14 RC-oscillation

version

Small-

scale

package,

general-

purpose

applica-

tions

PD789052 −

PD789177 − 8 ch

PD789167

16 K to 24 K

3 ch 1 ch

8 ch −

31 −

PD789156 − 4 ch

PD789146

8 K to 16 K

4 ch −

On-chip

EEPROM

PD789134A − 4 ch

PD789124A 4 ch −

RC-oscillation

version

PD789114A − 4 ch

Small-

scale

package,

general-

purpose

applica-

tions +

A/D

converter

PD789104A

2 K to 8 K

1 ch

−

1 ch

4 ch −

1 ch (UART: 1 ch)

1.8 V

−

PD789835

24 K to 60 K

6 ch − 3 ch 37 1.8 VNote

PD789830 24 K 1 ch

− 1 ch (UART: 1 ch)

30 2.7 V

Dot LCD

supported

PD789489

32 K to 48 K

−

8 ch

PD789479

24 K to 48 K

8 ch −

2 ch (UART: 1 ch) 45

PD789417A − 7 ch

PD789407A

12 K to 24 K

3 ch

1 ch

1 ch 1 ch

7 ch −

1 ch (UART: 1 ch) 43

1.8 V −

PD789456 − 6 ch

PD789446 6 ch −

PD789436 − 6 ch

PD789426

12 K to 16 K

6 ch

PD789316 RC-oscillation

version

PD789306

8 K to 16 K

− 2 ch (UART: 1 ch) 23

PD789467 1 ch − 18

LCD

drive

PD789327

4 K to 24 K

2 ch

−

1 ch 21

−

Note Flash memory version: 3.0 V

CHAPTER 1 GENERAL

User’s Manual U13952EJ3V1UD 29

Series for ASSP

Timer VDD Function

Subseries

ROM

Capacity

(Bytes) 8-Bit 16-Bit Watch WDT

8-Bit

A/D

10-Bit

A/D

Serial Interface I/O

MIN.Value

Remarks

USB

PD789800 8 K 2 ch − − 1 ch − − 2 ch (USB: 1 ch) 31 4.0 V −

Inverter

control

PD789842 8 K to 16 K 3 ch Note 1 1 ch 1 ch 8 ch − 1 ch (UART: 1 ch) 30 4.0 V −

On-chip

bus

controller

PD789850 16 K 1 ch 1 ch − 1 ch 4 ch − 2 ch (UART: 1 ch) 18 4.0 V −

PD789861 1.8 V RC-oscillation

version,

on-chip

EEPROM

PD789860

4 K 2 ch − − 1 ch − − − 14

Keyless

entry

PD789862 16 K 1 ch 2 ch 1 ch (UART: 1 ch) 22

On-chip

EEPROM

VFD

drive

PD789871 4 K to 8 K 3 ch − 1 ch 1 ch − − 1 ch 33 2.7 V −

Meter

control

PD789881 16 K

2 ch 1 ch − 1 ch − − 1 ch (UART: 1 ch) 28 2.7 VNote 2 −

Notes 1. 10-bit timer: 1 channel

2. Flash memory version: 3.0 V

CHAPTER 1 GENERAL

30 User’s Manual U13952EJ3V1UD

1.6 Block Diagram

78K/0S

CPU core

ROM

(flash

memory)

RAM

DD0

DD1

SS0

SS1

)

TI0/P24 8-bit timer

event/counter 00 P00 to P03

Port 0

P20 to P27

Port 2

P40 to P47Port 4

P50 to P53

Port 5

P60 to P66

Port 6

P80 to P87

Port 8

P90 to P93

Port 9

System control

TI1/P25 8-bit timer

event/counter 01

TO2/P23 8-bit timer 02

TO5/P26

CPT5/P27 16-bit timer 50

Watch timer

Watchdog timer

Serial

interface

SCK/ASCK/P20

SI/RxD/P22

SO/TxD/P21

Comparator

CMPTOUT0/P23

CMPREF0/P61

CMPIN0/P60

A/D converter

ANI0/P60

ANI2/P62 to

ANI6/P66

ANI1/P61

REF

LC0

to V

LC2

BIAS

S0 to S15

S16/P93 to S19/P90

S20/P87 to S27/P80

COM0 to COM3

LCD

controller/driver

RESET

XT1

XT2

Interrupt

control

INTP0/P24

INTP1/P25

INTP2/P26

INTP3/P27

KR0/P40 to KR5/P45

Remarks 1. The internal ROM capacity varies depending on the product.

2. The parenthesized values apply to the

PD78F9418A.

CHAPTER 1 GENERAL

User’s Manual U13952EJ3V1UD 31

1.7 Overview of Functions

Part Number

Item

PD789405A

PD789415A

PD789406A

PD789416A

PD789407A

PD789417A

PD78F9418A

Internal memory ROM Mask ROM Flash memory

12 KB 16 KB 24 KB 32 KB

High-speed RAM 512 bytes

LCD data RAM 28 × 4 bits

Minimum instruction execution time • 0.4/1.6

s (@ 5.0 MHz operation with main system clock)

• 122

s (@ 32.768 kHz operation with subsystem clock)

General-purpose registers 8 bits × 8 registers

Instruction set • 16-bit operations

• Bit manipulation (set, reset, and test)

I/O ports Total of 43 port pins

• 7 CMOS input pins

• 32 CMOS I/O pins

• 4 N-ch open-drain pins (12 V withstanding voltage)

A/D converters • Seven channels with 8-bit resolution (for

PD789407A Subseries)

• Seven channels with 10-bit resolution (for

PD789417A Subseries)

Comparator With timer output control function

Serial interface Switchable between 3-wire serial I/O and UART modes

LCD controller/driver • Up to 28 segment signal outputs

• Up to 4 common signal outputs

• Bias switchable between 1/2 and 1/3

Timers • 16-bit timer: 1 channel

• 8-bit timer: 1 channel

• 8-bit timer/event counters: 2 channels

• Watch timer: 1 channel

• Watchdog timer: 1 channel

Timer output 2 outputs

Maskable Internal: 11, external: 5

Non-maskable Internal: 1

Power supply voltage VDD = 1.8 to 5.5 V

Operating ambient temperature TA = −40 to +85°C

Package • 80-pin plastic QFP (14 x 14)

• 80-pin plastic TQFP (fine pitch) (12 x 12)

Vectored interrupt

sources

CHAPTER 1 GENERAL

32 User’s Manual U13952EJ3V1UD

An outline of the timer is shown below.

16-Bit

Timer 50

8-Bit

Timer/Event

Counters 00, 01

8-Bit

Timer 02

Watch Timer Watchdog

Timer

Interval timer – 1 channel 1 channel 1 channelNote 1 1 channelNote 2 Operation

mode External event

counter

– 1 channel – – –

Timer outputs 1 – 1 – –

Square-wave

outputs

– – 1 – –

Capture 1 input – – – –

Function

Interrupt

sources

1 1 1 2 2

Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.

2. The watchdog timer has watchdog timer and interval timer functions. However, use the watchdog timer

by selecting either the watchdog timer function or interval timer function.

User’s Manual U13952EJ3V1UD 33

CHAPTER 2 PIN FUNCTIONS

2.1 List of Pin Functions

(1) Port pins

Pin Name I/O Function After Reset Alternate Function

P00 to P03 I/O Port 0.

4-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, use of an on-chip pull-up resistor

can be specified by setting pull-up resistor option register 0

(PU0).

Input −

P20 SCK/ASCK

P21 SO/TxD

P22 SI/RxD

P23 CMPTOUT0/TO2

P24 INTP0/TI0

P25 INTP1/TI1

P26 INTP2/TO5

P27

I/O Port 2.

8-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, use of an on-chip pull-up resistor

can be specified by setting pull-up resistor option register 1

(PU1).

Input

INTP3/CPT5

P40 to P45 KR0 to KR5

P46, P47

I/O Port 4.

8-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, use of an on-chip pull-up resistor

can be specified by setting pull-up resistor option register 0

(PU0).

Input

−

P50 to P53 I/O Port 5.

4-bit N-ch open-drain I/O port.

Input/output can be specified in 1-bit units.

For a mask ROM version, use of an on-chip pull-up resistor can

be specified by the mask option.

Input −

P60 ANI0/CMPIN0

P61 ANI1/CMPREF0

P62 to P66

Input Port 6.

7-bit input port.

Input

ANI2 to ANI6

P80 to P87 I/O Port 8.

8-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, use of an on-chip pull-up resistor

can be specified by setting pull-up resistor option register 2

(PU2).

Input S27 to S20

P90 to P93 I/O Port 9.

4-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, use of an on-chip pull-up resistor

can be specified by setting pull-up resistor option register 2

(PU2).

Input S19 to S16

CHAPTER 2 PIN FUNCTIONS

34 User’s Manual U13952EJ3V1UD

(2) Non-port pins (1/2)

Pin Name I/O Function After Reset Alternate Function

INTP0 P24/TI0

INTP1 P25/TI1

INTP2 P26/TO5

INTP3

Input External interrupt input for which the valid edge (rising edge,

falling edge, or both rising and falling edges) can be specified

Input

P27/CPT5

KR0 to KR5 Input Key return signal detection Input P40 to P45

SI Input Serial interface serial data input Input P22/RxD

SO Output Serial interface serial data output Input P21/TxD

SCK I/O Serial interface serial clock input/output Input P20/ASCK

ASCK Input Serial clock input for asynchronous serial interface Input P20/SCK

RxD Input Serial data input for asynchronous serial interface Input P22/SI

TxD Output Serial data output for asynchronous serial interface Input P21/SO

TI0 Input External count clock input to 8-bit timer (TM00) Input P24/INTP0

TI1 Input External count clock input to 8-bit timer (TM01) Input P25/INTP1

TO2 Output 8-bit timer (TM02) output Input P23/CMPTOUT0

TO5 Output 16-bit timer (TM50) output Input P26/INTP2

CPT5 Input Capture edge input Input P27/INTP3

CMPTOUT0 Output Comparator output Input P23/TO2

CMPIN0 Input Comparator input Input P60/ANI0

CMPREF0 Input Comparator reference voltage input Input P61/ANI1

ANI0 Input A/D converter analog input Input P60/CMPIN0

ANI1 P61/CMPREF0

ANI2 to ANI6 P62 to P66

AVREF − A/D converter reference voltage − •−•

AVSS − A/D converter ground potential − •−•

AVDD − A/D converter analog power supply − •−•

S0 to S15 Output LCD controller/driver segment signal output Output •−•

S16 to S19 Input P93 to P90

S20 to S27 P87 to P80

COM0 to COM3 Output LCD controller/driver common signal output Output −

VLC0 to VLC2 − LCD driving voltage − •−•

BIAS − Supply voltage for LCD driving − •−•

X1 Input Connecting crystal resonator for main system clock oscillation − •−•

X2 − − •−•

XT1 Input Connecting crystal resonator for subsystem clock oscillation − •−•

XT2 − − •−•

RESET Input System reset input Input •−•

CHAPTER 2 PIN FUNCTIONS

User’s Manual U13952EJ3V1UD 35

(2) Non-port pins (2/2)

Pin Name I/O Function After Reset Alternate Function

VDD0 − Positive power supply for ports − •−•

VDD1 − Positive power supply for circuits other than ports − •−•

VSS0 − Ground potential for ports − •−•

VSS1 − Ground potential of circuits other than ports − •−•

IC − Internally connected. Connect directly to VSS0 or VSS1. − •−•

VPP − Sets flash memory programming mode.

Applies high voltage when a program is written or verified.

− •−•

CHAPTER 2 PIN FUNCTIONS

36 User’s Manual U13952EJ3V1UD

2.2 Description of Pin Functions

2.2.1 P00 to P03 (Port 0)

These pins constitute a 4-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode

up resistor option register 0 (PU0).

2.2.2 P20 to P27 (Port 2)

These pins constitute an 8-bit I/O port. In addition to I/O port pins, these pins can also function as the data and

clock I/O of the serial interface, external interrupt input, and timer I/O.

The following operation modes can be specified in 1-bit units.

(1) Port mode

In this mode, P20 to P27 function as an 8-bit I/O port. These pins can be set to input or output mode in 1-bit

units by using port mode register 2 (PM2). When used as input port pins, an on-chip pull-up resistor can be

used by setting pull-up resistor option register 1 (PU1).

(2) Control mode

In this mode, P20 to P27 function as the data I/O and the clock I/O of the serial interface, the external

interrupt input, and timer I/O.

(a) SI, SO

These are the serial data I/O pins of the serial interface.

(b) SCK

This is the serial clock I/O pin of the serial interface.

These are the serial data I/O pins of the asynchronous serial interface.

(d) ASCK

This is the serial clock input pin of the asynchronous serial interface.

(e) TI0, TI1

These are external clock input pins for the 8-bit timer/event counter.

(f) TO2

This is the output pin of the 8-bit timer.

(g) TO5

This is the output pin of the 16-bit timer.

(h) CPT5

This is the capture edge input pin.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U13952EJ3V1UD 37

(i) INTP0 to INTP3

These are external interrupt input pins for which a valid edge (rising edge, falling edge, or both rising

and falling edges) can be specified.

(j) CMPTOUT0

This is the comparator output pin.

Caution When using P20 to P27 as serial interface pins, the I/O mode and output latch must be set

according to the function to be used. For details of the setting, refer to Table 13-2.

2.2.3 P40 to P47 (Port 4)

These pins constitute an 8-bit I/O port. In addition to I/O port pins, these pins can also function as key return

signal detection pins.

The following operation modes can be specified in 1-bit units.

(1) Port mode

In this mode, P40 to P47 function as an 8-bit I/O port. These pins can be set to input or output mode in 1-bit

units by using port mode register 4 (PM4). When used as input port pins, an on-chip pull-up resistor can be

used by setting pull-up resistor option register 0 (PU0).

(2) Control mode

In this mode, the pins function as key return signal detection pins (KR0 to KR5).

2.2.4 P50 to P53 (Port 5)

These pins constitute a 4-bit N-channel open-drain I/O port. In the mask ROM version, it is possible to specify that

pull-up resistors be used, via a mask option.

2.2.5 P60 to P66 (Port 6)

These pins constitute a 7-bit input-only port. In addition to general-purpose input port pins, these pins can also

function as A/D converter analog input pins and comparator input pins.

(1) Port mode

In this port mode, P60 to P66 function as a 7-bit input-only port.

(2) Control mode

In this mode, the pins can be used as A/D converter analog inputs and comparator inputs.

(a) ANI0 to ANI6

These are the A/D converter analog input pins.

(b) CMPIN0

This is the comparator input pin.

This is the comparator reference voltage input pin.

CHAPTER 2 PIN FUNCTIONS

38 User’s Manual U13952EJ3V1UD

2.2.6 P80 to P87 (Port 8)

These pins constitute an 8-bit I/O port. In addition to I/O port pins, these pins can also function as LCD

controller/driver segment signal.

The following operation modes can be specified in 1-bit units.

(1) Port mode

In this port mode, P80 to P87 function as an 8-bit I/O port. These pins can be set to input or output mode in

1-bit units by using port mode register 8 (PM8). When used as an input port pins, an on-chip pull-up resistor

can be used by setting pull-up resistor option register 2 (PU2).

(2) Control mode

In this mode, P80 to P87 function as segment signal output pins (S20 to S27) for the LCD controller/driver.

2.2.7 P90 to P93 (Port 9)

These pins constitute a 4-bit I/O port. In addition to I/O port pins, these pins can also function as LCD

controller/driver segment signal.

The following operation modes can be specified in 1-bit units.

(1) Port mode

In this mode, P90 to P93 function as a 4-bit I/O port. These pins can be set to input or output mode in 1-bit

units by using port mode register 9 (PM9). When used as input port pins, an on-chip pull-up resistor can be

used by setting pull-up resistor option register 2 (PU2).

(2) Control mode

In this mode, P90 to P93 function as segment signal output pins (S16 to S19) for the LCD controller/driver.

2.2.8 S0 to S15

These pins are segment signal output pins for the LCD controller/driver.

2.2.9 COM0 to COM3

These pins are common signal output pins for the LCD controller/driver.

2.2.10 VLC0 to VLC2

These pins are power supply voltage pins to drive the LCD.

2.2.11 BIAS

This pin supplies power to drive the LCD.

2.2.12 AVREF

This pin is the A/D converter reference voltage pin. Connect it to VDD0, VDD1, VSS0, or VSS1 when not using the A/D

converter.

2.2.13 AVDD

This pin is the A/D converter analog circuit power supply pin. Always keep it at the same potential as the VDD0 pin

(even when the A/D converter is not used).

CHAPTER 2 PIN FUNCTIONS

User’s Manual U13952EJ3V1UD 39

2.2.14 AVSS

This pin is the A/D converter ground potential pin. Always keep it at the same potential as the VSS0 pin (even when

the A/D converter is not used).

2.2.15 RESET

This pin inputs an active-low system reset signal.

2.2.16 X1, X2

These pins are used to connect a crystal resonator for main system clock oscillation.

To supply an external clock, input the clock to X1 and input the inverted signal to X2.

2.2.17 XT1, XT2

These pins are used to connect a crystal resonator for subsystem clock oscillation.

To supply an external clock, input the clock to XT1 and input the inverted signal to XT2.

2.2.18 VDD0, VDD1

VDD0 is the positive power supply pin for ports, while VDD1 is the positive power supply pin for other than ports.

2.2.19 VSS0, VSS1

VSS0 is the ground potential pin for ports, while the VSS1 is the ground potential pin for other than ports.

2.2.20 VPP (

PD78F9418A only)

A high voltage should be applied to this pin when the flash memory programming mode is set and when the

program is written or verified.

Handle the pins in either of the following ways.

• Independently connect a 10 kΩ pull-down resistor.

• Switch this pin to be directly connected to the dedicated flash programmer in programming mode or to VSS0 or

VSS1 in normal operation mode using a jumper on the board.

If the wiring between the VPP pin and VSS0 or VSS1 pin is long, or external noise is superimposed on the VPP pin, the

user program may not run correctly.

CHAPTER 2 PIN FUNCTIONS

40 User’s Manual U13952EJ3V1UD

2.2.21 IC (mask ROM version only)

The IC (internally connected) pin is used to set the

PD789407A and

PD789417A Subseries in the test mode

before shipment. In the normal operation mode, directly connect this pin to the VSS0 or VSS1 pin with as short a wiring

length as possible.

If a potential difference is generated between the IC pin and VSS0 or VSS1 pin due to a long wiring length between

these pin, or due to external noise superimposed on the IC pin, the user program may not run correctly.

• Directly connect the IC pin to the VSS0 or VSS1 pin.

SS0

SS1

Keep short

CHAPTER 2 PIN FUNCTIONS

User’s Manual U13952EJ3V1UD 41

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.

For the I/O circuit configuration of each type, see Figure 2-1.

Table 2-1. Types of Pin I/O Circuits

Pin Name I/O Circuit

Type

I/O Recommended Connection of Unused Pins

P00 to P03 5-H

P20/SCK/ASCK

P21/SO/TxD

P22/SI/RxD

8-C

P23/CMPTOUT0/TO2 10-B

Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor.

Output: Leave open.

P24/INTP0/TI0

P25/INTP1/TI1

P26/INTP2/TO5

P27/INTP3/CPT5

Input: Independently connect to VSS0 or VSS1 via a resistor.

Output: Leave open.

P40/KR0 to P45/KR5

8-C

P46, P47 5-H

Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor.

Output: Leave open.

P50 to P53 (Mask ROM version) 13-U

P50 to P53 (

PD78F9418A) 13-T

I/O

Input: Independently connect to VDD0 or VDD1 via a resistor.

Output: Leave open.

P60/ANI0/CMPIN0

P61/ANI1/CMPREF0

9-D

P62/ANI2 to P66/ANI6 9-C

Input Connect directly to VDD0, VDD1, VSS0, or VSS1.

P80/S27 to P87/S20

P90/S19 to P93/S16

17-F I/O Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor.

Output: Leave open.

S0 to S15 17-B

COM0 to COM3 18-A

Output

VLC0 to VLC2

Leave open.

BIAS Leave open. However, independently connect to VSS0 or VSS1 via a resistor

when none of VLC0 to VLC2 are used.

AVDD Connect directly to VDD0 or VDD1.

AVREF Connect directly to VDD0, VDD1, VSS0, or VSS1.

AVSS

•−•

Connect directly to VSS0 or VSS1.

XT1 Input Connect directly to VSS0 or VSS1.

XT2

−

− Leave open.

RESET 2 Input −

IC (Mask ROM version) Connect directly to VSS0 or VSS1.

VPP (

PD78F9418A)

− •−•

Independently connect to a 10 kΩ pull-down resistor or connect directly

to VSS0 or VSS1.

CHAPTER 2 PIN FUNCTIONS

42 User’s Manual U13952EJ3V1UD

Figure 2-1. Pin I/O Circuits (1/2)

Type 2 Type 9-D

Schmitt-triggered input with hysteresis characteristics

–

P-ch

N-ch

Input

enable

Comparator

REF

(Threshold voltage)

Type 5-H Type 10-B

Pull-up

enable

Data

Output

disable

Input

enable

DD0

P-ch

DD0

P-ch

IN/OUT

N-ch

SS0

Pull-up

enable

Data

Open drain

Output disable

DD0

P-ch

DD0

P-ch

IN/OUT

N-ch

SS0

Type 8-C Type 13-T

Pull-up

enable

Data

Output

disable

VDD0

P-ch

VDD0

P-ch

IN/OUT

N-ch

VSS0

SS0

Data

Output disable

IN/OUT

N-ch

Middle-voltage

input buffer

Input

enable

Type 9-C Type 13-U

Comparator

–

REF

(Threshold voltage)

P-ch

N-ch

Input

enable

SS0

Output data

Output disable

IN/OUT

DD0

N-ch

Middle-voltage

input buffer

Input enable

Pull-up resistor

(mask option)

CHAPTER 2 PIN FUNCTIONS

User’s Manual U13952EJ3V1UD 43

Figure 2-1. Pin I/O Circuits (2/2)

Type 17-B Type 17-F

P-ch

LC0

LC1

N-ch

P-ch

N-ch

LC2

SS1

SEG

data

P-ch

OUT

N-ch

Type 18-A

COM

data

OUT

P-ch

VLC0

VLC1 N-ch

VLC2

VSS1

P-ch

N-ch

P-ch

N-ch

P-ch

VLC0

VLC1

VLC2

VSS1

SEG

data P-ch

N-ch

Data

Output

disable

P-ch

VDD0

VSS0

N-ch

SEG

output

disable

Input

enable

P-ch

VDD0

Pull-up

enable

IN/OUT

44 User’s Manual U13952EJ3V1UD

CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

The

PD789407A and

PD789417A Subseries can access 64 KB of memory space. Figures 3-1 through 3-4

show the memory maps.

Figure 3-1. Memory Map (

PD789405A and

PD789415A)

Special function registers

256 × 8 bits

Internal high-speed RAM

512 × 8 bits

RAM space for LCD data

28 × 4 bits

Reserved

Internal ROM

12288 × 8 bits

FFFFH

FF00H

FEFFH

FD00H

FCFFH

FA00H

F9FFH

0000H

Program

memory space

Data

memory space

2FFFH

0000H

Program area

0080H

007FH

Program area

0040H

003FH

CALLT table area

0024H

0023H

Vector table area

FA1CH

FA1BH

3000H

2FFFH

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U13952EJ3V1UD 45

Figure 3-2. Memory Map (

PD789406A and

PD789416A)

Special function registers

256 × 8 bits

Internal high-speed RAM

512 × 8 bits

Internal ROM

16384 × 8 bits

FFFFH

FF00H

FEFFH

0000H

Program

memory space

Data

memory space

3FFFH

0000H

Program area

0080H

007FH

Program area

0040H

003FH

CALLT table area

0024H

0023H

Vector table area

RAM space for LCD data

28 × 4 bits

Reserved

FD00H

FCFFH

FA00H

F9FFH

FA1CH

FA1BH

4000H

3FFFH

CHAPTER 3 CPU ARCHITECTURE

46 User’s Manual U13952EJ3V1UD

Figure 3-3. Memory Map (

PD789407A and

PD789417A)

Special function registers

256 × 8 bits

Internal high-speed RAM

512 × 8 bits

Internal ROM

24576 × 8 bits

FFFFH

FF00H

FEFFH

0000H

Program

memory space

Data

memory space

5FFFH

0000H

Program area

0080H

007FH

Program area

0040H

003FH

CALLT table area

0024H

0023H

Vector table area

RAM space for LCD data

28 × 4 bits

Reserved

FD00H

FCFFH

FA00H

F9FFH

FA1CH

FA1BH

6000H

5FFFH

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U13952EJ3V1UD 47

Figure 3-4. Memory Map (

PD78F9418A)

Special function registers

256 × 8 bits

Internal high-speed RAM

512 × 8 bits

Flash memory

32768 × 8 bits

FFFFH

FF00H

FEFFH

0000H

Program

memory space

Data

memory space

7FFFH

0000H

Program area

0080H

007FH

Program area

0040H

003FH

CALLT table area

0024H

0023H

Vector table area

RAM space for LCD data

28 × 4 bits

Reserved

FD00H

FCFFH

FA00H

F9FFH

FA1CH

FA1BH

8000H

7FFFH

CHAPTER 3 CPU ARCHITECTURE

48 User’s Manual U13952EJ3V1UD

3.1.1 Internal program memory space

The internal program memory space stores programs and table data. This space is usually addressed by the

program counter (PC).

The products in the

PD789407A and

PD789417A Subseries contain the following internal ROM (or flash

memory) capacities.

Table 3-1. Internal ROM Capacity

Part Number Internal ROM

Structure Capacity

PD789405A, 789415A Mask ROM 12288 × 8 bits

PD789406A, 789416A 16384 × 8 bits

PD789407A, 789417A 24576 × 8 bits

PD78F9418A Flash memory 32768 × 8 bits

The following areas are allocated to the internal program memory space.

(1) Vector table area

The 36-byte area of addresses 0000H to 0023H is reserved as a vector table area. This area stores program

start addresses to be used when branching by RESET input or interrupt request generation. Of a 16-bit

program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd

address.

Table 3-2. Vector Table

Vector Table Address Interrupt Request Vector Table Address Interrupt Request

0000H RESET input 0014H INTWTI

0004H INTWDT 0016H INTTM00

0006H INTP0 0018H INTTM01

0008H INTP1 001AH INTTM02

000AH INTP2 001CH INTTM50

000CH INTP3 001EH INTKR00

000EH INTSR00/INTCSI00 0020H INTAD0

0010H INTST00 0022H INTCMP0

0012H INTWT

(2) CALLT instruction table area

The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of

addresses 0040H to 007FH.

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U13952EJ3V1UD 49

3.1.2 Internal data memory space

The

PD789407A and

PD789417A Subseries products incorporate the following RAM:

(1) Internal high-speed RAM

An internal high-speed RAM is allocated to the area between FD00H and FEFFH.

The internal high-speed RAM is also used as a stack.

(2) LCD data RAM

An LCD data RAM is allocated to the area between FA00H and FA1BH.

The LCD display RAM can also be used as ordinary RAM.

3.1.3 Special function register (SFR) area

Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see

Table 3-3).

CHAPTER 3 CPU ARCHITECTURE

50 User’s Manual U13952EJ3V1UD

3.1.4 Data memory addressing

The

PD789407A and

PD789417A Subseries are provided with a variety of addressing modes to make memory

manipulation as efficient as possible. In the area that holds data memory (FD00H to FFFFH) especially, specific

modes of addressing that correspond to the particular function of an area, such as the special function registers (SFR)

or general-purpose registers, are available. Figures 3-5 through 3-8 show the data memory addressing modes.

Figure 3-5. Data Memory Addressing (

PD789405A and

PD789415A)

Special function registers (SFR)

256 × 8 bits

Internal high-speed RAM

512 × 8 bits

Internal ROM

12288 × 8 bits

FFFFH

0000H

Direct addressing

addressing

Based addressing

FF00H

FEFFH

FF20H

FF1FH

FE20H

FE1FH

SFR addressing

Short direct

addressing

RAM space for LCD data

28 × 4 bits

Reserved

FD00H

FCFFH

FA00H

F9FFH

3000H

2FFFH

FA1CH

FA1BH

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U13952EJ3V1UD 51

Figure 3-6. Data Memory Addressing (

PD789406A and

PD789416A)

Special function registers (SFR)

256 × 8 bits

Internal high-speed RAM

512 × 8 bits

Internal ROM

16384 × 8 bits

FFFFH

0000H

Direct addressing

addressing

Based addressing

FF00H

FEFFH

FF20H

FF1FH

FE20H

FE1FH

SFR addressing

Short direct

addressing

RAM space for LCD data

28 × 4 bits

Reserved

FD00H

FCFFH

FA00H

F9FFH

4000H

3FFFH

FA1CH

FA1BH

CHAPTER 3 CPU ARCHITECTURE

52 User’s Manual U13952EJ3V1UD

Figure 3-7. Data Memory Addressing (

PD789407A and

PD789417A)

Special function registers (SFR)

256 × 8 bits

Internal high-speed RAM

512 × 8 bits

Internal ROM

24576 × 8 bits

FFFFH

0000H

Direct addressing

addressing

Based addressing

FF00H

FEFFH

FF20H

FF1FH

FE20H

FE1FH

SFR addressing

Short direct

addressing

RAM space for LCD data

28 × 4 bits

Reserved

FD00H

FCFFH

FA00H

F9FFH

6000H

5FFFH

FA1CH

FA1BH

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U13952EJ3V1UD 53

Figure 3-8. Data Memory Addressing (

PD78F9418A)

Special function registers (SFR)

256 × 8 bits

Internal high-speed RAM

512 × 8 bits

Flash memory

32768 × 8 bits

FFFFH

0000H

Direct addressing

addressing

Based addressing

FF00H

FEFFH

FF20H

FF1FH

FE20H

FE1FH

SFR addressing

Short direct

addressing

RAM space for LCD data

28 × 4 bits

Reserved

FD00H

FCFFH

FA00H

F9FFH

8000H

7FFFH

FA1CH

FA1BH

CHAPTER 3 CPU ARCHITECTURE

54 User’s Manual U13952EJ3V1UD

3.2 Processor Registers

The

PD789407A and

PD789417A Subseries are provided with the following on-chip processor registers.

3.2.1 Control registers

The control registers contains special functions to control the program sequence statuses and stack memory. A

program counter, a program status word, and a stack pointer constitute the control registers.

(1) Program counter (PC)

The program counter is a 16-bit register that holds the address information of the next program to be

executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the instruction

to be fetched. When a branch instruction is executed, immediate data or register contents are set.

RESET input sets the program counter to the reset vector table values at addresses 0000H and 0001H.

Figure 3-9. Program Counter Configuration

015

PC14PC15PC PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set/reset by instruction

execution.

Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW

instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions.

RESET input sets the PSW to 02H.

Figure 3-10. Program Status Word Configuration

IE Z 0 AC 0 0 1 CY

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U13952EJ3V1UD 55

(a) Interrupt enable flag (IE)

This flag controls the interrupt request acknowledgment operations of the CPU.

When 0, IE is set to the interrupt disable status (DI), and all interrupt requests other than non-maskable

interrupts are disabled.

When 1, IE is set to the interrupt enable status (EI). At this time, interrupt request acknowledgment is

controlled by an interrupt mask flag corresponding to the interrupt source.

IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI

instruction execution.

(b) Zero flag (Z)

When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all

other cases.

(d) Carry flag (CY)

This flag stores an overflow or underflow upon add/subtract instruction execution. It stores the shift-out

value upon rotate instruction execution and functions as a bit accumulator during bit manipulation

instruction execution.

CHAPTER 3 CPU ARCHITECTURE

56 User’s Manual U13952EJ3V1UD

(3) Stack pointer (SP)

This is a 16-bit register used to hold the start address of the memory stack area. Only the internal high-

speed RAM area can be set as the stack area.

Figure 3-11. Stack Pointer Configuration

015

SP14SP15SP SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore)

from the stack memory.

Each stack operation saves/restores data as shown in Figures 3-12 and 3-13.

Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before

instruction execution.

Figure 3-12. Data Saved to Stack Memory

Interrupt

PSW

PC15 to PC8

PC7 to PC0

Lower

SP SP _ 2

SP _ 2

CALL, CALLT

instructions

PUSH rp

instruction

SP _ 1

SP SP _ 2

SP _ 2

SP _ 1

PC7 to PC0

SP _ 3

SP _ 2

SP _ 1

SP SP _ 3

Higher

Figure 3-13. Data Restored from Stack Memory

RETI instruction

PSW

PC15 to PC8

PC7 to PC0

Lower

RET instructionPOP rp

instruction

SP PC7 to PC0

Higher

SP + 1

SP SP + 2

SP + 1

SP SP + 2

SP + 1

SP + 2

SP SP + 3

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U13952EJ3V1UD 57

3.2.2 General-purpose registers

The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H).

Each register can be used as an 8-bit register, and two 8-bit registers can be used in pairs as a 16-bit register (AX,

BC, DE, and HL).

General-purpose registers can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and

HL) and absolute names (R0 to R7 and RP0 to RP3).

Figure 3-14. General-Purpose Register Configuration

(a) Absolute names

15 0 7 0

16-bit processing 8-bit processing

RP3

RP2

RP1

RP0

(b) Functional names

15 0 7 0

16-bit processing 8-bit processing

CHAPTER 3 CPU ARCHITECTURE

58 User’s Manual U13952EJ3V1UD

3.2.3 Special function registers (SFR)

Unlike a general-purpose register, each special function register has a special function.

SFRs are allocated in the 256-byte area FF00H to FFFFH.

A special function register can be manipulated, like a general-purpose register, using operation, transfer, and bit

manipulation instructions. The manipulatable bit unit (1, 8, or 16) differs depending on the special function register

type.

Each manipulation bit unit can be specified as follows.

• 1-bit manipulation

Describes a symbol reserved by assembler for the 1-bit manipulation instruction operand (sfr.bit). This

manipulation can also be specified by an address.

• 8-bit manipulation

Describes a symbol reserved by assembler for the 8-bit manipulation instruction operand (sfr). This

manipulation can also be specified by an address.

• 16-bit manipulation

Describes a symbol reserved by assembler for the 16-bit manipulation instruction operand. When addressing an

address, describe an even address.

Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows:

• Symbol

Indicates the address of the special function register. The symbols shown in this column are reserved words in

the assembler, and have been defined in the header file named “sfrbit.h” in the C compiler. Therefore, these

symbols can be used as instruction operands if an assembler or integrated debugger is used.

• R/W

Indicates whether the special function register in question can be read or written.

R/W: Read/write

R: Read only

W: Write only

• Manipulatable bit unit

Indicates the bit units (1, 8, 16) in which the special function register in question can be manipulated.

• After reset

Indicates the status of the special function register when the RESET signal is input.

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U13952EJ3V1UD 59

Table 3-3. Special Function Register List (1/2)

Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After Reset

1 Bit 8 Bits 16 Bits

FF00H Port 0 P0 R/W √ √ − 00H

FF02H Port 2 P2 √ √ −

FF04H Port 4 P4 √ √ −

FF05H Port 5 P5 √ √ −

FF06H Port 6 P6 R √ √ −

FF08H Port 8 P8 R/W √ √ −

FF09H Port 9 P9 √ √ −

FF10H Transmit shift register 00 TXS00 SIO00 W − √ − FFH

Receive buffer register 00 RXB00 R − √ − Undefined

FF14H A/D conversion result register 0 ADCR0 − √Note 1 √Note 2

FF15H

FF16H 16-bit compare register 50 CR50L W − − √Notes 2, 3 FFFFH

FF17H CR50H

CR50

FF18H 16-bit timer counter 50 TM50L − − √Notes 2, 3 0000H

FF19H TM50H

TM50

FF1AH 16-bit capture register 50 TCP50L − − √Notes 2, 3 Undefined

FF1BH TCP50H

TCP50

FF20H Port mode register 0 PM0 R/W √ √ − FFH

FF22H Port mode register 2 PM2 √ √ −

FF24H Port mode register 4 PM4 √ √ −

FF25H Port mode register 5 PM5 √ √ −

FF28H Port mode register 8 PM8 √ √ −

FF29H Port mode register 9 PM9 √ √ −

FF42H Timer clock selection register 2 TCL2 − √ − 00H

FF48H 16-bit timer mode control register 50 TMC50 √ √ −

FF4AH Watch timer mode control register WTM √ √ −

FF4EH Comparator mode register 0 CMPRM0 √ √ −

Notes 1. If the A/D conversion result register is used for the 8-bit A/D converter (

PD789407A Subseries), it can

be accessed only in 8-bit units. In this case, it is considered to have been mapped at address FF15H.

If the register is used for the 10-bit A/D converter (

PD789417A Subseries), it can be accessed only in

16-bit units. If the

PD78F9418A is used as the flash memory version of the

PD789405A,

PD789406A, or

PD789407A, 8-bit access is also possible, provided that the object file has been

assembled using the

PD789405A,

PD789406A, or

PD789407A.

2. 16-bit access is possible only in short direct addressing.

3. Although CR50, TM50, and TCP50 are 16-bit access dedicated registers, an 8-bit access is also

possible. When performing an 8-bit access, use direct addressing.

CHAPTER 3 CPU ARCHITECTURE

60 User’s Manual U13952EJ3V1UD

Table 3-3. Special Function Register List (2/2)

Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After Reset

1 Bit 8 Bits 16 Bits

FF50H 8-bit compare register 00 CR00 W − √ − Undefined

FF51H 8-bit timer counter 00 TM00 R − √ − 00H

FF53H 8-bit timer mode control register 00 TMC00 R/W √ √ −

FF54H 8-bit compare register 01 CR01 W − √ − Undefined

FF55H 8-bit timer counter 01 TM01 R − √ − 00H

FF57H 8-bit timer mode control register 01 TMC01 R/W √ √ −

FF58H 8-bit compare register 02 CR02 W − √ − Undefined

FF59H 8-bit timer counter 02 TM02 R − √ −

FF5BH 8-bit timer mode control register 02 TMC02 R/W √ √ −

FF70H Asynchronous serial interface mode register

ASIM00

√ √ −

FF71H Asynchronous serial interface status register

ASIS00 R

√ √ −

FF72H Serial operation mode register 00 CSIM00 R/W √ √ −

FF73H Baud rate generator control register 00 BRGC00 − √ −

FF80H A/D converter mode register 0 ADM0 √ √ −

FF84H A/D input selection register 0 ADS0 √ √ −

FFB0H LCD display mode register 0 LCDM0 √ √ −

FFB1H LCD port selector 0 LPS0 √ √ −

FFB2H LCD clock control register 0 LCDC0 √ √ −

FFE0H Interrupt request flag register 0 IF0 √ √ −

FFE1H Interrupt request flag register 1 IF1 √ √ −

00H

FFE4H Interrupt mask flag register 0 MK0 √ √ − FFH

FFE5H Interrupt mask flag register 1 MK1 √ √ −

FFECH External interrupt mode register 0 INTM0 − √ − 00H

FFEDH External interrupt mode register 1 INTM1 − √ −

FFF0H Suboscillation mode register SCKM √ √ −

FFF2H Subclock control register CSS √ √ −

FFF3H Pull-up resistor option register 1 PU1 √ √ −

FFF4H Pull-up resistor option register 2 PU2 √ √ −

FFF5H Key return mode register 00 KRM00 √ √ −

FFF7H Pull-up resistor option register 0 PU0 √ √ −

FFF9H Watchdog timer mode register WDTM √ √ −

FFFAH Oscillation stabilization time selection

OSTS

− √ − 04H

FFFBH Processor clock control register PCC √ √ − 02H

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U13952EJ3V1UD 61

3.3 Instruction Address Addressing

An instruction address is determined by program counter (PC) contents. PC contents are normally incremented

(+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another

instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and

branched by the following addressing (for details of each instruction, refer to the 78K/0S Series Instructions User’s

Manual (U11047E)).

3.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the

start address of the following instruction is transferred to the program counter (PC) and branched. The

displacement value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit.

This means that information is relatively branched to a location between −128 and +127, from the start address

of the next instruction when relative addressing is used.

This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

15 0

876

jdisp8

When S = 0, α indicates all bits 0.

... PC is the start address of

the next instruction of

a BR instruction.

When S = 1, α indicates all bits 1.

CHAPTER 3 CPU ARCHITECTURE

62 User’s Manual U13952EJ3V1UD

3.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and branched.

This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed.

The CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space.

[Illustration]

In case of CALL !addr16 and BR !addr16 instructions

15 0

CALL or BR

Low addr.

High addr.

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U13952EJ3V1UD 63

3.3.3 Table indirect addressing

[Function]

The table contents (branch destination address) of the particular location to be addressed by the lower 5-bit

immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and

branched.

This function is carried out when the CALLT [addr5] instruction is executed. The instruction enables a branch

to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH.

[Illustration]

15 1

15 0

Low addr.

High addr.

Memory (table)

Effective address + 1

Effective address 01

00000000

65 0

001

765 10

ta4–0

Instruction code

3.3.4 Register addressing

[Function]

The register pair (AX) contents to be specified with an instruction word are transferred to the program counter

(PC) and branched.

This function is carried out when the BR AX instruction is executed.

[Illustration]

15 0

CHAPTER 3 CPU ARCHITECTURE

64 User’s Manual U13952EJ3V1UD

3.4 Operand Address Addressing

The following methods are available to specify the register and memory (addressing) to undergo manipulation

during instruction execution.

3.4.1 Direct addressing

[Function]

The memory indicated with immediate data in an instruction word is directly addressed.

[Operand format]

Identifier Description

addr16 Label or 16-bit immediate data

[Description example]

MOV A, !FE00H; When setting !addr16 to FE00H

Instruction code 0 0 101001Opcode

00000000

11111110

00H

FEH

[Illustration]

Opcode

addr16 (low)

addr16 (high)

Memory











CHAPTER 3 CPU ARCHITECTURE

User’s Manual U13952EJ3V1UD 65

3.4.2 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.

The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. An internal high-

speed RAM and special function registers (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH,

respectively.

The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the whole SFR area.

Ports that are frequently accessed in a program and a compare register of the timer/event counter are mapped

in this area, and these SFRs can be manipulated with a small number of bytes and clocks.

When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,

bit 8 is set to 1. See [Illustration] below.

[Operand format]

Identifier Description

saddr Label or FE20H to FF1FH immediate data

saddrp Label or FE20H to FF1FH immediate data (even address only)

[Description example]

MOV FE30H, #50H; When setting saddr to FE30H and the immediate data to 50H

Instruction code 1 1110101

00110000

01010000

Opcode

30H (saddr-offset)

50H (Immediate data)

[Illustration]

15 0

Short direct memory

Effective

address 1111111

Opcode

saddr-offset

When 8-bit immediate data is 20H to FFH, α = 0.

When 8-bit immediate data is 00H to 1FH, α = 1.

CHAPTER 3 CPU ARCHITECTURE

66 User’s Manual U13952EJ3V1UD

3.4.3 Special function register (SFR) addressing

[Function]

A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction

word.

This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the

SFRs mapped at FF00H to FF1FH can be accessed using short direct addressing.

[Operand format]

Identifier Description

sfr Special function register name

[Description example]

MOV PM0, A; When selecting PM0 for sfr

Instruction code 11100111

00100000

[Illustration]

15 0

SFR

Effective

Address 1111111

Opcode

sfr-offset

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U13952EJ3V1UD 67

3.4.4 Register addressing

[Function]

In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose

8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.

[Operand format]

Identifier Description

r X, A, C, B, E, D, L, H

rp AX, BC, DE, HL

r and rp can be described using absolute names (R0 to R7 and RP0 to RP3) as well as functional names (X, A,

C, B, E, D, L, H, AX, BC, DE, and HL).

[Description example]

MOV A, C; When selecting the C register for r

Instruction code 00001010

00100101

INCW DE; When selecting the DE register pair for rp

Instruction code 10001000

CHAPTER 3 CPU ARCHITECTURE

68 User’s Manual U13952EJ3V1UD

3.4.5 Register indirect addressing

[Function]

In the register indirect addressing mode, memory is manipulated according to the contents of a register pair

specified as an operand. The register pair to be accessed is specified by the register pair specification code in

an instruction code.

This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier Description

− [DE], [HL]

[Description example]

MOV A, [DE]; When selecting register pair [DE]

Instruction code 0 0101011

[Illustration]

15 0

7 0

Addressed memory

contents are

transferred.

Memory address

specified with

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U13952EJ3V1UD 69

3.4.6 Based addressing

[Function]

8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is

used to address the memory. Addition is performed by expanding the offset data as a positive number to 16

bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier Description

− [HL+byte]

[Description example]

MOV A, [HL+10H]; When setting byte to 10H

Instruction code 00101101

00010000

3.4.7 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents.

This addressing method is automatically employed when the PUSH, POP, subroutine call, and return

instructions are executed or the register is saved/restored upon generation of an interrupt request.

Stack addressing can only be used to access the internal high-speed RAM area.

[Description example]

In the case of PUSH DE

Instruction code 10101010

70 User’s Manual U13952EJ3V1UD

CHAPTER 4 PORT FUNCTIONS

4.1 Function of Port

The

PD789407A and

PD789417A Subseries are provided with the ports shown in Figure 4-1, enabling various

methods of control.

Numerous other functions are provided that can be used in addition to the digital I/O port function. For more

information on these additional functions, see CHAPTER 2 PIN FUNCTIONS.

Figure 4-1. Port Types

P50

P53

P00

P03

P60

P66

P80

P87

P40

P47

P90

P93

Port 5

Port 6





















Port 9





















Port 8











Port 4











P20

P27

Port 2

Port 0











CHAPTER 4 PORT FUNCTIONS

User’s Manual U13952EJ3V1UD 71

Table 4-1. Port Functions

Pin Name I/O Function After Reset Alternate Function

P00 to P03 I/O Port 0.

4-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, use of an on-chip pull-up

resistor can be specified by setting pull-up resistor

option register 0 (PU0).

Input −

P20 SCK/ASCK

P21 SO/TxD

P22 SI/RxD

P23 CMPTOUT0/TO2

P24 INTP0/TI0

P25 INTP1/TI1

P26 INTP2/TO5

P27

I/O Port 2.

8-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, use of an on-chip pull-up

resistor can be specified by setting pull-up resistor

option register 1 (PU1).

Input

INTP3/CPT5

P40 to P45

Input KR0 to KR5

P46, P47

I/O Port 4.

8-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, use of an on-chip pull-up

resistor can be specified by setting pull-up resistor

option register 0 (PU0).

−

P50 to P53 I/O Port 5.

4-bit N-ch open-drain I/O port.

Input/output can be specified in 1-bit units.

For a mask ROM version, use of an on-chip pull-up

resistor can be specified by the mask option.

Input −

P60 Input ANI0/CMPIN0

P61 ANI1/CMPREF0

P62 to P66

Input Port 6.

7-bit input port.

ANI2 to ANI6

P80 to P87 I/O Port 8.

8-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, use of an on-chip pull-up

resistor can be specified by setting pull-up resistor

option register 2 (PU2).

Input S27 to S20

P90 to P93 I/O Port 9.

4-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, use of an on-chip pull-up

resistor can be specified by setting pull-up resistor

option register 2 (PU2).

Input S19 to S16

CHAPTER 4 PORT FUNCTIONS

72 User’s Manual U13952EJ3V1UD

4.2 Configuration of Ports

The ports consist of the following hardware.

Table 4-2. Configuration of Port

Item Configuration

Control registers Port mode registers (PMm: m = 0, 2, 4, 5, 8, 9)

Pull-up resistor option registers (PUm: m = 0 to 2)

Ports Total: 43 (input: 7, I/O: 36)

Pull-up resistors • Mask ROM version

Total: 36 (software control: 32, mask option control: 4)

• Flash memory version

Total: 32 (software control only)

4.2.1 Port 0

This is a 4-bit I/O port with an output latch. Port 0 can be specified as input or output in 1-bit units by using port

mode register 0 (PM0). When the P00 to P03 pins are used as input port pins, on-chip pull-up resistors can be

connected in 4-bit units by setting pull-up resistor option register 0 (PU0).

Port 0 is set to input mode when the RESET signal is input.

Figure 4-2 shows a block diagram of port 0.

Figure 4-2. Block Diagram of P00 to P03

Internal bus

PU0

PORT

PU00

Output latch

(P00 to P03)

PM00 to PM03

DD0

P-ch

P00 to P03

Selector

PU0: Pull-up resistor option register 0

PM: Port mode register

RD: Port 0 read signal

WR: Port 0 write signal

CHAPTER 4 PORT FUNCTIONS

User’s Manual U13952EJ3V1UD 73

4.2.2 Port 2

This is an 8-bit I/O port with an output latch. Port 2 can be specified as input or output in 1-bit units by using port

mode register 2 (PM2). When using the P20 to P27 pins as input port pins, on-chip pull-up resistors can be connected

in 1-bit units by setting pull-up resistor option register 1 (PU1).

Port 2 is also used as a data I/O and clock I/O to and from the serial interface, timer I/O, and external interrupt.

Port 2 is set to input mode when the RESET signal is input.

Figures 4-3 through 4-7 show block diagrams of port 2.

Caution When using the pins of port 2 for the serial interface, the I/O or output latch must be set

according to the function to be used. For how to set the latches, see Table 13-2 Operation Mode

Settings of Serial Interface 00.

Figure 4-3. Block Diagram of P20

Internal bus

DD0

P-ch

P20/ASCK/

SCK

PU1

PORT

PU120

Alternate

function

Output latch

(P20)

PM20

Alternate

function

Selector

PU1: Pull-up resistor option register 1

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

CHAPTER 4 PORT FUNCTIONS

74 User’s Manual U13952EJ3V1UD

Figure 4-4. Block Diagram of P21

Internal bus

DD0

P-ch

P21/TxD/

PU1

PORT

PU121

Output latch

(P21)

PM21

Alternate

function

Selector

PU1: Pull-up resistor option register 1

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

CHAPTER 4 PORT FUNCTIONS

User’s Manual U13952EJ3V1UD 75

Figure 4-5. Block Diagram of P22 and P24

Internal bus

DD0

P-ch

P22/RxD/SI

P24/INTP0/TI0

PU1

PORT

PU122, PU124

Alternate

function

Output latch

(P22, P24)

PM22, PM24

Selector

PU1: Pull-up resistor option register 1

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

CHAPTER 4 PORT FUNCTIONS

76 User’s Manual U13952EJ3V1UD

Figure 4-6. Block Diagram of P23

Internal bus

WRPU1

OPDR

PM23

Alternate

function

Alternate

function

Output latch

(P23)

PU123 P-ch

WRPORT

WRPM

VDD0

P-ch

N-ch

P23/TO2

/CMPTOUT0

Selector

OPDR: Bit 1 of comparator mode register 0, selection of N-ch open-drain output

PU1: Pull-up resistor option register 1

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

CHAPTER 4 PORT FUNCTIONS

User’s Manual U13952EJ3V1UD 77

Figure 4-7. Block Diagram of P25 to P27

Internal bus

VDD0

P25/INTP1/TI1

P26/INTP2/TO5

P27/INTP3/CPT5

WRPU1

WRPORT

WRPM

PU125 to PU127

Alternate

function

Alternate

function

Output latch

(P25 to P27)

PM25 to PM27

Selector

P-ch

PU1: Pull-up resistor option register 1

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

CHAPTER 4 PORT FUNCTIONS

78 User’s Manual U13952EJ3V1UD

4.2.3 Port 4

This is an 8-bit I/O port with an output latch. Port 4 can be specified as input or output in 1-bit units by using port

mode register 4 (PM4). When using the P40 to P47 pins as input port pins, on-chip pull-up resistors can be connected

in 8-bit units by setting pull-up resistor option register 0 (PU0).

Port 4 is also used as a key return input.

Port 4 is set to input mode when the RESET signal is input.

Figures 4-8 and 4-9 show block diagrams of port 4.

Caution When using the pins of port 4 as the key return, the key return mode register must be set

according to the function to be used. For how to set the registers, see 15.3 (6) Key return mode

Figure 4-8. Block Diagram of P40 to P45

WRKRM

Internal bus

VDD0

P40/KR0 to

P45/KR5

WRPU0

WRPORT

WRPM

PU04

Alternate

function

Output latch

(P40 to P45)

PM40 to PM45

KRM000 to

KRM005

Selector

P-ch

KRM00: Key return mode register 00

PU0: Pull-up resistor option register 0

PM: Port mode register

RD: Port 4 read signal

WR: Port 4 write signal

CHAPTER 4 PORT FUNCTIONS

User’s Manual U13952EJ3V1UD 79

Figure 4-9. Block Diagram of P46 and P47

Internal bus

PU0

PORT

PU04

Output latch

(P46, P47)

PM46, PM47

DD0

P-ch

P46, P47

Selector

PU0: Pull-up resistor option register 0

PM: Port mode register

RD: Port 4 read signal

WR: Port 4 write signal

CHAPTER 4 PORT FUNCTIONS

80 User’s Manual U13952EJ3V1UD

4.2.4 Port 5

This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified as input or output in 1-bit units

by using port mode register 5 (PM5). For a mask ROM version, whether a pull-up resistor is to be incorporated can be

specified by a mask option.

Port 5 is set to input mode when the RESET signal is input.

Figure 4-10 shows a block diagram of port 5.

Figure 4-10. Block Diagram of P50 to P53

Internal bus

Selector

PM50 to PM53

P50 to P53

N-ch

WRPORT

Output latch

(P50 to P53)

WRPM

VDD0

Mask option resistor

Mask ROM version only.

For the flash memory version,

a pull-up resistor is not

incorporated.

PM: Port mode register

RD: Port 5 read signal

WR: Port 5 write signal

CHAPTER 4 PORT FUNCTIONS

User’s Manual U13952EJ3V1UD 81

4.2.5 Port 6

This is a 7-bit input port.

Port 6 is also used as an analog input to the A/D converter or comparator input.

Port 6 is set to input mode when the RESET signal is input.

Figures 4-11 and 4-12 show block diagrams of port 6.

Figure 4-11. Block Diagram of P60 and P61

Internal bus

VREF

A/D converter

P60/ANI0/CMPIN0

P61/ANI1/CMPREF0

Comparator

–

CHAPTER 4 PORT FUNCTIONS

82 User’s Manual U13952EJ3V1UD

Figure 4-12. Block Diagram of P62 to P66

Internal bus

REF

–

A/D converter

P62/ANI2 to

P66/ANI6

CHAPTER 4 PORT FUNCTIONS

User’s Manual U13952EJ3V1UD 83

4.2.6 Port 8

This is an 8-bit I/O port with an output latch. Port 8 can be specified as input or output in 1-bit units by using port

mode register 8 (PM8). When using the P80 to P87 pins as input port pins, internal pull-up resistors can be connected

in 2-bit units by using pull-up resistor option register 2 (PU2).

Port 8 is also used to output segment signals for the LCD controller/driver.

Port 8 is set to input mode when the RESET signal is input.

Figure 4-13 shows a block diagram of port 8.

Figure 4-13. Block Diagram of P80 to P87

Internal bus

PU2

DD0

P-ch

PORT

Output latch

(P8m)

PM8m

LPS0

Segment output

LPS

PU28n

P80/S27 to P87/S20

Selector

PU2: Pull-up resistor option register 2

PM: Port mode register

RD: Port 8 read signal

WR: Port 8 write signal

LPS0: LCD port selector 0

n = 0, 2, 4, 6, m = 0 to 7

CHAPTER 4 PORT FUNCTIONS

84 User’s Manual U13952EJ3V1UD

4.2.7 Port 9

This is a 4-bit I/O port with an output latch. Port 9 can be specified as input or output in 1-bit units by using port

mode register 9 (PM9). When using the P90 to P93 pins as input port pins, on-chip pull-up resistors can be connected

in 2-bit units by using pull-up resistor option register 2 (PU2).

Port 9 is also used to output segment signals for the LCD controller/driver.

Port 9 is set to input mode when the RESET signal is input.

Figure 4-14 shows a block diagram of port 9.

Figure 4-14. Block Diagram of P90 to P93

Internal bus

PU2

DD0

P-ch

PORT

Output latch

(P9m)

PM9m

LPS0

Segment output

LPS

PU29n

P90/S19 to P93/S16

Selector

PU2: Pull-up resistor option register 2

PM: Port mode register

RD: Port 9 read signal

WR: Port 9 write signal

LPS0: LCD port selector 0

n = 0, 2, m = 0 to 3

CHAPTER 4 PORT FUNCTIONS

User’s Manual U13952EJ3V1UD 85

4.3 Registers Controlling Ports

The following two registers control the ports.

• Port mode registers (PM0, PM2, PM4, PM5, PM8, and PM9)

• Pull-up resistor option registers (PU0 to PU2)

(1) Port mode registers (PM0, PM2, PM4, PM5, PM8, and PM9)

These registers are used to set port input/output in 1-bit units.

The port mode registers are independently set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets these registers to FFH.

When port pins are used as alternate-function pins, set the port mode register and output latch according to

Table 4-3.

Caution As port 2 has an alternate function as the external interrupt input, when the port function

output mode is specified and the output level is changed, the interrupt request flag is set.

When the output mode is used, therefore, the interrupt mask flag should be set to 1

beforehand.

Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate Functions

Alternate Function Pin Name

Name I/O

PMxx Pxx

CMPTOUT0 Output 0 0 P23

TO2 Output 0 0

INTP0 Input 1 x P24

TI0 Input 1 x

INTP1 Input 1 x P25

TI1 Input 1 x

INTP2 Input 1 x P26

TO5 Output 0 0

INTP3 Input 1 x P27

CPT5 Input 1 x

P40 to P45Note KR0 to KR5 Input 1 x

P80 to P87 S27 to S20 Output 0 0

P90 to P93 S19 to S16 Output 0 0

Note Set key return mode register 00 (KRM00) to 1 when using the alternate function (see 15.3 (6) Key return

mode register 00 (KRM00)).

Caution When port 2 is used for the serial interface, the I/O or output latch must be set according to the

function used. For the setting method, see Table 13-2 Operation Mode Settings of Serial

Interface 00.

Remark x: Don’t care

PMxx: Port mode register

Pxx: Port output latch

CHAPTER 4 PORT FUNCTIONS

86 User’s Manual U13952EJ3V1UD

Figure 4-15. Format of Port Mode Register

PMmn

0 Output mode (output buffer on)

Input mode (output buffer off) 1

PM27

PM87

PM26

PM86

PM25

PM85

PM24

PM84

PM03

PM23

PM83

PM93

PM02

PM22

PM82

PM92

PM01

PM21

PM81

PM91

PM00

PM20

PM80

PM90

PM0

PM2

PM8

PM9

Symbol Address After reset

6543210 R/W

FF20H

FF22H

FF28H

FF29H

FFH

R/W

PM47

PM46

PM45

PM44

PM43

PM53

PM42

PM52

PM41

PM51

PM40

PM50

PM4

PM5

FF24H

FF25H

FFH

R/W

Pmn pin I/O mode selection

m = 0, 5, 9: n = 0 to 3

m = 2, 4, 8: n = 0 to 7

(2) Pull-up resistor option registers (PU0 to PU2)

The pull-up resistor option registers (PU0 to PU2) set whether an on-chip pull-up resistor is used on each

port.

On a port specified by PU0 to PU2 to use an on-chip pull-up resistor, the pull-up resistor can be internally

used only for the bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the

output mode regardless of the setting of PU0 to PU2. This also applies when using the pins for alternate

functions.

PU0 to PU2 are set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PU0 to PU2 to 00H.

Figure 4-16. Format of Pull-Up Resistor Option Register 0

Pm on-chip pull-up resistor selection

Note

(m = 0 or 4)

0 0 0 PU04 0 0 0 PU00PU0

Address After reset R/W

FFF7H 00H R/W

765<4>321<0>

PU0m

On-chip pull-up resistor not used

On-chip pull-up resistor used

Symbol

Note PU0 selects whether on-chip pull-up resistors are to be used in 8-bit units, except for port 0, for which on-

chip pull-up resistors can be used only for four bits (P00 to P03).

Caution Bits 1, 2, 3, 5, 6, and 7 must be fixed to 0.

CHAPTER 4 PORT FUNCTIONS

User’s Manual U13952EJ3V1UD 87

Figure 4-17. Format of Pull-Up Resistor Option Register 1

P2 on-chip pull-up resistor selectionNote

(m = 0 to 7)

PU127 PU126 PU125 PU124 PU123 PU122 PU121 PU120

PU1

Address After reset R/W

FFF3H 00H R/W

<7> <6> <5> <4> <3> <2> <1> <0>

PU12m

On-chip pull-up resistor not used

On-chip pull-up resistor used

Symbol

Note PU1 selects whether on-chip pull-up resistors are to be used in 1-bit units.

Figure 4-18. Format of Pull-Up Resistor Option Register 2

Pm on-chip pull-up resistor selection

Note

(m = 8 or 9; n = 0, 2, 4, or 6)

PU292 PU290 PU286 PU284 PU282 PU280

PU2

Address After reset R/W

FFF4H 00H R/W

7 6 <5> <4> <3> <2> <1> <0>

PU2mn

On-chip pull-up resistor not used

On-chip pull-up resistor used

Symbol

Note PU2 selects whether on-chip pull-up resistors are to be used in 2-bit units (bit n and bit n+1).

Caution Bits 6 and 7 must be fixed to 0.

CHAPTER 4 PORT FUNCTIONS

88 User’s Manual U13952EJ3V1UD

4.4 Operation of Ports

The operation of a port differs depending on whether the port is set in the input or output mode, as described

below.

4.4.1 Writing to I/O port

(1) In output mode

A value can be written to the output latch of a port by using a transfer instruction. The contents of the output

latch can be output from the pins of the port.

Once data is written to the output latch, it is retained until new data is written to the output latch.

(2) In input mode

A value can be written to the output latch by using a transfer instruction. However, the status of the port pin

is not changed because the output buffer is off.

Once data is written to the output latch, it is retained until new data is written to the output latch.

Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.

However, this instruction accesses the port in 8-bit units. When this instruction is

executed to manipulate a bit of an I/O port, therefore, the contents of the output latch of the

pin that is set in the input mode and not subject to manipulation become undefined.

4.4.2 Reading from I/O port

(1) In output mode

The contents of the output latch can be read by using a transfer instruction. The contents of the output latch

are not changed.

(2) In input mode

The status of a pin can be read by using a transfer instruction. The contents of the output latch are not

changed.

4.4.3 Arithmetic operation of I/O port

(1) In output mode

An arithmetic operation can be performed on the contents of the output latch. The result of the operation is

written to the output latch. The contents of the output latch are output from the port pins.

Once data is written to the output latch, it is retained until new data is written to the output latch.

(2) In input mode

The contents of the output latch become undefined. However, the status of the pin is not changed because

the output buffer is off.

Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.

However, this instruction accesses the port in 8-bit units. When this instruction is

executed to manipulate a bit of an I/O port, therefore, the contents of the output latch of the

pin that is set in the input mode and not subject to manipulation become undefined.

User’s Manual U13952EJ3V1UD

CHAPTER 5 CLOCK GENERATOR

5.1 Functions of Clock Generator

The clock generator generates the clock to be supplied to the CPU and peripheral hardware.

The following two types of system clock oscillators are used.

• Main system clock oscillator

This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting

the processor clock control register (PCC).

• Subsystem clock oscillator

This circuit oscillates at 32.768 kHz. Oscillation can be stopped by the suboscillation mode register (SCKM).

5.2 Configuration of Clock Generator

The clock generator consists of the following hardware.

Table 5-1. Configuration of Clock Generator

Item Configuration

Control registers Processor clock control register (PCC)

Suboscillation mode register (SCKM)

Subclock control register (CSS)

Oscillators Main system clock oscillator

Subsystem clock oscillator

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90 User’s Manual U13952EJ3V1UD

Figure 5-1. Block Diagram of Clock Generator

Prescaler

1/2

Prescaler

Watch timer

LCD controller/driver

Clock to

peripheral

hardware

CPU clock

CPU

)

Standby

controller

Wait

controller

Selector

STOP MCC PCC1 CLS CSS0

Internal bus

Suboscillation mode register

(SCKM)

FRC SCC

Internal bus

Subclock control

Processor clock

control register

(PCC)

Subsystem

clock

oscillator

XT1

XT2

Main system

clock

oscillator

CHAPTER 5 CLOCK GENERATOR

User’s Manual U13952EJ3V1UD 91

5.3 Registers Controlling Clock Generator

The clock generator is controlled by the following registers.

• Processor clock control register (PCC)

• Suboscillation mode register (SCKM)

• Subclock control register (CSS)

(1) Processor clock control register (PCC)

PCC selects the CPU clock and sets the division ratio.

PCC is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PCC to 02H.

Figure 5-2. Format of Processor Clock Control Register

0.4 s

1.6 s

122 s

Control of main system clock oscillator operation

MCC00000PCC1 0PCC

Symbol Address After reset R/W

FFFBH 02H R/W

76543210

MCC

Operation enabled

Operation disabled

Selection of CPU clock (f

CPU

)

Note

CSS0

PCC1

Minimum instruction execution time: 2/f

CPU

= 5.0 MHz or f

= 32.768 kHz operation

Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control

Cautions 1. Bits 0 and 2 to 6 must be fixed to 0.

2. The MCC bit can be set only when the subsystem clock has been selected as the CPU clock.

Remarks 1. fX: Main system clock oscillation frequency

2. f

XT: Subsystem clock oscillation frequency

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92 User’s Manual U13952EJ3V1UD

(2) Suboscillation mode register (SCKM)

SCKM selects whether a feedback resistor is used for the subsystem clock, and controls the oscillation of the

clock.

SCKM is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets SCKM to 00H.

Figure 5-3. Format of Suboscillation Mode Register

Feedback resistor selection

Note

000000FRCSCCSCKM

Symbol Address After reset R/W

FFF0H 00H R/W

76543210

FRC

On-chip feedback resistor used

On-chip feedback resistor not used

Control of subsystem clock oscillator operation

SCC

Operation enabled

Operation disabled

Note The feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid

point of the supply voltage. Only when the subclock is not used, the power consumption in STOP mode

can be further reduced by setting FRC = 1.

Cautions 1. Bits 2 to 7 must be fixed to 0.

2. Do not set the SCC bit when an external clock pulse is input, because the XT2 pin is pulled

up to VDD0 or VDD1.

CHAPTER 5 CLOCK GENERATOR

User’s Manual U13952EJ3V1UD 93

(3) Subclock control register (CSS)

CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies how

the CPU clock operates.

CSS is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets CSS to 00H.

Figure 5-4. Format of Subclock Control Register

CPU clock operation status

0 0 CLS CSS0 0000CSS

Address After reset R/W

FFF2H 00H R/W

76543210

CLS

Operation based on the output of the divided main system clock

Operation based on the subsystem clock

Selection of main system or subsystem clock oscillatorCSS0

Divided output from the main system clock oscillator

Output from the subsystem clock oscillator

Symbol

Note

Note Bit 5 is read only.

Caution Bits 0, 1, 2, 3, 6, and 7 must be fixed to 0.

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94 User’s Manual U13952EJ3V1UD

5.4 System Clock Oscillators

5.4.1 Main system clock oscillator

The main system clock oscillator is oscillated by a crystal or ceramic resonator (5.0 MHz TYP.) connected across

the X1 and X2 pins.

An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the

inverted signal to the X2 pin.

Figure 5-5 shows the external circuit of the main system clock oscillator.

Figure 5-5. External Circuit of Main System Clock Oscillator

(a) Crystal or ceramic oscillation (b) External clock

Crystal

ceramic resonator

VSS0, VSS1

External

clock X1

Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed

by the broken lines in Figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line

through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as VSS0 and VSS1.

Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

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User’s Manual U13952EJ3V1UD 95

5.4.2 Subsystem clock oscillator

The subsystem clock oscillator is oscillated by a crystal resonator (32.768 kHz TYP.) connected across the XT1

and XT2 pins.

An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the

inverted signal to the XT2 pin.

Figure 5-6 shows the external circuit of the subsystem clock oscillator.

Figure 5-6. External Circuit of Subsystem Clock Oscillator

(a) Crystal oscillation (b) External clock

XT2

SS0

SS1

XT1

32.768

kHz

Crystal resonator

External

clock XT1

XT2

Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed

by the broken lines in Figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line

through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as VSS0 and VSS1.

Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

When using the subsystem clock oscillator, pay special attention because the subsystem clock

oscillator has low amplification to minimize current consumption.

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96 User’s Manual U13952EJ3V1UD

5.4.3 Examples of incorrect resonator connection

Figure 5-7 shows examples of incorrect resonator connection.

Figure 5-7. Examples of Incorrect Resonator Connection (1/2)

(a) Too long wiring (b) Crossed signal line

VSS0,

VSS1 X1 X2

VSS0,

VSS1 X1 X2

PORTn

(n = 0, 2, 4, 5, 6, 8, 9)

(potential at points A, B, and C fluctuates)

VSS0,

VSS1 X1 X2

High current

VSS0,

VSS1 X1

AB C

Pmn

VDD0, VDD1

High current

Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect resistors

to the XT2 side in series.

CHAPTER 5 CLOCK GENERATOR

User’s Manual U13952EJ3V1UD 97

Figure 5-7. Examples of Incorrect Resonator Connection (2/2)

(e) Signal is fetched (f) Signal lines of main system clock and subsystem

clock are parallel and close together

VSS0,

VSS1 X1 X2

VSS0,

VSS1 X2

XT2 is wired parallel to X1.

X1 XT2 XT1

Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect resistors

to the XT2 side in series.

Caution If the X1 wire is parallel with the XT2 wire, crosstalk noise may occur between X1 and XT2,

resulting in a malfunction.

To avoid this, do not place the X1 and XT2 wires in parallel.

5.4.4 Divider

The divider divides the output of the main system clock oscillator (fX) to generate various clocks.

5.4.5 When no subsystem clock is used

If a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation,

handle the XT1 and XT2 pins as follows:

XT1: Connect directly to VSS0 or VSS1

XT2: Leave open

In this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator

when the main system clock is stopped. To avoid this, set bit 1 (FRC) of the suboscillation mode register (SCKM) so

that the on-chip feedback resistor will not be used. Also in this case, handle the XT1 and XT2 pins as stated above.

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98 User’s Manual U13952EJ3V1UD

5.5 Operation of Clock Generator

The clock generator generates the following clocks and controls the operation modes of the CPU, such as the

standby mode.

• Main system clock fX

• Subsystem clock fXT

• CPU clock fCPU

• Clock to peripheral hardware

The operation of the clock generator is determined by the processor clock control register (PCC), suboscillation

mode register (SCKM), and subclock control register (CSS), as follows.

(a) The slow mode (1.6

s at 5.0 MHz operation) of the main system clock is selected when the RESET

signal is generated (PCC = 02H). While a low level is being input to the RESET pin, oscillation of the

main system clock is stopped.

(b) Three types of minimum instruction execution time (0.4

s and 1.6

s main system clock (at 5.0 MHz

operation), 122

s subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM, and

CSS settings.

where no subsystem clock is used, setting bit 1 (FRC) of SCKM so that the on-chip feedback resistor

cannot be used reduces current consumption in the STOP mode. In a system where a subsystem clock

is used, setting bit 0 of SCKM to 1 can cause the subsystem clock to stop oscillation.

(d) Bit 4 (CSS0) of CSS can be used to select the subsystem clock so that low current consumption

operation is used (at 122

s, 32.768 kHz operation).

(e) With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating by

setting bit 7 (MCC) of PCC. The HALT mode can be used, but the STOP mode cannot.

(f) The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system

clock. The subsystem clock pulse is supplied to 8-bit timer 02, the watch timer, and the LCD

controller/driver only. As a result, 8-bit timer 02 (when watch timer output is selected for the count clock

when the subsystem clock is running) and the watch function can continue running even in the standby

mode. The other hardware stops when the main system clock stops, because it runs based on the main

system clock (except for external input clock pulses).

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User’s Manual U13952EJ3V1UD 99

5.6 Changing Setting of System Clock and CPU Clock

5.6.1 Time required for switching between system clock and CPU clock

The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4

(CSS0) of the subclock control register (CSS).

Actually, the specified clock is not selected immediately after the setting of PCC has been changed; the old clock

is used for the duration of several instructions after that (see Table 5-2).

Table 5-2. Maximum Time Required for Switching CPU Clock

Set Value Before Switching Set Value After Switching

CSS0 PCC1 CSS0 PCC1 CSS0 PCC1 CSS0 PCC1

0 0 0 1 1 x

0 0 4 clocks 2fX/fXT clocks

(306 clocks)

1 2 clocks fX/2fXT clocks

(76 clocks)

1 x 2 clocks 2 clocks

Remarks 1. Two clocks is the minimum instruction execution time of the CPU clock before switching.

2. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.

3. x: Don’t care

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100 User’s Manual U13952EJ3V1UD

5.6.2 Switching between system clock and CPU clock

The following figure illustrates how the CPU clock and system clock are switched.

Figure 5-8. Switching Between System Clock and CPU Clock

System clock

CPU clock

Interrupt request signal

RESET

Low-speed

operation

High-speed

operation

Subsystem clock

operation

High-speed

operation

Wait (6.55 ms: at 5.0 MHz operation)

Internal reset operation

<1> The CPU is reset when the RESET pin is made low on power application. Reset is released when the

RESET pin is later made high, and the main system clock starts oscillating. At this time, the oscillation

stabilization time (215/fX) is automatically secured.

After that, the CPU starts instruction execution at the low speed of the main system clock (1.6

s at

5.0 MHz operation).

<2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at the high speed

has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock

control register (CSS) are rewritten so that the high-speed operation can be selected.

<3> A drop of the VDD voltage is detected by an interrupt request signal. The clock is switched to the subsystem

clock (at this moment, the subsystem clock must be in the stable oscillation status).

<4> Recovery of the VDD voltage is detected by an interrupt request signal. Bit 7 (MCC) of PCC is set to 0, and

the main system clock starts oscillating. After the time required for the oscillation to stabilize has elapsed,

PCC1 and CSS0 are rewritten so that high-speed operation can be selected again.

Caution When the main system clock is stopped and the device is operating on the subsystem

clock, wait until the oscillation stabilization time has been secured by the program before

switching back to the main system clock.

User’s Manual U13952EJ3V1UD

101

CHAPTER 6 16-BIT TIMER 50

16-bit timer 50 references the free-running counter and provides functions such as timer interrupt and timer output.

In addition, the count value can be captured by a trigger pin.

6.1 Function of 16-Bit Timer 50

16-bit timer 50 has the following functions.

• Timer interrupt

• Timer output

• Count value capture

(1) Timer interrupt

An interrupt is generated when the count value and compare value match.

(2) Timer output

Timer output control is possible when the count value and compare value match.

(3) Count value capture

The count value of 16-bit timer counter 50 (TM50) is latched to the capture register in synchronization with

the capture trigger and retained.

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102 User’s Manual U13952EJ3V1UD

6.2 Configuration of 16-Bit Timer 50

16-bit timer 50 consists of the following hardware.

Table 6-1. Configuration of 16-Bit Timer 50

Item Configuration

Timer counter 16 bits × 1 (TM50)

Registers Compare register: 16 bits × 1 (CR50)

Capture register: 16 bits × 1 (TCP50)

Timer outputs 1 (TO5)

Control registers 16-bit timer mode control register 50 (TMC50)

Port mode register 2 (PM2)

Figure 6-1. Block Diagram of 16-Bit Timer 50

CPT5/P27/

INTP3

Internal bus

16-bit timer mode

control register 50

(TMC50)

16-bit timer mode

control register 50

TOF50

CPT501 CPT500

TOC50

TCL501 TCL500

TOE50

fX/25

Edge

detector

16-bit capture

16-bit counter

read buffer

16-bit timer counter 50 (TM50)

16-bit compare register 50 (CR50)

Match

Selector

OVF

F/F

TOD50

TO5/P26/

INTP2

INTTM50

P26

output latch

PM26

CHAPTER 6 16-BIT TIMER 50

User’s Manual U13952EJ3V1UD 103

(1) 16-bit compare register 50 (CR50)

This register compares the value set to CR50 with the count value of 16-bit timer counter 50 (TM50), and

when they match, generates an interrupt request (INTTM50).

CR50 is set using a 16-bit memory manipulation instruction. Values from 0000H to FFFFH can be set.

RESET input sets CR50 to FFFFH.

Cautions 1. Although this register is manipulated by a 16-bit memory manipulation instruction, an 8-

bit memory manipulation instruction can also be used. When manipulated by an 8-bit

memory manipulation instruction, the accessing method should be direct addressing.

2. When rewriting CR50 during a count operation, preset CR50 to interrupt disabled using

interrupt mask flag register 1 (MK1). Also, set the timer output data to inversion

disabled using 16-bit timer mode control register 50 (TMC50).

If CR50 is rewritten while interrupts are enabled, an interrupt request may be generated

at the time of the rewrite.

(2) 16-bit timer counter 50 (TM50)

This is a 16-bit register that counts count pulses.

TM50 is read using a 16-bit memory manipulation instruction.

TM50 is in free-running mode during count clock input.

RESET input sets TM50 to 0000H, after which it enters free-running mode again.

Cautions 1. The count value after releasing stop becomes undefined because the count operation is

executed during the oscillation stabilization time.

2. Although this register is manipulated by a 16-bit memory manipulation instruction, an 8-

bit memory manipulation instruction can also be used. When manipulated by an 8-bit

memory manipulation instruction, the accessing method should be direct addressing.

3. When manipulated by an 8-bit memory manipulation instruction, readout should be

performed in order from lower byte to higher byte and must be in pairs.

(3) 16-bit capture register 50 (TCP50)

This is a 16-bit register that captures the contents of 16-bit timer counter 50 (TM50).

TCP50 is set using a 16-bit memory manipulation instruction.

RESET input makes TCP50 undefined.

Caution Although this register is manipulated by a 16-bit memory manipulation instruction, an 8-bit

memory manipulation instruction can also be used. When manipulated by an 8-bit memory

manipulation instruction, the accessing method should be direct addressing.

(4) 16-bit counter read buffer

This buffer latches the counter value of 16-bit timer counter 50 (TM50) and retains the count value.

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104 User’s Manual U13952EJ3V1UD

6.3 Registers Controlling 16-Bit Timer 50

The following two registers are used to control 16-bit timer 50.

• 16-bit timer mode control register 50 (TMC50)

• Port mode register 2 (PM2)

(1) 16-bit timer mode control register 50 (TMC50)

16-bit timer mode control register 50 (TMC50) controls the setting of the count clock, capture edge, etc.

TMC50 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets TMC50 to 00H.

CHAPTER 6 16-BIT TIMER 50

User’s Manual U13952EJ3V1UD 105

Figure 6-2. Format of 16-Bit Timer Mode Control Register 50

TOC50

TOD50 TOF50 CPT501 CPT500 TOC50 TCL501 TCL500 TOE50

TMC50

R/W

FF48H 00H R/W

<6>54321

CPT501

CPT500

Capture operation disabled

Rising edge of CPT5

Falling edge of CPT5

Both edges of CPT5

TOF50

7 <0>

Set by overflow of 16-bit timer

Symbol Address After reset

Timer output data inverse control

Inverse disabled

Inverse enabled

Capture edge selection

TOE50

TCL501

Other than

above

TCL500

(5.0 MHz)

(156.3 kHz)

Setting prohibited

16-bit timer 50 output control

Output disabled (port mode)

Output enabled

TOD50

Timer output data

Timer output is “0”

Timer output is “1”

16-bit timer 50 count clock selection

Overflow flag set

Clear by reset and software

Note 1

Note 2

Note 3

Notes 1. Bit 7 is read-only.

2. If the count clock is set to fX (TCL501 = 0, TCL500 = 0), the capture function cannot be used. When

reading, set the CPU clock to the main system clock high-speed mode (PCC1 = 0, CSS0 = 0) (see

Figure 5-2).

3. When reading, specify the main system clock as the CPU clock (PCC1 = 0, CSS0 = 0 or PCC1 = 1,

CSS0 = 0) (see Figure 5-2).

Remarks 1. fX: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz.

CHAPTER 6 16-BIT TIMER 50

106 User’s Manual U13952EJ3V1UD

(2) Port mode register 2 (PM2)

This register sets input/output of port 2 in 1-bit units.

To use the P26/INTP2/TO5 pin for timer output, set PM26 and the output latch of P26 to 0.

PM2 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PM2 to FFH.

Figure 6-3. Format of Port Mode Register 2

PM27 PM26

PM25 PM24

PM23 PM22 PM21 PM20PM2

R/W

FF22H FFH R/W

654321

PM26

Input mode (output buffer off)

Symbol Address After reset

P26 pin I/O mode selection

Output mode (output buffer on)

CHAPTER 6 16-BIT TIMER 50

User’s Manual U13952EJ3V1UD 107

6.4 Operation of 16-Bit Timer 50

6.4.1 Operation as timer interrupt

In the timer interrupt function, interrupts are repeatedly generated at the count value set to 16-bit compare register

50 (CR50) in advance at the interval set in TCL501 and TCL500.

To operate the 16-bit timer as a timer interrupt, the following settings are required.

• Set the count value to CR50

• Set 16-bit timer mode control register 50 (TMC50) as shown in Figure 6-4.

Figure 6-4. Settings of 16-Bit Timer Mode Control Register 50 for Timer Interrupt Operation

–0/1 0/1 0/1 0/1 0 0/1 0/1

TOD50 TOF50

CPT501 CPT500

TOC50

TCL501 TCL500

TOE50

TMC50

Setting of count clock (see Table 6-2)

Caution If both the CPT501 flag and CPT500 flag are set to 0, the capture edge becomes operation

prohibited.

When the count value of 16-bit timer counter 50 (TM50) matches the value set to CR50, counting of TM50

continues and an interrupt request signal (INTTM50) is generated.

Table 6-2 shows the interval time, and Figure 6-5 shows the timing of the timer interrupt operation.

Caution Be sure to process as follows when rewriting CR50 during a count operation.

<1> Set interrupts to disabled (TMMK50 (bit 4 of interrupt mask flag register 1 (MK1)) = 1)

<2> Set the inversion control of timer output data to disabled (TOC50 = 0)

If CR50 is rewritten while interrupts are enabled, an interrupt request may be generated at the

time of rewrite.

Table 6-2. Interval Time of 16-Bit Timer 50

TCL501 TCL500 Count Clock Interval Time

0 0

1/fX (0.2

s) 216/fX (13.1 ms)

0 1

25/fX (6.4

s) 221/fX (419.4 ms)

Other than above Setting prohibited

Remarks 1. f

X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz.

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108 User’s Manual U13952EJ3V1UD

Figure 6-5. Timing of Timer Interrupt Operation

Count clock

TM50 count value

CR50

INTTM50

TO5

TOF50

0000H

0001H

FFFFH 0000H 0001H

FFFFH

NN N NN

Interrupt acknowledged Interrupt acknowledged

Overflow flag set

Remark N = 0000H to FFFFH

CHAPTER 6 16-BIT TIMER 50

User’s Manual U13952EJ3V1UD 109

6.4.2 Operation as timer output

Timer outputs are repeatedly generated at the count value set to 16-bit compare register 50 (CR50) in advance at

the interval set in TCL501 and TCL500.

To operate 16-bit timer as a timer output, the following settings are required.

• Set P26 to output mode (PM26 = 0)

• Set the output latch of P26 to 0

• Set the count value to CR50

• Set 16-bit timer mode control register 50 (TMC50) as shown in Figure 6-6

Figure 6-6. Settings of 16-Bit Timer Mode Control Register 50 for Timer Output Operation

–0/1 0/1 0/1 10 0/1 1

TOD50 TOF50

CPT501 CPT500

TOC50

TCL501 TCL500

TOE50

TMC50

Setting of count clock (see Table 6-2)

Inverse enable of timer output data

TO5 output enable

Caution If both the CPT501 flag and CPT500 flag are set to 0, the capture edge becomes operation

prohibited.

When the count value of 16-bit timer counter 50 (TM50) matches the value set in CR50, the output status of the

TO5/INTP2/P26 pin is inverted. This enables timer output. At that time, TM50 counting continues and an interrupt

request signal (INTTM50) is generated.

Figure 6-7 shows the timing of timer output (see Table 6-2 for the interval time of 16-bit timer 50).

Figure 6-7. Timer Output Timing

Note The TO5 initial value becomes low level when output is enabled (TOE50 = 1).

Remark N = 0000H to FFFFH

Count clock

TM50 count value

CR50

INTTM50

TO5

Note

TOF50

0000H

0001H

FFFFH 0000H 0001H

FFFFH

NN N NN

Interrupt acknowledged Interrupt acknowledged

Overflow flag set

CHAPTER 6 16-BIT TIMER 50

110 User’s Manual U13952EJ3V1UD

6.4.3 Capture operation

In a capture operation, the count value of 16-bit timer counter 50 (TM50) is captured and latched to the capture

Set as shown in Figure 6-8 to allow the 16-bit timer to start a capture operation.

Figure 6-8. Settings of 16-Bit Timer Mode Control Register 50 for Capture Operation

–0/1 0/1 0/1

0/1 0 0/1 0/1

TOD

TOF

CPT501 CPT500

TOC

TCL501 TCL500

TOE

TMC50

Count clock selection

Capture edge selection (see Table 6-3)

16-bit capture register 50 (TCP50) starts a capture operation after the CPT5 capture trigger edge is defected, and

latches and retains the count value of 16-bit timer counter 50 (TM50). TCP50 fetches the count value within 2 clocks

and retains the count value until the next capture edge detection.

Table 6-3 and Figure 6-9 shows the settings of the capture edge and the capture operation timing, respectively.

Table 6-3. Settings of Capture Edge

CPT501 CPT500 Capture Edge Selection

0 0 Capture operation prohibited

0 1 CPT5 pin rising edge

1 0 CPT5 pin falling edge

1 1 CPT5 pin both edges

Caution Because TCP50 is rewritten when a capture trigger edge is detected during TCP50 read, disable

capture trigger edge detection during TCP50 read.

Figure 6-9. Capture Operation Timing (Both Edges of CPT5 Pin Are Specified)

Count clock

TM50

16-bit counter read buffer

TCP50

CPT5

0000H

0001H

Undefined

M – 1 M

Capture start Capture start

Capture edge detection Capture edge detection

CHAPTER 6 16-BIT TIMER 50

User’s Manual U13952EJ3V1UD 111

6.4.4 16-bit timer counter 50 readout

The count value of 16-bit timer counter 50 (TM50) is read out by a 16-bit manipulation instruction.

TM50 readout is performed via a 16-bit counter read buffer. The 16-bit counter read buffer latches the TM50 count

value, the buffer operation is held pending at the CPU clock falling edge after the read signal of the TM50 lower byte

rises, and the count value is retained. The 16-bit counter read buffer value in the retention state can be read out as

the count value.

Cancellation of pending is performed at the CPU clock falling edge after the read signal of the TM50 higher byte

falls.

RESET input sets TM50 to 0000H and then to free-running mode again.

Figure 6-10 shows the timing of 16-bit timer counter 50 readout.

Cautions 1. The count value after releasing stop becomes undefined because the count operation is

executed during the oscillation stabilization time.

2. AIthough TM50 is manipulated by a 16-bit transfer instruction, 8-bit transfer instruction can

also be used.

When using an 8-bit transfer instruction, execute by direct addressing.

3. When using an 8-bit transfer instruction, execute in order from lower byte to higher byte in

pairs. If the only lower byte is read, the pending state of the 16-bit counter read buffer is not

canceled, and if the only higher byte is read, an undefined count value is read.

Figure 6-10. Readout Timing of 16-Bit Timer Counter 50

CPU clock

Count clock

TM50

16-bit counter read buffer

TM50 read signal

0000H

0001H

N + 1

Read signal latch

prohibited period

CHAPTER 6 16-BIT TIMER 50

112 User’s Manual U13952EJ3V1UD

6.5 Cautions on Using 16-Bit Timer 50

6.5.1 Restrictions when rewriting 16-bit compare register 50

(1) Disable interrupts (TMMK50 = 1) and the inversion control of timer output (TOC50 = 0) before rewriting the

compare register (CR50).

If CR50 is rewritten with interrupts enabled, an interrupt request may be generated immediately.

(2) Depending on the timing of rewriting the compare register (CR50), the interval time may become twice as

long as the intended time. Similarly, a shorter waveform or twice-longer waveform than the intended timer

output waveform may be output.

To avoid this problem, rewrite the compare register using either of the following procedures.

<Countermeasure A> When rewriting using 8-bit access

<1> Disable interrupts (TMMK50 = 1) and the inversion control of timer output (TOC50 = 0).

<2> First rewrite the higher 1 byte of CR50 (16 bits).

<3> Then rewrite the lower 1 byte of CR50 (16 bits).

<4> Clear the interrupt request flag (TMIF50).

<5> Enable timer interrupts/timer output inversion after half a cycle or more of the count clock has elapsed from

the beginning of the interrupt.

<Program example A> (count clock = 32/fX, CPU clock = fX)

TM50_VCT: SET1 TMMK50 ; Disable timer interrupts (6 clocks)

CLR1 TMC50.3 ; Disable timer output inversion (6 clocks)

MOV A,#xxH ; Set the rewrite value of higher byte (6 clocks)

MOV !0FF17H,A ; Rewrite CR50 higher byte (8 clocks)

MOV A,#yyH ; Set the rewrite value of lower byte (6 clocks)

MOV !0FF16H,A ; Rewrite CR50 lower byte (8 clocks)

CLR1 TMIF50 ; Clear interrupt request flag (6 clocks)

CLR1 TMMK50 ; Enable timer interrupts (6 clocks)

SET1 TMC50.3 ; Enable timer output inversion

Note Because the INTTM50 signal becomes high level for half a cycle of the count clock after an interrupt is

generated, the output is inverted if TOC50 is set to 1 during this period.

Total: 16 clocks or

moreNote

CHAPTER 6 16-BIT TIMER 50

User’s Manual U13952EJ3V1UD 113

<Countermeasure B> When rewriting using 16-bit access

<1> Disable interrupts (TMMK50 = 1) and the inversion control of timer output (TOC50 = 0).

<2> Rewrite CR50 (16 bits).

<3> Wait for one cycle or more of the count clock.

<4> Clear the interrupt request flag (TMIF50).

<5> Enable timer interrupts/timer output inversion.

<Program example B> (count clock = 32/fX, CPU clock = fX)

TM50_VCT SET1 TMMK50 ; Disable timer interrupts

CLR1 TMC50.3 ; Disable timer output inversion

MOVW AX,#xxyyH ; Set the rewrite value of CR50

MOVW CR50,AX ; Rewrite CR50

NOP

: ; 16 NOP instructions (wait for 32/fX)Note

NOP

CLR1 TMIF50 ; Clear interrupt request flag

CLR1 TMMK50 ; Enable timer interrupts

SET1 TMC50.3 ; Enable timer output inversion

Note Clear the interrupt request flag (TMIF50) after waiting for one cycle or more of the count clock from the

instruction rewriting CR50 (MOVW CR50, AX).

User’s Manual U13952EJ3V1UD

114

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

7.1 Function of 8-Bit Timer/Event Counters 00 to 02

8-bit timer/event counters 00 to 02 have the following functions.

• Interval timer (timer 00, timer 01, and timer 02)

• External event counter (timer 00 and timer 01 only)

• Square-wave output (timer 02 only)

The

PD789407A and

PD789417A Subseries are provided with two 8-bit timer/event counter channels (timer 00

and timer 01) and one 8-bit timer channel (timer 02). When reading the description of timer 02, timer/event counter

should be read as a timer.

(1) 8-bit interval timer

When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at an arbitrary time

interval set in advance.

Table 7-1. Interval Time of 8-Bit Timer/Event Counter 00

Minimum Interval Time Maximum Interval Time Resolution

26/fX (12.8

s) 214/fX (3.28 ms) 26/fX (12.8

29/fX (102.4

s) 217/fX (26.2 ms) 29/fX (102.4

Remarks 1. f

X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz.

Table 7-2. Interval Time of 8-Bit Timer/Event Counter 01

Minimum Interval Time Maximum Interval Time Resolution

24/fX (3.2

s) 212/fX (819.2

s) 24/fX (3.2

28/fX (51.2

s) 216/fX (13.1 ms) 28/fX (51.2

Remarks 1. f

X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz.

Table 7-3. Interval Time of 8-Bit Timer 02

Minimum Interval Time Maximum Interval Time Resolution

23/fX (1.6

s) 211/fX (409.6

s) 23/fX (1.6

27/fX (25.6

s) 215/fX (6.55 ms) 27/fX (25.6

1/fXT (30.5

s) 28/fXT (7.81 ms) 1/fXT (30.5

Remarks 1. f

X: Main system clock oscillation frequency

2. f

XT: Subsystem clock oscillation frequency

3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

User’s Manual U13952EJ3V1UD 115

(2) External event counter

The number of pulses of an externally input signal can be measured.

(3) Square-wave output

A square wave of any frequency can be output.

Table 7-4. Square-Wave Output Range of 8-Bit Timer 02

Minimum Pulse Width Maximum Pulse Width Resolution

23/fX (1.6

s) 211/fX (409.6

s) 23/fX (1.6

27/fX (25.6

s) 215/fX (6.55 ms) 27/fX (25.6

1/fXT (30.5

s) 28/fXT (7.81 ms) 1/fXT (30.5

Remarks 1. f

X: Main system clock oscillation frequency

2. f

XT: Subsystem clock oscillation frequency

3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.

7.2 Configuration of 8-Bit Timer/Event Counters 00 to 02

8-bit timer/event counters 00 to 02 consist of the following hardware.

Table 7-5. Configuration of 8-Bit Timer/Event Counters 00 to 02

Item Configuration

Timer counter 8 bits × 3 (TM00, TM01, and TM02)

Timer output 1 (TO2)

Control registers 8-bit timer mode control registers 00, 01, and 02 (TMC00, TMC01, and TMC02)

Port mode register 2 (PM2)

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

116 User’s Manual U13952EJ3V1UD

Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 00

Internal bus

8-bit compare register 00

(CR00)

Match INTTM00

TI0/P24/INTP0

Selector

Clear

8-bit timer counter 00

(TM00)

Internal bus

TCE00

TCL001 TCL000

8-bit timer mode

control register 00 (TMC00)

Selector

Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter 01

Internal bus

8-bit compare register 01

(CR01)

Match INTTM01

Selector

Clear

8-bit timer counter 01 (TM01)

TCE01

TCL011 TCL010

8-bit timer mode

control register 01 (TMC01)

Internal bus

fX/24

fX/28

TI1/P25/INTP1

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

User’s Manual U13952EJ3V1UD 117

Figure 7-3. Block Diagram of 8-Bit Timer 02

Internal bus

8-bit compare register 02

(CR02)

Match INTTM02

Clear

8-bit timer counter 02

(TM02)

TO2/CMPTOUT0/

P23

TCE02 TCL021 TCL020 TOE02

8-bit timer mode

control register 02 (TMC02)

F/F

P23 output

latch PM23

ComparatorNote

Selector

Internal bus

Note See CHAPTER 12 COMPARATOR for details of the comparator.

(1) 8-bit compare register 0n (CR0n)

This is an 8-bit register that compares the value set to CR0n with the 8-bit timer counter 0n (TM0n) count

value, and if they match, an interrupt request (INTTM0n) is generated.

CR0n is set using an 8-bit memory manipulation instruction. Values from 00H to FFH can be set.

RESET input makes CR0n undefined.

Caution Be sure to stop the operation of the timer before rewriting CR0n. If CR0n is rewritten while

the timer is operation-enabled, an interrupt request match signal may be generated at the

time of the rewrite.

Remark n = 0 to 2

(2) 8-bit timer counter 0n (TM0n)

This is an 8-bit register that counts pulses.

TM0n is read using an 8-bit memory manipulation instruction.

RESET input sets TM0n to 00H.

Remark n = 0 to 2

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

118 User’s Manual U13952EJ3V1UD

7.3 Registers Controlling 8-Bit Timer/Event Counters 00 to 02

The following two registers are used to control 8-bit timer/event counters 00 to 02.

• 8-bit timer mode control registers 00, 01, and 02 (TMC00, TMC01, and TMC02)

• Port mode register 2 (PM2)

(1) 8-bit timer mode control register 00 (TMC00)

TMC00 enables/stops operation of 8-bit timer counter 00 (TM00) and sets the count clock of TM00.

TMC00 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets TMC00 to 00H.

Figure 7-4. Format of 8-Bit Timer Mode Control Register 00

TCE00

0000

TCL001 TCL000

0TMC00

R/W

FF53H 00H R/W

654321

TCL001

TCL000

TCE00

(78.1 kHz)

(9.76 kHz)

<7> 0

Operation enabled

Symbol Address After reset

Count clock selection of 8-bit timer/event counter 00

Rising edge of TI0

Falling edge of TI0

Operation control of 8-bit timer counter 00

Operation stopped (TM00 is cleared to 00H)

Caution Be sure to stop the operation of the timer before setting TMC00.

Remarks 1. f

X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz.

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

User’s Manual U13952EJ3V1UD 119

(2) 8-bit timer mode control register 01 (TMC01)

TMC01 determines whether to enable or stop operation of 8-bit timer counter 01 (TM01) and specifies the

count clock for 8-bit timer/event counter 01.

TMC01 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets TMC01 to 00H.

Figure 7-5. Format of 8-Bit Timer Mode Control Register 01

TCE01

0000

TCL011 TCL010

0TMC01

Symbol Address After reset R/W

FF57H 00H R/W

6<7> 543210

TCL011

Count clock selection of 8-bit timer/event counter 01

TCL010

Rising edge of TI1

Falling edge of TI1

TCE01

Operation control of 8-bit timer counter 01

Operation stopped (TM01 is cleared to 00H)

Operation enabled

(312.5 kHz)

(19.5 kHz)

Caution Be sure to stop the operation of the timer before setting TMC01.

Remarks 1. f

X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz.

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

120 User’s Manual U13952EJ3V1UD

(3) 8-bit timer mode control register 02 (TMC02)

TMC02 determines whether to enable or stop operation of 8-bit timer counter 02 (TM02) and specifies the

count clock for 8-bit timer 02. It also controls the operation of the output controller.

TMC02 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets TMC02 to 00H.

Figure 7-6. Format of 8-Bit Timer Mode Control Register 02

TCE02

0000

TCL021 TCL020

TOE02

TMC02

Symbol Address After reset R/W

FF5BH 00H R/W

6<7> <0>54321

TOE02

Output control of 8-bit timer 02

Output disabled (port mode)

Output enabled

TCL021

Count clock selection of 8-bit timer 02

TCL020

/23

/27

(32.768 kHz)

Setting prohibited

TCE02

Operation control of 8-bit timer counter 02

Operation stopped (TM02 is cleared to 00H)

Operation enabled

(625 kHz)

(39.1 kHz)

Caution Be sure to stop the operation of the timer before setting TMC02.

Remarks 1. f

X: Main system clock oscillation frequency

2. f

XT: Subsystem clock oscillation frequency

3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

User’s Manual U13952EJ3V1UD 121

(4) Port mode register 2 (PM2)

This register sets port 2 to input/output in 1-bit units.

When using the P23/COMPTOUT0/TO2 pin for timer output, set PM23 and the output latch of P23 to 0.

PM2 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PM2 to FFH.

Figure 7-7. Format of Port Mode Register 2

PM23

PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20PM2

7654 R/W

R/W

3210

Input mode (output buffer off)

Symbol Address

FF22H FFH

After reset

P23 pin I/O mode selection

Output mode (output buffer on)

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

122 User’s Manual U13952EJ3V1UD

7.4 Operation of 8-Bit Timer/Event Counters 00 to 02

7.4.1 Operation as interval timer

The interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit

compare registers 00, 01, and 02 (CR00, CR01, and CR02) in advance.

To operate the 8-bit timer/event counter as an interval timer, make the settings in the following order.

<1> Set 8-bit timer counter 0n (TM0n) to operation-disabled (TCE0n (bit 7 of 8-bit timer mode control register 0n

(TMC0n)) = 0)

<2> Select the count clock of the 8-bit timer/event counter (see Tables 7-6 to 7-8)

<3> Set the count value to CR0n

<4> Set TM0n to operation-enabled (TCE0n = 1)

When the count value of 8-bit timer counter 0n (TM0n) matches the value set to CR0n, the value of TM0n is

cleared to 00H and TM0n continues counting. At the same time, an interrupt request signal (INTTM0n) is generated.

Tables 7-6 through 7-8 show the interval time, and Figures 7-8 and 7-9 show the timing of interval timer operation.

Caution When the setting of the count clock using TMC0n and the setting of the TM0n to operation-

enable using an 8-bit memory manipulation instruction are performed at the same time, an error

of one clock or more may occur in the first cycle after the timer is started. Because of this,

when the 8-bit timer/event counter operates as an interval timer, be sure to make the settings in

the order described above.

Remark n = 0 to 2

Table 7-6. Interval Time of 8-Bit Timer/Event Counter 00

TCL001 TCL000 Minimum Interval Time Maximum Interval Time Resolution

0 0

26/fX (12.8

s) 214/fX (3.28 ms) 26/fX (12.8

0 1

29/fX (102.4

s) 217/fX (26.2 ms) 29/fX (102.4

1 0 TI0 input cycle 28 × TI0 input cycle TI0 input edge cycle

1 1 TI0 input cycle 28 × TI0 input cycle TI0 input edge cycle

Remarks 1. f

X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz.

Table 7-7. Interval Time of 8-Bit Timer/Event Counter 01

TCL011 TCL010 Minimum Interval Time Maximum Interval Time Resolution

0 0

24/fX (3.2

s) 212/fX (819.2

s) 24/fX (3.2

0 1

28/fX (51.2

s) 216/fX (13.1 ms) 28/fX (51.2

1 0 TI1 input cycle 28 × TI1 input cycle TI1 input edge cycle

1 1 TI1 input cycle 28 × TI1 input cycle TI1 input edge cycle

Remarks 1. f

X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz.

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

User’s Manual U13952EJ3V1UD 123

Table 7-8. Interval Time of 8-Bit Timer 02

TCL021 TCL020 Minimum Interval Time Maximum Interval Time Resolution

0 0

23/fX (1.6

s) 211/fX (409.6

s) 23/fX (1.6

0 1

27/fX (25.6

s) 215/fX (6.55 ms) 27/fX (25.6

1 0

1/fXT (30.5

s) 28/fXT (7.81 ms) 1/fXT (30.5

1 1 Setting prohibited

Remarks 1. f

X: Main system clock oscillation frequency

2. f

XT: Subsystem clock oscillation frequency

3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.

Figure 7-8. Interval Timer Operation Timing of Timer 00 and Timer 01

Clear Clear

Interrupt acknowledged Interrupt acknowledged

Count start

Interval time Interval time Interval time

Count clock

TM0n count value

CR0n

TCE0n

INTTM0n

N0100N0100N00 01

NN NN

Remarks 1. Interval time = (N + 1) × t where N = 00H to FFH

2. n = 0, 1

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

124 User’s Manual U13952EJ3V1UD

Figure 7-9. Interval Timer Operation Timing of Timer 02

Clear Clear

Interrupt acknowledged Interrupt acknowledged

Count start

Interval time Interval time Interval time

Count clock

TM02 count value

CR02

TCE02

INTTM02

TO2

N0100N0100N00 01

NN NN

Remark Interval time = (N + 1) × t where N = 00H to FFH

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

User’s Manual U13952EJ3V1UD 125

7.4.2 Operation as external event counter (timer 00 and timer 01 only)

The external event counter counts the number of external clock pulses input to the TI0/P24/INTP0 and

TI1/P25/INTP1 pins by using 8-bit timer counters 00 and 01 (TM00 and TM01).

To operate 8-bit timer/event counters 00 and 01 as an external event counter, make the settings in the following

order.

<1> Set P24 and P25 to input mode (PM24 = 1, PM25 = 1)

<2> Set 8-bit timer counter 0n (TM0n) to operation-disabled (TCE0n (bit 7 of 8-bit timer mode control register 0n

(TMC0n)) = 0)

<3> Specify the rising edge/falling edge of TIn (see Tables 7-6 and 7-7)

<4> Set the count value to CR0n

<5> Set TM0n to operation-enabled (TCE0n = 1)

Each time the valid edge specified by bit 1 (TCL0n0) of TMC0n is input, the value of 8-bit timer counter 0n (TM0n)

is incremented.

When the count value of TM0n matches the value set to CR0n, the value of TM0n is cleared to 00H and TM0n

continues counting. At the same time, an interrupt request signal (INTTM0n) is generated.

Figure 7-10 shows the timing of external event counter operation (with rising edge specified).

Caution When the setting of the count clock using TMC0n and the setting of the TM0n to operation-

enable using an 8-bit memory manipulation instruction are performed at the same time, an error

of one clock or more may occur in the first cycle after the timer is started. Because of this,

when the 8-bit timer/event counter operates as an external event counter, be sure to make the

settings in the order described above.

Remark n = 0, 1

Figure 7-10. External Event Counter Operation Timing (with Rising Edge Specified)

TIn pin input

TM0n count value

CR0n

TCE0n

INTTM0n

00 01 02 03 04 05

N – 1

N 00010203

Remarks 1. N = 00H to FFH

2. n = 0, 1

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

126 User’s Manual U13952EJ3V1UD

7.4.3 Operation as square-wave output (timer 02 only)

The 8-bit timer can generate a square-wave output of any frequency at intervals specified by the count value

preset to 8-bit compare register 02 (CR02).

To operate 8-bit timer 02 as a square-wave output, make the settings in the following order.

<1> Set P23 to output mode (PM23 = 0), and set the output latch of P23 to 0

<2> Disable 8-bit timer counter 02 (TM02) operation (TCE02 (bit 0 of 8-bit timer mode control register 02

(TMC02)) = 1)

<3> Set the count clock of 8-bit timer 02 (see Table 7-9), and enable TO2 to output (TOE02 (bit 0 of TMC02) = 1)

<4> Set the count value to CR02

<5> Enable TM02 operation (TCE02 = 1)

When the count value of 8-bit timer counter 02 (TM02) matches the value set in CR02, the TO2/P23/CMPTOUT0

pin output is inverted. Through application of this mechanism, square waves of any frequency can be output. As

soon as a match occurs, the TM02 value is cleared to 00H, then counting continues count and an interrupt request

signal (INTTM02) is generated.

Setting bit 7 of TMC02 (TCE02) to 0 clears the square-wave output to 0.

Table 7-9 lists the square-wave output range, and Figure 7-11 shows the timing of square-wave output.

Caution When the setting of the count clock using TMC02 and the setting of the TM02 to operation-

enable using an 8-bit memory manipulation instruction are performed at the same time, an error

of one clock or more may occur in the first cycle after the timer is started. Because of this,

when the 8-bit timer operates as a square-wave output, be sure to make the settings in the order

described above.

Table 7-9. Square-Wave Output Range of 8-Bit Timer 02

TCL021 TCL020 Minimum Pulse Width Maximum Pulse Width Resolution

0 0

23/fX (1.6

s) 211/fX (409.6

s) 23/fX (1.6

0 1

27/fX (25.6

s) 215/fX (6.55 ms) 27/fX (25.6

1 0

1/fXT (30.5

s) 28/fXT (7.81 ms) 1/fXT (30.5

1 1 Setting prohibited

Remarks 1. f

X: Main system clock oscillation frequency

2. f

XT: Subsystem clock oscillation frequency

3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

User’s Manual U13952EJ3V1UD 127

Figure 7-11. Square-Wave Output Timing

Clear Clear

Interrupt acknowledged Interrupt acknowledged

Count start

Count clock

TM02 count value

CR02

TCE02

INTTM02

TO2

Note

N0100N0100N00 01

NN NN

Note The initial value of TO2 when output is enabled (TOE02 = 1) becomes low level.

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02

128 User’s Manual U13952EJ3V1UD

7.5 Cautions on Using 8-Bit Timer/Event Counters 00 to 02

(1) Error on starting timer

An error of up to 1 clock occurs after the timer has been started until a match signal is generated. This is

because 8-bit timer counters 00, 01, and 02 (TM00, TM01, and TM02) are started asynchronous to the count

pulse.

Figure 7-12. Start Timing of 8-Bit Timer Counters 00, 01, and 02

Count pulse

TM00, TM01, TM02

count value

Timer starts

00H 01H 02H 03H 04H

(2) Setting of 8-bit compare register

8-bit compare registers 00, 01, and 02 (CR00, CR01, and CR02) can be set to 00H.

Therefore, one pulse can be counted when an 8-bit timer/event counter operates as an event counter.

Figure 7-13. External Event Counter Operation Timing

TI0, TI1 input

CR00, CR01 00H

TM00, TM01

count value

00H 00H 00H 00H

Interrupt request flag

User’s Manual U13952EJ3V1UD 129

CHAPTER 8 WATCH TIMER

8.1 Functions of Watch Timer

The watch timer has the following functions.

• Watch timer

• Interval timer

The watch and interval timers can be used at the same time.

Figure 8-1 is a block diagram of the watch timer.

Figure 8-1. Block Diagram of Watch Timer

Clear

9-bit prescaler

Selector

Clear

5-bit counter INTWT

INTWTI

WTM7 WTM6 WTM5 WTM4 WTM1 WTM0

Watch timer mode

control register (WTM)

Internal bus

Selector

CHAPTER 8 WATCH TIMER

130 User’s Manual U13952EJ3V1UD

(1) Watch timer

The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to issue an interrupt request

(INTWT) at 0.5-second intervals.

Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a

0.5-second interval. In this case, the subsystem clock, which operates at 32.768 kHz,

should be used instead.

(2) Interval timer

The interval timer is used to generate an interrupt request (INTWT) at specified intervals.

Table 8-1. Interval Time of Interval Timer

Interval Operation at fX = 5.0 MHz Operation at fX = 4.19 MHz Operation at fXT = 32.768 kHz

24 × 1/fW 409.6

s 489

s 488

25 × 1/fW 819.2

s 978

s 977

26 × 1/fW 1.64 ms 1.96 ms 1.95 ms

27 × 1/fW 3.28 ms 3.91 ms 3.91 ms

28 × 1/fW 6.55 ms 7.82 ms 7.81 ms

29 × 1/fW 13.1 ms 15.6 ms 15.6 ms

Remark f

W: Watch timer clock frequency (fX/27 or fXT)

X: Main system clock oscillation frequency

fXT: Subsystem clock oscillation frequency

8.2 Configuration of Watch Timer

The watch timer consists of the following hardware.

Table 8-2. Configuration of Watch Timer

Item Configuration

Counter 5 bits × 1

Prescaler 9 bits × 1

Control register Watch timer mode control register (WTM)

CHAPTER 8 WATCH TIMER

User’s Manual U13952EJ3V1UD 131

8.3 Register Controlling Watch Timer

The watch timer mode control register (WTM) is used to control the watch timer.

• Watch timer mode control register (WTM)

WTM selects a count clock for the watch timer and specifies whether to enable operation of the timer. It also

specifies the prescaler interval and how the 5-bit counter is controlled.

WTM is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets WTM to 00H.

Figure 8-2. Format of Watch Timer Mode Control Register

Watch timer count clock selection

WTM7 WTM6 WTM5 WTM4 0 0 WTM1 WTM0WTM

Symbol Address After reset R/W

FF4AH 00H R/W

76543210

WTM7

Prescaler interval selectionWTM6

WTM5

(488 s)

(977 s)

(1.95 ms)

(3.91 ms)

(7.81 ms)

(15.6 ms)

WTM4

Control of 5-bit counter operation

WTM1

Cleared after stop

Started

Watch timer operationWTM0

Operation stopped (both prescaler and timer cleared)

Operation enabled

Other than above

(32.768 kHz)

(39.1 kHz)

Setting prohibited

Remarks 1. fW: Watch timer clock frequency (fX/27 or fXT)

2. f

X: Main system clock oscillation frequency

3. f

XT: Subsystem clock oscillation frequency

4. The parenthesized values apply to operation at fW = 32.768 kHz.

CHAPTER 8 WATCH TIMER

132 User’s Manual U13952EJ3V1UD

8.4 Operation of Watch Timer

8.4.1 Operation as watch timer

The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used as a watch timer that generates

interrupts at 0.5-second intervals.

By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer

starts counting. By setting them to 0, the 5-bit counter is cleared and the watch timer stops counting.

When the interval timer also operates at the same time by setting WTM1 to 0, only the watch timer can be started

from 0 seconds. However, an error of up to 29 × 1/fW seconds may occur for the first overflow of the watch timer

(INTWT) after a 0-second start, because the 9-bit prescaler is not cleared in this case.

8.4.2 Operation as interval timer

The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count

value.

The interval time can be selected by bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM).

Table 8-3. Interval Time of Interval Timer

WTM6 WTM5 WTM4 Interval Operation at

fX = 5.0 MHz

Operation at

fX = 4.19 MHz

Operation at

fXT = 32.768 kHz

0 0 0

24 × 1/fW 409.6

s 489

s 488

0 0 1

25 × 1/fW 819.2

s 978

s 977

0 1 0

26 × 1/fW 1.64 ms 1.96 ms 1.95 ms

0 1 1

27 × 1/fW 3.28 ms 3.91 ms 3.91 ms

1 0 0

28 × 1/fW 6.55 ms 7.82 ms 7.81 ms

1 0 1

29 × 1/fW 13.1 ms 15.6 ms 15.6 ms

Other than above Setting prohibited

Remark f

X: Main system clock oscillation frequency

XT: Subsystem clock oscillation frequency

W: Watch timer clock frequency

CHAPTER 8 WATCH TIMER

User’s Manual U13952EJ3V1UD 133

Figure 8-3. Watch Timer/Interval Timer Operation Timing

Start Overflow Overflow

5-bit counter

Count clock

Watch timer

interrupt

INTWT

Interval timer

interrupt

INTWTI

Watch timer interrupt time (0.5 s) Watch timer interrupt time (0.5 s)

Interval

timer (T)

Remark fW: Watch timer clock frequency

The parenthesized values apply to operation at fW = 32.768 kHz.

134 User’s Manual U13952EJ3V1UD

CHAPTER 9 WATCHDOG TIMER

9.1 Functions of Watchdog Timer

The watchdog timer has the following functions.

• Watchdog timer

• Interval timer

Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode

(1) Watchdog timer

The watchdog timer is used to detect an inadvertent program loop. When the program loop is detected, a

non-maskable interrupt or the RESET signal can be generated.

Table 9-1. Program Loop Detection Time of Watchdog Timer

Program Loop Detection Time Operation at fX = 5.0 MHz

211 × 1/fX 410

213 × 1/fX 1.64 ms

215 × 1/fX 6.55 ms

217 × 1/fX 26.2 ms

fX: Main system clock oscillation frequency

(2) Interval timer

The interval timer generates an interrupt at any intervals set in advance.

Table 9-2. Interval Time

Interval Time Operation at fX = 5.0 MHz

211 × 1/fX 410

213 × 1/fX 1.64 ms

215 × 1/fX 6.55 ms

217 × 1/fX 26.2 ms

fX: Main system clock oscillation frequency

CHAPTER 9 WATCHDOG TIMER

User’s Manual U13952EJ3V1UD 135

9.2 Configuration of Watchdog Timer

The watchdog timer consists of the following hardware.

Table 9-3. Configuration of Watchdog Timer

Item Configuration

Control registers Timer clock selection register 2 (TCL2)

Watchdog timer mode register (WDTM)

Figure 9-1. Block Diagram of Watchdog Timer

Internal bus

Prescaler

Selector

Controller

7-bit counter

Clear

TMIF4

TMMK4

TCL22 TCL21 TCL20

Timer clock selection register 2

(TCL2)

Watchdog timer mode register

(WDTM)

WDTM4

RUN

WDTM3

INTWDT

maskable

interrupt request

RESET

INTWDT

non-maskable

interrupt request

CHAPTER 9 WATCHDOG TIMER

136 User’s Manual U13952EJ3V1UD

9.3 Registers Controlling Watchdog Timer

The following two registers are used to control the watchdog timer.

• Timer clock selection register 2 (TCL2)

• Watchdog timer mode register (WDTM)

(1) Timer clock selection register 2 (TCL2)

This register sets the watchdog timer count clock.

TCL2 is set using an 8-bit memory manipulation instruction.

RESET input sets TCL2 to 00H.

Figure 9-2. Format of Timer Clock Selection Register 2

TCL22

00000TCL22 TCL21 TCL20TCL2

R/W

76543210

TCL21

fX/24

fX/26

fX/28

fX/210

211/fX

213/fX

215/fX

217/fX

TCL20

Setting prohibited

Symbol Address

FF42H 00H

After reset

Other than above

Watchdog timer count clock selection Interval time

(410 s)

(1.64 ms)

(6.55 ms)

(26.2 ms)

(312.5 kHz)

(78.1 kHz)

(19.5 kHz)

(4.88 kHz)

Remarks 1. fX: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz.

CHAPTER 9 WATCHDOG TIMER

User’s Manual U13952EJ3V1UD 137

(2) Watchdog timer mode register (WDTM)

This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog

timer.

WDTM is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets WDTM to 00H.

Figure 9-3. Format of Watchdog Timer Mode Register

RUN

Selection of operation of watchdog timer

Note 1

RUN 0 0

WDTM4 WDTM3

000WDTM

Symbol Address After reset R/W

FFF9H 00H R/W

<7>6543210

Stop counting

Clear counter and start counting

WDTM4

Selection of operation mode of watchdog timer

Note 2

WDTM3

Operation stopped

Interval timer mode (overflow and maskable interrupt occur)

Note 3

Watchdog timer mode 1 (overflow and non-maskable interrupt occur)

Watchdog timer mode 2 (overflow occurs and reset operation started)

Notes 1. Once RUN has been set to (1), it cannot be cleared to (0) by software. Therefore, when counting is

started, it cannot be stopped by any means other than RESET input.

2. Once WDTM3 and WDTM4 have been set to (1), they cannot be cleared to (0) by software.

3. The watchdog timer starts operation as an interval timer when RUN is set to 1.

Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to

0.8% shorter than the time set by timer clock selection register 2 (TCL2).

2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming that TMIF4 (bit 0 of interrupt

request flag register 0 (IF0)) is set to 0. While TMIF4 is 1, a non-maskable interrupt is

generated upon write completion if watchdog timer mode 1 or 2 is selected.

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138 User’s Manual U13952EJ3V1UD

9.4 Operation of Watchdog Timer

9.4.1 Operation as watchdog timer

The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register

(WDTM) is set to 1.

The count clock (program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20

to TCL22) of timer clock selection register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is

started. Set RUN to 1 within the set program loop detection time interval after the watchdog timer has been started.

By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the program

loop detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the value of bit 3

(WDTM3) of WDTM.

The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1

before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.

Cautions 1. The actual program loop detection time may be up to 0.8% shorter than the set time.

2. When the subsystem clock is selected as the CPU clock, the watchdog timer stops counting.

Table 9-4. Program Loop Detection Time of Watchdog Timer

TCL22 TCL21 TCL20 Program Loop Detection Time Operation at fX = 5.0 MHz

0 0 0

211 × 1/fX 410

0 1 0

213 × 1/fX 1.64 ms

1 0 0

215 × 1/fX 6.55 ms

1 1 0

217 × 1/fX 26.2 ms

fX: Main system clock oscillation frequency

CHAPTER 9 WATCHDOG TIMER

User’s Manual U13952EJ3V1UD 139

9.4.2 Operation as interval timer

When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,

respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time

intervals specified by a preset count value.

Select the count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock selection register 2

(TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1.

In the interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be

generated. The priority of INTWDT is set as the highest of all the maskable interrupts.

The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1

before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.

Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the

interval timer mode is not set, unless the RESET signal is input.

2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the

set time.

Table 9-5. Interval Time of Interval Timer

TCL22 TCL21 TCL20 Interval Time Operation at fX = 5.0 MHz

0 0 0

211 × 1/fX 410

0 1 0

213 × 1/fX 1.64 ms

1 0 0

215 × 1/fX 6.55 ms

1 1 0

217 × 1/fX 26.2 ms

fX: Main system clock oscillation frequency

User’s Manual U13952EJ3V1UD

140

CHAPTER 10 8-BIT A/D CONVERTER (

PD789407A SUBSERIES)

10.1 Function of 8-Bit A/D Converter

The 8-bit A/D converter converts input analog voltages to digital signals with an 8-bit resolution. It can control up

to seven analog input channels (ANI0 to ANI6).

A/D conversion can be started only by software.

One of analog inputs ANI0 to ANI6 is selected for A/D conversion. A/D conversion is performed repeatedly, with

an interrupt request (INTAD0) being issued each time an A/D conversion is completed.

10.2 Configuration of 8-Bit A/D Converter

The 8-bit A/D converter consists of the following hardware.

Table 10-1. Configuration of 8-Bit A/D Converter

Item Configuration

Analog inputs 7 channels (ANI0 to ANI6)

Registers Successive approximation register (SAR)

A/D conversion result register 0 (ADCR0)

Control registers A/D converter mode register 0 (ADM0)

A/D input selection register 0 (ADS0)

CHAPTER 10 8-BIT A/D CONVERTER (

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Figure 10-1. Block Diagram of 8-Bit A/D Converter

ANI0/P60

ANI1/P61

ANI2/P62

ANI3/P63

ANI4/P64

ANI5/P65

ANI6/P66

Selector

Sample & hold circuit

Voltage comparator

Series resistor string

Successive

approximation

Controller

A/D conversion result

Tap selector

INTAD0

A/D converter mode

A/D input selection

Internal bus

ADCS0

FR02 FR01 FR00

ADS02 ADS01 ADS00

REF

P-ch

(1) Successive approximation register (SAR)

The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison

voltage), received from the series resistor string, starting from the most significant bit (MSB).

Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D

conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0).

(2) A/D conversion result register 0 (ADCR0)

ADCR0 holds the result of A/D conversion. Each time A/D conversion ends, the conversion result received

from the successive approximation register is loaded into ADCR0, which is an 8-bit register that holds the

result of A/D conversion.

ADCR0 is read using an 8-bit memory manipulation instruction.

RESET input makes ADCR0 undefined.

(3) Sample & hold circuit

The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends

them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.

(4) Voltage comparator

The voltage comparator compares an analog input with the voltage output by the series resistor string.

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(5) Series resistor string

The series resistor string is configured between AVREF and AVSS. It generates the reference voltages against

which analog inputs are compared.

(6) ANI0 to ANI6 pins

The ANI0 to ANI6 pins are analog input pins for the seven-channel A/D converter. They are used to receive

the analog signals to be subject to A/D conversion.

Caution Do not supply the ANI0 to ANI6 pins with voltages that fall outside the rated range. If a

voltage greater than AVREF or less than AVSS (even if within the absolute maximum rating) is

supplied to any of these pins, the conversion value for the corresponding channel will be

undefined. Furthermore, the conversion values for the other channels may also be

affected.

(7) AVREF pin

The AVREF pin is a reference voltage pin for the A/D converter.

Signals received at the ANI0 to ANI6 pins are converted to digital signals based on the voltage across the

AVREF and AVSS pins.

(8) AVSS pin

The AVSS pin is a ground potential pin for the A/D converter. This pin must be held at the same potential as

the VSS0 pin, even while the A/D converter is not being used.

(9) AVDD pin

The AVDD pin is an analog power supply pin for the A/D converter. This pin must be held at the same

potential as the VDD0 pin, even while the A/D converter is not being used.

CHAPTER 10 8-BIT A/D CONVERTER (

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User’s Manual U13952EJ3V1UD 143

10.3 Registers Controlling 8-Bit A/D Converter

The following two registers are used to control the 8-bit A/D converter.

• A/D converter mode register 0 (ADM0)

• A/D input selection register 0 (ADS0)

(1) A/D converter mode register 0 (ADM0)

ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion.

ADM0 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets ADM0 to 00H.

Figure 10-2. Format of A/D Converter Mode Register 0

A/D conversion control

ADCS0

0 FR02 FR01 FR00 0 0 0ADM0

Symbol Address After reset R/W

FF80H 00H R/W

<7>6543210

ADCS0

A/D conversion time selection

Note 1

FR02

144/fx

120/fx

96/fx

72/fx

60/fx

48/fx

FR01

(28.8 s)

(24 s)

(19.2 s)

(14.4 s)

(Setting prohibited

Note 2

)

(Setting prohibited

Note 2

)

FR00

Other than above

Conversion stopped

Conversion enabled

Setting prohibited

Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least

2. These bit combinations must not be used, as the A/D conversion time will fall below 14

Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined.

2. The result of conversion performed after ADCS0 is cleared may be undefined (see 10.5 (5)

Timing that makes the A/D conversion result undefined for details).

Remarks 1. f

X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz.

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(2) A/D input selection register 0 (ADS0)

ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal.

ADS0 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets ADS0 to 00H.

Figure 10-3. Format of A/D Input Selection Register 0

00000

ADS02 ADS01 ADS00

ADS0

Symbol Address After reset R/W

FF84H 00H R/W

76543210

Analog input channel specification

ADS02

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

Setting prohibited

ADS01

ADS00

Caution Bits 3 to 7 must be fixed to 0.

CHAPTER 10 8-BIT A/D CONVERTER (

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User’s Manual U13952EJ3V1UD 145

10.4 Operation of 8-Bit A/D Converter

10.4.1 Basic operation of 8-bit A/D converter

<1> Select a channel for A/D conversion, using A/D input selection register 0 (ADS0).

<2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit.

<3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input

analog voltage until A/D conversion is completed.

<4> Bit 7 of the successive approximation register (SAR) is set. The series resistor string voltage tap at the tap

selector is set to half of AVREF.

<5> The series resistor string tap voltage is compared with the analog input voltage using the voltage comparator.

If the analog input voltage is higher than half of AVREF, the MSB of the SAR remains set. If it is lower than

half of AVREF, the MSB is reset.

<6> Bit 6 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the

series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows:

• Bit 7 = 1: Three quarters of AVREF

• Bit 7 = 0: One quarter of AVREF

The tap voltage is compared with the analog input voltage. Bit 6 is set or reset according to the result of

comparison.

• Analog input voltage ≥ tap voltage: Bit 6 = 1

• Analog input voltage < tap voltage: Bit 6 = 0

<7> Comparison is repeated until bit 0 of the SAR is reached.

<8> When comparison is completed for all of the 8 bits, a significant digital result is left in the SAR. This value is

sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate

an A/D conversion end interrupt request (INTAD0).

Cautions 1. The first A/D conversion value immediately following the start of A/D conversion may be

undefined.

2. When the A/D converter enters the standby mode, it stops operating.

CHAPTER 10 8-BIT A/D CONVERTER (

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Figure 10-4. Basic Operation of 8-Bit A/D Converter

Conversion

time

Sampling

time

Sampling A/D conversion

Undefined 80H C0H

or 40H

Conversion

result

Conversion

result

A/D converter

operation

SAR

ADCR0

INTAD0

A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software.

If an attempt is made to write to ADM0 or A/D input selection register 0 (ADS0) during A/D conversion, the current

A/D conversion is canceled. In this case, A/D conversion is restarted from the beginning, if the ADCS0 bit is set (1).

RESET makes A/D conversion result register 0 (ADCR0) undefined.

10.4.2 Input voltage and conversion result

The relationship between the analog input voltage at the analog input pins (ANI0 to ANI6) and the A/D conversion

result (A/D conversion result register 0 (ADCR0)) is represented by:

ADCR0 = INT ( × 256 + 0.5)

(ADCR0 – 0.5) × ≤ VIN < (ADCR0 + 0.5) ×

INT( ): Function that returns the integer part of a parenthesized value

VIN: Analog input voltage

AVREF: AVREF pin voltage

ADCR0: Value in A/D conversion result register 0 (ADCR0)

Figure 10-5 shows the relationship between the analog input voltage and the A/D conversion result.

VIN

AVREF

256

AVREF

256

CHAPTER 10 8-BIT A/D CONVERTER (

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Figure 10-5. Relationship Between Analog Input Voltage and A/D Conversion Result

255

254

253

A/D conversion

result (ADCR0)

512

256

512

256

512

256

507

512

254

256

509

512

255

256

511

512

Input voltage/AVREF

CHAPTER 10 8-BIT A/D CONVERTER (

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10.4.3 Operation mode of 8-bit A/D converter

The 8-bit A/D converter is initially in the select mode. In this mode, A/D input selection register 0 (ADS0) is used

to select an analog input channel from ANI0 to ANI6 for A/D conversion.

A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADM0).

The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt

request signal (INTAD0) is generated.

• Software-started A/D conversion

Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for a voltage applied to

the analog input pin specified in A/D input selection register 0 (ADS0). Upon completion of A/D conversion, the

conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request

signal (INTAD0) is generated. Once A/D conversion is activated, and completed, another session of A/D

conversion is started. A/D conversion is repeated until new data is written to ADM0. If data where the ADCS0

bit is 1 is written to ADM0 again during A/D conversion, the current session of A/D conversion is discontinued,

and a new session of A/D conversion begins for the new data. If data where the ADCS0 bit is 0 is written to

ADM0 again during A/D conversion, A/D conversion is stopped immediately.

Figure 10-6. Software-Started A/D Conversion

Rewriting ADM0

ADCS0 = 1

Rewriting ADM0

ADCS0 = 1 ADCS0 = 0

A/D conversion

ADCR0

INTAD0

ANIn ANIn ANIn ANIm ANIm

Stop

ANIn ANIn ANIm

Conversion is

discontinued;

no conversion

result is preserved.

Remarks 1. n = 0, 1, ..., 6

2. m = 0, 1, ..., 6

CHAPTER 10 8-BIT A/D CONVERTER (

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10.5 Cautions on Using 8-Bit A/D Converter

(1) Current consumption in the standby mode

When the A/D converter enters the standby mode, it stops operating. Stopping conversion (bit 7 (ADCS0) of

A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption.

Figure 10-7 shows how to reduce the current consumption in the standby mode.

Figure 10-7. How to Reduce Current Consumption in Standby Mode

REF

P-ch

Series resistor string

ADCS0

(2) Input range for the ANI0 to ANI6 pins

Be sure to keep the input voltage at ANI0 to ANI6 within the rated range. If a voltage greater than AVREF or

less than AVSS (even within the absolute maximum rating) is input to a conversion channel, the conversion

output of the channel becomes undefined, and the conversion output of the other channels may also be

affected.

(3) Conflict

<1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and reading

from the ADCR0 bit

Reading from the ADCR0 bit takes precedence. After reading, the new conversion result is written to the

ADCR0 bit.

<2> Conflict between writing to the ADCR0 bit at the end of conversion and writing to A/D converter mode

Writing to ADM0 or ADS0 takes precedence. A request to write to the ADCR0 bit is ignored. No A/D

conversion end interrupt request signal (INTAD0) is generated.

(4) Conversion results immediately following start of A/D conversion

The first A/D conversion value immediately following the start of A/D conversion may be undefined. Be sure

to poll the A/D conversion end interrupt request (INTAD0) and perform processing such as discarding the first

conversion result.

(5) Timing that makes the A/D conversion result undefined

If the timing of the end of A/D conversion and the timing of the stop of operation of the A/D converter conflict,

the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result

while the A/D converter is in operation. Furthermore, when reading out an A/D conversion result after A/D

conversion has stopped, be sure to have done so by the time the next conversion result is complete.

The conversion result readout timing is shown in Figures 10-8 and 10-9.

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Figure 10-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value)

A/D conversion end A/D conversion end

Normal conversion result Undefined value

Normal conversion result read out A/D operation stopped Undefined

value read out

ADCR0

INTAD0

ADCS0

Figure 10-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value)

Normal conversion result

A/D conversion end

Normal conversion

result read out

A/D operation stopped

ADCR0

INTAD0

ADCS0

(6) Noise elimination

To maintain a resolution of 8 bits, it is necessary to avoid noise at the AVREF and ANI0 to ANI6 pins. The

higher the output impedance of the analog input source, the larger the effect by noise. To eliminate noise,

attach an external capacitor to the relevant pins as shown in Figure 10-10.

CHAPTER 10 8-BIT A/D CONVERTER (

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Figure 10-10. Analog Input Pin Processing

Reference voltage

input

C = 100 to 1000 pF

If noise greater than AV

REF

or less than

is likely to come to the AV

REF

pin, clamp

the voltage at the pin by attaching a diode with a

small V

(0.3 V or lower).

DD0

SS0

REF

(7) ANI0 to ANI6

The analog input pins (ANI0 to ANI6) are alternate-function pins. They are also used as port pins (P60 to

P66).

If any of ANI0 to ANI6 has been selected for A/D conversion, do not execute input instructions for the ports.

Otherwise, the conversion resolution may become lower.

If a digital pulse is applied to a pin adjacent to the analog input pins during A/D conversion, coupling noise

may occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital

pulse to pins adjacent to the analog input pins during A/D conversion.

(8) Input impedance of ANI0 to ANI6 pins

This A/D converter charges the internal sampling capacitor for about 1/10 of the conversion time, and

performs sampling.

Therefore at times other than sampling, only the leak current is output. During sampling, the current for

charging the capacitor is also output, so the input impedance fluctuates and has no meaning.

However, to ensure adequate sampling, it is recommended that the output impedance of the analog input

source be set to below 10 kΩ, or a 100 pF capacitor be connected to the ANI0 to ANI6 pins (see Figure 10-

10).

(9) Input impedance of the AVREF pin

A series resistor string of several tens of kΩ is connected across the AVREF and AVSS pins.

If the output impedance of the reference voltage source is high, this high impedance is eventually connected

in parallel with the series resistor string across the AVREF and AVSS pins, leading to a higher reference

voltage error.

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(10) Interrupt request flag (ADIF0)

Changing the contents of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag

(ADIF0).

If the voltage at the analog input pins is changed during A/D conversion, therefore, the A/D conversion result

and the conversion end interrupt request flag may reflect the previous analog input just before writing to

ADM0. In this case, the ADIF0 may appear to be set if it is read-accessed just after ADM0 is write-accessed,

even when A/D conversion has not been completed for the new analog input.

In addition, ADIF0 must be cleared before A/D conversion is restarted.

Figure 10-11. A/D Conversion End Interrupt Request Generation Timing

Rewriting to ADM0

(to begin conversion

for ANIn)

A/D conversion

ADCR0

INTAD0

ANIn ANIn ANIm

ANIm

Rewriting to ADM0

(to begin conversion

for ANIm)

ADIF0 has been set, but conversion

for ANIm has not been completed.

Remarks 1. n = 0, 1, ..., 6

2. m = 0, 1, ..., 6

(11) AVDD pin

The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to

ANI6 input circuit.

If your application is designed to be switched to backup power, the AVDD pin must be supplied with the same

voltage level as for the VDD0 pin, as shown in Figure 10-12.

Figure 10-12. AVDD Pin Processing

Main power

source Backup

capacitor

VDD0

AVDD

VSS0

AVSS

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CHAPTER 11 10-BIT A/D CONVERTER (

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11.1 Function of 10-Bit A/D Converter

The 10-bit A/D converter converts input analog voltages to digital signals with a 10-bit resolution. It can control up

to seven analog input channels (ANI0 to ANI6).

A/D conversion can be started only by software.

One of analog inputs ANI0 to ANI6 is selected for A/D conversion. A/D conversion is performed repeatedly, with

an interrupt request (INTAD0) being issued each time an A/D conversion is completed.

11.2 Configuration of 10-Bit A/D Converter

The A/D converter consists of the following hardware.

Table 11-1. Configuration of 10-Bit A/D Converter

Item Configuration

Analog inputs 7 channels (ANI0 to ANI6)

Registers Successive approximation register (SAR)

A/D conversion result register 0 (ADCR0)

Control registers A/D converter mode register 0 (ADM0)

A/D input selection register 0 (ADS0)

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Figure 11-1. Block Diagram of 10-Bit A/D Converter

ANI0/P60

ANI1/P61

ANI2/P62

ANI3/P63

ANI4/P64

ANI5/P65

ANI6/P66

Selector

Sample & hold circuit

Series resistor string

Voltage comparator

Successive

approximation

Controller

A/D conversion result

Tap selector

AVSS

INTAD0

A/D converter mode

A/D input selection

Internal bus

AVSS

ADCS0

FR02 FR01 FR00

ADS02 ADS01 ADS00

AVREF

P-ch

AVDD

(1) Successive approximation register (SAR)

The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison

voltage), received from the series resistor string, starting from the most significant bit (MSB).

Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D

conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0).

(2) A/D conversion result register 0 (ADCR0)

ADCR0 is a 16-bit register that holds the result of A/D conversion. Lower 6 bits are fixed to 0. Each time A/D

conversion ends, the conversion result in the successive approximation register is loaded into ADCR0. The

conversion results are stored in ADCR0 starting from the most significant bit (MSB). The higher 8 bits of the

conversion results are stored in FF15H and the lower 2 bits of the conversion results are stored in FF14H.

ADCR0 is read using a 16-bit memory manipulation instruction.

RESET input makes ADCR0 undefined.

Symbol

ADCR0

FF15H

000

FF14H

FF14H,

FF15H

Address After reset

Undefined

R/W

Caution When the

PD78F9418A is used as the flash memory version of the

PD789405A, 789406A,

and 789407A, 8-bit access is possible, providing an object file has been assembled in the

PD789405A, 789406A, and 789407A.

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(3) Sample & hold circuit

The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends

them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.

(4) Voltage comparator

The voltage comparator compares an analog input with the voltage output by the series resistor string.

(5) Series resistor string

The series resistor string is configured between AVREF and AVSS. It generates the reference voltages against

which analog inputs are compared.

(6) ANI0 to ANI6 pins

The ANI0 to ANI6 pins are analog input pins for the seven-channel A/D converter. They are used to receive

the analog signals to be subject to A/D conversion.

Caution Do not supply the ANI0 to ANI6 pins with voltages that fall outside the rated range. If a

voltage greater than AVREF or less than AVSS (even if within the absolute maximum rating) is

supplied to any of these pins, the conversion value for the corresponding channel will be

undefined. Furthermore, the conversion values for the other channels may also be

affected.

(7) AVREF pin

The AVREF pin is a reference voltage pin for the A/D converter.

Signals received at the ANI0 to ANI6 pins are converted to digital signals based on the voltage across the

AVREF and AVSS pins.

(8) AVSS pin

The AVSS pin is a ground potential pin for the A/D converter. This pin must be held at the same potential as

the VSS0 pin, even while the A/D converter is not being used.

(9) AVDD pin

The AVDD pin is an analog power supply pin for the A/D converter. This pin must be held at the same

potential as the VDD0 pin, even while the A/D converter is not being used.

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11.3 Registers Controlling 10-Bit A/D Converter

The following two registers are used to control the 10-bit A/D converter.

• A/D converter mode register 0 (ADM0)

• A/D input selection register 0 (ADS0)

(1) A/D converter mode register 0 (ADM0)

ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion.

ADM0 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets ADM0 to 00H.

Figure 11-2. Format of A/D Converter Mode Register 0

A/D conversion control

ADCS0

0 FR02 FR01 FR00 0 0 0ADM0

Symbol Address After reset R/W

FF80H 00H R/W

<7>6543210

ADCS0

A/D conversion time selection

Note 1

FR02

144/fx

120/fx

96/fx

72/fx

60/fx

48/fx

FR01

(28.8 s)

(24 s)

(19.2 s)

(14.4 s)

(Setting prohibited

Note 2

)

(Setting prohibited

Note 2

)

FR00

Other than above

Conversion stopped

Conversion enabled

Setting prohibited

Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least

2. These bit combinations must not be used, as the A/D conversion time will fall below 14

Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined.

2. The result of conversion performed after ADCS0 is cleared may be undefined (see 11.5 (5)

Timing that makes the A/D conversion result undefined for details).

Remarks 1. f

X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz.

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(2) A/D input selection register 0 (ADS0)

ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal.

ADS0 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets ADS0 to 00H.

Figure 11-3. Format of A/D Input Selection Register 0

00000

ADS02 ADS01 ADS00

ADS0

Symbol Address After reset R/W

FF84H 00H R/W

76543210

Analog input channel specification

ADS02

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

Setting prohibited

ADS01

ADS00

Caution Bits 3 to 7 must be fixed to 0.

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11.4 Operation of 10-Bit A/D Converter

11.4.1 Basic operation of 10-bit A/D converter

<1> Select a channel for A/D conversion, using A/D input selection register 0 (ADS0).

<2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit.

<3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input

analog voltage until A/D conversion is completed.

<4> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap at the tap

selector is set to half of AVREF.

<5> The series resistor string tap voltage is compared with the analog input voltage using the voltage comparator.

If the analog input voltage is higher than half of AVREF, the MSB of the SAR remains set. If it is lower than

half of AVREF, the MSB is reset.

<6> Bit 8 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the

series resistor string is selected according to bit 9, which reflects the previous comparison result, as follows:

• Bit 9 = 1: Three quarters of AVREF

• Bit 9 = 0: One quarter of AVREF

The tap voltage is compared with the analog input voltage. Bit 8 is set or reset according to the result of

comparison.

• Analog input voltage ≥ tap voltage: Bit 8 = 1

• Analog input voltage < tap voltage: Bit 8 = 0

<7> Comparison is repeated until bit 0 of the SAR is reached.

<8> When comparison is completed for all of the 10 bits, a significant digital result is left in the SAR. This value is

sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate

an A/D conversion end interrupt request (INTAD0).

Cautions 1. The first A/D conversion value immediately following the start of A/D conversion may be

undefined.

2. When the A/D converter enters the standby mode, it stops operating.

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Figure 11-4. Basic Operation of 10-Bit A/D Converter

Conversion

time

Sampling

time

Sampling A/D conversion

Undefined Conversion

result

Conversion

result

A/D converter

operation

SAR

ADCR0

INTAD0

80H C0H

or 40H

A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software.

If an attempt is made to write to ADM0 or A/D input selection register 0 (ADS0) during A/D conversion, the current

A/D conversion is canceled. In this case, A/D conversion is restarted from the beginning, if the ADCS0 bit is set (1).

RESET makes A/D conversion result register 0 (ADCR0) undefined.

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11.4.2 Input voltage and conversion result

The relationship between the analog input voltage at the analog input pins (ANI0 to ANI6) and the A/D conversion

result (A/D conversion result register 0 (ADCR0)) is represented by:

ADCR0 = INT ( × 1024 + 0.5)

(ADCR0 – 0.5) × ≤ VIN < (ADCR0 + 0.5) ×

INT( ): Function that returns the integer part of a parenthesized value

VIN: Analog input voltage

AVREF: AVREF pin voltage

ADCR0: Value in A/D conversion result register 0 (ADCR0)

Figure 11-5 shows the relationship between the analog input voltage and the A/D conversion result.

Figure 11-5. Relationship Between Analog Input Voltage and A/D Conversion Result

1023

1022

1021

A/D conversion

result (ADCR0)

2048

1024

2048

1024

2048

1024

2043

2048

1022

1024

2045

2048

1023

1024

2047

2048

Input voltage/AV

REF

VIN

AVREF

1024

AVREF

1024

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11.4.3 Operation mode of 10-bit A/D converter

The 10-bit A/D converter is initially in the select mode. In this mode, A/D input selection register 0 (ADS0) is used