IS61SF12832 - 128K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns, and 11ns Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data inputs and control signals Pentium or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address pipelining Common data inputs and data outputs JEDEC 100-Pin TQFP and 119-pin PBGA package Single +3.3V +10%, 5% power supply Power-down snooze mode ADVANCE INFORMATION JUNE 1998 DESCRIPTION The JSS7 1S61SF12832 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium, 680X0, and PowerPC microprocessors. It is organized as 131,072 words by 32 bits, fabricated with JSSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into asingle monolithic circuit. Allsynchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses canbe generated internally by the |S61SF12832 and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol Parameter 7.5 8 8.5 10 11 Units tka Clock Access Time 7.5 8 8.5 10 11 ns tke Cycle Time 8.5 10 11 15 20 ns Frenquency 117 100 90 66 50 MHz This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 1998, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR046-0A 06/05/98IS61SF12832 BLOCK DIAGRAM ii A16-A0 17 > CLK BINARY COUNTER CE a1 oS a CLR Al D Q 15 17 ig qo = m Og z ADDRESS REGISTER Loy CE > CLK > pad 2 BYTE WRITE REGISTERS > CLK D Dac 2 BYTE WRITE REGISTERS > CLK > pap BYTE WRITE REGISTERS > CLK D Daa @ BYTE WRITE REGISTERS > CLK D Q 128K x 32 MEMORY ARRAY 32 INPUT ENABLE REGISTER Loa CE > CLK ENABLE DELAY REGISTER > CLK L D Q | REGISTERS > CLK I 32 32 / B DAQ/31:0] Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR046-0A 06/05/98IS61SF12832 PIN CONFIGURATION 119-pin PBGA (Top View) and 100-Pin TQFP KO jo 1 2 3 4 5 6 7 SEER EDS 2s E EEE y \ 22BSEEBERS 5 SBEBERE 22 A oO oO oO oO oO Oo oO OOO if COO vCcQ AG A4 ADSP AS A16 vCcQ 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 8 84 83 82 81 B oO Oo oO oO Oo oO NCT11@ 80 [7 NC NC CE2 A3 ADSC AQ CE NC DQct [J 2 79 [1 DQb8 c oO Oo oO oO DQc2 ] 3 78 [1 DQb7 NC A7 A2 vcc Al2 A15 NC veca CF] 4 7717] VCCQ D Oo Oo oO oO oO oO GND C] 5 76 | GND DQc1 NC GND NC GND NG DQb8 DQc3 [-] 6 75 [] DQb6 E O O O Oo Oo O O DQo4 7 74 DaQbs DQc2 DQc3 GND CE GND DQb6 DQb7 DQc5 [-] 8 73 [7 DQb4 F oO Oo oO QO Oo O oO DQc6 [| 9 72 [1 DQb3 vccq DQc4 GND OE GND DQb5 vccQ GND [-] 10 71 (7-7 GND G O O oO Oo O O Oo vec@ C] 11 70 [1 veca DQc5S DQc6 BW3 ADV BWw2 DQb4 DQb3 DQc7 L] 12 69 [1 DQb2 H O O O OQ. Oo O O DQc8 | 13 68 [4 DaQbt DQc7 DQc8 GND GW GND DQb2 DQb1 GNDQ CJ 14 67 [_] GND J O Oo O O Oo O O vec 15 66 | NC vecQ VCC NC vcc NC vcc VCCQ NC C1 16 65 (1 vcc . a noe Qo ox Qo oor a exp od ae a a DQd1 [J 18 63 [1 DQa8 L O Oo oO Oo oO Oo Oo DQd2 [-] 19 62 [1 DQa7 DQd4-DQds.-BW4- NCO BWT)= DQaS_s:(Qab voco EJ] 20 61 4 veca M Oo OO 9O oO GND C] 21 60 | GND vecQ. DQd5 GND BWE GND DQa4 vCCQ pads CJ 22 50 Fo Daas N 0X6 Sir Qo 2 No DQ Ddae Dada (| 2 58 | Daas DQd5 [_] 24 57 1] DQa4 P O O O O O Dade | 25 56 [1 DQa3 DQd8 NC GND AO GND NC DQa1 GND [-] 26 55 [|] GND R O O O O O O vecQ [] 27 54{ vec NC AS MODE vcc GNDQ A13 NC DQd7 [-] 28 53 [1 DQa2 tT] O O O O O O o Daas (| 29 52 [J Daat NC NC A10 Al Al4 NC ZZ O oO oO O oO oO O Nc LJ} 30 51 [1 NC U 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 @ rae er ore DOUUUUUOUUUUUUUUUooo B2zZ@eVgeogegeeseses = PIN DESCRIPTIONS AO, Al Synchronous Address Inputs. These G Synchronous Global Write Enable pins must tied to the two LSBs of the CE, CE2, CE2 Synchronous Chip Enable address bus. ____ OE Output Enable A2-A16 Synchronous Address Inputs P DQa-DQd Synchronous Data Input/Output CLK Synchronous Clock y P P MODE Burst Sequence Mode Selection ADSP Synchronous Processor Address q Status Vcc +3.3V Power Supply ADSC Synchronous Controller Address GND Ground Status Vcca Isolated Output Buffer Supply: DV Synchronous Burst Address Advance +3.3V BW1-BW4 Synchronous Byte Write Enable ZZ Snooze Enable BWE Synchronous Byte Write Enable GNDa Isolated Output Buffer Ground Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR046-0A 06/05/98IS61SF12832 TRUTH TABLE Address __ eee Operation Used CE cCE2 CE2 ADSP ADSC ADV WRITE OE DQ Deselected, Power-down None H Xx Xx Xx L X X X High-2 Deselected, Power-down None L Xx H L Xx X X X High-2 Deselected, Power-down None L L Xx L Xx X X X High-2 Deselected, Power-down None Xx Xx H H L X X X High-2 Deselected, Power-down None Xx 0 Xx H L X X X High-2 Read Cycle, Begin Burst External L H L L x x x X High-Z Read Cycle, Begin Burst External L H L H 0 x Read X High-Z Write Cycle, Begin Burst External L H L H L x Write X High-Z Read Cycle, Continue Burst Next Xx Xx Xx H H L Read L Q Read Cycle, Continue Burst Next x x x H H L Read H High-Z Read Cycle, Continue Burst Next H Xx Xx Xx H L Read L Q Read Cycle, Continue Burst Next H x x x H L Read H High-Z Write Cycle, Continue Burst Next x x x H H L Write X High-Z Write Cycle, Continue Burst Next H x x x H L Write X High-Z Read Cycle, Suspend Burst Current x x x H H H Read L Q Read Cycle, Suspend Burst Current x x x H H H Read H High-Z Read Cycle, Suspend Burst Current H x x x H H Read L Q Read Cycle, Suspend Burst Current H x x x H H Read H High-Z Write Cycle, Suspend Burst Current x x x H H H Write X High-Z Write Cycle, Suspend Burst Current H x x x H H Write X High-Z PARTIAL TRUTH TABLE Function GW BWE BWi BW2 BWs BW4 Read H H X X X X Read H L H H H H Write Byte 1 H L L H H H Write All Bytes H L L L L L Write All Bytes L x x x xX xX 4 Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR046-0A 06/05/98ia INTERLEAVED BURST ADDRESS TABLE (MODE = Vcca or No Connect) External Address 1st Burst Address 2nd Burst Address 3rd Burst Address IS61SF12832 A1 AO A1 AO A1 AO A1 AO 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = GNDa) o At', AO = 1,1 S LU ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit TBIAS Temperature Under Bias 40 to +85 C TsTG Storage Temperature 55 to +150 C Pb Power Dissipation 1.6 Ww lout Output Current (per I/O) 100 mA Vin, Vout Voltage Relative to GND for I/O Pins 0.5to Vcca+03 V VIN Voltage Relative to GND for 0.5 to Vcc + 0.5 Vv for Address and Control Inputs Vcc Voltage on Vcc Supply Relatiive to GND 0.5 to 4.6 Vv Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. Integrated Silicon Solution, Inc. 5 ADVANCE INFORMATION SR046-0A 06/05/98IS61SF12832 OPERATING RANGE Range Ambient Temperature Vcc Commercial 0C to +70C 3.3V +10%, -5% Industrial 40C to +85C 3.3V +10%, -5% DC ELECTRICAL CHARACTERISTICS" (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VoH Output HIGH Voltage loH = 4.0 mA 2.4 _ Vv VoL Output LOW Voltage loL=8.0 mA _ 0.4 Vv VIH Input HIGH Voltage 2.0 Vceca+0.3 Vv ViL Input LOW Voltage 0.3 0.8 Vv Iu Input Leakage Current GND < Vin < Veca) Com. -2 2 uA Ind. -5 5 ILo Output Leakage Current GND < Vout < Veca, OE = Vin Com. 2 2 LA Ind. -5 5 POWER SUPPLY CHARACTERISTICS (Over Operating Range) 75 8 8.5 10 11 Symbol _ Parameter Test Conditions Max. Max. Max. Max. Max. Unit lec AC Operating Device Selected, Com. 350 325 300 275 250 mA Supply Current All Inputs = Vit or Vin Ind. _ 345 320 295 270 OE = Vin, Voc = Max. Cycle Time > tke min. Isp Standby Current Device Deselected, Com. 95 95 95 95 95 mA Vcc = Max., Ind. _ 105 105 105 105 All Inputs = Vin or Vi CLK Cycle Time 2 tke min. Iz Power-cown ZZ = Veca Com. 5 5 5 5 5 mA Mode Current Clock Running Ind. _ 15 15 15 15 All Inputs < GND +0.2V or 2 Vec-0.2V Note: 1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to Vcca. 2. The MODE pin should be tied to Vec or GND. It exhibits +10 pA maximum leakage current when tied to < GND + 0.2V or > Vee - 0.2V. Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR046-0A 06/05/98IS61SF12832 CAPACITANCE) Symbol Parameter Conditions Max. Unit CIN Input Capacitance Vin = OV 5 pF Court Input/Output Capacitance Vout = OV 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25C, f = 1 MHz, Vec = 3.3V. AC TEST CONDITIONS Parameter Unit Input Pulse Level OV to 3.0V Input Rise and Fall Times 1.5 ns Input and Output Timing 1.5V and Reference Level Output Load See Figures 1 and 2 AC TEST LOADS Zo = 500 Output 30 pF Buffer P 50 Figure 1 3179 3.3V OUTPUT 5 pF Including jig and scope = = 351 Figure 2 Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR046-0A 06/05/98IS61SF12832 ii READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) 7.5 8 8.5 10 11 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit fMAX Clock Frequency 117 100 90 6 50 MHz tke Cycle Time 85 100 Woo 15 20 ns tKH Clock High Time 30 4 45 45 45 ns tKL Clock Low Time 30 4 45 45 45 ns tka Clock Access Time 75 8 85 10 11 ns tkax'? ~~ Clock High to Output Invalid 2 - 2 - 2 - 2 - 2 0 - ns tkaiz") Clock High to Output Low-Z oO oo. oO oO 0 _ ns tkaHz") Clock High to Output High-Z 2 3.5 2 35 2 3.5 2 35 2 35 ns toEa Output Enable to Output Valid 35 35 35 35 35 ns toe." ~ Qutput Enable to Output Low-Z oO oo. oO oO 0 ns toeHz"? Qutput Disable to Output High-Z 3.5 35 35 35 35 ns tas Address Setup Time 20- 2 _ 20- 20 0- 2 _ ns tss Address Status Setup Time 20- 2 _ 20- 20- 2 _ ns tws Write Setup Time 20- 2 _ 20- 20 0- 2 _ ns tces Chip Enable Setup Time 20- 2 _ 20- 20 0- 2 _ ns tavs Address Advance Setup Time 20- 2 _ 20- 20 0- 2 _ ns TAH Address Hold Time 0.5 05 05 05 05 ns tsH Address Status Hold Time 0.5 05 05 05 05 ns {WH Write Hold Time 0.5 05 05 05 05 ns tceH Chip Enable Hold Time 0.5 05 05 05 05 ns tAVH Address Advance Hold Time 0.5 05 05 05 05 ns Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR046-0A 06/05/98IS61SF12832 READ/WRITE CYCLE TIMING ox\ | I | | | | | | tKH ra | }o | | | | | tss LtsH | | | | | ADSP is blocked by CE inactive | | | ADGP | at AT AYN : : : : ALS | | | | | | | _ tss4 | | | | | | | | | \ | I | I T T f T STE ee i TX TST OLA LA! Ez | | | | | | | | | | ts | | | | | | | | | | A15-A0 RD1 Xwrt X X RO2X X RD3X | | | |! | |! |! | | | | tws-leabeot tit | | | | | | | | | i L_ ts feof tin | | | | | | | | | BWE SH} ifs PAY AY AY . | | | | | | | | | | | | | l |! a ! | ices leo cet | | | | | | CE Masks ADSP |! | | | i CE : Ld . LL : VL | A | | | | | | | | | | {ces le->y<-oL {CEH | | CE2 and CE2 only sampled with AD SP or ADSC | | | | 7 \ | | eH | Mf | AS | | A | toes ~e-preat ce | | | | | | | | Unselected with CE2 CE2 Uf LI / Vif / | \ ! | | | | | | | | | | | | <> tOEHZ | | | | | | | | OE 7\ fT T | l p44 ! ! ! ! ! " | | | | tOEOX | | | | | | pe tkax | DATAOUT } High-Z (+_X 2a x 2b x 2c xX 2 | kau | | | | | | | woke | | ka . | | | | | | | | | tkonz' | | | | | | | | DATAN High-Z iz) ! , l I I I I I | | tDs {DH | | | | | Single Read Single Write >|___ Burst Read -->- Uns elected Flow-through Integrated Silicon Solution, Inc. 9 ADVANCE INFORMATION SR046-0A 06/05/98ii WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) IS61SF12832 7.5 8 8.5 10 11 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tke Cycle Time 85 100 Woo 15 20 ns tKH Clock High Time 30 4 45 45 45 ns tKL Clock Low Time 30 4 45 45 45 ns tas Address Setup Time 20- 2 _ 20- 20 0- 2 _ ns tss Address Status Setup Time 20- 2 _ 20- 20- 2 _ ns tws Write Setup Time 20- 2 _ 20- 20 0- 2 _ ns tos Data In Setup Time 20- 2 _ 20- 20 0- 2 _ ns tces Chip Enable Setup Time 20- 2 _ 20- 20 0- 2 _ ns tavs Address Advance Setup Time 20- 2 _ 20- 20 0- 2 _ ns TAH Address Hold Time 0.5 05 05 05 05 ns tsH Address Status Hold Time 0.5 05 05 05 05 ns tOH Data In Hold Time 05 05 05 05 05 ns {WH Write Hold Time 0.5 05 05 05 05 ns tceH Chip Enable Hold Time 0.5 05 05 05 05 ns tAVH Address Advance Hold Time 0.5 05 05 05 05 ns 10 Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR046-0A 06/05/98IS61SF12832 WRITE CYCLE TIMING Le CE2 and CE2 only sampled with ADSP or ADSC | DATAOUT High-Z | | DATAIN High-Z BW4-BW1 only are applied to first oycle of WR2 | 22 XX_% XX_20 XX_20_ XX | | | | | | | | 32 l | | | | | | | | | | | (< Single Write 1-___ Burst Write >- Write Unselected. > Integrated Silicon Solution, Inc. 11 ADVANCE INFORMATION SR046-0A 06/05/98IS61SF12832 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) ii 7.5 8 8.5 10 11 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tke Cycle Time 85 100 Woo 15 20 ns tKH Clock High Time 30 4 45 45 45 ns tKL Clock Low Time 30 4 45 45 45 ns tka Clock Access Time 75 8 85 10 11 ns tkax'? ~~ Clock High to Output Invalid 2 - 2 - 2 - 2 - 2 0 - ns tkaiz") Clock High to Output Low-Z oO oo. oO oO 0 _ ns tkaHz") Clock High to Output High-Z 2 3.5 2 35 2 3.5 2 35 2 35 ns toEa Output Enable to Output Valid 35 35 35 35 35 ns toe." ~ Qutput Enable to Output Low-Z oO oo. oO oO 0 ns toeHz"? Qutput Disable to Output High-Z 3.5 35 35 35 35 ns tas Address Setup Time 20- 2 _ 20- 20 0- 2 _ ns tss Address Status Setup Time 20- 2 _ 20- 20- 2 _ ns tces Chip Enable Setup Time 20- 2 _ 20- 20 0- 2 _ ns TAH Address Hold Time 0.5 05 05 05 05 ns tsH Address Status Hold Time 0.5 05 05 05 05 ns tceH Chip Enable Hold Time 0.5 05 05 05 05 ns tzzs ZZ Standby 20 20- 20 20 2 cyc tzzrec - ZZ Recovery 20 20- 20 2 0- 2 cyc Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 12 Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR046-0A 06/05/98N ap) N - LL. w = 2 SNOOZE AND RECOVERY CYCLE TIMING i L pa aaet nT] le tk > / xa 3s x LZ wn 2 <= |O 8319 a [8 |Z c= lc ADV RD1 A15-A0 Ss |g \\ \\ \ ion nd be LI cl aa] aa a] ne] | = a 2 o Do FJ ___ _-_ _ FJ TT FT TTT N cc sg oO a = = = EE i _ _ pd wo NI So So wa r [ = LC + + 4 =e =r 7 wn N Q xc a _54__ | __ rsE Oo 2 | NI \ | {CEH | | <->} tCEH | | {CEH | | \ tOEQ+<> | Ld tOELZ->| | __o tKo.zfe feo | | | | | | I _ >] <p> vis CE2 ZZ | | tces-+e I | teste CE2 7 | | {CES 7 | | | DATAOUT High-Z | | | DATAN} HighZ | | | | | | kk Single Read l 13 Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR046-0A 06/05/98IS61SF12832 ORDERING INFORMATION Commercial Range: 0C to +70C Frequency Order Part Number Package 7.5 1S61SF12832-7.5TQ TQFP IS61SF12832-7.5B PBGA 8 IS61SF12832-8TQ TQFP IS61SF12832-8B PBGA 8.5 IS61SF12832-8.5TQ TQFP IS61SF12832-8.5B PBGA 10 IS61SF12832-10TQ TQFP IS61SF12832-10B PBGA 11 IS61SF12832-11TQ TQFP IS61SF12832-11B PBGA Industrial Range: 40C to +85C Frequency Order Part Number Package 8 IS61SF12832-8TQI TQFP 8.5 1S61SF12832-8.5TQI TQFP 10 IS61SF12832-10TQI TQFP 11 IS61SF12832-11TQI TQFP _ Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 e-mail: sales@issiusa.com http://www.issiusa.com 14 Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR046-0A 06/05/98