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X9523
Laser Diode Control for Fiber Optic Modules
DESCRIPTION
The X9523 combines two Digitally Controlled Potentiome-
ters (DCPs), V1 / Vcc Power On Reset (POR) circuitry, qnd
two programmable voltage monitor inputs with software and
hardware indicators. All functions of the X9523 are
accessed by an industry standard 2-Wire serial interface.
The DCPs of the X9523 may be utilized to control the bias
and modulation currents of the laser diode in a Fiber Optic
module. The programmable POR circuit may be used to
ensure that V1 / Vcc is stable before power is applied to the
laser diode / module. The programmable voltage monitors
may be used for monitoring various module alarm levels.
The features of the X9523 are ideally suited to simplifying
the design of fiber optic modules . The integration of these
functions into one package significantly reduces board
area, cost and increases reliability of laser diode modules.
BLOCK DIAGRAM
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
SDA
SCL
POWER ON /
LOW VOLTAGE
CONSTAT
REGISTER
PROTECT LOGIC
THRESHOLD
RESET LOGIC
GENERATION
RESET
V2
VTRIP
V1 / Vcc
VTRIP
V3
+
-
2
3
1
V1RO
RH2
RW2
RL2
MR
8
WIPER
REGISTER
RH1
RW1
RL1
COUNTER
V2RO
WP
V3RO
7 - BIT
NONVOLATILE
MEMORY
NONVOLATILE
MEMORY
WIPER
REGISTER
COUNTER
8 - BIT
2
VTRIP
+
-
+
-
Hot Pluggable
Dual DCP, POR, Dual Voltage Monitors
FEATURES
• Two Digitally Controlled Potentiometers (DCPs)
—100 Tap - 10 k
Ω
—256 Tap - 100 k
Ω
—Nonvolatile
—Write Protect Function
• 2-Wire industry standard Serial Interface
• Power On Reset (POR) Circuitry
—Programmable Threshold Voltage
—Software Selectable reset timeout
—Manual Reset
• Two Supplementary Voltage Monitors
—Programmable Threshold Voltages
• Single Supply Operation
—2.7 V to 5.5 V
• Hot Pluggable
• 20 Pin packages
—XBGA
TM
—TSSOP
Preliminary Information
©2000 Xicor Inc., Patents Pending
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X9523
– Preliminary Information
DETAILED DEVICE DESCRIPTION
The X9523 combines two Xicor Digitally Controlled
Potentiometer (DCP) devices, V1 / Vcc power on reset
control, V1 / Vcc low voltage reset control, and two sup-
plementary voltage monitors in one package. These func-
tions are suited to the control, support, and monitoring of
various system parameters in fiber optic modules. The
combination of the X9523 fucntionality lowers system
cost, increases reliability, and reduces board space
requirements using Xicor’s unique XBGA™ packaging.
Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents.
Applying voltage to V
CC
activates the Power On Reset cir-
cuit which allows the V1RO output to go HIGH, until the
supply the supply voltage stabilizes for a period of time
(selectable via software). The V1RO output then goes
LOW. The Low Voltage Reset circuitry allows the V1RO
output to go HIGH when V
CC
falls below the minimum
V
CC
trip point. V1RO remains HIGH until V
CC
returns to
proper operating level. A Manual Reset (MR) input allows
the user to externally trigger the V1RO output (HIGH).
Two supplementary Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If an input
voltage exceeds it’s associated trip level, a hardware out-
put (V3RO, V2RO) are allowed to go HIGH. If the input
voltage becomes lower than it’s associated trip level, the
corresponding output is driven LOW. A corresponding
binary representation of the two monitor circuit outputs
(V2RO and V3RO) are also stored in latched, volatile
(CONSTAT) register bits. The status of these two monitor
outputs can be read out via the 2-wire serial port.
Xicor’s unique circuits allow for all internal trip voltages to
be individually programmed with high accuracy. This gives
the designer great flexibility in changing system parame-
ters, either at the time of manufacture, or in the field.
The device features a 2-Wire interface and software pro-
tocol allowing operation on an I
2
C™ compatible serial
bus.
PIN CONFIGURATION
V2
RL2
NC
3
4
V1 / Vcc
SCL
NC
NC
RW1
RH1
7
8
V3
VSS 10 RL1
RH2 1
18
19
17
20
14
15
13
16
12
11
MR 6
RW2 2
SDA 9
V3RO 5
WP
V1RO
V2RO
NOT TO SCALE
XBGA
20 Pin TSSOP
2 3
4
A
B
C
D
E
Top View – Bumps Down
1
RL2
RW2
RH2
V2
WPV3RO
SCL
NC
SDA
RL1
V2RO V1 / Vcc
V3
V1RO
NC NC
RH1 MR
VSS RW1
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X9523
– Preliminary Information
PIN ASSIGNMENT
Pin XBGA Name Function
1B3
R
H2
Connection to end of resistor array for (the 256 Tap) DCP 2.
2A3
R
w2
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
3A4
R
L2
Connection to other end of resistor array for (the 256 Tap) DCP2.
4B4V3
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit.
When the V3 input is higher than the
V
TRIP3
threshold voltage, V3RO makes a transition
to a HIGH level. Connect V3 to V
SS
when not used.
5 C3 V3RO
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is
greater than
V
TRIP3 and goes LOW when V3 is less than VTRIP3. There is no delay cir-
cuitry on this pin. The V3RO pin requires the use of an external “pull-up” resistor.
6D3MR
Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) ini-
tiates a reset cycle to the V1RO pin (V1 / Vcc RESET Output pin). V1RO will remain HIGH
for time t
purst
after MR has returned to it’s normally LOW state. The reset time can be se-
lected using bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use
of an external “pull-down” resistor.
7C4WP
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write
Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” opera-
tions. Also, when the Write Protection is enabled, and the device DCP Write Lock feature is
active (i.e. the DCP Write Lock bit is “1”), then no “write” (volatile or nonvolatile) operations
can be performedon the wiper position of any of the integrated Digitally Controlled Potenti-
ometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the
write protection feature is disabled.
8 D4 SCL Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing
for data input and output.
9E4SDA
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and
out of the device. The SDA pin input buffer is always active (not gated). This pin requires
an external pull up resistor.
10 E1 Vss Ground.
11 E3 R
L1
Connection to other end of resistor for (the 100 Tap) DCP 1.
12 E2 R
w1
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1
13 D1 R
H1
Connection to end of resistor array for (the 100 Tap) DCP 1.
17 B1 V2
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit.
When the V2 input is greater than the
V
TRIP2 threshold voltage, V2RO makes a transition
to a HIGH level. Connect V2 to V
SS
when not used.
18 A1 V2RO
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is
greater than
V
TRIP2, and goes LOW when V2 is less than
V
TRIP2. There is no power up
reset delay circuitry on this pin. The V2RO pin requires the use of an external “pull-up” re-
sistor.
19 B2 V1RO
V1 / Vcc RESET Output. This is an active HIGH, open drain output which becomes active
whenever V1 / Vcc falls below
V
TRIP1. V1RO becomes active on power up and remains
active for a time t
purst
after the power supply stabilizes (t
purst
can be changed by varying
the POR0 and POR1 bits of the internal control register). The V1RO pin requires the use
of an external “pull-up” resistor. The V1RO pin can be forced active (HIGH) using the man-
ual reset (MR) input pin.
20 A2 V1 / Vcc Supply Voltage.
14, 15,
16,
C1, C2,
D2 NC No Connect
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X9523
– Preliminary Information
PRINCIPLES OF OPERATION
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides
the clock for both transmit and receive operations. There-
fore, the X9523 operates as a slave in all applications.
Serial Clock and Data
Data states on the SDA line can change only while SCL is
LOW. SDA state changes while SCL is HIGH are
reserved for indicating START and STOP conditions. See
Figure 1.On power up of the X9523, the SDA pin is in the
input mode.
Serial Start Condition
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not respond
to any command until this condition has been met. See
Figure 2.
Serial Stop Condition
All communications must be terminated by a STOP condi-
tion, which is a LOW to HIGH transition of SDA while SCL
is HIGH. The STOP condition is also used to place the
device into the Standby power mode after a read
sequence. A STOP condition can only be issued after the
transmitting device has released the bus. See Figure 2.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention
used to indicate a successful data transfer. The transmit-
ting device, either master or slave, will release the bus
after transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to ACKNOWL-
EDGE that it received the eight bits of data. Refer to Fig-
ure 3.
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If a
write operation is selected, the device will respond with an
ACKNOWLEDGE after the receipt of each subsequent
eight bit word.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master, the
device will continue to transmit data. The device will termi-
SCL
SDA
Data Stable Data Change Data Stable
Figure 1. Valid Data Changes on the SDA Bus
SCL
SDA
Start Stop
Figure 2. Valid Start and Stop Conditions
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X9523
– Preliminary Information
nate further data transmissions if an ACKNOWLEDGE is
not detected. The master must then issue a STOP condi-
tion to place the device into a known state.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9523
can be split up into two main parts:
—Two Digitally Controlled Potentiometers (DCPs)
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on each
of these individual parts, a 1, 2 or 3 Byte protocol is used.
All operations however must begin with the Slave Address
Byte being issued on the SDA pin. The Slave address
selects the part of the X9523 to be addressed, and speci-
fies if a Read or Write operation is to be performed.
It should be noted that in order to perform a write opera-
tion to a DCP, the Write Enable Latch (WEL) bit must first
be set (See “WEL: Write Enable Latch (Volatile)” on
page 10.).
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of three parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9523.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 111 internally selects
the DCP structures in the X9523. The CONSTAT Regis-
ter may be selected using the Internal Device Address
010.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
SCL
from
Master
Data Output
from
Transmitter
Data Output
from
Receiver
81 9
Start Acknowledge
Figure 3. Acknowledge Response From Receiver
SCL
from
Master
SA6SA7 SA5 SA3 SA2 SA1 SA0
DEVICE TYPE
IDENTIFIER
READ /
SA4
Internal Address
(SA3 - SA1)
Internally Addressed
Device
010 CONSTAT Register
111 DCP
All Others RESERVED
Bit SA0 Operation
0 WRITE
1 READ
R/W
Figure 4. Slave Address Format
1010
WRITE
ADDRESS
INTERNAL
DEVICE
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X9523
– Preliminary Information
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the Non Volatile Memory of a DCP (NVM), or the CON-
STAT Register) has been correctly issued (including the
final STOP condition), the X9523 initiates an internal high
voltage write cycle. This cycle typically requires 5 ms. Dur-
ing this time, no further Read or Write commands can be
issued to the device. Write Acknowledge Polling is used to
determine when this high voltage write cycle has been
completed.
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal Device
Address. The LSB of the Slave Address (R/W) can be set
to either 1 or 0 in this case. If the device is still busy with
the high voltage cycle then no ACKNOWLEDGE will be
returned. If the device has completed the write operation,
an ACKNOWLEDGE will be returned and the host can
then proceed with a read or write operation. (Refer to
Figure 5.).
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
The X9523 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
Hx
and R
Lx
inputs - where x = 1,2).
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
(R
w
x
) output. Within each individual array, only one switch
may be turned on at any one time. These switches are
controlled by the Wiper Counter Register (WCR) (See
Figure 6). The WCR is a volatile register.
On power up of the X9523, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below shows
the Initial Values of the DCP WCR’s before the contents of
the NVM is loaded into the WCR.
The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
before break” sequence is used internally for the FET
ACK
returned?
Issue Slave Address
Byte (Read or Write)
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
High Voltage Cycle
complete. Continue
command sequence?
Issue STOP
NO
Continue normal
Read or Write
command sequence
PROCEED
YES
Figure 5. Acknowledge Polling Sequence
DECODER RESISTOR
ARRAY
RHx
FET
SWITCHES
RLx
RWx
0
1
2
N
WIPER
REGISTER
COUNTER
NON
MEMORY
VOLATILE
(WCR)
(NVM)
“WIPER”
Figure 6. DCP Internal Structure
DCP Initial Values Before Recall
R1 / 100 TAP VL / TAP = 0
R2 / 256 TAP VH / TAP = 255
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X9523 – Preliminary Information
switches when the wiper is moved from one tap position
to another.
Hot Pluggability
Figure 7 shows a typical waveform that the X9523 might
experience in a Hot Pluggable situation. On power up, V1
/ Vcc applied to the X9523 may exhibit some amount of
ringing, before it settles to the required value.
The device is designed such that the wiper terminal (RWx)
is recalled to the correct position (as per the last stored in
the DCP NVM), when the voltage applied to V1 / Vcc
exceeds VTRIP1 for a time exceeding tpurst (the Power On
Reset time, set in the CONSTAT Register - See “CON-
TROL AND STATUS REGISTER” on page 10.).
Therefore, if ttrans is defined as the time taken for V1 / Vcc
to settle above VTRIP1 (Figure 7): then the desired wiper
terminal position is recalled by (a maximum) time: ttrans +
tpurst. It should be noted that ttrans is determined by sys-
tem hot plug conditions.
DCP Operations
In total there are three operations that can be performed
on any internal DCP structure:
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new “wiper
position” setting is recalled into the WCR after V1 / Vcc of
the X9523 is powered down and then powered back up.
A volatile write operation to a DCP however, changes the
“wiper position” by writing new data to the associated
WCR only. The contents of the associated NVM register
remains unchanged. Therefore, when V1 / Vcc to the
device is powered down then back up, the “wiper position”
reverts to that last position written to the DCP using a
nonvolatile write operation.
Both volatile and nonvolatile write operations are
executed using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a Data
Byte (See Figure 9)
A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting
of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again (Refer
to Figure 10.).
Instruction Byte
While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which
DCP is being addressed.
The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device Address
bits of the Slave Address are set to 1010111. In this
case, the two Least Significant Bit’s (I1 - I0) of the
Instruction Byte are used to select the particular DCP (0
- 2). In the case of a Write to any of the DCPs (i.e. the LSB
of the Slave Address is 0), the Most Significant Bit of the
Instruction Byte (I7), determines the Write Type (WT) per-
formed.
If WT is “1”, then a Nonvolatile Write to the DCP occurs. In
this case, the “wiper position” of the DCP is changed by
simultaneously writing new data to the associated WCR
and NVM. Therefore, the new “wiper position” setting is
Figure 7. DCP Power up
t
V1 / Vcc
VTRIP1
V1 / Vcc (Max.)
tpurst
Maximum Wiper Recall time
0
ttrans
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X9523 – Preliminary Information
recalled into the WCR after V1 / Vcc of the X9523 has
been powered down then powered back up.
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of the
associated NVM register remains unchanged. Therefore,
when V1 / Vcc to the device is powered down then back
up, the “wiper position” reverts to that last written to the
DCP using a nonvolatile write operation.
DCP Write Operation
A write to DCPx (x=1,2) can be performed using the three
byte command sequence shown in Figure 9.
In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Regis-
ter must first be set (See “WEL: Write Enable Latch (Vola-
tile)” on page 10.)
The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9523 after the Slave Address, if it has
been received correctly.
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9523.
Following the Instruction Byte, a Data Byte is issued to the
X9523 over SDA. The Data Byte contents is latched into
the WCR of the DCP on the first rising edge of the clock
signal, after the LSB of the Data Byte (D0) has been
issued on SDA (See Figure 29).
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
For DCP2 (256 Tap), the Data Byte maps one to one to
the “wiper position” of the DCP “wiper terminal”. There-
fore, the Data Byte 00001111 (1510) corresponds to set-
ting the “wiper terminal” to tap position 15. Similarly, the
Data Byte 00011100 (2810) corresponds to setting the
“wiper terminal” to tap position 28. The mapping of the
Data Byte to “wiper position” data for DCP1 (100 Tap), is
shown in “APPENDIX 1”. An example of a simple C lan-
WT†Description
0Select a Volatile Write operation to be performed
on the DCP pointed to by bits P1 and P0
1Select a Nonvolatile Write operation to be per-
formed on the DCP pointed to by bits P1 and P0
00WT 0 0 0 P1 P0
WRITE TYPE DCP SELECT
†This bit has no effect when a Read operation is being performed.
I5I6I7 I4 I3 I2 I1 I0
Figure 8. Instruction Byte Format
S
T
A
R
T
10101110A
C
K
WT 0 0 0 0 0 P1 P0 A
C
K
S
T
O
P
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
SLAVE ADDRESS BYTE INSTRUCTION BYTE DATA BYTE
Figure 9. DCP Write Command Sequence
P1- P0 DCPx # Taps Max. Data Byte
0 0 RESERVED
0 1 x=1 100 Refer to Appendix 1
1 0 x=2 256 FFh
1 1 RESERVED
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X9523 – Preliminary Information
guage function which “translates” between the tap posi-
tion (decimal) and the Data Byte (binary) for DCP1, is
given in “APPENDIX 2”.
It should be noted that all writes to any DCP of the X9523
are random in nature. Therefore, the Data Byte of consec-
utive write operations to any DCP can differ by an arbi-
trary number of bits. Also, setting the bits P1=1, P0=1 is a
reserved sequence, and will result in no ACKNOWL-
EDGE after sending an Instruction Byte on SDA.
The factory default setting of all “wiper position” settings is
with 00h stored in the NVM of the DCPs. This corre-
sponds to having the “wiper teminal” RWX (x=1,2) at the
“lowest” tap position, Therefore, the resistance between
RWX and RLX is a minimum (essentially only the Wiper
Resistance, RW).
DCP Read Operation
A read of DCPx (x=1,2) can be performed using the three
byte random read command sequence shown in Figure
10.
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9523 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1-P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9523.
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W bit set to 1. Then the X9523
issues an ACKNOWLEDGE followed by Data Byte, and
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by bits
P1 and P0.
Slave
Address
Instruction
Byte
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address Data Byte
A
C
K
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
Figure 10. DCP Read Sequence
“Dummy” write
READ Operation
101 11100
00 000
W
TP
1P
0
101 11110
WRITE Operation
-
MSB LSB
DCPx
x = 1
x = 2
“-” = DON’T CARE
S
t
a
r
t
S
t
o
p
Slave
Address
Address
Byte Data
Byte
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
Figure 11. EEPROM Byte Write Sequence
Internal
Device
Address
101 00000
WRITE Operation
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X9523 – Preliminary Information
It should be noted that when reading out the data byte for
DCP1 (100 Tap), the upper most significant bit is an
“unknown”. For DCP2 (256 Tap) however, all bits of the
data byte are relevant (See Figure 10).
CONTROL AND STATUS REGISTER
The Control and Status (CONSTAT) Register provides the
user with a mechanism for changing and reading the sta-
tus of various parameters of the X9523 (See Figure 12).
The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CONSTAT
register retain their stored values even when V1 / Vcc is
powered down, then powered back up. The volatile bits
however, will always power up to a known logic state “0”
(irrespective of their value at power down).
A detailed description of the function of each of the CON-
STAT register bits follows:
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the entire
X9523 device. This bit must first be enabled before ANY
write operation (to DCPs, or the CONSTAT register). If the
WEL bit is not first enabled, then ANY proceeding (volatile
or nonvolatile) write operation to DCPs or the CONSTAT
register, is aborted and no ACKNOWLEDGE is issued
after a Data Byte.
The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state. The WEL bit is enabled / set by writ-
ing 00000010 to the CONSTAT register. Once enabled,
the WEL bit remains set to “1” until either it is reset to “0”
(by writing 00000000 to the CONSTAT register) or until
the X9523 powers down, and then up again.
Writes to the WEL bit do not cause an internal high volt-
age write cycle. Therefore, the device is ready for another
operation immediately after a STOP condition is executed
in the CONSTAT Write command sequence (See Figure
13).
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9523. Therefore, in order to write to
any of the bits of the CONSTAT Register (except WEL),
the RWEL bit must first be set to “1”. The RWEL bit is a
volatile bit that powers up in the disabled, LOW (“0”) state.
It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT Reg-
ister Write Operation").
The RWEL bit will reset itself to the default “0” state, in
one of two cases:
—After a successful write operation to any bits of the
CONSTAT register has been completed (See Figure
13).
—When the X9523 is powered down.
DWLK: DCP Write Lock bit - (Nonvolatile)
The DCP Write Lock bit (DWLK) is used to inhibit a DCP
write operation (changing the “wiper position”).
When the DCP Write Lock bit of the CONSTAT register is
set to “1”, then the “wiper position” of the DCPs cannot be
changed - i.e. DCP write operations cannot be conducted:
The factory default setting for this bit is DWLK= 0.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9523 is active (HIGH), then nonvolatile write operations
to the DCPs are inhibited, irrespective of the DCP Write
Lock bit setting (See "WP: Write Protection Pin").
Bit(s) Description
POR1 Power On Reset bit
V2OS V2 Output Status flag
V1OS V1 Output Status flag
CS4 Always set to “0” (RESERVED)
DWLK Sets the DCP Write Lock
RWEL Register Write Enable Latch bit
WEL Write Enable Latch bit
POR0 Power On Reset bit
POR1 WEL POR0
CS5
CS6CS7 CS4 CS3 CS2 CS1 CS0
V3OS
V2OS DWLK
0RWEL
Figure 12. CONSTAT Register Format
NV NV
NV
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
DWLK DCP Write Operation Permissible
0 YES (Default)
1NO
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X9523 – Preliminary Information
POR1, POR0: Power On Reset bits - (Nonvolatile)
Applying voltage to VCC activates the Power On Reset cir-
cuit which holds V1RO output HIGH, until the supply volt-
age stabilizes above the VTRIP1 threshold for a period of
time, tPURST (See Figure 25).
The Power On Reset bits, POR1 and POR0 of the CON-
STAT register determine the tPURST delay time of the
Power On Reset circuitry (See "VOLTAGE MONITORING
FUNCTIONS"). These bits of the CONSTAT register are
nonvolatile, and therefore power up to the last written
state.
The nominal Power On Reset delay time can be selected
from the following table, by writing the appropriate bits to
the CONSTAT register:
The default for these bits are POR1 = 0, POR0 = 1.
V2OS, V3OS: Voltage Monitor Status Bits (Volatile)
Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status of the
Voltage Monitor reset output pins V2RO and V3RO.
At power up the VxOS (x=2,3) bits default to the value “0”.
These bits can be set to a “1” by writing the appropriate
value to the CONSTAT register. To provide consistency
between the VxRO and VxOS however, the status of the
VxOS bits can only be set to a “1” when the correspond-
ing VxRO output is HIGH.
Once the VxOS bits have been set to “1”, they will be
reset to “0” if:
—The device is powered down, then back up,
—The corresponding VxRO output becomes LOW.
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following the
Slave Address Byte, access to the CONSTAT register
requires an Address Byte which must be set to FFh. Only
one data byte is allowed to be written for each CONSTAT
register Write operation. The user must issue a STOP,
after sending this byte to the register, to initiate the nonvol-
atile cycle that stores the DWLK, POR1 and POR0 bits.
The X9523 will not ACKNOWLEDGE any data bytes writ-
ten after the first byte is entered (Refer to Figure 13.).
When writing to the CONSTAT register, the bit CS4 must
always be set to “0”. Writing a “1” to bit CS4 of the CON-
STAT register is a reserved operation.
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with the
whole sequence requiring 3 steps
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded by
a START and ended with a STOP).
—Write a 06H to the CONSTAT Register to set the Regis-
ter Write Enable Latch (RWEL) AND the WEL bit. This
is also a volatile cycle. The zeros in the data byte are
required. (Operation preceded by a START and ended
with a STOP).
POR1 POR0 Power on Reset delay (tPUV1RO)
0 0 50ms
0 1 100ms (Default)
1 0 200ms
1 1 300ms
S
T
A
R
T
1010010R/W
A
C
K
11111
111 A
C
K
SCL
SDA
S
T
O
P
A
C
K
CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
SLAVE ADDRESS BYTE ADDRESS BYTE CONSTAT REGISTER DATA IN
Figure 13. CONSTAT Register Write Command Sequence
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X9523 – Preliminary Information
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT
register can be represented as qxyst01r in binary,
where xy are the Voltage Monitor Output Status (V2OS
and V3OS) bits, t is the DCP Write Lock (DWLK) bit,
and qr are the Power On Reset delay time (tPUV1RO)
control bits (POR1 - POR0). This operation is pro-
ceeded by a START and ended with a STOP bit. Since
this is a nonvolatile write cycle, it will typically take 5ms
to complete. The RWEL bit is reset by this cycle and the
sequence must be repeated to change the nonvolatile
bits again. If bit 2 is set to ‘1’ in this third step (qxys t11r)
then the RWEL bit is set, but the V2OS, V3OS, POR1,
POR0, and DWLK bits remain unchanged. Writing a
second byte to the control register is not allowed. Doing
so aborts the write operation and the X9523 does not
return an ACKNOWLEDGE.
For example, a sequence of writes to the device CON-
STAT register consisting of [02H, 06H, 02H] will reset all of
the nonvolatile bits in the CONSTAT Register to “0”.
It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect pin
of the X9523 is active (HIGH) (See "WP: Write Protection
Pin").
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at
any time by performing a random read (See Figure 14).
Using the Slave Address Byte set to 10100101, and an
Address Byte of FFh. Only one byte is read by each regis-
ter read operation. The X9523 resets itself after the first
byte is read. The master should supply a STOP condition
to be consistent with the bus protocol.
After setting the WEL and / or the RWEL bit(s) to a “1”, a
CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write opera-
tion.
When performing a read operation on the CONSTAT reg-
isterm, bit CS4 will always return a “0” value.
DATA PROTECTION
There are a number of levels of data protection features
designed into the X9523. Any write to the device first
requires setting of the WEL bit in the CONSTAT register. A
write to the CONSTAT register itself, further requires the
setting of the RWEL bit. DCP Write Lock protection of the
device enables the user to inhibit writes to all the DCPs.
One further level of data protection in the X9523, is incor-
porated in the form of the Write Protection pin.
Figure 14. CONSTAT Register Read Command Sequence
0
Slave
Address
Address
Byte
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
1
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
0 1 0 0 1 011 0 1 0 0 1 0
WRITE Operation
“Dummy” Write
READ Operation
CS7
…
CS0
X9522 Write Permission Status
DWLK
(DCP Write Lock
bit status)
WP
(Write Protect pin
status)
DCP Volatile Write
Permitted
DCP Nonvolatile
Write Permitted
Write to CONSTAT Register
Permitted
Volatile Bits Nonvolatile Bits
1 1 NO NO YES NO
0 1 YES NO YES NO
1
0
NO NO YES YES
0
0
YES YES YES YES
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X9523
– Preliminary Information
WP: Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9523.
The table below (X9523 Write Permission Status) sum-
marizes the effect of the WP pin (and DCP Write Lock), on
the write permission status of the device.
Additional Data Protection Features
In addition to the preceding features, the X9523 also
incorporates the following data protection functionality:
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvol-
atile write cycle.
VOLTAGE MONITORING FUNCTIONS
V1 / Vcc Monitoring
The X9523 monitors the supply voltage and drives the
V1RO output HIGH (using an external “pull up” resistor) if
V1 / Vcc is lower than V
TRIP1
threshold. The V1RO out-
put will remain HIGH until V1 / Vcc exceeds V
TRIP1
for
a minimum time of t
PURST
. After this time, the V1RO
pin is driven to a LOW state. See Figure 25.
For the Power On / Low Voltage Reset function of the
X9523, the V1RO output may be driven HIGH down to a
V1 / Vcc of 1V (V
RVALID
). See Figure 25. Another feature
of the X9523, is that the value of t
PURST
may be selected
in software via the CONSTAT register (See “POR1,
POR0: Power On Reset bits - (Nonvolatile)” on page 11.).
Is is recommended to stop communication to the device
while while V1RO is HIGH. Also, setting the Manual Reset
(MR) pin HIGH overrides the Power On / Low Voltage
circuitry and forces the V1RO output pin HIGH (See
"Manual Reset").
Manual Reset
The V1RO output can be forced HIGH externally using
the Manual Reset (MR) input. MR is a de-bounced, TTL
compatible input, and so it may be operated by connect-
ing a push-button directly from V1 / Vcc to the MR pin.
V1RO remains HIGH for time t
PURST
after MR has
returned to its LOW state (See Figure 15). An external
“pull down” resistor is required to hold this pin (nor-
mally) LOW.
V2 monitoring
The X9523 asserts the V2RO output HIGH if the volt-
age V2 exceeds the corresponding V
TRIP2
threshold
(See Figure 16). The bit V2OS in the CONSTAT regis-
ter is then set to a “0” (assuming that it has been set to
“1” after system initilization).
The V2RO output may remain active HIGH with V
CC
down to 1V.
V3 monitoring
The X9523 asserts the V3RO output HIGH if the volt-
age V3 exceeds the corresponding V
TRIP3
threshold
(See Figure 16). The bit V3OS in the CONSTAT regis-
ter is then set to a “0” (assuming that it has been set to
“1” after system initilization).
The V3RO output may remain active HIGH with V
CC
down to 1V.
V
TRIPX
THRESHOLDS (X=1,2,3)
The X9523 is shipped with pre-programmed threshold
(V
TRIPx
) voltages. In applications where the required
thresholds are different from the default values, or if a
higher precision / tolerance is required, the X9523 trip
points may be adjusted by the user, using the steps
detailed below.
Setting a V
TRIPx
Voltage (x=1,2,3)
There are two procedures used to set the threshold
voltages (V
TRIPx
), depending if the threshold voltage to
be stored is higher or lower than the present value. For
example, if the present V
TRIPx
is 2.9 V and the new
V
TRIPx
is 3.2 V, the new voltage can be stored directly
MR
V1RO
V1 / Vcc
0 Volts
0 Volts
tPURST
Figure 15. Manual Reset Response
0 Volts
VTRIP1
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X9523 – Preliminary Information
into the VTRIPx cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
“reset” the VTRIPx voltage before setting the new value.
Setting a Higher VTRIPx Voltage (x=1,2,3)
To set a VTRIPx threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired VTRIPx threshold voltage to the corre-
sponding input pin (V1 / Vcc, V2 or V3). Then, a pro-
gramming voltage (Vp) must be applied to the WP pin
before a START condition is set up on SDA. Next, issue
on the SDA pin the Slave Address A0h, followed by the
Byte Address 01h for VTRIP1, 09h for VTRIP2, and 0Dh
for VTRIP3, and a 00h Data Byte in order to program
VTRIPx. The STOP bit following a valid write operation
initiates the programming sequence. Pin WP must then
be brought LOW to complete the operation (See Figure
18). The user does not have to set the WEL bit in the
CONSTAT register before performing this write
sequence.
Setting a Lower VTRIPx Voltage (x=1,2,3).
In order to set VTRIPx to a lower voltage than the
present value, then VTRIPx must first be “reset” accord-
ing to the procedure described below. Once VTRIPx
has been “reset”, then VTRIPx can be set to the desired
voltage using the procedure described in “Setting a
Higher VTRIPx Voltage”.
01234567
SCL
SDA
A0h
01234567
WP
VP
01234567
VTRIPx
V2, V3
01h† sets VTRIP1
Figure 17. Setting VTRIPx to a higher level (x=1,2,3).
09h† sets VTRIP2
0Dh† sets VTRIP3
Data Byte †
V1 / Vcc
00h
S
T
A
R
T
†
† All others Reserved.
SDA
A0h
†
01234567
SCL
01234567
WP
V
P
01234567
Figure 18. Resetting the VTRIPx Level
03h
†
Resets
VTRIP1
0Bh
†
Resets
VTRIP2
0Fh
†
Resets
VTRIP3
Data Byte
00h
†
S
T
A
R
T† All others Reserved.
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X9523 – Preliminary Information
Resetting the VTRIPx Voltage (x=1,2,3).
To reset a VTRIPx voltage, apply the programming volt-
age (Vp) to the WP pin before a START condition is set
up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
VTRIP1, 0Bh for VTRIP2, and 0Fh for VTRIP3, followed
by 00h for the Data Byte in order to reset VTRIPx. The
STOP bit following a valid write operation initiates the
programming sequence. Pin WP must then be brought
LOW to complete the operation (See Figure 18).The
user does not have to set the WEL bit in the CONSTAT
register before performing this write sequence.
After being reset, the value of VTRIPx becomes a nomi-
nal value of 1.7V.
VTRIPx Accuracy (x=1,2,3).
The accuracy with which the VTRIPx thresholds are set,
can be controlled using the iterative process shown in
Figure 19.
If the desired threshold is less that the present threshold
voltage, then it must first be “reset” (See "Resetting the
VTRIPx Voltage (x=1,2,3).").
The desired threshold voltage is then applied to the
appropriate input pin (V1 / Vcc, V2 or V3) and the pro-
cedure described in Section “Setting a Higher VTRIPx
Voltage“ must be followed.
Once the desired VTRIPx threshold has been set, the error
between the desired and (new) actual set threshold can
be determined. This is achieved by applying V1 / Vcc to
the device, and then applying a test voltage higher than
the desired threshold voltage, to the input pin of the volt-
age monitor circuit whose VTRIPx was programmed. For
example, if VTRIP2 was set to a desired level of 3.0 V,
then a test voltage of 3.4 V may be applied to the voltage
monitor input pin V2. In the case of setting of VTRIP1 then
only V1 / Vcc need be applied. In all cases, care should
be taken not to exceed the maximum input voltage limits.
After applying the test voltage to the voltage monitor input
pin, the test voltage can be decreased (either in discrete
steps, or continuously) until the output of the voltage mon-
itor circuit changes state. At this point, the error between
the actual / measured, and desired threshold levels is cal-
culated.
For example, the desired threshold for VTRIP2 is set to 3.0
V, and a test voltage of 3.4 V was applied to the input pin
V2 (after applying power to V1 / Vcc). The input voltage is
decreased, and found to trip the associated output level of
pin V2RO from a LOW to a HIGH, when V2 reaches 3.09
V. From this, it can be calculated that the programming
error is 3.09 - 3.0 = 0.09 V.
If the error between the desired and measured VTRIPx is
less than the maximum desired error, then the program-
ming process may be terminated. If however, the error is
greater than the maximum desired error, then another
iteration of the VTRIPx programming sequence can be
performed (using the calculated error) in order to further
increase the accuracy of the threshold voltage.
If the calculated error is greater than zero, then the VTRIPx
must first be “reset”, and then programmed to the a value
equal to the previously set VTRIPx minus the calculated
error. If it is the case that the error is less than zero, then
the VTRIPx must be programmed to a value equal to the
previously set VTRIPx plus the absolute value of the calcu-
lated error.
Continuing the previous example, we see that the calcu-
lated error was 0.09V. Since this is greater than zero, we
must first “reset” the VTRIP2 threshold, then apply a volt-
age equal to the last previously programmed voltage,
minus the last previously calculated error. Therefore, we
must apply VTRIP2 = 2.91 V to pin V2 and execute the
programming sequence (See "Setting a Higher VTRIPx
Voltage (x=1,2,3)").
Using this process, the desired accuracy for a particular
VTRIPx threshold may be attained using a successive
number of iterations.
Figure 16. Voltage Monitor Response
Vx
VxRO
0V
0V
VTRIPx
(x = 2,3)
0 Volts
VTRIP1
V1 / Vcc
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X9523 – Preliminary Information
VTRIPx Programming
Apply Vcc & Voltage
Decrease Vx
switches?
Actual VTRIPx
- Desired VTRIPx
DONE
Execute
Sequence
VTRIPx Reset
Set Vx = desired VTRIPx
Execute
Sequence
Set Higher VTRIPx
New Vx applied =
Old Vx applied + | Error |
Execute
Sequence
Reset VTRIPx
New Vx applied =
Old Vx applied - | Error |
Error < MDE–
| Error | < | MDE |
YES
NO
Error >MDE+
NO
YES
Figure 19. VTRIPx Setting / Reset Sequence (x=1,2,3)
> Desired VTRIPx to Vx
Desired VTRIPx <
present value?
Note: X = 1,2,3.
Let: MDE = Maximum Desired Error
Output
Acceptable
Error Range
MDE+
MDE–
Error = Actual – Desired
= Error
Desired Value
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X9523 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability
Figure 20. Equivalent A.C. Circuit
Figure 21. DCP SPICE Macromodel
Parameter Min. Max. Units
Temperature under Bias –65 +135 °C
Storage Temperature –65 +150 °C
Voltage on WP pin (With respect to Vss) –1.0 +15 V
Voltage on other pins (With respect to Vss) –1.0 +7 V
| Voltage on RHx– Voltage on RLx | (x=0,1,2. Referenced to Vss)V1 / Vcc V
D.C. Output Current (SDA,V1RO,V2RO,V3RO) 05mA
Lead Temperature (Soldering, 10 seconds) 300 °C
Supply Voltage Limits (Applied V1 / Vcc voltage, referenced to Vss) 2.7 5.5 V
Temperature Min. Max. Units
Commercial 070
°C
Industrial –40 +85 °C
V1 / Vcc = 5V
V2RO 100pF
SDA
2300Ω
V3RO
V1RO
CH
CL
RWx
10pF
10pF
RHx RLx
RTOTAL
CW
25pF
RW
(x=0,1,2)
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X9523 – Preliminary Information
TIMING DIAGRAMS
Figure 22. Bus Timing
Figure 23. WP Pin Timing
Figure 24. Write Cycle Timing
tSU:STO
tDH
tHIGH
tSU:STA tHD:STA
tHD:DAT
tSU:DAT
SCL
SDA IN
SDA OUT
tFtLOW
tBUF
tA
tR
tHD:WP
SCL
SDA IN
WP tSU:WP
Clk 1 Clk 9
START
SCL
SDA
tWC
8th bit of last byte ACK
Stop
Condition
Start
Condition
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X9523 – Preliminary Information
Figure 25. Power-Up and Power-Down Timing
Figure 26. Manual Reset Timing Diagram
Figure 27. V2, V3 Timing Diagram
V1 / Vcc
tPURST
tRtF
0 Volts
VTRIP1
V1RO
tRPD
0 Volts
tPURST
MR 0 Volts
0 Volts
MR
V1RO
tPURST
tMRD
0 Volts
V1 / Vcc
V1 / Vcc
VTRIP1
tMRPW
Vx
tRx tFx
VTRIPx
VRVALID
VxRO
tRPDx
0 Volts
Note : x = 2,3. 0 Volts
0 Volts
tRPDx tRPDx
tRPDx
VTRIP1
V1 / Vcc
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X9523 – Preliminary Information
Figure 28. VTRIPX Programming Timing Diagram (x=1,2,3).
Figure 29. DCP “Wiper Position” Timing
WP
t
VPS
VP
tVPO
SCL
SDA
twc
tTSU tTHD
V1 / Vcc, V2, V3
VTRIPx
00h
tVPH
NOTE : V1/Vcc must be greater than V2, V3 when programming.
S
T
A
R
T
10101110A
C
K
WT 0 0 0 0 0 P1 P0 A
C
K
S
T
O
P
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
SLAVE ADDRESS BYTE INSTRUCTION BYTE DATA BYTE
SCL
SDA
Time
Rwx (x=0,1,2)
twr
Rwx(n+1)
Rwx(n-1)
Rwx(n)
n = tap position
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X9523 – Preliminary Information
D.C. OPERATING CHARACTERISTICS
Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the
Slave Address Byte are incorrect; 200nS after a STOP ending a read operation; or tWC after a STOP ending a write operation.
Notes: 2. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; tWC after a STOP that
initiates a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave
Address Byte.
Notes: 3. Current through external pull up resistor not included.
Notes: 4. VIN = Voltage applied to input pin.
Notes: 5. VOUT = Voltage applied to output pin.
Notes: 6. See “ORDERING INFORMATION” on page 31.
Notes: 7. VIL Min. and VIH Max. are for reference only and are not tested
Symbol Parameter Min Typ Max Unit Test Conditions / Notes
ICC1(1)
Current into VCC Pin
(X9523: Active)
Read memory array (3)
Write nonvolatile memory
0.4
1.5
mA fSCL = 400KHz
ICC2(2)
Current into VCC Pin
(X9523:Standby)
With 2-Wire bus activity (3)
No 2-Wire bus activity
30.0
30.0
µA
VSDA = VCC
MR = Vss
WP = Vss or Open/Floating
VSCL= VCC (when no bus activity
else fSCL = 400kHz)
ILI
Input Leakage Current (SCL, SDA, MR) 0.1 10 µAVIN (4) = GND to VCC.
Input Leakage Current (WP) 1µA
ILO Output Leakage Current (SDA, V1RO,
V2RO, V3RO) 0.1 10 µAVOUT (5) = GND to VCC.
X9523 is in Standby(2)
VTRIP1PR VTRIP1 Programming Range 2.75 4.70 V
VTRIPxPR VTRIPx Programming Range (x=2,3) 1.8 4.70 V
VTRIP1 (6) Pre - programmed VTRIP1 threshold 2.95
4.65
3.0
4.7
3.05
4.75 VFactory shipped default option A
Factory shipped default option B
VTRIP2 (6) Pre - programmed VTRIP2 threshold 1.75
2.95
1.8
3.0
1.85
3.05 VFactory shipped default option A
Factory shipped default option B
VTRIP3 (6) Pre - programmed VTRIP3 threshold 1.75
2.95
1.8
3.0
1.85
3.05 VFactory shipped default option A
Factory shipped default option B
IVx V2 Input leakage current
V3 Input leakage current
1
1µAVSDA=VSCL=VCC
Others=GND or VCC
VIL (7) Input LOW Voltage (SCL, SDA, WP, MR) -0.5 0.8 V
VIH (7) Input HIGH Voltage (SCL,SDA, WP, MR) 2.0 VCC
+0.5 V
VOLx V1RO, V2RO, V3RO, SDA Output Low
Voltage 0.4 V ISINK = 2.0mA
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X9523 – Preliminary Information
A.C. CHARACTERISTICS (See Figure 22, Figure 23, Figure 24)
A.C. TEST CONDITIONS
NONVOLATILE WRITE CYCLE TIMING
CAPACITANCE (TA = 25˚C, F = 1.0 MHZ, VCC = 5V)
Notes: 1. Typical values are for TA = 25˚C and VCC = 5.0V
Notes: 2. Cb = total capacitance of one bus line in pF.
Notes: 3. Over recommended operating conditions, unless otherwise specified
Notes: 4. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write
cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Notes: 5. This parameter is not 100% tested.
Symbol Parameter
400kHz
Min Max Units
fSCL SCL Clock Frequency 0 400 KHz
tIN (5) Pulse width Suppression Time at inputs 50 ns
tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs
tBUF Time the bus free before start of new transmission 1.3 µs
tLOW Clock LOW Time 1.3 µs
tHIGH Clock HIGH Time 0.6 µs
tSU:STA Start Condition Setup Time 0.6 µs
tHD:STA Start Condition Hold Time 0.6 µs
tSU:DAT Data In Setup Time 100 ns
tHD:DAT Data In Hold Time 0µs
tSU:STO Stop Condition Setup Time 0.6 µs
tDH Data Output Hold Time 50 ns
tR (5) SDA and SCL Rise Time 20 +.1Cb (2) 300 ns
tF (5) SDA and SCL Fall Time 20 +.1Cb (2) 300 ns
tSU:WP WP Setup Time 0.6 µs
tHD:WP WP Hold Time 0µs
Cb Capacitive load for each bus line 400 pF
Input Pulse Levels 0.1VCC to 0.9VCC
Input Rise and Fall Times 10ns
Input and Output Timing Levels 0.5VCC
Output Load See Figure 20
Symbol Parameter Min. Typ.(1) Max. Units
tWC(4) Nonvolatile Write Cycle Time 5 10 ms
Symbol Parameter Max Units Test Conditions
COUT (5) Output Capacitance (SDA, V1RO, V2RO, V3RO) 8 pF VOUT = 0V
CIN (5) Input Capacitance (SCL, WP, MR) 6 pF VIN = 0V
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X9523 – Preliminary Information
POTENTIOMETER CHARACTERISTICS
Notes: 1. Power Rating between the wiper terminal RWX(n) and the end terminals RHX or RLX - for ANY tap position n, (x=0,1,2).
Notes: 2. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (Rwx(n)(actual) – Rwx(n)(expected))
= ±1 Ml Maximum (x=0,1,2).
Notes: 3. Relative Linearity is a measure of the error in step size between taps = RWx(n+1) – [Rwx(n) + Ml] = ±0.2 Ml (x=0,1,2)
Notes: 4. 1 Ml = Minimum Increment = RTOT / (Number of taps in DCP - 1).
Notes: 5. Typical values are for TA = 25°C and nominal supply voltage.
Notes: 6. This parameter is periodically sampled and not 100% tested.
Symbol Parameter
Limits
Test Conditions/NotesMin. Typ. Max. Units
RTOL End to End Resistance Tolerance –20 +20 %
VRHx RH Terminal Voltage (x=0,1,2) Vss VCC V
VRLx RL Terminal Voltage (x=0,1,2) Vss VCC V
PRPower Rating (1) 10 mW RTOTAL = 10 KΩ (DCP0,
DCP1)
5mW
RTOTAL = 100 KΩ (DCP2)
RWDCP Wiper Resistance
200 400 ΩIW = 1mA, VCC = 5 V, VRHx =
Vcc, VRLx = Vss (x=0,1,2).
300 700 ΩIW = 1mA, VCC = 3.3 V, VRHx =
Vcc, VRLx = Vss (x=0,1,2),
400 1000 ΩIW = 1mA, VCC = 2.7 V, VRHx =
Vcc, VRLx = Vss (x=0,1,2)
IWWiper Current 4.4 mA
Noise
mV /
sqt(Hz) RTOTAL = 10 kΩ (DCP0, DCP1)
mV /
sqt(Hz) RTOTAL = 100 kΩ (DCP2)
Absolute Linearity (2) -1 +1 MI(4) Rw(n)(actual) – Rw(n)(expected)
Relative Linearity (3) -0.2 +0.2 MI(4) Rw(n+1) – [Rw(n)+MI]
RTOTAL Temperature Coefficient ±300 ppm/°C RTOTAL = 10 kΩ (DCP0, DCP1)
±300 ppm/°C RTOTAL = 100 kΩ (DCP2)
CH/CL/
CW
Potentiometer Capacitances 10/10/
25
pF See Figure 21.
twr Wiper Response time 200 µsSee Figure 29.
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X9523 – Preliminary Information
VTRIPX (X=1,2,3) PROGRAMMING PARAMETERS (See Figure 28)
Notes: 1. This parameter is not 100% tested.
Parameter Description Min Typ Max Units
tVPS VTRIPx Program Enable Voltage Setup time 10 µs
tVPH VTRIPx Program Enable Voltage Hold time 10 µs
tTSU VTRIPx Setup time 10 µs
tTHD VTRIPx Hold (stable) time 10 µs
tVPO VTRIPx Program Enable Voltage Off time
(Between successive adjustments) 1ms
twc VTRIPx Write Cycle time 510 ms
VPProgramming Voltage 10 15 V
Vta1(1) Initial VTRIPx Program Voltage accuracy
(Vx applied - VTRIPx) (Programmed at 25oC.) -0.1 +0.2 V
Vta2(1) Subsequent VTRIPx Program Voltage accuracy
[(Vx applied - Vta1) - VTRIPx. Programmed at 25oC.) -25 +10 +25 mV
Vtv VTRIP Program variation after programming (-40 - 85oC).
(Programmed at 25oC.) -25 +10 +25 mV
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X9523 – Preliminary Information
V1RO, V2RO, V3RO OUTPUT TIMING. (See Figure 25, Figure 26, Figure 27)
Notes: 1. See Figure 26 for timing diagram.
Notes: 2. See Figure 20 for equivalent load.
Notes: 3. This parameter describes the lowest possible V1 / Vcc level for which the outputs V1RO, V2RO, and V3RO will be correct with
respect to their inputs (V1 / Vcc, V2, V3).
Notes: 4. From MR rising edge crossing VIH, to V1RO rising edge crossing VOH.
Symbol Description Condition Min. Typ. Max. Units
tPURST Power On Reset delay time
POR1= 0, POR0= 0 25 50 75 ms
POR1= 0, POR0= 1 50 100 150 ms
POR1= 1, POR0= 0 100 200 300 ms
POR1= 1, POR0= 1 150 300 450 ms
tMRD
(26)(2) MR to V1RO propagation delay See (1),(2),(4).5µs
tMRDPW MR pulse width 500 ns
tRPDx
V1 / Vcc, V2, V3 to V1RO,
V2RO, V3RO propagation
delay (respectively)
20 µs
tFx V1 / Vcc, V2, V3 Fall Time 20 mV/µs
tRx V1 / Vcc, V2, V3 Rise Time 20 mV/µs
VRVALID V1 / Vcc for V1RO, V2RO,
V3RO Valid (3).1V
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X9523 – Preliminary Information
APPENDIX 1
DCP1 (100 Tap) Tap position to Data Byte translation Table
Tap
Position
Data Byte
Decimal Binary
0 0 0000 0000
1 1 0000 0001
.
.
.
.
.
.
23 23 0001 0111
24 24 0001 1000
25 56 0011 1000
26 55 0011 0111
.
.
.
.
.
.
48 33 0010 0001
49 32 0010 0000
50 64 0100 0000
51 65 0100 0001
.
.
.
.
.
.
73 87 0101 0111
74 88 0101 1000
75 120 0111 1000
76 119 0111 0111
.
.
.
.
.
.
98 97 0110 0001
99 96 0110 0000
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X9523 – Preliminary Information
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1)
unsigned DCP1_TAP_Position(int tap_pos)
{
int block;
int i;
int offset;
int wcr_val;
offset= 0;
block = tap_pos / 25;
if (block < 0) return ((unsigned)0);
else if (block <= 3)
{ switch(block)
{ case (0): return ((unsigned)tap_pos) ;
case (1):
{
wcr_val = 56;
offset = tap_pos - 25;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
case (2):
{
wcr_val = 64;
offset = tap_pos - 50;
for (i=0; i<= offset; i++) wcr_val++ ;
return ((unsigned)--wcr_val);
}
case (3):
{
wcr_val = 120;
offset = tap_pos - 75;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
}
}
return((unsigned)01100000);
}
REV 1.1.6 9/14/01 Characteristics subject to change without notice. 28 of 31
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X9523 – Preliminary Information
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2)
unsigned DCP100_TAP_Position(int tap_pos)
{
/* optional range checking
*/ if (tap_pos < 0) return ((unsigned)0); /* set to min val */
else if (tap_pos >99) return ((unsigned) 96); /* set to max val */
/* 100 Tap DCP encoding formula */
if (tap_pos > 74)
return ((unsigned) (195 - tap_pos));
else if (tap_pos > 49)
return ((unsigned) (14 + tap_pos));
else if (tap_pos > 24)
return ((unsigned) (81 - tap_pos));
else return (tap_pos);
}
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X9523 – Preliminary Information
20 Ball BGA (X9523)
a
B
A
D
C
E
1234
B
A
D
C
E
1234
b
Top View (Bump Side Down)
Side View (Bump Side Down)
Bottom View (Bump Side Up)
c
d
e
f
k
a
j
b
Note: Drawing not to scale
= Die Orientation mark
Symbol
Millimeters Inches
Min Nom Max Min Nom Max
Package Body Dimension X a 2.524 2.554 2.584 0.09938 0.10056 0.10174
Package Body Dimension Y b 3.794 3.824 3.854 0.14938 0.15056 0.15174
Package Height c 0.654 0.682 0.710 0.02575 0.02685 0.02795
Body Thickness d 0.444 0.457 0.470 0.01748 0.01799 0.01850
Ball Height e 0.210 0.225 0.240 0.00827 0.00886 0.00945
Ball Diameter f 0.316 0.326 0.336 0.01244 0.01283 0.01323
Ball Pitch – X Axis j 0.5 0.01969
Ball Pitch – Y Axis k 0.5 0.01969
Ball to Edge Spacing –
Distance Along X l 0.497 0.527 0.557 0.01957 0.02075 0.02193
Ball to Edge Spacing –
Distance Along Y m 0.882 0.912 0.942 0.03473 0.03591 0.03709
l
m
Ball Matrix
4321
ARL2 RW2 V1/VCC V2RO
BV3 RH2 V1RO V2
CWP V3RO NC NC
DSCL MR NC RH1
ESDA RL1 RW1 VSS
REV 1.1.6 9/14/01 Characteristics subject to change without notice. 30 of 31
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X9523 – Preliminary Information
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.169 (4.3)
.177 (4.5) .252 (6.4) BSC
.025 (.65) BSC
.252 (6.4)
.260 (6.6)
.002 (.05)
.006 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
See Detail “A”
.031 (.80)
.041 (1.05)
0° – 8°
.010 (.25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
Detail A (20X)
(4.16) (7.72)
(1.78)
(0.42)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
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X9523 – Preliminary Information
ORDERING INFORMATION
Device Preset (Factory Shipped) VTRIPx Threshold Levels (x=1,2,3)
A = Optimized for 3.3 V system monitoring †
B = Optimized for 5 V system monitoring †
Temperature Range
I = Industrial -40°C to +85°C
Package
V20 = 20-Lead TSSOP
B20 = 20-Lead XBGA
X9523 P T
XBGA PART MARK CONVENTION
20 Lead XBGA Top Mark
X9523B20I-A XACO
X9523B20I-B XACS
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc.
All others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461;
4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880;
5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents
pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure
to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
-y
† For details of preset threshold values, See "D.C. OPERATING CHARACTERISTICS"
