DATA SH EET
Product specification
File under Integrated Circuits, IC04 January 1995
INTEGRATED CIRCUITS
HEF4040B
MSI
12-stage binary counter
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
12-stage binary counter HEF4040B
MSI
DESCRIPTION
The HEF4040B is a 12-stage binary ripple counter with a
clock input (CP), an overriding asynchronous master reset
input (MR) and twelve fully buffered outputs (O0to O11).
The counter advances on the HIGH to LOW transition of
CP. A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of CP. Each counter stage is a
static toggle flip-flop. Schmitt-trigger action in the clock
input makes the circuit highly tolerant to slower clock rise
and fall times.
Fig.1 Functional diagram.
HEF4040BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4040BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4040BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
APPLICATION INFORMATION
Some examples of applications for the HEF4040B are:
•Frequency dividing circuits
•Time delay circuits
•Control counters
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
CP clock input (HIGH to LOW edge-triggered)
MR master reset input (active HIGH)
O0to O11 parallel outputs
January 1995 3
Philips Semiconductors Product specification
12-stage binary counter HEF4040B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb =25°C; CL= 50 pF; input transition times ≤20 ns
VDD
VSYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP →O05 105 210 ns 78 ns +(0,55 ns/pF) CL
HIGH to LOW 10 tPHL 45 90 ns 34 ns +(0,23 ns/pF) CL
15 35 70 ns 27 ns +(0,16 ns/pF) CL
5 85 170 ns 58 ns +(0,55 ns/pF) CL
LOW to HIGH 10 tPLH 40 80 ns 29 ns +(0,23 ns/pF) CL
15 30 60 ns 22 ns +(0,16 ns/pF) CL
On→On+15 35 70 ns note 1 (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 15 30 ns note 1 (0,23 ns/pF) CL
15 10 20 ns note 1 (0,16 ns/pF) CL
5 35 70 ns note 1 (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 15 30 ns note 1 (0,23 ns/pF) CL
15 10 20 ns note 1 (0,16 ns/pF) CL
MR →On5 90 180 ns 63 ns +(0,55 ns/pF) CL
HIGH to LOW 10 tPHL 40 80 ns 29 ns +(0,23 ns/pF) CL
15 30 60 ns 22 ns +(0,16 ns/pF) CL
Output transition times 5 60 120 ns 10 ns +(1,0 ns/pF) CL
HIGH to LOW 10 tTHL 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
5 60 120 ns 10 ns +(1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
Fig.3 Logic diagram.
January 1995 4
Philips Semiconductors Product specification
12-stage binary counter HEF4040B
MSI
Note
1. For other loads than 50 pF at the nth output, use the slope given.
Minimum clock 5 50 25 ns
see also waveforms
Fig.4
pulse width; HIGH 10 tWCPH 30 15 ns
15 20 10 ns
Minimum MR 5 40 20 ns
pulse width; HIGH 10 tWMRH 30 15 ns
15 20 10 ns
Recovery time 5 40 20 ns
for MR 10 tRMR 30 15 ns
15 20 10 ns
Maximum clock 5 10 20 MHz
pulse frequency 10 fmax 15 30 MHz
15 25 50 MHz
VDD
VTYPICAL FORMULA FOR P (µW)
Dynamic power 5 400 fi+∑(foCL)×VDD2where
dissipation per 10 2 000 fi+∑(foCL)×VDD2fi= input freq. (MHz)
package (P) 15 5 200 fi+∑(foCL)×VDD2fo= output freq. (MHz)
CL= load cap. (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
VDD
VSYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION
FORMULA
January 1995 5
Philips Semiconductors Product specification
12-stage binary counter HEF4040B
MSI
Fig.4 Waveforms showing propagation delays for MR to Onand CP to O0, minimum MR and CP pulse widths.
