SST25VF080-20-4I-S2AE - Microchip Technology, Inc.

S71250-01-000 12/03

The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Advance Information

FEATURES:

• Single Voltage Read and Write Operations

– 2.7-3.6V for SST25VF080

• Serial In terface Architecture

– SPI Compatible: Mode 0 and Mode 3

• 20 MHz Max Clock Frequen cy

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Read Current: 7 mA (typical)

– Standby Current: 8 µA (typical)

• Flexible Erase Capabil i ty

– Uniform 4 KByte sectors

– Uniform 32 KByte overlay blocks

• Fast Erase and Byte-Program:

– Chip-Erase Time: 70 ms (typical)

– Sector- or Block-Erase Time: 18 ms (typical)

– Byte-Program T ime: 14 µs (typical)

• Auto Address Increm ent (AAI) Programming

– Decrease total chip programming time over

Byte-Program operations

• End-of-Write Detection

– Software Status

• Hold Pin (HOLD#)

– Suspends a serial sequence to the memory

without deselecting the device

• Write Protection (WP# )

– Enables/Disables the Lock-Down function of the

status register

• Software Write Protection

– Write protection through Block-Protection bits in

status register

• Temperature Range

– Commercial: 0°C to +70°C

– Industrial: -40°C to +85°C

• Packages Available

– 8-lead SOIC 200 mil body width

PRODUCT DESCRIPTION

SST’s serial flash family features a four-wire, SPI-com-

patible interface that allows for a low pin-count package

occupying less board space and ultimately lowering total

system costs. SST25VF080 SPI serial flash memories

are manufactured with SST’s proprietary, high perfor-

mance CM OS Supe r Flash tech nol ogy. The sp lit- gat e cell

design and t hic k-o xide t unnelin g injecto r attain be tter reli-

ability and manufacturability compared with alternate

approaches.

The SST25VF080 devices significantly improve perfor-

mance, while lowering power consumption. The total

energy consumed is a function of the applied voltage,

current, and time of application. Since for any given volt-

age range, the SuperFlash technology uses less current

to pr ogr am an d has a sh orter erase time , the tota l energy

consumed du ring any Erase or Program ope ration is less

than alternative flash memory technologies. The

SST25VF080 devices operate with a single 2.7-3.6V

power su ppl y.

The SST25VF 080 dev ices are offered in an 8-lead SOIC

package with 200 mil body width. See Figure 1 for pin

assignments.

8 Mbit SPI Serial Flash

SST25VF080

SST25VF0808Mb Serial Peripheral Interface (SPI) flash memory

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

1250 B1.0

I/O Buffers

and

Data Latches

SuperFlash

Memory

X - Decoder

Control Logic

Address

Buffers

and

Latches

CE#

Y - Decoder

SCK SI SO WP# HOLD#

Serial Interface

FUNCTIONAL BLOCK DIAGRAM

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

PIN DESCRIPTION

FIGURE 1: PIN ASSIGNMENTS FOR 8-LEAD SOIC

TABLE 1: PIN DESCRIPTION

Symbol Pin Name Functions

SCK Serial Clock To provide the timing of the serial interface.

Commands, addresses , or i nput data are lat che d on the rising edge of th e c lock in put , while outpu t

data is shifted out on the falling edge of the clock input.

SI Serial Data

Input To transfer commands, addresses, or data serially into the device.

Inputs are latched on the rising edge of the serial clock.

SO Serial Data

Output To transfer data serially out of the device.

Data is shifted out on the falling edge of the serial clock.

CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of

any command sequence.

WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.

HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device.

VDD Power Supply To provide power supply voltage: 2.7-3.6V for SST25VF080

VSS Ground

T1.0 1250

CE#

WP#

VSS

VDD

HOLD#

SCK

Top View

1250 08-soic P1.0

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

PRODUCT IDENTIFICATION

MEMORY ORGANIZATION

The SST25VF080 SuperFlash memory array is organized

in 4 KByt e sector s with 32 KBy te o verla y b loc ks .

DEVICE OPERATION

The SST25VF080 is accessed through the SPI (Serial

Peripheral In terface) bus compatible protocol. The SPI bus

consi st of four c ontrol l ines; Chip Enable (CE#) is used t o

sele ct the device, and d ata is acces sed t hrou gh the S eri al

Data Inpu t (SI ), Ser ial D ata O utput (S O), an d Ser ial Clock

(SCK).

The SST25VF080 supports both Mode 0 (0,0) and Mode 3

(1,1) of SPI bus operations. The difference between the

two mode s, as shown in Figu re 2, is the sta te of th e SCK

signal when the bus master is in Stand-by mode and no

data is being transf erred. The SCK signal is low f or Mode 0

and SCK signal is high for Mode 3. For both modes, the

Serial Data In (SI) is sampled at the rising edge of the SCK

clock signal and the Serial Data Output (SO) is driv en after

the falling edge of the SCK clock signal.

FIGURE 2: SPI PROTOCOL

TABLE 2: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 00000H BFH

Device ID

SST25VF080 00001H 80H

T2.0 1250

1250 F02.0

MODE 3

SCK

CE#

MODE 3

DON'T CARE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0MODE 0

HIGH IMPEDANCE

MSB

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

Hold Operation

HOLD# p in is us ed to pa use a seria l sequ ence un derway

with the SPI flash memory without resetting the clocking

sequenc e. To activate the HOLD# mode, CE# mus t be in

active low state. The HOLD# mode be gins when the SCK

active low state coincides with the falling edge of the

HOLD# signal. The HOLD mode ends when the HOLD#

signal’ s rising edge coincides with the SCK activ e low state.

If the falling edge of the HOLD# signal does not coincide

with the SCK active low state, then the device enters Hold

mode when the SCK next reaches the active low state.

Similarly, if the rising edge of the HOLD# signal does not

coincide with the SCK active low state, then the device

exits in Hold m ode wh en the S CK next reaches the ac tive

low state . See Figure 3 for Hold Condition wav eform.

Once the device enters Hold mode, SO will be in high-

impedance state while SI and SCK can be VIL or VIH.

If CE# is driven active high during a Hold condition, it r esets

the internal logic of the device. As long as HOLD# signal is

low, the memory remains in the Hold condition. To resume

communication with the device, HOLD# must be driven

active high, and CE# must be driven activ e low . See Figure

17 for Hold timing.

FIGURE 3: HOLD CONDITION WAVEFORM

Write Protec tion

SST25VF080 provides software Write protection. The

Write Pro t ect pi n (WP# ) en ables or disables th e lo ck-d own

function of the status register. The Block-Protection bits

(BP1, BP0, and BPL) in the status register provide Write

protection to the memory arra y and the status register . See

Tab le 5 f or Bloc k-Pr otec tion de scripti on.

Write Protect Pin (WP#)

The Wr ite Protect (WP#) pin enables the lock-down func-

tion of th e B PL bi t (bi t 7) i n th e s ta tus regi s ter. When W P #

is driven low, the execution of the Write-Status-Register

(WRSR) i nstr u ctio n is det er mi ned by the value of the B PL

bit (see Table 3). When WP# is high, the lock-down func-

tion of the BPL bit is disabled.

Active Hold Active Hold Active

1250 F03.0

SCK

HOLD#

TABLE 3: CONDITIONS TO EXECUTE WRITE-STATUS-

WP# BPL Execute WRSR Instruction

L1Not Allowed

L0Allowed

HXAllowed

T3.0 1250

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

Status Register

The softwa re stat us regist er pro vides s tatus on whether the

flash memory arr a y is av ailable f or any Read or Write oper-

ation, whether the de vice is Write enab led, and the state of

the memory Write protection. During an internal Erase or

Program operation, the status register may be read only to

determine the completion of an operation in progress.

Table 4 describes the function of each bit in the software

status register.

Busy

The Busy bit determines whether there is an internal Erase

or Program operation in progress. A “1” for the Busy bit indi-

cates the de vice is busy with an operation in progress. A “0”

indicates the device is ready for the next valid operation.

Write Enable Latch (WEL)

The Write-Enab le-Latch bit indicates the status of the inter-

nal memory Write Enab le Latch. If the Write-Enable-Latch

bit is set to “1”, it indicates the de vice is Write enabled. If the

bit is set to “0” (reset), it indicates the device is not Write

enabled and does not accept any memory Write (Program/

Erase) commands. The Write-Enable-Latch bit is automati-

cally reset under the following conditions:

•Power-up

•Write-Disable (WRDI) instruction completion

•Byte-Program instruction completion

•Auto Address Increment (AAI) programming

reached its highest memory address

•Sector-Er ase instruction completion

•Block-Erase instruction completion

•Chip- Era se ins truction co mpl et i on

TABLE 4: SOFTWARE STATUS REGISTER

Bit Name Function Default at

Power-up Read/Write

0 BUSY 1 = Internal Write operation is in progress

0 = No internal Write operation is in progress 0R

1 WEL 1 = De vice is memory Write enabled

0 = De vice is not memory Write enabled 0R

2 BP0 Indicate current lev el of bloc k write protection (See Table 5) 1 R/W

3 BP1 Indicate current lev el of bloc k write protection (See Table 5) 1 R/W

4:5 RES Reserv ed for future use 0 N/A

6 AAI A uto Address Increment Pr ogramming status

1 = AAI programming mode

0 = Byte-Program mode

7 BPL 1 = BP1, BP0 are read-only bits

0 = BP1, BP0 are read/writable 0R/W

T4.0 1250

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

Block Protection (BP1, BP0)

The Block-Protection (BP1, BP0) bits define the size of the

memory area, as defined in Table 5, to be software pro-

tected against any memory Write (Program or Erase)

operat ions. Th e Writ e-St atus- Regist er (WR SR) ins tru ction

is used to program the BP1 and BP0 bits as long as WP#

is high or the Block-Protect-Loc k (BPL) bit is 0. Chip-Erase

can only be executed if Block-Protection bits are both 0.

After po wer-up , BP1 and BP0 are set to 1.

Block Protection Lock-Down (BPL)

WP# pin driven low (VIL), enables the Block-Protection-

Loc k-Do wn (BPL) bit. Whe n BPL is se t to 1, i t pre v ents any

further alter a tio n o f th e BP L, BP1 , a nd BP0 bit s . Wh en th e

WP# pin is driven high (VIH), the BPL bit ha s no ef fect an d

its value is “Don’t Care”. After power-up, the BPL bit is

reset to 0.

Auto Address Increment (AAI)

The Auto Address Inc rement Program ming-Sta tus bit pro-

vides status on whe ther the device is in AAI programm ing

mode or Byte-Program mode. The default at power up is

Byte-P rogram mode .

TABLE 5: SOFTWARE STATUS REGISTER BLOCK PROTECTION1

1. Default at power-up for BP1 and BP0 is ‘11’.

Protection Level

Status

Bit Protected Memory Area

BP1 BP0 8 Mbit

000None

1 (1/4 Memory Array) 0 1 0C0000H-0FFFFFH

2 (1/2 Memory Array) 1 0 080000H-0FFFFFH

3 (Full Memory Array) 1 1 000000H-0FFFFFH

T5.0 1250

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

Instructions

Instructions are used to Read, Write ( Erase and Progr am),

and configure the SST25VF080. The instruction bus

cycles are 8 bits each f or commands (Op Code), data, and

addresses. Prior to executing any Byte-Program, Auto

Address Increment (AAI) programming, Sector-Erase,

Block-Erase, or Chip-Erase instructions, the Write-Enable

(WREN) instruction must be executed first. The complete

list of the instructions is provided in Table 6. All instructions

are synchronized off a high to low transition of CE#. Inputs

will be accepted on the rising edge of SCK starting wi th the

most significant bit. CE# must be driven low before an

instruction is entered and m ust be driven high after the last

bit of the instruction has been shifted in (except for Read,

Read-ID and Read-Status-Register instructions). Any low

to high transition on CE#, before receiving the last bit of an

instruction bus cycle, will terminate the instruction in

progress and return the device to the standby mode.

Instruction commands (Op Code), addresses, and data are

all input from the most significant bit (MSB) first.

TABLE 6: DEVICE OPERATION INSTRUCTIONS1

1. AMS = Most Significant Address

AMS = A19 for SST25VF080

Address bits above the most significant bit of each density can be VIL or VIH

Cycle Type/

Operation2,3

2. Operation: SIN = Serial In , S OUT = Serial Out

3. X = Dummy Input Cycles (VIL or VIH);

- = Non-Applicable Cycles (Cycles are not necessar y)

Bus Cycle4

4. One bus cycle is eight clock periods.

123456

SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT

Read 03H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z X DOUT

Sector-Erase5,6

5. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH

6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase , or Chip-Erase operation, the Write-Enable (WREN) instruction

must be executed.

20H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z - -

Block-Erase5,7

7. Block addresses for: use AMS-A15, remaining addresses can be VIL or VIH

52H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z - -

Chip-Erase660H Hi-Z - - - - - - - -

Byte-Program602H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z DIN Hi-Z

Auto Address Increment

(AAI) Single-Byte Program6,8

8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,

followed by the data to be programmed.

AFH Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z DIN Hi-Z

Read-Status-Register

(RDSR) 05H Hi-Z X DOUT -Note

9. The Read-Status-R egister is continuous with ongoing clock cycles until termina ted by a low to high transition on CE#.

-Note

9-Note

Enable-Write-Status-Register

(EWSR)10

10. The Enable-Writ e-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of

each other. The WRSR instruc tion must be executed immediately (very next bus cycle) after the EWSR instruction to make both

instructions effective.

50H Hi-Z - - - - - - - -

Write-Status-Register

(WRSR)10 01H Hi-Z Data Hi-Z - - -. - - -

Write-Enable (WREN) 06H H i-Z - - - - - - - -

Write-Disable (WRDI) 04H Hi-Z - - - - - - - -

Read-ID 90H or

ABH Hi-Z 00H Hi-Z 00H Hi-Z ID

Addr11

11. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer and Device

ID output stream is continuous until terminated by a low to high transition on CE#

Hi-Z X DOUT12

12. Device ID = 80H for SST25VF080

T6.0 1250

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

Read

The Read instruction supports up to 20 MHz, it outputs the

data starting from the specified address location. The data

output stream is continuous through all addresses until ter-

minated by a low to high transition on CE#. The internal

addres s pointer will auto matical ly increm ent unti l the hig h-

est memory address is reached. Once the highest memory

address is reached, the address pointer will automatically

increment to the beginning (wrap-around) of the address

space, i.e. for 8 Mbit density, once the data from address

location 0FFFFFH had been read, the next output will be

from address location 000000H.

The Read instruction is initiated by executing an 8-bit com-

mand, 03H, followed by address bits [A23-A0]. CE# must

remain active low for the duration of the Read cycle. See

Figu re 4 f or th e Read se quence .

FIGURE 4: READ SEQUENCE

1250 F04.0

CE#

SCK

ADD.

012345678

ADD. ADD.

HIGH IMPEDANCE

15 16 23 24 31 32 39 40 7047 48 55 56 63 64

N+2 N+3 N+4N N+1

DOUT

MSB MSB

MSB

MODE 0

MODE 3

DOUT DOUT DOUT DOUT

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

Byte-Program

The Byte-Program instruction programs the bits in the

selec ted byte to the desi red data. The selec ted byte must

be in the erased state (FFH) when initiating a Program

operation. A Byte-Program instruction applied to a pro-

tected memory area will be ignored.

Prior to any Write operation, the Write-Enable (WREN)

inst r uc ti on mus t b e executed. CE # must r em ai n ac ti ve low

for the duration o f the By te-Pr ogram inst r ucti on. Th e Byte-

Program instruct ion is init iated by executing an 8-bit com-

mand, 02H, f ollowed by address bits [A23-A0]. Following the

addr ess, the data is input in order from MSB (bit 7) to LSB

(bit 0). CE# must be driven high before the instruction is

executed. The user may poll the Busy bit in the software

status register or wait TBP f or the completion of the internal

self-timed Byte-Program operation. See Figure 5 for the

Byte-P rogram sequence.

FIGURE 5: BYTE-PROGRAM SEQUENCE

1250 F05.0

CE#

SCK

ADD.

012345678

ADD. ADD. DIN

HIGH IMPEDANCE

15 16 23 24 31 32 39

MODE 0

MODE 3

MSBMSB

MSB LSB

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

Auto Address Increment (AAI) Program

The AAI program instruction allows multiple bytes of data to

be programmed without re-issuing the next sequential

address location. This feature decreases total program-

ming time when the entire memory array is to be pro-

grammed. An AAI program instruction pointing to a

protected memory area will be ignored. The selected

address range must be in the er ased state (FFH) when ini-

tiating an AAI program instruction.

Prior to any write operation, the Write-Enable (WREN)

inst r u ct i on mus t be execu ted . T h e A AI pr o gram i ns tructio n

is initiated by executing an 8-bit command, AFH, followed

by address bits [A23-A0]. F ollowing the addresses, the data

is input sequentially from MSB (Bit 7) to LSB (Bit 0). CE#

must be dr iven high before the AA I program instruction is

exec ut ed. The user must poll the BUS Y bi t i n t he so ftwa re

statu s re gi ster or wait TBP for the comp le ti on o f ea ch in ter -

nal self-timed Byte-Program cycle. Once the device com-

pletes prog ramming byte, the next sequential address may

be program, enter the 8-bit command, AFH, f ollowed by the

data to be programmed. When the last desired byte had

been programmed, execute the Write-Disable (WRDI)

instruction, 04H, to terminate AAI. After execution of the

WRDI co mmand, the user must po ll the Status re gister to

ensure the device completes programming. See Figure 6

f or AAI programming sequence.

There is no wrap mode during AAI prog ramming; once the

highest unprotected memory address is reached, the

device will exit AAI operation and reset the Write-Enable-

Latch bit (WEL = 0).

FIGURE 6: AUTO ADDRESS INCREMENT (AAI) PROGRAM SEQUENCE

CE#

SCK

A[23:16] A[15:8] A[7:0]

AF Data Byte 1 AF Data Byte 2

CE#

SCK

Write Disable (WRDI)

Instruction to terminate

AAI Operation

Read Status Register (RDSR)

Instruction to verify end of

AAI Operation

04Last Data ByteAF 05

DOUT

MODE 3

MODE 0

TBP TBP

TBP

1250 F06.0

0 1 2 3 4 5 6 7 8 323334353637383915 16 23 24 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01

012345670123456789101112131415 0123456789101112131415

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

Sector-Erase

The Sector-Erase instruction clears all bits in the selected 4

KByte sector to FFH. A Sector-Erase instruction applied to

a protected memory area will be ignored. Prior to any Write

operation, the Write-Enable (WREN) instruction must be

executed. CE# must remain active low for the duration of

the any command sequence. The Sector-Erase instruction

is initiated by executing an 8-bit command, 20H, followed

by address bits [A23-A0]. Address bits [AMS-A12]

(AMS = Most Significant address) are used to determine the

sector address (SAX), remaining address bits can be VIL or

VIH. CE# must be driven high before th e ins tructio n i s exe-

cuted. The user may poll the Busy bit in the software status

timed Sector-Erase cycle. See Figure 7 for the Sector-

Erase sequence.

FIGURE 7: SECTOR-ERASE SEQUENCE

Block-Erase

The Block-Erase instruction clears all bits in the selected 32

KByte block to FFH. A Block-Erase instruction applied to a

protec ted memor y a rea will be ignored. Prior to any Write

operation, the Write-Enable (WREN) instruction must be

executed. CE# must remain active low for the duration of

any command sequence. The Block-Erase instruction is

init iated by executin g an 8-bit comman d, 52H, followed by

address bits [A23-A0]. Address bits [AMS-A15] (AMS = Most

significant address) are used to determine block address

(BAX), remaining address bits can be VIL or VIH. CE# m u s t

be driven high before the instruction is executed. The user

may poll the Busy bit in the soft ware s tatu s r eg is te r or wait

TBE for the completion of the internal self-timed Block-

Erase cycle. See Figure 8 f or the Block-Erase sequence.

FIGURE 8: BLOCK-ERASE SEQUENCE

CE#

SCK

ADD.

012345678

ADD. ADD.

HIGH IMPEDANCE

15 16 23 24 31

MODE 0

MODE 3

1250 F07.0

MSBMSB

CE#

SCK

ADD.

012345678

ADD. ADD.

HIGH IMPEDANCE

15 16 23 24 31

MODE 0

MODE 3

1250 F08.0

MSB MSB

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

Chip-Erase

The Chip-Erase instruction clears all bits in the device to

FFH. A Chip-Erase i nstr uctio n will be ignore d if any of th e

memory area is protected. Prior to any Write operation, the

Write-Enable (WREN) instruction must be executed. CE#

must remain active low for the duration of the Chip-Erase

instruction sequence. The Chip-Er ase instruction is initiated

by executing an 8 -b it c om ma nd, 6 0H. CE# must be driven

high before the instruction is executed. The user may poll

the Busy bit in the software status register or wait TCE for

the com pletion of the i nter nal self-t imed Chi p-Erase cycle.

See Figure 9 for the Chip-Erase sequence.

FIGURE 9: CHIP-ERASE SEQUENCE

Read-Status-Register (RDSR)

The Read- Status-Register (RDSR) ins truct ion all ows read-

ing of the status register . The status register may be read at

any time even during a Write (Program/Erase) operation.

When a Wri te oper ation is in prog ress , the Bu sy bit ma y be

checked before sending an y ne w commands to assure that

the new commands are properly received by the device.

CE# must be driven low before the RDSR instruction is

entered and remain low until the status data is read. Read-

Status-Register is continuous with ongoing clock cycles

until i t is terminated by a low t o hig h tran sition of th e C E#.

See Figure 10 for the RDSR instruction sequence.

FIGURE 10: READ-STATUS-REGISTER (RDSR) SEQUENCE

CE#

SCK

01234567

HIGH IMPEDANCE

MODE 0

MODE 3

1250 F09.0

MSB

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

1250 F10.0

MODE 3

SCK

CE#

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

HIGH IMPEDANCE

Status

MSB

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

Write-Enable (WREN)

The Write-Enable (WREN) instruction sets the Write-

Enable-Latch bit to 1 allowing Write operations to occur.

The WREN in struct ion m ust be exec uted prior to a ny Wri te

(Program/Erase) operation. CE# must be driven high

before the WREN instruction is ex ecuted.

FIGURE 11: WRITE ENABLE (WREN) SEQUENCE

Write-Disable (WRDI)

The Write-Disable (WRDI) instruction resets the Write-

Enable-La tch bit and AA I bit t o 0 disa bling any new Writ e

operations from occurring. CE# must be driven high before

the WRDI ins tructio n i s exec ute d.

FIGURE 12: WRITE DISABLE (WRDI) SEQUENCE

Enable-Write-Status-Register (EWSR)

The Enable-Write-Status-Register (EWSR) instruction

arms the Write-Status-Register (WRSR) instruction and

opens the status re gister for alteration. The Enable-Wr ite-

Status-Register instruction does not have any effect and

will be w a sted , if i t is not f o llo we d im medi atel y b y the Write-

Status-Register (WRSR) instruction. CE# must be driven

low before the EWSR instruction is entered and must be

driv en hi gh bef or e the EWSR instructio n is e x ec uted.

CE#

SCK

01234567

HIGH IMPEDANCE

MODE 0

MODE 3

1250 F11.0

MSB

CE#

SCK

01234567

HIGH IMPEDANCE

MODE 0

MODE 3

1250 F12.0

MSB

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

Write-Status-Register (WRSR)

The Wr ite- Status -Regis ter inst ruct ion wor ks in conjun ction

with the Enable-Write-Status-Register (EWSR) instruction

to write new values to the BP1, BP0, and BPL bits of the

status register. The Write-Status-Register instr uction must

be ex ecuted immediately after the e x ecution of the Enable-

Write-Status-Register instruction (ver y next instruction bus

cycle). This two-step instruction sequence of the EWSR

instruction followed by the WRSR instruction works like

SDP (software data prot ection) command structure which

prev ents any accidental alteration of the status register val-

ues. The Write-Status-Register instruction will be ignored

when WP# is low and BPL bit is set to “1”. When the WP#

is low, the BPL bit can only be set from “0” to “1” to lock-

down the status register , but cannot be reset fr om “1” to “0”.

When WP# is high, the lock-down function of the BPL bit is

dis ab led and the BPL, BP0, an d BP1 b its in the st atus reg-

ister can all be ch anged. As lo ng as BPL bit is se t to 0 or

WP# pin is driven high (VIH) prio r t o the low -to-h igh tran si-

tion of th e C E# pi n at th e e n d of t he W RSR in st ruc ti on, t he

BP0, BP1, and BPL bit in the status register can all be

altered by the WRSR instruction. In this case, a single

WRSR instr uction can set the BPL bit to “1” to lock down

the st atus re giste r as well as alter i ng the BP0 and B P1 bi t

at the same time. See Table 3 for a summary description of

WP# and BPL functions. CE# must be driven low before

the command sequence of the WRSR instruction is

entered and driven high before the WRSR instruction is

executed. See Figure 13 f or EWSR and WRSR instruction

sequences.

FIGURE 13: ENABLE-WRITE-STATUS-REGISTER (EWSR) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE

1250 F13.0

MODE 3

HIGH IMPEDANCE

MODE 0

STATUS

76543210

MSBMSBMSB

MODE 3

SCK

CE#

MODE 0

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

Read-ID

The Read-ID instruction identifies the devices as

SST25VF080 and manufacturer as SST. The device infor-

mation can be read from ex ecuting an 8-bit command, 90H

or ABH, followed by address bits [A23-A0]. Following the

Read-ID instruction, the manufacturer’s ID is located in

address 00000H and the device ID is located in address

00001H. O nce the device i s in Read-ID m ode, the manu-

facturer’s and device ID output data toggles between

addres s 0000 0H and 00001H until te rmi nated by a low to

high transition on CE#.

FIGURE 14: READ-ID SEQUENCE

1250 F14.0

CE#

SCK

012345678

00 ADD

90 or AB

HIGH IMPEDANCE

15 16 23 24 31 32 39 40 47 48 55 56 63

BF Device ID BF Device ID

Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.

Device ID = 80H for SST25VF080

1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.

HIGH

IMPEDANCE

MODE 3

MODE 0

MSB MSB

MSB

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

ELEC TRICA L SPECIFICATI ONS

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may caus e per manent d amage to the device. This is a stres s rating only and funct ional operatio n

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potentia l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V

Pac kage Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Cur rent1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Output shorted for no more than one second. No more than one output shor t ed at a time.

OPERATING RANGE

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 19 and 20

TABLE 7: DC OPERATING CHARACTERISTICS

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDDR Read Current 10 mA CE#=0.1 VDD/0.9 VDD@20 MHz, SO=open

IDDW Program and Erase Current 30 mA CE#=VDD

ISB Standby Current 15 µA CE#=VDD, VIN=VDD or VSS

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 0.7 VDD VV

DD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T7.0 1250

TABLE 8: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

VDD Min to Read Operation 10 µs

TPU-WRITE1VDD Min to Write Operation 10 µs

T8.0 1250

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

TABLE 9: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

COUT1Output Pin Capacitance VOUT = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T9.0 1250

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 10: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T10.0 1250

TABLE 11: AC OPERATING CHARACTERISTICS

Symbol Parameter Min Max Units

FCLK Serial Clock Frequency 20 MHz

TSCKH Serial Clock High Time 20 ns

TSCKL Serial Clock Low Time 20 ns

TCES1

1. Relative to SCK.

CE# Active Setup Time 20 ns

TCEH1CE# Active Hold Time 20 ns

TCHS1CE# Not Active Setup Time 10 ns

TCHH1CE# Not Active Hold Time 10 ns

TCPH CE# High Time 100 ns

TCHZ CE# High to High-Z Output 20 ns

TCLZ SCK Low to Low-Z Output 0 ns

TDS Data In Setup Time 5 ns

TDH Data In Hold Time 5 ns

THLS HOLD# Low Setup Time 10 ns

THHS HOLD# High Setup Time 10 ns

THLH HOLD# Low Hold Time 15 ns

THHH HOLD# High Hold Time 10 ns

THZ HOLD# Low to High-Z Output 20 ns

TLZ HOLD# High to Low-Z Output 20 ns

TOH Output Hold from SCK Change 0 ns

TVOutput Valid from SCK 20 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 100 ms

TBP Byte-Program 20 µs

T11.0 1250

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

FIGURE 15: SERIAL INPUT TIMING DIAGRAM

FIGURE 16: SERIAL OUTPUT TIMING DIAGRAM

HIGH-Z HIGH-Z

CE#

SCK

MSB LSB

TDS TDH

TCHH

TCES

TCEH TCHS

TSCKR

TSCKF

TCPH

1250 F15.0

1250 F16.0

CE#

SCK

MSB

TCLZ

TSCKH

TCHZ

TOH

TSCKL

LSB

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

FIGURE 17: HOLD TIMING DIAGRAM

FIGURE 18: POWER-UP TIMING DIAGRAM

THZ TLZ

THHH THLS

THLH

THHS

1250 F17.0

HOLD#

CE#

SCK

Time

Min

Max

Device fully accessible

PU-READ

PU-WRITE

Chip selection is not allowed.

All commands are rejected by the device.

1250 F18.0

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

FIGURE 19: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 20: A TEST LOAD EXAMPLE

1250 F19.0

REFERENCE POINTS OUTPUTINPUT

VHT

VLT

VHT

VLT

VIHT

VILT

A C test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement reference points

f or inputs and outputs are VHT (0.7VDD) and VLT (0.3VDD). Input rise and f all times (10% ↔ 90%) are <5 ns.

Note: VHT - VHIGH Test

VLT - VLOW Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1250 F20.0

TO TESTER

TO DUT

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

PRODUCT ORDERING INFORMATION

Valid combinations for SST25VF080

SST25VF080-20-4C-S2A

SST25VF080-20-4C-S2AE

SST25VF080-20-4I-S2A

SST25VF080-20-4I-S2AE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

SST 25 VF 080 - 33 - 4C - S2A E

XX XXXXXXX - XXX -XX-XXXX

Environmental Attribute

E = non-Pb

Package Modifier

A = 8 leads or contacts

Package Type

S2 = SOIC 200 mil body width

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Operating Frequency

20 = 20 MHz

Device Density

080 = 8 Mbit

Voltage

V = 2.7-3.6V

Product Seri es

25 = Serial Peripheral Interface flash memory

Advance Information

8 Mbit SPI Serial Flash

SST25VF080

PACKAGING DIAGRAMS

8-LEAD S MALL OUTLINE INTEGRATED CIRCUIT (SOIC) 200 MIL BODY WIDTH (5.2MM X 8MM)

SST PACKAGE CODE: S2A

TABLE 12: REVISION HISTORY

Number Description Date

00 •Initial release of data sheet Oct 2003

01 •2004 Data Book Dec 2003

08-soic-EIAJ-S2A-2

Note: 1. All linear dimensions are in millimeters (max/min).

2. Coplanarity: 0.1 mm

3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.

TOP VIEW SIDE VIEW

END VIEW

5.40

5.15

8.10

7.70

5.40

5.15

Pin #1

Identifier

0.50

0.35

1.27 BSC

0.25

0.05

2.20

1.75

0.25

0.19

0.80

0.50

0˚

8˚

1mm

Silicon Stor age Technology, Inc. • 1171 Sonora C ourt • Sunnyvale , CA 940 86 • Teleph one 408-73 5-91 10 • Fax 408-735-9036