Single-Phase Energy Measurement IC
with 8052 MCU, RTC, and LCD Driver
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B
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GENERAL FEATURES
Wide supply voltage operation: 2.4 V to 3.7 V
Internal bipolar switch between regulated and battery inputs
Ultralow power operation with power saving modes (PSM)
Full operation: 4 mA to 1.6 mA (PLL clock dependent)
Battery mode: 3.2 mA to 400 μA (PLL clock dependent)
Sleep mode
Real-time clock (RTC) mode: 1.5 μA
RTC and LCD mode: 38 μA (LCD charge pump enabled)
Reference: 1.2 V ± 0.1% (10 ppm/°C drift)
64-lead RoHS package options
Lead frame chip scale package (LFCSP)
Low profile quad flat package (LQFP)
Operating temperature range: −40°C to +85°C
ENERGY MEASUREMENT FEATURES
Proprietary analog-to-digital converters (ADCs) and digital
signal processing (DSP) provide high accuracy active
(watt), reactive (var), and apparent energy (volt-ampere
(VA)) measurement
<0.1% error on active energy over a dynamic range of
1000 to 1 @ 25°C
<0.5% error on reactive energy over a dynamic range of
1000 to 1 @ 25°C (ADE7169 and ADE7569 only)
<0.5% error on root mean square (rms) measurements
over a dynamic range of 500 to 1 for current (Irms) and
100 to 1 for voltage (Vrms) @ 25°C
Supports IEC 62053-21, IEC 62053-22, and IEC 62053-23;
EN 50470-3 Class A, Class B, and Class C; and ANSI C12-16
Differential input with programmable gain amplifiers (PGAs)
supports shunts, current transformers, and di/dt current
sensors (ADE7169 and ADE7569 only)
2 current inputs for antitamper detection in the
ADE7116/ADE7156/ADE7166/ADE7169
High frequency outputs proportional to Irms, active, reactive,
or apparent power (AP)
Table 1. Features Available on Each Part
Feature Part No.
Antitamper ADE7116, ADE7156, ADE7166, ADE7169
Watt, VA, Irms, Vrms ADE7116, ADE7156, ADE7166, ADE7169,
ADE7566, ADE7569
Var ADE7169, ADE7569
di/dt Sensor ADE7169, ADE7569
MICROPROCESSOR FEATURES
8052-based core
Single-cycle 4 MIPS 8052 core
8052-compatible instruction set
32.768 kHz external crystal with on-chip PLL
2 external interrupt sources
External reset pin
Low power battery mode
Wake-up from I/O, temperature change1, alarm, and
universal asynchronous receiver/transmitter (UART)
LCD driver operation
Temperature measurement
Real-time clock (RTC)
Counter for seconds, minutes, and hours
Automatic battery switchover for RTC backup
Operation down to 2.4 V
Ultralow battery supply current: 1.5 μA
Selectable output frequency: 1 Hz to 16 kHz
Embedded digital crystal frequency compensation for
calibration and temperature variation of 2 ppm resolution
Integrated LCD driver
108-segment driver for the ADE7566/ADE7569 and
104-segment driver for the ADE7116/ADE7156/
ADE7166/ADE7169
2×, 3×, or 4× multiplexing
LCD voltages generated internally2 or with external resistors
Internal adjustable drive voltages up to 5 V independent
of power supply level2
On-chip peripherals
UART interface
SPI or I2C
Watchdog timer
Power supply management with user-selectable levels
Memory: 16 kB flash memory, 512 bytes RAM
Development tools
Single-pin emulation
IDE-based assembly and C-source debugging
1 Not available in the ADE7116.
2 Not available in the ADE7116 or ADE7156.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 2 of 152
TABLE OF CONTENTS
General Features ............................................................................... 1
Energy Measurement Features ........................................................ 1
Microprocessor Features .................................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Functional Block Diagrams ............................................................. 4
Specifications ..................................................................................... 6
Energy Metering ........................................................................... 6
Analog Peripherals ....................................................................... 7
Digital Interface ............................................................................ 8
Timing Specifications ................................................................ 10
Absolute Maximum Ratings .......................................................... 15
Thermal Resistance .................................................................... 15
ESD Caution ................................................................................ 15
Pin Configurations and Function Descriptions ......................... 16
Typical Performance Characteristics ........................................... 22
Performance Curves for the ADE7169 and ADE7569 Only 25
Terminology .................................................................................... 26
Special Function Register (SFR) Mapping .................................. 27
Power Management ........................................................................ 29
Power Management Register Details ....................................... 29
Power Supply Architecture ........................................................ 32
Battery Switchover ...................................................................... 32
Power Supply Management (PSM) Interrupt ......................... 33
Using the Power Supply Features ............................................. 35
Operating Modes ............................................................................ 37
PSM0 (Normal Mode) ............................................................... 37
PSM1 (Battery Mode) ................................................................ 37
PSM2 (Sleep Mode) .................................................................... 37
3.3 V Peripherals and Wake-Up Events ................................... 38
Transitioning Between Operating Modes ............................... 39
Using the Power Management Features .................................. 39
Energy Measurement ..................................................................... 40
Access to Energy Measurement SFRs ...................................... 40
Access to Internal Energy Measurement Registers ................ 40
Energy Measurement Registers ................................................ 43
Energy Measurement Internal Register Details ..................... 44
Interrupt Status/Enable SFRs .................................................... 47
Analog Inputs .............................................................................. 49
Analog-to-Digital Conversion .................................................. 50
Fault Detection ........................................................................... 54
di/dt Current Sensor and Digital Integrator for the
ADE7169/ADE7569 ................................................................... 55
Power Quality Measurements ................................................... 57
Phase Compensation ................................................................. 59
RMS Calculation ........................................................................ 59
Active Power Calculation .......................................................... 62
Active Energy Calculation ........................................................ 64
Reactive Power Calculation (ADE7169/ADE7569) .............. 67
Reactive Energy Calculation (ADE7169/ADE7569) ............. 68
Apparent Power Calculation ..................................................... 72
Apparent Energy Calculation ................................................... 73
Ampere-Hour Accumulation ................................................... 74
Energy-to-Frequency Conversion............................................ 75
Energy Register Scaling ............................................................. 76
Energy Measurement Interrupts .............................................. 76
Temperature, Battery, and Supply Voltage Measurements........ 77
Temperature Measurement ....................................................... 79
Battery Measurement ................................................................. 79
External Voltage Measurement ................................................ 80
8052 MCU Core Architecture....................................................... 82
MCU Registers ............................................................................ 82
Basic 8052 Registers ................................................................... 84
Standard 8052 SFRs .................................................................... 85
Memory Overview ..................................................................... 85
Addressing Modes ...................................................................... 86
Instruction Set ............................................................................ 88
Read-Modify-Write Instructions ............................................. 90
Instructions That Affect Flags .................................................. 90
Dual Data Pointers ......................................................................... 92
Interrupt System ............................................................................. 93
Standard 8052 Interrupt Architecture ..................................... 93
Interrupt Architecture ............................................................... 93
Interrupt Registers...................................................................... 93
Interrupt Priority ........................................................................ 94
Interrupt Flags ............................................................................ 95
Interrupt Vectors ........................................................................ 97
Interrupt Latency ........................................................................ 97
Context Saving ............................................................................ 97
Watchdog Timer ............................................................................. 98
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 3 of 152
LCD Driver ................................................................................... 100
LCD Registers ........................................................................... 100
LCD Setup ................................................................................. 103
LCD Timing and Waveforms ................................................. 103
Blink Mode ................................................................................ 104
Display Element Control ......................................................... 104
Voltage Generation .................................................................. 105
LCD External Circuitry ........................................................... 106
LCD Function in PSM2 Mode ............................................... 106
Flash Memory ............................................................................... 108
Flash Memory Overview ......................................................... 108
Flash Memory Organization ................................................... 109
Using the Flash Memory ......................................................... 109
Protecting the Flash Memory ................................................. 113
In-Circuit Programming ......................................................... 114
Timers ............................................................................................ 115
Timer Registers ......................................................................... 115
Timer 0 and Timer 1 ................................................................ 117
Timer 2 ...................................................................................... 118
PLL ................................................................................................. 120
PLL Registers ............................................................................ 120
Real-Time Clock (RTC) .............................................................. 121
RTC SFRs .................................................................................. 121
Read and Write Operations .................................................... 124
RTC Modes ............................................................................... 124
RTC Interrupts ......................................................................... 124
RTC Calibration ........................................................................ 125
UART Serial Interface ................................................................... 126
UART SFRs ................................................................................ 126
UART Operation Modes .......................................................... 129
UART Baud Rate Generation .................................................. 130
UART Additional Features ...................................................... 132
Serial Peripheral Interface (SPI) .................................................. 133
SPI Registers .............................................................................. 133
SPI Pins ....................................................................................... 136
SPI Master Operating Modes .................................................. 137
SPI Interrupt and Status Flags ................................................. 138
I2C-Compatible Interface ............................................................. 139
Serial Clock Generation ........................................................... 139
Slave Addresses .......................................................................... 139
I2C Registers ............................................................................... 139
Read and Write Operations ..................................................... 140
I2C Receive and Transmit FIFOs ............................................. 141
I/O Ports ......................................................................................... 142
Parallel I/O ................................................................................. 142
I/O Registers .............................................................................. 143
Port 0 ........................................................................................... 146
Port 1 ........................................................................................... 146
Port 2 ........................................................................................... 146
Determining the Version of the Part .......................................... 147
Outline Dimensions ...................................................................... 148
Ordering Guide ......................................................................... 149
REVISION HISTORY
11/08—Rev. A to Rev. B
Added ADE7116/ADE7156 ......................................... Throughout
Changes to Table 1 ............................................................................ 1
Added Figure 2 .................................................................................. 5
Changes to Table 13 ........................................................................ 16
Added Figure 10 and Table 14; Renumbered Sequentially ........ 19
Added Exposed Pad Notation to Outline Dimensions ............148
Changes to Ordering Guide .........................................................149
12/07—Rev. 0 to Rev. A
Added ADE7166/ADE7169 .............................................. Universal
Changes to Table 1 ............................................................................ 1
Changes to Ordering Guide .........................................................144
11/07—Revision 0: Initial Version
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 4 of 152
GENERAL DESCRIPTION
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE75691 integrate the Analog Devices, Inc., energy (ADE)
metering IC analog front end and fixed function DSP solution
with an enhanced 8052 MCU core, an RTC, an LCD driver, and
all the peripherals to make an electronic energy meter with an
LCD display in a single part.
The ADE measurement core includes active, reactive, and apparent
energy calculations, as well as voltage and current rms measure-
ments. This information is accessible for energy billing by using
the built-in energy scalars. Many power line supervisory features
such as SAG, peak, and zero crossing are included in the energy
measurement DSP to simplify energy meter design.
The microprocessor functionality includes a single-cycle 8052
core, a real-time clock with a power supply backup pin, an SPI
or I2C® interface, and a UART interface. The ready-to-use infor-
mation from the ADE core reduces the program memory size
requirement, making it easy to integrate complicated design
into 16 kB of flash memory.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 also include a 108-/104-segment LCD driver. In the
ADE7166/ADE7169/ADE7566/ADE7569, this driver generates
voltages capable of driving LCDs up to 5 V.
1 Patents pending.
FUNCTIONAL BLOCK DIAGRAMS
IP
IN
VP
VN
REF
IN/OUT
ENERGY
MEASUREMENT
DSP
OSC
COM0
...
...
COM3
...
CF1
CF2
LDO
3V/5V LCD
CHARGE PUMP
SINGLE
CYCLE
8052
MCU
ADE7566/ADE7569
FP26
V
DCIN
VBAT
V
DD
V
SWOUT
V
INTD
V
INTA
RESET
DGND
AGND
TxD
UART
SERIAL
PORT
LCDVA
LCDVB
LCDVC
...
FP0
FP15
RTC
SS
SCLK
MISO
MOSI/SDATA
RxD
SDEN
T2
T2EX
T0
T1
LCDVP2
XTAL2
XTAL1
INT0
INT1
FP16
FP17
FP23
FP22
FP21
FP20
FP19
FP18
FP25
FP24
1.20V
REF
52
53
55
49
50
63
54
58
64 61
60 62 56 51 44 36 37 4647 48 45
5
FP28
FP27
2
1
6
7
8
9
10
11
12
13
14
20
35
1
4
15
17
18
16
57 43 42 39 38 7 638 39 40 41
59
PGA2
–
+
PGA1
–
+
ADC
ADC
TEMP
ADC
VDCIN
ADC
PROGRAM MEMORY
16kB FLASH
POWER SUPPLY
CONTROL AND
MONITORING
USER RAM
256 BYTES
USER XRAM
256 BYTES
TEMP
SENSOR
BATTERY
ADC
SPI/I2C
SERIAL
INTERFACE
3 × 16-BIT
COUNTER
TIMERS
108-SEGMENT
LCD DRIVER
WATCHDOG
TIMER
DOWNLOADER
DEBUGGER
PLL
1-PIN
EMULATOR
LDO
EA
UART
TIMER
POR
06353-001
44
14
13
12
45 11 43 42 41 40 39 38 37 36 5678910
P0.7/SS/T1
P0.6/SCLK/T0
P0.5/MISO
P0.4/MOSI/SDATA
P0.0 (BCTRL/INT1/P0.0)
P1.0/RxD
P1.1/TxD
P1.2/FP25
P1.3/T2EX/FP24
P1.6/FP21
P1.7/FP20
P1.4/T2/FP23
P1.5/FP22
P0.1/FP19
P0.2/CF1/RTCCAL
P0.3/CF2
P2.0/FP18
P2.1/FP17
P2.2/FP16
P2.3 (SDEN/P2.3)
Figure 1. ADE7566/ADE7569 Functional Block Diagram
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 5 of 152
ADC
I
PA
I
N
I
PB
REF
IN/OUT
ENERGY
MEASUREMENT
DSP
OSC
COM0
...
...
COM3
...
CF1
CF2
LDO
3V/5V LCD
CHARGE PUMP
SINGLE
CYCLE
8052
MCU
ADE7116/ADE7156/ADE7166/ADE7169
V
DCIN
V
BAT
V
DD
V
SWOUT
V
INTD
V
INTA
RESET
DGND
AGND
TxD
UART
SERIAL
PORT
LCDVA
LCDVB
LCDVC
...
FP0
FP15
RTC
SS
SCLK
MISO
MOSI/SDATA
RxD
SDEN
T2
T2EX
T0
T1
LCDVP1
LCDVP2
XTAL2
XTAL1
INT0
INT1
FP16
FP17
FP23
FP22
FP21
FP20
FP19
FP18
FP25
FP24
1.20V
REF
52
53
55
V
P
V
N
49
63
54
58
64 61
60 62 56 51 44 36 37 4647 48 45
5
6
7
8
9
10
11
12
13
14
20
35
1
4
15
17
18
16
19
57 43 42 39 38 7 638 39 40 41
59
PGA1
–
+
ADC
50
PGA2
–
+
PGA1
–
+
ADC
TEMP
ADC
VDCIN
ADC
PROGRAM MEMORY
16kB FLASH
POWER SUPPLY
CONTROL AND
MONITORING
USER RAM
256 BYTES
USER XRAM
256 BYTES
TEMP
SENSOR
BATTERY
ADC
SPI/I
2
C
SERIAL
INTERFACE
3 × 16-BIT
COUNTER
TIMERS
104-SEGMENT
LCD DRIVER
WATCHDOG
TIMER
DOWNLOADER
DEBUGGER
PLL
1-PIN
EMULATOR
LDO
EA
UART
TIMER
POR
06353-119
44
14
13
12
45 11 43 42 41 40 39 38 37 36 5678910
P0.7/SS/T1
P0.6/SCLK/T0
P0.5/MISO
P0.4/MOSI/SDATA
P0.0 (BCTRL/INT1/P0.0)
P1.0/RxD
P1.1/TxD
P1.2/FP25
P1.3/T2EX/FP24
P1.6/FP21
P1.7/FP20
P1.4/T2/FP23
P1.5/FP22
P0.1/FP19
P0.2/CF1/RTCCAL
P0.3/CF2
P2.0/FP18
P2.1/FP17
2
1
FP27
FP28
P2.2/FP16
P2.3 (SDEN/P2.3)
Figure 2. ADE7116/ADE7156/ADE7166/ADE7169 Functional Block Diagram
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 6 of 152
SPECIFICATIONS
VDD = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTALx = 32.768 kHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
ENERGY METERING
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
MEASUREMENT ACCURACY1
Phase Error Between Channels2
PF = 0.8 Capacitive ±0.05 Degrees Phase lead: 37°
PF = 0.5 Inductive ±0.05 Degrees Phase lag: 60°
Active Energy Measurement Error2 0.1 % of reading Over a dynamic range of 1000 to 1 at 25°C
AC Power Supply Rejection2
V
DD = 3.3 V + 100 mV rms/120 Hz
Output Frequency Variation 0.01 % IPx = VP = ±100 mV rms
DC Power Supply Rejection2
V
DD = 3.3 V ± 117 mV dc
Output Frequency Variation 0.01 %
Active Energy Measurement Bandwidth1
8 kHz
Reactive Energy Measurement Error2, 3
0.5 % of reading Over a dynamic range of 1000 to 1 at 25°C
Vrms Measurement Error2
0.5 % of reading Over a dynamic range of 100 to 1 at 25°C
Vrms Measurement Bandwidth1
3.9 kHz
Irms Measurement Error2
0.5 % of reading Over a dynamic range of 500 to 1 at 25°C
Irms Measurement Bandwidth1
3.9 kHz
ANALOG INPUTS
Maximum Signal Levels ±400 mV peak VP − VN differential input
ADE7566/ADE7569 ±400 mV peak IP − IN differential input
ADE7116/ADE7156/ADE7166/ADE7169 ±250 mV peak IPA − IN and IPB − IN differential inputs
Input Impedance (DC) 770 kΩ
ADC Offset Error2
±10 mV PGA1 = PGA2 = 1
±1 mV PGA1 = 16
Gain Error2
Current Channel ±3 % IPA = IPB = 0.4 V dc or IP = 0.4 V dc
Voltage Channel ±3 +3 % VP − VN = 0.4 V dc
Gain Error Match ±0.2 %
CF1 AND CF2 PULSE OUTPUT
Maximum Output Frequency 13.5 kHz VP − VN = 400 mV peak, IPA − IN = 250 mV,
PGA1 = 2 sine wave
Duty Cycle 50 % If CF1 or CF2 frequency, >5.55 Hz
Active High Pulse Width 90 ms If CF1 or CF2 frequency, <5.55 Hz
FAULT DETEC TION 4
Fault Detection Threshold
Inactive Input ≠ Active Input 6.25 % of active IPA or IPB active
Input Swap Threshold
Inactive Input > Active Input 6.25 % of active IPA or IPB active
Accuracy Fault Mode Operation
IPA Active, IPB = AGND 0.1 % of reading Over a dynamic range of 500 to 1
IPB Active, IPA = AGND 0.1 % of reading Over a dynamic range of 500 to 1
Fault Detection Delay 3 Seconds
Swap Delay 3 Seconds
1 These specifications are not production tested but are guaranteed by design and/or characterization data on production release.
2 See the Terminology section for definition.
3 This function is not available in the ADE7166 or ADE7566.
4 This function is not available in the ADE7566 or ADE7569.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 7 of 152
ANALOG PERIPHERALS
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
INTERNAL ADCs (BATTERY, TEMPERATURE, VDCIN)1
Power Supply Operating Range 2.4 3.7 V Measured on VSWOUT
No Missing Codes28 Bits
Conversion Delay3 38 μs
ADC Gain
VDCIN Measurement 15.3 mV/LSB
VBAT Measurement 14.6 mV/LSB
Temperature Measurement 0.78 °C/LSB
ADC Offset
VDCIN Measurement at 3 V 206 LSB
VBAT Measurement at 3.7 V 205 LSB
Temperature Measurement at 25°C 129 LSB
VDCIN Analog Input
Maximum Signal Levels 0 3.3 V
Input Impedance (DC) 1 MΩ
Low VDCIN Detection Threshold 1.09 1.2 1.27 V
POWER-ON RESET (POR)
VDD POR
Detection Threshold 2.5 2.95 V
POR Active Timeout Period 33 ms
VSWOUT POR
Detection Threshold 1.8 2.2 V
POR Active Timeout Period 20 ms
VINTD POR
Detection Threshold 2.0 2.25 V
POR Active Timeout Period 16 ms
VINTA POR
Detection Threshold 2.05 2.25 V
POR Active Timeout Period 120 ms
BATTERY SWITCHOVER
Voltage Operating Range (VSWOUT) 2.4 3.7 V
VDD to VBAT Switching
Switching Threshold (VDD) 2.5 2.95 V
Switching Delay 10 ns When VDD to VBAT switch activated by VDD
30 ms When VDD to VBAT switch activated by VDCIN
VBAT to VDD Switching
Switching Threshold (VDD) 2.5 2.95 V
Switching Delay 30 ms Based on VDD > 2.75 V
VSWOUT to VBAT Leakage Current 10 nA VBAT = 0 V, VSWOUT = 3.43 V, TA = 25°C
LCD, CHARGE PUMP ACTIVE4
Charge Pump Capacitance Between LCDVP1 and
LCDVP2
100 nF
LCDVA, LCDVB, LCDVC Decoupling Capacitance 470 nF
LCDVA 0 1.75 V
LCDVB 0 3.5 V 1/3 bias mode
LCDVC 0 5.3 V 1/3 bias mode
V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 μA
V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 μA
V3 Segment Line Voltage LCDVC − 0.1 LCDVC V Current on segment line = −2 μA
DC Voltage Across Segment and COMx Pin 50 mV LCDVC − LCDVB, LCDVC − LCDVA, or
LCDVB − LCDVA
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 8 of 152
Parameter Min Typ Max Unit Test Conditions/Comments
LCD, RESISTOR LADDER ACTIVE
Leakage Current ±20 nA 1/2 and 1/3 bias modes, no load
V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 μA
V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 μA
V3 Segment Line Voltage LCDVC − 0.1 LCDVC V Current on segment line = −2 μA
ON-CHIP REFERENCE
Reference Error ±0.9 mV TA = 25°C
Power Supply Rejection 80 dB
Temperature Coefficient2
10 50 ppm/°C
1 This function is not available in the ADE7116.
2 These specifications are not production tested but are guaranteed by design and/or characterization data on production release.
3 Delay between ADC conversion request and interrupt set.
4 This function is not available in the ADE7116 or ADE7156.
DIGITAL INTERFACE
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS1
All Inputs Except XTAL1, XTAL2, BCTRL,
INT0, INT1, RESET
Input High Voltage, VINH 2.0 V
Input Low Voltage, VINL 0.8 V
BCTRL, INT0, INT1, RESET
Input High Voltage, VINH 1.3 V
Input Low Voltage, VINL 0.8 V
Input Currents
RESET 100 nA
RESET = VSWOUT = 3.3 V
Port 0, Port 1, Port 2 ±100 nA Internal pull-up disabled, input = 0 V or VSWOUT
−3.75 −8.5 μA Internal pull-up enabled, input = 0 V, VSWOUT = 3.3 V
Input Capacitance 10 pF All digital inputs
FLASH MEMORY
Endurance220,000 Cycles
Data Retention320 Years TJ = 85°C
CRYSTAL OSCILLATOR4
Crystal Equivalent Series Resistance 30 50 kΩ
Crystal Frequency 32 32.768 33.5 kHz
XTAL1 Input Capacitance 12 pF
XTAL2 Output Capacitance 12 pF
MCU CLOCK RATE (fCORE) 4.096 MHz Crystal = 32.768 kHz and CD bits = 000
32 kHz Crystal = 32.768 kHz and CD bits = 111
LOGIC OUTPUTS
Output High Voltage, VOH 2.4 V VDD = 3.3 V ± 5%
ISOURCE 80 μA
Output Low Voltage, VOL5 0.4 V VDD = 3.3 V ± 5%
ISINK 2 mA
START-UP TIME6
PSM0 Power-On Time 880 ms VDD at 2.75 V to PSM0 code execution
From Power Saving Mode 1 (PSM1)
PSM1 to PSM0 130 ms VDD at 2.75 V to PSM0 code execution
From Power Saving Mode 2 (PSM2)
PSM2 to PSM1 48 ms Wake-up event to PSM1 code execution
PSM2 to PSM0 186 ms VDD at 2.75 V to PSM0 code execution
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 9 of 152
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY INPUTS
VDD 3.13 3.3 3.46 V
VBAT 2.4 3.3 3.7 V
INTERNAL POWER SUPPLY SWITCH (VSWOUT)
VBAT to VSWOUT On Resistance 22 Ω VBAT = 2.4 V
VDD to VSWOUT On Resistance 10.2 Ω VDD = 3.13 V
VBAT to/from VDD Switching Open Time 40 ns
BCTRL State Change and Switch Delay 18 μs
VSWOUT Output Current Drive 6 mA
POWER SUPPLY OUTPUTS
VINTA 2.3 2.70 V
VINTD 2.3 2.70 V
VINTA Power Supply Rejection 60 dB
VINTD Power Supply Rejection 50 dB
POWER SUPPLY CURRENTS
Current in Normal Mode (PSM0) 4 5.3 mA fCORE = 4.096 MHz, LCD and meter active
2.1 mA fCORE = 1.024 MHz, LCD and meter active
1.6 mA fCORE = 32.768 kHz, LCD and meter active
3 3.9 mA
fCORE = 4.096 MHz, metering ADC and DSP powered
down
Current in PSM1 3.2 5.05 mA fCORE = 4.096 MHz, LCD active, VBAT = 3.7 V
880 μA fCORE = 1.024 MHz, LCD active
Current in PSM2 38 μA LCD active with charge pump at 3.3 V + RTC, VBAT = 3.3 V
1.5 μA RTC only, TA = 25°C, VBAT = 3.3 V
1 Specifications guaranteed by design.
2 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
3 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
4 Recommended crystal specifications.
5 Test carried out with all the I/Os set to a low output level.
6 Delay between power supply valid and execution of first instruction by 8052 core.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 10 of 152
TIMING SPECIFICATIONS
AC inputs during testing were driven at VSWOUT − 0.5 V for Logic 1
and at 0.45 V for Logic 0. Timing measurements were made at VIH
minimum for Logic 1 and at VIL maximum for Logic 0, as shown in
Figure 3.
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs. A port pin begins to
float when a 100 mV change from the loaded VOH/VOL level
occurs, as shown in Figure 3.
CLOAD for all outputs is equal to 80 pF, unless otherwise noted.
VDD = 2.7 V to 3.6 V; all specifications TMIN to TMAX, unless
otherwise noted.
VSWOUT – 0.5V
0.45V
0.2VSWOUT + 0.9V
TEST POINTS
0.2VSWOUT – 0.1V
VLOAD – 0.1V
VLOAD
VLOAD + 0.1V
TIMING
REFERENCE
POINTS
VLOAD – 0.1V
VLOAD
VLOAD – 0.1V
06353-002
Figure 3. Timing Waveform Characteristics
Table 5. Clock Input (External Clock Driven XTAL1) Parameter
32.768 kHz External Crystal
Parameter Description Min Typ Max Unit
tCK XTAL1 period 30.52 μs
tCKL XTAL1 width low 6.26 μs
tCKH XTAL1 width high 6.26 μs
tCKR XTAL1 rise time 9 ns
tCKF XTAL1 fall time 9 ns
1/tCORE Core clock frequency1 1.024 MHz
1 The internal PLL locks onto a multiple (512×) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system. The core can
operate at this frequency or at a binary submultiple defined by the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26).
Table 6. I2C-Compatible Interface Timing Parameters (400 kHz)
Parameter Description Typ Unit
tBUF Bus-free time between stop condition and start condition 1.3 μs
tL SCLK low pulse width 1.36 μs
tH SCLK high pulse width 1.14 μs
tSHD Start condition hold time 251.35 μs
tDSU Data setup time 740 ns
tDHD Data hold time 400 ns
tRSU Setup time for repeated start 12.5 ns
tPSU Stop condition setup time 400 ns
tR Rise time of both SCLK and SDATA 200 ns
tF Fall time of both SCLK and SDATA 300 ns
tSUP1Pulse width of spike suppressed 50 ns
1 Input filtering on both the SCLK and SDATA inputs suppresses noise spikes of <50 ns.
MSB
tBUF
SDATA (I/O)
SCLK (I)
STOP
CONDITION
START
CONDITION
REPEATED
START
LSB ACK MSB
12TO 7 89 1
S(R)
PS
tPSU
tDSU
tSHD
tDHD
tSUP
tDSU tDHD
tH
tSUP
tL
tRSU tR
tR
tF
tF
06353-003
Figure 4. I2C-Compatible Interface Timing
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 11 of 152
Table 7. SPI Master Mode Timing (SPICPHA = 1) Parameters
Parameter Description Min Typ Max Unit
tSL SCLK low pulse width 2SPIR × tCORE 1 ns
tSH SCLK high pulse width 2SPIR × tCORE1
ns
tDAV Data output valid after SCLK edge 3 × tCORE1
ns
tDSU Data input setup time before SCLK edge 0 ns
tDHD Data input hold time after SCLK edge tCORE1
ns
tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
tSF SCLK fall time 19 ns
1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz.
SCLK
(SPICPOL = 0)
tDSU
SCLK
(SPICPOL = 1)
MOSI
MISO
MSB LSB
LSB IN
BITS [6:1]
BITS [6:1]
tDHD
tDR
tDAV tDF
tSH tSL
tSR tSF
MSB IN
06353-004
Figure 5. SPI Master Mode Timing (SPICPHA = 1)
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 12 of 152
Table 8. SPI Master Mode Timing (SPICPHA = 0) Parameters
Parameter Description Min Typ Max Unit
tSL SCLK low pulse width 2SPIR × tCORE 1(SPIR + 1) × tCORE1
ns
tSH SCLK high pulse width 2SPIR × tCORE1
(SPIR + 1) × tCORE1 ns
tDAV Data output valid after SCLK edge 3 × tCORE1
ns
tDOSU Data output setup before SCLK edge 75 ns
tDSU Data input setup time before SCLK edge 0 ns
tDHD Data input hold time after SCLK edge tCORE1
ns
tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
tSF SCLK fall time 19 ns
1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz.
SCLK
(SPICPOL = 0)
t
DSU
SCLK
(SPICPOL = 1)
MOSI
MISO
MSB LSB
LSB IN
BITS [6:1]
BITS [6:1]
t
DHD
t
DR
t
DAV
t
DF
t
DOSU
t
SH
t
SL
t
SR
t
SF
MSB IN
0
6353-005
Figure 6. SPI Master Mode Timing (SPICPHA = 0)
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 13 of 152
Table 9. SPI Slave Mode Timing (SPICPHA = 1) Parameters
Parameter Description Min Typ Max Unit
tSS SS to SCLK edge 145 ns
tSL SCLK low pulse width 6 × tCORE 1 ns
tSH SCLK high pulse width 6 × tCORE1
ns
tDAV Data output valid after SCLK edge 25 ns
tDSU Data input setup time before SCLK edge 0 ns
tDHD Data input hold time after SCLK edge 2 × tCORE1 + 0.5 μs μs
tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
tSF SCLK fall time 19 ns
tSFS SS high after SCLK edge 0 ns
1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz.
MSB
MOSI
BITS
[6:1]
t
DHD
t
DSU
MSB IN LSB IN
BITS
[6:1]
LSB
t
DR
t
DF
t
DAV
MISO
tSL
tSH
tSR tSF
tSFS
tSS
SCLK
(SPICPOL = 1)
SCLK
(SPICPOL = 0)
SS
06353-006
Figure 7. SPI Slave Mode Timing (SPICPHA = 1)
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 14 of 152
Table 10. SPI Slave Mode Timing (SPICPHA = 0) Parameters
Parameter Description Min Typ Max Unit
tSS SS to SCLK edge 145 ns
tSL SCLK low pulse width 6 × tCORE 1 ns
tSH SCLK high pulse width 6 × tCORE1
ns
tDAV Data output valid after SCLK edge 25 ns
tDSU Data input setup time before SCLK edge 0 ns
tDHD Data input hold time after SCLK edge 2 × tCORE1+ 0.5 μs μs
tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
tSF SCLK fall time 19 ns
tDOSS Data output valid after SS edge 0 ns
tSFS SS high after SCLK edge 0 ns
1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz.
MSB
MOSI BITS [6:1]
t
DHD
t
DSU
LSB IN
BITS [6:1] LSB
t
DR
t
DF
t
DAV
MISO
t
SR
t
SF
t
SFS
t
SS
SCLK
(SPICPOL = 1)
SCLK
(SPICPOL = 0)
SS
t
SH
t
SL
t
DOSS
MSB IN
06353-007
Figure 8. SPI Slave Mode Timing (SPICPHA = 0)
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 15 of 152
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 11.
Parameter Rating
VDD to DGND −0.3 V to +3.7 V
VBAT to DGND −0.3 V to +3.7 V
VDCIN to DGND −0.3 V to VSWOUT + 0.3 V
Input LCD Voltage to AGND, LCDVA,
LCDVB, LCDVC1
−0.3 V to VSWOUT + 0.3 V
Analog Input Voltage to AGND, VP, VN,
IP, IPA, IPB, and IN
−2 V to +2 V
Digital Input Voltage to DGND −0.3 V to VSWOUT + 0.3 V
Digital Output Voltage to DGND −0.3 V to VSWOUT + 0.3 V
Operating Temperature Range
(Industrial)
−40°C to +85°C
Storage Temperature Range −65°C to +150°C
64-Lead LQFP, Power Dissipation
Lead Temperature (Soldering, 30 sec) 300°C
1 When used with external resistor divider.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 12. Thermal Resistance
Package Type θJA θ
JC Unit
64-Lead LQFP 60 20.5 °C/W
64-Lead LFCSP 27.1 2.3 °C/W
ESD CAUTION
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 16 of 152
COM2/FP28
COM1
COM0
P1.4/T2/FP23
P1.3/T2EX/FP24
P1.2/FP25
COM3/FP27
P1.5/FP22
P1.6/FP21
P1.7/FP20
P2.0/FP18
P2.1/FP17
P2.2/FP16
LCDVC
LCDVP2
P0.1/FP19
LCDVB
LCDVA
LCDVP1
FP15
FP14
FP13
FP12
FP11
FP10
FP9
FP8
FP7
FP6
FP5
FP4
FP3
ADE7566/ADE7569
VDCIN
DGND
VINTD
VSWOUT
VDD
VINTA
VBAT
REFIN/OU
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
T
FP26
AGND
IN
IP
VN
VP
RESET
EA
XTAL1
XTAL2
P0.3/CF2
P0.2/CF1/RTCCAL
P0.4/MOSI/SDATA
P0.5/MISO
P0.6/SCLK/T0
P1.0/RxD
P1.1/TxD
FP0
FP1
FP2
INT0
PIN 1
INDICATOR
BCTRL/INT1/P0.0
SDEN/P2.3
P0.7/SS/T1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP BE
CONNECTED TO THE GROUND PLANE ON THE BOARD.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
TOP VIEW
(Not to Scale)
06353-120
Figure 9. Pin Configuration for the ADE7566/ADE7569
Table 13. Pin Function Descriptions
Pin No. Mnemonic Description
1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane.
2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane.
3 COM1 Common Output 1. COM1 is used for the LCD backplane.
4 COM0 Common Output 0. COM0 is used for the LCD backplane.
5 P1.2/FP25 General-Purpose Digital I/O Port 1.2/LCD Segment Output 25.
6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24.
7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23.
8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22.
9 P1.6/FP21 General-Purpose Digital I/O Port 1.6/LCD Segment Output 21.
10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20.
11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19.
12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18.
13 P2.1/FP17 General-Purpose Digital I/O Port 2.1/LCD Segment Output 17.
14 P2.2/FP16 General-Purpose Digital I/O Port 2.2/LCD Segment Output 16.
15 LCDVC This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when
the LCD charge pump is enabled. When this pin is an analog output, it should be decoupled with a 470 nF
capacitor. When this pin is an analog input, it is internally connected to VDD. A resistor should be connected
between this pin and LCDVB to generate the two highest voltages for the LCD waveforms (see the LCD
Driver section).
16 LCDVP2 This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when
the LCD charge pump is enabled. When this pin is an analog output, a 100 nF capacitor should be connected
between this pin and LCDVP1. When this pin is an analog input, it is internally connected to LCDVP1 (see the
LCD Driver section).
17 LCDVB This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when
the LCD charge pump is enabled. When this pin is an analog output, it should be decoupled with a 470 nF
capacitor. When this pin is an analog input, a resistor should be connected between this pin and LCDVC to
generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be
connected between this pin and LCDVA to generate another intermediate voltage. In 1/2 bias LCD mode,
LCDVB and LCDVA are internally connected (see the LCD Driver section).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 17 of 152
Pin No. Mnemonic Description
18 LCDVA This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the
LCD charge pump is enabled. When this pin is an analog output, it should be decoupled with a 470 nF
capacitor. When this pin is an analog input, a resistor should be connected between this pin and LCDVP1
to generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be
connected between this pin and LCDVB to generate another intermediate voltage. In 1/2 bias LCD mode,
LCDVA and LCDVB are internally connected (see the LCD Driver section).
19 LCDVP1 This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the
LCD charge pump is enabled. When this pin is an analog output, a 100 nF capacitor should be connected
between this pin and LCDVP2. When this pin is an analog input, a resistor should be connected between this
pin and LCDVA to generate an intermediate voltage for the LCD driver. Another resistor must be connected
between LCDVP1 and DGND to generate another intermediate voltage (see the LCD Driver section).
20 to 35 FP15 to FP0 LCD Segment Output 15 to LCD Segment Output 0.
36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous).
37 P1.0/RxD General-Purpose Digital I/O Port 1.0/Receiver Data Input (Asynchronous).
38 P0.7/SS/T1 General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input.
39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input.
40 P0.5/MISO General-Purpose Digital I/O Port 0.5/Data Input for SPI Port.
41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line.
42 P0.3/CF2 General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, Irms, or apparent power information.
43 P0.2/CF1/RTCCAL
General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1/RTC Calibration Frequency Logic
Output. The CF1 logic output gives instantaneous active, reactive, Irms, or apparent information. The RTCCAL
logic output gives access to the calibrated RTC output.
44 SDEN/P2.3 Serial Download Mode Enable/General-Purpose Digital I/O Port 2.3. This pin is used to enable serial
download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily
becomes an input, and the status of the pin is sampled. If there is no pull-down resistor in place, the pin
momentarily goes high and then user code is executed. If the pin is pulled down on reset, the embedded
serial download/debug kernel executes, and this pin remains low during the internal program execution.
After reset, this pin can be used as a digital output port pin (P2.3).
45 BCTRL/INT1/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic
input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left
open, the connection between VDD or VBAT and VSWOUT is selected internally.
46 XTAL2 A crystal can be connected across this pin and XTAL1 to provide a clock source for the ADE7566/ADE7569.
The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate oscillator
circuit. An internal 6 pF capacitor is connected to this pin.
47 XTAL1 An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected
across XTAL1 and XTAL2 to provide a clock source for the ADE7566/ADE7569. The clock frequency for
specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin.
48 INT0 External Interrupt Input 0.
49, 50 VP, VN Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±400 mV for specified operation. This channel also has an internal PGA.
51 EA This pin is used as an input for emulation. When held high, this input enables the device to fetch code from
internal program memory locations. The ADE7566/ADE7569 do not support external code memory. This pin
should not be left floating.
52, 53 IP, IN Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±400 mV for specified operation. This channel also has an internal PGA.
54 AGND This pin provides the ground reference for the analog circuitry.
55 FP26 LCD Segment Output 26.
56 RESET Reset Input, Active Low.
57 REFIN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
1.2 V ± 0.1% and a maximum temperature coefficient of 50 ppm/°C. This pin should be decoupled with a 1
μF capacitor in parallel with a ceramic 100 nF capacitor.
58 VBAT Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to VDD when
the battery is selected as the power supply for the ADE7566/ADE7569.
59 VINTA This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 18 of 152
Pin No. Mnemonic Description
60 VDD 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is
selected as the power supply for the ADE7566/ADE7569. This pin should be decoupled with a 10 μF capacitor
in parallel with a ceramic 100 nF capacitor.
61 VSWOUT 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the
ADE7566/ADE7569. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF
capacitor.
62 VINTD This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
63 DGND Ground Reference for Digital Circuitry.
64 VDCIN Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to
AGND. This pin is used to monitor the preregulated dc voltage.
EP Exposed Pad The exposed pad on the bottom of the LFCSP enhances thermal performance and is electrically connected
to ground inside the package. It is recommended that the exposed pad be connected to the ground plane
on the board.
ADE7169/ADE7566/ADE7569ADE7116/ADE7156/ADE7166/
Rev. B | Page 19 of 152
LCDV
LCD
LCDV
FP
FP
FP
FP
FP
FP
COM2/FP28
COM1
COM0
P1.4/T2/FP23
P1.3/T2EX/FP24
P1.2/FP25
COM3/FP27
P1.5/FP22
P1.6/FP21
P1.7/FP20
P2.0/FP18
P2.1/FP17
P2.2/FP16
LCDVC
LCDVP2
P0.1/FP19
B
VA
P1
15
14
13
12
11
10
FP9
FP8
FP7
FP6
FP5
FP4
FP3
ADE7116/ADE7156/
ADE7166/ADE7169
VDCIN
DGND
VINTD
VSWOUT
VDD
VINTA
VBAT
REFIN/OUT
IPB
AGND
IN
IPA
VN
VP
RESET
EA
XTAL1
XTAL2
P0.3/CF2
P0.2/CF1/RTCCAL
P0.4/MOSI/SDATA
P0.5/MISO
P0.6/SCLK/T0
P1.0/RxD
P1.1/TxD
FP0
FP1
FP2
INT0
BCTRL/INT1/P0.0
SDEN/P2.3
P0.7/SS/T1
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP BE
CONNECTED TO THE GROUND PLANE ON THE BOARD.
TOP VIEW
(Not to Scale)
06353-120
Figure 10. Pin Configuration for the ADE7116/ADE7156/ADE7166/ADE7169
Table 14. Pin Function Descriptions
Pin No. Mnemonic Description
1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane.
2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane.
3 COM1 Common Output 1. COM1 is used for the LCD backplane.
4 COM0 Common Output 0. COM0 is used for the LCD backplane.
5 P1.2/FP25 General-Purpose Digital I/O Port 1.2/LCD Segment Output 25.
6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24.
7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23.
8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22.
9 P1.6/FP21 General-Purpose Digital I/O Port 1.6/LCD Segment Output 21.
10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20.
11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19.
12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18.
13 P2.1/FP17 General-Purpose Digital I/O Port 2.1/LCD Segment Output 17.
14 P2.2/FP16 General-Purpose Digital I/O Port 2.2/LCD Segment Output 16.
15 LCDVC In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or
an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an
analog input. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this
pin is an analog input, it is internally connected to VDD. A resistor should be connected between this pin and
LCDVB to generate the two highest voltages for the LCD waveforms (see the LCD Driver section).
16 LCDVP2 In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or
an analog output when the LCD charge pump is enabled. In the ADE7116 and ADE7156, this pin is always an
analog input. When this pin is an analog output, a 100 nF capacitor should be connected between this pin and
LCDVP1. When this pin is an analog input, it is internally connected to LCDVP1 (see the LCD Driver section).
17 LCDVB In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or
an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an
analog input. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this
pin is an analog input, a resistor should be connected between this pin and LCDVC to generate an
intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between
this pin and LCDVA to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVB and LCDVA are
internally connected (see the LCD Driver section).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 20 of 152
Pin No. Mnemonic Description
18 LCDVA In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or
an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an
analog input. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this
pin is an analog input, a resistor should be connected between this pin and LCDVP1 to generate an inter-
mediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this
pin and LCDVB to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVA and LCDVB are
internally connected (see the LCD Driver section).
19 LCDVP1 In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or
an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an
analog input. When this pin is an analog output, a 100 nF capacitor should be connected between this pin and
LCDVP2. When this pin is an analog input, a resistor should be connected between this pin and LCDVA to
generate an intermediate voltage for the LCD driver. Another resistor must be connected between LCDVP1
and DGND to generate another intermediate voltage (see the LCD Driver section).
20 to 35 FP15 to FP0 LCD Segment Output 0 to LCD Segment Output 15.
36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous).
37 P1.0/RxD General-Purpose Digital I/O Port 1.0/Receiver Data Input (Asynchronous).
38 P0.7/SS/T1 General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input.
39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input.
40 P0.5/MISO General-Purpose Digital I/O Port 0.5/Data Input for SPI Port.
41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line.
42 P0.3/CF2 General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, Irms, or apparent power information.
43 P0.2/CF1/RTCCAL
General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1/RTC Calibration Frequency Logic
Output. The CF1 logic output gives instantaneous active, reactive, Irms, or apparent power information. The
RTCCAL logic output gives access to the calibrated RTC output.
44 SDEN/P2.3 Serial Download Mode Enable/General-Purpose Digital I/O Port 2.3. This pin is used to enable serial
download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily
becomes an input, and the status of the pin is sampled. If there is no pull-down resistor in place, the pin
momentarily goes high and then user code is executed. If the pin is pulled down on reset, the embedded
serial download/debug kernel executes, and this pin remains low during the internal program execution.
After reset, this pin can be used as a digital output port pin (P2.3).
45 BCTRL/INT1/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic
input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left
open, the connection between VDD or VBAT and VSWOUT is selected internally.
46 XTAL2 A crystal can be connected across this pin and XTAL1 to provide a clock source for the ADE7116/ADE7156/
ADE7166/ADE7169. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or
by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin.
47 XTAL1 An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected
across XTAL1 and XTAL2 to provide a clock source for the ADE7116/ADE7156/ADE7166/ADE7169. The clock
frequency for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin.
48 INT0 External Interrupt Input 0.
49, 50 VP, VN Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±400 mV for specified operation. This channel also has an internal PGA.
51 EA This pin is used as an input for emulation. When held high, this input enables the device to fetch code from
internal program memory locations. The ADE7116/ADE7156/ADE7166/ADE7169 do not support external
code memory. This pin should not be left floating.
52, 53 IPA, IN Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±400 mV for specified operation. This channel also has an internal PGA.
54 AGND This pin provides the ground reference for the analog circuitry.
55 IPB Analog Input for Second Current Channel (IPB). This input is fully differential with a maximum differential
level of ±400 mV, referred to IN for specified operation. This channel also has an internal PGA.
56 RESET Reset Input, Active Low.
57 REFIN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
1.2 V ± 0.1% and a maximum temperature coefficient of 50 ppm/°C. This pin should be decoupled with a 1
μF capacitor in parallel with a ceramic 100 nF capacitor.
58 VBAT Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to VDD when
the battery is selected as the power supply for the ADE7116/ADE7156/ADE7166/ADE7169.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 21 of 152
Pin No. Mnemonic Description
59 VINTA This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
60 VDD 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is
selected as the power supply for the ADE7116/ADE7156/ADE7166/ADE7169. This pin should be decoupled
with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
61 VSWOUT 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the
ADE7116/ADE7156/ADE7166/ADE7169. This pin should be decoupled with a 10 μF capacitor in parallel with
a ceramic 100 nF capacitor.
62 VINTD This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
63 DGND Ground Reference for Digital Circuitry.
64 VDCIN Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to
AGND. This pin is used to monitor the preregulated dc voltage.
EP Exposed Pad The exposed pad on the bottom of the LFCSP enhances thermal performance and is electrically connected
to ground inside the package. It is recommended that the exposed pad be connected to the ground plane
on the board.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 22 of 152
TYPICAL PERFORMANCE CHARACTERISTICS
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–40°C; PF = 1
+25°C; PF = 1 +85°C; PF = 1
MID CLASS C
MID CLASS C
0.1 1 10 100
06353-107
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 1 10 100
06353-115
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE
+85°C; PF = 0.866
+25°C; PF = 0.866
–40°C; PF = 0.866
+85°C; PF = 0
+25°C; PF = 0
–40°C; PF = 0
Figure 11. Active Energy Error as a Percentage of Reading (Gain = 1)
over Temperature with Internal Reference, Integrator Off
Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = 1)
over Power Factor with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–40°C; PF = 1
+25°C; PF = 1 +85°C; PF = 1
MID CLASS C
MID CLASS C
0.1 1 10 100
06353-109
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0.1 1 10 100
06353-108
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
MID CLASS C
MID CLASS C
+25°C; PF = 1
+85°C; PF = 1
–40°C; PF = 1
+25°C; PF = 0.5
+85°C; PF = 0.5
–40°C; PF = 0.5
Figure 12. Active Energy Error as a Percentage of Reading (Gain = 1)
over Power Factor with Internal Reference, Integrator Off
Figure 15. Current RMS Error as a Percentage of Reading (Gain = 1)
over Temperature with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–40°C; PF = 1
–40°C; PF = 0.5
+25°C; PF = 1
+25°C; PF = 0.5 +85°C; PF = 0.5
+85°C; PF = 1
MID CLASS C
MID CLASS C
0.1 1 10 100
06353-110
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 1 10 100
06353-114
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE
+85°C; PF = 0
+25°C; PF = 0
–40°C; PF = 0
Figure 16. Current RMS Error as a Percentage of Reading (Gain = 1)
over Power Factor with Internal Reference, Integrator Off
Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = 1)
over Temperature with Internal Reference, Integrator Off
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 23 of 152
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.1 1 10 100
06353-111
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE
V
rms
; 3.3V
I
rms
; 3.13V
I
rms
; 3.3V
I
rms
; 3.43V V
rms
; 3.13V
V
rms
; 3.43V
Figure 17. Voltage and Current RMS Error as a Percentage of Reading (Gain = 1)
over Power Supply with Internal Reference, Integrator Off
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
40 45 50 55 60 65 70
PF = 1
PF = 0.5
MID CLASS B
MID CLASS B
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE
06353-112
LINE FREQUENCY (Hz)
ERROR (% of Reading)
Figure 18. Active Energy Error as a Percentage of Reading (Gain = 1)
over Frequency with Internal Reference, Integrator Off
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.1 1 10 100
06353-113
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE
VAR; 3.3V
W; 3.43V
W; 3.13V
W; 3.3V
VAR; 3.43V
VAR; 3.13V
Figure 19. Active and Reactive Energy Error as a Percentage of Reading
(Gain = 1) over Power Supply with Internal Reference, Integrator Off
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0.1 1 10 100
PF = +0.5
PF = 1 PF = –0.5
MID CLASS C
MID CLASS C
06353-094
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 8
INTEGRATOR OFF
INTERNAL REFERENCE
Figure 20. Active Energy Error as a Percentage of Reading (Gain = 8)
over Power Factor with Internal Reference, Integrator Off
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
PF = +0.5
PF = –0.5
–1.0
1.0
0.1 1 10 100
06353-095
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 8
INTEGRATOR OFF
INTERNAL REFERENCE
PF = 1
Figure 21. Reactive Energy Error as a Percentage of Reading (Gain = 8)
over Power Factor with Internal Reference, Integrator Off
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0.1 1 10 100
PF = +0.5
PF = 1
PF = –0.5
MID CLASS C
MID CLASS C
06353-096
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 8
INTEGRATOR OFF
INTERNAL REFERENCE
Figure 22. Current RMS Error as a Percentage of Reading (Gain = 8)
over Power Factor with Internal Reference, Integrator Off
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 24 of 152
–0.8
–1.0
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0.1 1 10 100
06353-100
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 16
INTEGRATOR OFF
INTERNAL REFERENCE
–40°C; PF = 0
+85°C; PF = 0
+85°C; PF = 0.866
–40°C; PF = 0.866
+25°C; PF = 0.866
+25°C; PF = 0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–40°C; PF = 1
+25°C; PF = 1
+85°C; PF = 1
MID CLASS C
MID CLASS C
0.1 1 10 100
06353-097
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 16
INTEGRATOR OFF
INTERNAL REFERENCE
Figure 23. Active Energy Error as a Percentage of Reading (Gain = 16)
over Temperature with Internal Reference, Integrator Off
Figure 26. Reactive Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator Off
–40°C; PF = 1
+85°C; PF = 1
MID CLASS C
MID CLASS C
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 1 10 100
06353-101
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 16
INTEGRATOR OFF
INTERNAL REFERENCE
+25°C; PF = 1
MID CLASS C
MID CLASS C
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 1 10 100
06353-098
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 16
INTEGRATOR OFF
INTERNAL REFERENCE
+85°C; PF = 1
–40°C; PF = 1
–40°C; PF = 0.5
+85°C; PF = 0.5
+25°C; PF = 1
+25°C; PF = 0.5
Figure 24. Active Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator Off
Figure 27. Current RMS Error as a Percentage of Reading (Gain = 16)
over Temperature with Internal Reference, Integrator Off
MID CLASS C
MID CLASS C
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 1 10 100
06353-102
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 16
INTEGRATOR OFF
INTERNAL REFERENCE
–40°C; PF = 1
+25°C; PF = 1
–40°C; PF = 0.5
+85°C; PF = 0.5
+25°C; PF = 0.5
+85°C; PF = 1
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
–1.0
1.0
0.1 1 10 100
06353-099
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 16
INTEGRATOR OFF
INTERNAL REFERENCE
+85°C; PF = 0
–40°C; PF = 0
+25°C; PF = 0
Figure 28. Current RMS Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator Off
Figure 25. Reactive Energy Error as a Percentage of Reading (Gain = 16)
over Temperature with Internal Reference, Integrator Off
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 25 of 152
PERFORMANCE CURVES FOR THE ADE7169 AND ADE7569 ONLY
MID CLASS C
MID CLASS C
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 1 10 100
06353-103
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 16
INTEGRATOR ON
INTERNAL REFERENCE
–40°C; PF = 1
+85°C; PF = 0.5
+25°C; PF = 0.5
–40°C; PF = 0.5
+25°C; PF = 1
+85°C; PF = 1
Figure 29. Active Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator On
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
–1.0
1.0
0.1 1 10 100
06353-104
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 16
INTEGRATOR ON
INTERNAL REFERENCE
+25°C; PF = 0
+85°C; PF = 0.866
–40°C; PF = 0
+25°C; PF = 0.866
+85°C; PF = 0
–40°C; PF = 0.866
Figure 30. Reactive Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator On
–40°C; PF = 1
MID CLASS C
MID CLASS C
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 1 10 100
06353-105
CURRENT CHANNEL (% of Full Scale)
ERROR (% of Reading)
GAIN = 16
INTEGRATOR ON
INTERNAL REFERENCE
+25°C; PF = 1
+25°C; PF = 0.5
+85°C; PF = 0.5
+85°C; PF = 1
–40°C; PF = 0.5
Figure 31. Current RMS Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator On
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 26 of 152
TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
is defined by the following formula:
Percentage Error =
%100×
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−
EnergyTrue EnergyTrueRegisterEnergy (1)
Phase Error Between Channels
The digital integrator and the high-pass filter (HPF) in the
current channel have a nonideal phase response. To offset this
phase response and equalize the phase response between
channels, two phase correction networks are placed in the
current channel: one for the digital integrator and the other for
the HPF. The phase correction networks correct the phase
response of the corresponding component and ensure a phase
match between current channel and voltage channel to within
±0.1° over a range of 45 Hz to 65 Hz with the digital integrator
off. With the digital integrator on, the phase is corrected to
within ±0.4° over a range of 45 Hz to 65 Hz.
Power Supply Rejection (PSR)
PSR quantifies the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 measurement error as a percentage of
reading when the power supplies are varied. For the ac PSR
measurement, a reading at nominal supplies (3.3 V) is taken.
A second reading is obtained with the same input signal levels
when an ac (100 mV rms/120 Hz) signal is introduced onto the
supplies. Any error introduced by this ac signal is expressed as a
percentage of reading (see the Measurement Error definition).
For the dc PSR measurement, a reading at nominal supplies
(3.3 V) is taken. A second reading is obtained with the same
input signal levels when the supplies are varied ±5%. Any error
introduced is again expressed as a percentage of the reading.
ADC Offset Error
ADC offset error is the dc offset associated with the analog
inputs to the ADCs. It means that, with the analog inputs
connected to AGND, the ADCs still see a dc analog input
signal. The magnitude of the offset depends on the gain
and input range selection (see the Typical Performance
Characteristics section). However, when HPF1 is switched
on, the offset is removed from the current channel, and the
power calculation is not affected by this offset. The offsets
can be removed by performing an offset calibration (see the
Analog Inputs section).
Gain Error
Gain error is the difference between the measured ADC output
code (minus the offset) and the ideal output code (see the
Current Channel ADC section and Voltage Channel ADC
section). It is measured for each of the gain settings on the
current channel (1, 2, 4, 8, and 16). The difference is expressed
as a percentage of the ideal code.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 27 of 152
SPECIAL FUNCTION REGISTER (SFR) MAPPING
Table 15.
Mnemonic Address Description
INTPR 0xFF
Interrupt pins configuration
(see Table 17).
SCRATCH4 0xFE Scratch Pad 4 (see Table 25).
SCRATCH3 0xFD Scratch Pad 3 (see Table 24).
SCRATCH2 0xFC Scratch Pad 2 (see Table 23).
SCRATCH1 0xFB Scratch Pad 1 (see Table 22).
BATVTH 0xFA
Battery detection threshold
(see Table 52).
STRBPER 0xF9 Peripheral ADC strobe period
(see Table 49).
IPSMF 0xF8
Power management interrupt flag
(see Table 18).
TEMPCAL 0xF7 RTC temperature compensation
(see Table 135).
RTCCOMP 0xF6 RTC nominal compensation
(see Table 134).
BATPR 0xF5
Battery switchover configuration (see
Table 19).
PERIPH 0xF4
Peripheral configuration
(see Table 20).
DIFFPROG 0xF3 Temperature and supply delta
(see Table 50).
B 0xF0 Auxiliary math (see Table 56).
VDCINADC 0xEF VDCIN ADC value (see Table 53).
LCDSEGE2 0xED LCD Segment Enable 2 (see Table 98).
IPSME 0xEC
Power management interrupt enable
(see Table 21).
SPISTAT 0xEA SPI interrupt status (see Table 150).
SPI2CSTAT 0xEA I2C interrupt status (see Table 154).
SPIMOD2 0xE9 SPI Configuration SFR 2 (see Table 149).
I2CADR 0xE9 I2C slave address (see Table 153).
SPIMOD1 0xE8 SPI Configuration SFR 1 (see Table 148).
I2CMOD 0xE8 I2C mode (see Table 152).
WAV2H 0xE7 Selection 2 sample MSB (see Table 31).
WAV2M 0xE6
Selection 2 sample middle byte
(see Table 31).
WAV2L 0xE5 Selection 2 sample LSB (see Table 31).
WAV1H 0xE4 Selection 1 sample MSB (see Table 31).
WAV1M 0xE3
Selection 1 sample middle byte (see
Table 31).
WAV1L 0xE2 Selection 1 sample LSB (see Table 31).
ACC 0xE0 Accumulator (see Table 56).
BATADC 0xDF Battery ADC value (see Table 54).
MIRQSTH 0xDE Interrupt Status 3 (see Table 42).
MIRQSTM 0xDD Interrupt Status 2 (see Table 41).
MIRQSTL 0xDC Interrupt Status 1 (see Table 40).
MIRQENH 0xDB Interrupt Enable 3 (see Table 45).
MIRQENM 0xDA Interrupt Enable 2 (see Table 44).
MIRQENL 0xD9 Interrupt Enable 1 (see Table 43).
ADCGO 0xD8 Start ADC measurement (see Table 51).
Mnemonic Address Description
TEMPADC 0xD7 Temperature ADC value (see Table 55).
IRMSH 0xD6 Irms measurement MSB (see Table 31).
IRMSM 0xD5
Irms measurement middle byte
(see Table 31).
IRMSL 0xD4 Irms measurement LSB (see Table 31).
VRMSH 0xD3 Vrms measurement MSB (see Table 31).
VRMSM 0xD2
Vrms measurement middle byte
(see Table 31).
VRMSL 0xD1 Vrms measurement LSB (see Table 31).
PSW 0xD0 Program status word (see Table 57).
TH2 0xCD Timer 2 high byte (see Table 120).
TL2 0xCC Timer 2 low byte (see Table 121).
RCAP2H 0xCB
Timer 2 reload/capture high byte
(see Table 122).
RCAP2L 0xCA
Timer 2 reload/capture low byte
(see Table 123).
T2CON 0xC8 Timer/Counter 2 control (see Table 115).
EADRH 0xC7 Flash high byte address (see Table 110).
EADRL 0xC6 Flash low byte address (see Table 109).
POWCON 0xC5 Power control (see Table 26).
KYREG 0xC1 Key (see Table 126).
WDCON 0xC0 Watchdog timer (see Table 85).
PROTR 0xBF Flash read protection (see Table 108).
PROTB1 0xBE
Flash Write/Erase Protection 1
(see Table 107).
PROTB0 0xBD
Flash Write/Erase Protection 0
(see Table 106).
EDATA 0xBC Flash data (see Table 105).
PROTKY 0xBB Flash protection key (see Table 104).
FLSHKY 0xBA Flash key (see Table 103).
ECON 0xB9 Flash control (see Table 102).
IP 0xB8 Interrupt priority (see Table 79).
PINMAP2 0xB4 Port 2 weak pull-up enable
(see Table 159).
PINMAP1 0xB3 Port 1 weak pull-up enable
(see Table 158).
PINMAP0 0xB2 Port 0 weak pull-up enable
(see Table 157).
LCDCONY 0xB1 LCD Configuration Y (see Table 91).
CFG 0xAF Configuration (see Table 63).
LCDDAT 0xAE LCD data (see Table 97).
LCDPTR 0xAC LCD pointer (see Table 96).
IEIP2 0xA9
Interrupt Enable and Priority 2
(see Table 80).
IE 0xA8 Interrupt enable (see Table 78).
DPCON 0xA7 Data pointer control (see Table 76).
INTVAL 0xA6 RTC alarm interval (see Table 133).
HOUR 0xA5 RTC hours counter (see Table 132).
MIN 0xA4 RTC minutes counter (see Table 131).
SEC 0xA3 RTC seconds counter (see Table 130).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 28 of 152
Mnemonic Address Description
HTHSEC 0xA2
RTC hundredths of a second counter
(see Table 129).
TIMECON 0xA1 RTC configuration (see Table 128).
P2 0xA0 Port 2 (see Table 162).
EPCFG 0x9F
Extended port configuration
(see Table 156).
SBAUDT 0x9E
Enhanced serial baud rate control (see
Table 142).
SBAUDF 0x9D
UART timer fractional divider
(see Table 143).
LCDCONX 0x9C LCD Configuration X (see Table 89).
SPI2CRx 0x9B SPI/I2C receive buffer (see Table 147).
SPI2CTx 0x9A SPI/I2C transmit buffer (see Table 146).
SBUF 0x99 Serial port buffer (see Table 141).
SCON 0x98
Serial communications control
(see Table 140).
LCDSEGE 0x97 LCD segment enable (see Table 95).
LCDCLK 0x96 LCD clock (see Table 92).
LCDCON 0x95 LCD configuration (see Table 88).
MDATH 0x94
Energy measurement pointer data MSB
(see Table 31).
Mnemonic Address Description
MDATM 0x93
Energy measurement pointer data
middle byte (see Table 31).
MDATL 0x92
Energy measurement pointer data LSB
(see Table 31).
MADDPT 0x91 Energy measurement pointer address
(see Table 30).
P1 0x90 Port 1 (see Table 161).
TH1 0x8D Timer 1 high byte (see Table 118).
TH0 0x8C Timer 0 high byte (see Table 116).
TL1 0x8B Timer 1 low byte (see Table 119).
TL0 0x8A Timer 0 low byte (see Table 117).
TMOD 0x89
Timer/Counter 0 and Timer/Counter 1
mode (see Table 113).
TCON 0x88
Timer/Counter 0 and Timer/Counter 1
control (see Table 114).
PCON 0x87 Program control (see Table 58).
DPH 0x83 Data pointer high (see Table 60).
DPL 0x82 Data pointer low (see Table 59).
SP 0x81 Stack pointer (see Table 62).
P0 0x80 Port 0 (see Table 160).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 29 of 152
POWER MANAGEMENT
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 have elaborate power management circuitry that
manages the switchover from regular power supply to battery
and manages power supply failures. The power management
functionalities can be accessed directly through the 8052 SFRs
(see Tabl e 16).
Table 16. Power Management SFRs
SFR Address R/W Mnemonic Description
0xEC R/W IPSME Power management interrupt enable (see Table 21).
0xF5 R/W BATPR Battery switchover configuration (see Table 19).
0xF8 R/W IPSMF Power management interrupt flag (see Table 18).
0xFF R/W INTPR Interrupt pins configuration (see Table 17).
0xF4 R/W PERIPH Peripheral configuration (see Table 20).
0xC5 R/W POWCON Power control (see Table 26).
0xFB R/W SCRATCH1 Scratch Pad 1 (see Table 22).
0xFC R/W SCRATCH2 Scratch Pad 2 (see Table 23).
0xFD R/W SCRATCH3 Scratch Pad 3 (see Table 24).
0xFE R/W SCRATCH4 Scratch Pad 4 (see Table 25).
POWER MANAGEMENT REGISTER DETAILS
Table 17. Interrupt Pins Configuration SFR (INTPR, Address 0xFF)
Bit Mnemonic Default Description
7 RTCCAL 0 Controls RTC calibration output. When set, the RTC calibration frequency selected by the FSEL bits is
output on the P0.2/CF1/RTCCAL pin.
[6:5] FSEL 00 Sets RTC calibration output frequency and calibration window.
FSEL Result (Calibration Window, Frequency)
00 30.5 sec, 1 Hz
01 30.5 sec, 512 Hz
10 0.244 sec, 500 Hz
11 0.244 sec, 16 kHz
4 Reserved N/A
[3:1] INT1PRG 000 Controls the function of INT1.
INT1PRG Result
X00 GPIO enabled
X01 BCTRL enabled
01X INT1 input disabled
11X INT1 input enabled
0 INT0PRG 0 Controls the function of INT0.
INT0PRG Result
0 INT0 input disabled
1 INT0 input enabled
Writing to the Interrupt Pins Configuration SFR (INTPR, Address 0xFF)
To protect the RTC from runaway code, a key must be written to the key SFR (KYREG, Address 0xC1) to obtain write access to INTPR.
KYREG (see Table 126) should be set to 0xEA to unlock this SFR and reset to 0 after a timekeeping register is written to. The RTC
registers can be written using the following 8052 assembly code:
MOV KYREG, #0EAh
MOV INTPR, #080h
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 30 of 152
Table 18. Power Management Interrupt Flag SFR (IPSMF, Address 0xF8)
Bit Bit Address Mnemonic Default Description
7 0xFF FPSR 0 Power supply restored interrupt flag. Set when the VDD power supply has been restored.
This occurs when the source of VSWOUT changes from VBAT to VDD.
6 0xFE FPSM 0 PSM interrupt flag. Set when an enabled PSM interrupt condition occurs.
5 0xFD FSAG 0 Voltage SAG interrupt flag. Set when an ADE energy measurement SAG condition occurs.
4 0xFC Reserved 0 This bit must be kept at 0 for proper operation.
3 0xFB FVADC10 VDCINADC monitor interrupt flag. Set when VDCIN changes by VDCIN_DIFF or when VDCIN
measurement is ready.
2 0xFA FBAT1
0 VBAT monitor interrupt flag. Set when VBAT falls below BATVTH or when VBAT measurement is ready.
1 0xF9 FBSO 0 Battery switchover interrupt flag. Set when VSWOUT switches from VDD to VBAT.
0 0xF8 FVDCIN1
0 VDCIN monitor interrupt flag. Set when VDCIN falls below 1.2 V.
1 This feature is not available in the ADE7116.
Table 19. Battery Switchover Configuration SFR (BATPR, Address 0xF5)
Bit Mnemonic Default Description
[7:2] Reserved 00 These bits must be kept at 0 for proper operation.
[1:0] BATPRG 00 Control bits for battery switchover.
BATPRG Result
00 Battery switchover enabled on low VDD
01 Battery switchover enabled on low VDD and low VDCIN
1X Battery switchover disabled
Table 20. Peripheral Configuration SFR (PERIPH, Address 0xF4)
Bit Mnemonic Default Description
7 RXFLAG 0 If set, indicates that an Rx edge event triggered wake-up from PSM2.
6 VSWSOURCE 1 Indicates the power supply that is internally connected to VSWOUT (0: VSWOUT = VBAT; 1: VSWOUT = VDD).
5 VDD_OK 1 If set, indicates that VDD power supply is ready for operation.
4 PLL_FLT 0 If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit (see Table 51) in
the start ADC measurement SFR (ADCGO, Address 0xD8) to acknowledge the fault and clear the
PLL_FLT bit.
3 REF_BAT_EN 0 Set this bit to enable internal voltage reference in PSM2 mode. This bit should be set if LCD is on in
PSM1 and PSM2 mode.
2 Reserved 0 This bit must be kept at 0 for proper operation.
[1:0] RXPROG 00 Controls the function of the P1.0/RxD pin.
RXPROG Result
00 GPIO
01 RxD with wake-up disabled
11 RxD with wake-up enabled
Table 21. Power Management Interrupt Enable SFR (IPSME, Address 0xEC)
Bit Mnemonic Default Description
7 EPSR 0 Enables a PSM interrupt when the power supply restored interrupt flag (FPSR) is set.
6 Reserved 0 Reserved.
5 ESAG 0 Enables a PSM interrupt when the voltage SAG interrupt flag (FSAG) is set.
4 Reserved 0 This bit must be kept at 0 for proper operation.
3 EVADC10 Enables a PSM interrupt when the VDCINADC monitor interrupt flag (FVADC) is set.
2 EBAT1 0 Enables a PSM interrupt when the VBAT monitor interrupt flag (FBAT) is set.
1 EBSO 0 Enables a PSM interrupt when the battery switchover interrupt flag (FBSO) is set.
0 EVDCIN1 0 Enables a PSM interrupt when the VDCIN monitor interrupt flag (FVDCIN) is set.
1 This feature is not available in the ADE7116.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 31 of 152
Table 22. Scratch Pad 1 SFR (SCRATCH1, Address 0xFB)
Bit Mnemonic Default Description
[7:0] SCRATCH1 0 Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 23. Scratch Pad 2 SFR (SCRATCH2, Address 0xFC)
Bit Mnemonic Default Description
[7:0] SCRATCH2 0 Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 24. Scratch Pad 3 SFR (SCRATCH3, Address 0xFD)
Bit Mnemonic Default Description
[7:0] SCRATCH3 0 Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 25. Scratch Pad 4 SFR (SCRATCH4, Address 0xFE)
Bit Mnemonic Default Description
[7:0] SCRATCH4 0 Value can be written/read in this register. This value is maintained in all the power saving modes.
Clearing the Scratch Pad Registers (SCRATCH1, Address 0xFB to SCRATCH4, Address 0xFE)
Note that these scratch pad registers are cleared only when the part loses VDD and VBAT.
Table 26. Power Control SFR (POWCON, Address 0xC5)
Bit Mnemonic Default Description
7 Reserved 1 Reserved.
6 METER_OFF 0 Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if
metering functions are not needed in PSM0 mode.
5 Reserved 0 This bit should be kept at 0 for proper operation.
4 COREOFF 0 Set this bit to shut down the core and enter PSM2 mode if in the PSM1 operating mode.
3 Reserved 0 Reserved.
[2:0] CD 010 Controls the core clock frequency, fCORE. fCORE = 4.096 MHz/2CD.
CD Result (fCORE in MHz)
000 4.096
001 2.048
010 1.024
011 0.512
100 0.256
101 0.128
110 0.064
111 0.032
Writing to the Power Control SFR (POWCON, Address 0xC5)
Writing data to the POWCON SFR involves writing 0xA7 into the key SFR (KYREG, Address 0xC1), which is described in Table 126,
followed by a write to the POWCON SFR. For example,
MOV KYREG,#0A7h ;Write KYREG to 0xA7 to get write access to the POWCON SFR
MOV POWCON,#10h ;Shut down the core
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 32 of 152
POWER SUPPLY ARCHITECTURE
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 has two power supply inputs, VDD and VBAT, which
require only a single 3.3 V power supply at VDD for full operation.
A battery backup, or secondary power supply, with a maximum
of 3.7 V can be connected to the VBAT input. Internally, the
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
connect VDD or VBAT to VSWOUT, which is used to derive power for
the device circuitry. The VSWOUT output pin reflects the voltage at
the internal power supply (VSWOUT) and has a maximum output
current of 6 mA. This pin can also be used to power a limited
number of peripheral components. The 2.5 V analog supply (VINTA)
and the 2.5 V supply for the core logic (VINTD) are derived by on-
chip linear regulators from VSWOUT. Figure 32 shows the power
supply architecture of the ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 provide automatic battery switchover between VDD
and VBAT based on the voltage level detected at VDD or VDCIN. In
addition, the BCTRL input can be used to trigger a battery
switchover. The conditions for switching VSWOUT from VDD to
VBAT and back to VDD are described in the Battery Switchover
section. VDCIN is an input pin that can be connected to a 0 V to
3.3 V dc signal. This input is intended for power supply super-
visory purposes and does not provide power to the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 circuitry.
POWER SUPPLY
MANAGEMENT
LDO
VINTD
LDO
VINTA
ADC
VSW
ADC
SCRATCH PAD LCD RTC
TEMPERATURE ADC
3.3V
MCU
ADE
SPI/I2C
UART
2.5V
VDCIN VDD VBAT VSWOUT
BCTRL
*NOT AVAILABLE IN THE ADE7116.
06353-011
*
*
*
Figure 32. Power Supply Architecture
BATTERY SWITCHOVER
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 monitor VDD, VBAT, and VDCIN. Automatic battery switch-
over from VDD to VBAT can be configured based on the status of
the VDD, VDCIN, or BCTRL pin. Battery switchover is enabled by
default. Setting Bit 1 in the Battery Switchover Configuration SFR
(BATPR, Address 0xF5) disables battery switchover so that VDD
is always connected to VSWOUT (see Tabl e 19). The source of
VSWOUT is indicated by Bit 6 in the Peripheral Configuration SFR
(PERIPH, Address 0xF4), which is described in Table 20 . Bit 6 is
set when VSWOUT is connected to VDD and cleared when VSWOUT is
connected to VBAT.
The battery switchover functionality provided by the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 allows a
seamless transition from VDD to VBAT. An automatic battery
switchover option ensures a stable power supply to the device, as
long as the external battery voltage is above 2.75 V. It allows
continuous code execution even while the internal power
supply is switching from VDD to VBAT and back. Note that the
energy metering ADCs are not available when VBAT is being
used for VSWOUT.
Power supply monitor (PSM) interrupts can be enabled to
indicate when battery switchover occurs and when the VDD
power supply is restored (see the Power Supply Management
(PSM) Interrupt section.)
VDD to VBAT
The following three events switch the internal power supply
(VSWOUT) from VDD to VBAT:
• VDCIN < 1.2 V. When VDCIN falls below 1.2 V, VSWOUT
switches from VDD to VBAT. This event is enabled when the
BATPRG[1:0] bits in the battery switchover configuration
SFR (BATPR, Address 0xF5) = 0b01. Setting these bits
disables switchover based on VDCIN. Battery switchover on
low VDCIN is disabled by default.
• VDD < 2.75 V. When VDD falls below 2.75 V, VSWOUT
switches from VDD to VBAT. This event is enabled when the
BATPRG[1:0] bits in the BATPR SFR are cleared.
• Falling edge on BCTRL. When the battery control pin,
BCTRL, goes low, VSWOUT switches from VDD to VBAT. This
external switchover signal can trigger a switchover to VBAT
at any time. Setting the INT1PRG bits to X01 in the
interrupt pins configuration SFR (INTPR, Address 0xFF)
enables the battery control pin (see Table 17).
Switching from VBAT to VDD
To s witc h VSWOUT from VBAT to VDD, all of the following events
must be true:
• VDD > 2.75 V. VSWOUT switches back to VDD after VDD remains
above 2.75 V.
• VDCIN > 1.2 V and VDD > 2.75 V. If the low VDCIN condition
is enabled, VSWOUT switches to VDD after VDCIN remains
above 1.2 V and VDD remains above 2.75 V.
• Rising edge on BCTRL. If the battery control pin is enabled,
VSWOUT switches back to VDD after BCTRL is high, and the
first or second bullet point is satisfied.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 33 of 152
POWER SUPPLY MANAGEMENT (PSM) INTERRUPT
The power supply monitor interrupt alerts the 8052 core of
power supply events. The PSM interrupt is disabled by default.
Setting the EPSM bit in the interrupt enable and Priority 2 SFR
(IEIP2, Address 0xA9) enables the PSM interrupt (see Table 80).
The power management interrupt enable SFR (IPSME,
Address 0xEC) controls the events that result in a PSM
interrupt (see Table 21). Figure 33 illustrates how the PSM
interrupt vector is shared among the PSM interrupt sources.
The PSM interrupt flags are latched and must be cleared by
writing to the IPSMF power management interrupt flag SFR,
Address 0xF8 (see Table 18).
06353-012
EPSR
FPSR
ESAG
FSAG
EVADC
FVADC
EBAT
FBAT
EBSO
FBSO
EVDCIN
FVDCIN
FPSM
EPSM TRUE? PENDING PSM
INTERRUPT
EPSR RESERVED ESAG RESERVED EVADC* EBAT* EBSO EVDCIN*
FPSR FPSM FSAG RESERVED FVADC* FBAT* FBSO FVDCIN*
RESERVED PTI RESERVED PSI EADE ETI EPSM ESI
IPSME ADDR. 0xEC
IPSMF ADDR. 0xF8
IEIP2 ADDR. 0xA9
NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN.
*NOTAVAILABLE IN THE ADE7116.
Figure 33. Power Supply Management Interrupt Sources
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 34 of 152
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 can be configured to generate a PSM interrupt when
the source of VSWOUT changes from VDD to VBAT, indicating
battery switchover. Setting the EBSO bit in the power manage-
ment interrupt enable SFR (IPSME, Address 0xEC) enables this
event to generate a PSM interrupt (see Table 21 ).
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 can also be configured to generate an interrupt when
the source of VSWOUT changes from VBAT to VDD, indicating that
the VDD power supply has been restored. Setting the EPSR bit in
the power management interrupt enable SFR (IPSME, Address
0xEC) enables this event to generate a PSM interrupt.
The flags in the IPSMF SFR for these interrupts, FBSO and
FPSR, are set regardless of whether the respective enable bits
have been set. The battery switchover and power supply restore
event flags, FBSO and FPSR, are latched. These events must be
cleared by writing a 0 to these bits. Bit 6 (VSWSOURCE) in the
peripheral configuration SFR (PERIPH, Address 0xF4) tracks
the source of VSWOUT. The bit is set when VSWOUT is connected to
VDD and cleared when VSWOUT is connected to VBAT.
VDCIN ADC PSM Interrupt
The ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 can be
configured to generate a PSM interrupt when VDCIN changes
magnitude by more than a configurable threshold. This threshold
is set in the temperature and supply delta SFR (DIFFPROG,
Address 0xF3), which is described in Table 5 0. See the External
Voltage Measurement section for more information. Setting the
EVADC bit in the power management interrupt enable SFR
(IPSME, Address 0xEC) enables this event to generate a PSM
interrupt. Note that this feature is not available in the ADE7116.
The VDCIN voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to check
the change in VDCIN. Conversions can also be initiated by writing to
the start ADC measurement SFR (ADCGO, Address 0xD8), as
described in Tabl e 51. The FVADC flag in the power manage-
ment interrupt flag SFR (IPSMF, Address 0xF8) indicates when
a VDCIN measurement is ready. See the External Voltage
Measurement section for details on how VDCIN is measured.
VBAT Monitor PSM Interrupt
The VBAT voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to
check the change in VBAT. The FBAT bit is set when the battery
level is lower than the threshold set in the battery detection
threshold SFR (BATVTH, Address 0xFA), described in Table 52,
or when a new measurement is ready in the battery ADC value
SFR (BATADC, Address 0xDF), described in Table 54. See the
Battery Measurement section for more information. Setting the
EBAT bit in the power management interrupt enable SFR
(IPSME, Address 0xEC) enables this event to generate a PSM
interrupt. Note that this feature is not available in the ADE7116.
VDCIN Monitor PSM Interrupt
The VDCIN voltage is monitored by a comparator. The FVDCIN
bit in the power management interrupt flag SFR (IPSMF,
Address 0xF8) is set when the VDCIN input level is lower than
1.2 V. Setting the EVDCIN bit in the IPSME SFR enables this
event to generate a PSM interrupt. This event, which is associated
with the SAG monitoring, can be used to detect that a power
supply (VDD) is compromised and to trigger further actions
prior to initiating a switch from VDD to VBAT. Note that this
feature is not available in the ADE7116.
SAG Monitor PSM Interrupt
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 energy measurement DSP monitors the ac voltage
input at the VP and VN input pins. The SAGLVL register
(Address 0x14) is used to set the threshold for a line voltage
SAG event. The FSAG bit in the power management interrupt
flag SFR (IPSMF, Address 0xF8) is set if the line voltage stays
below the level set in the SAGLVL register for the number of
line cycles set in the SAGCYC register (Address 0x13). See the
Line Voltage SAG Detection section for more information.
Setting the ESAG bit in the power management interrupt enable
SFR (IPSME, Address 0xEC) enables this event to generate a
PSM interrupt.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 35 of 152
USING THE POWER SUPPLY FEATURES
In an energy meter application, the 3.3 V power supply (VDD) is
typically generated from the ac line voltage and regulated to 3.3 V
by a voltage regulator IC. The preregulated dc voltage, typically
5 V to 12 V, can be connected to VDCIN through a resistor divider.
A 3.6 V battery can be connected to VBAT. Figure 34 shows how
the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 power supply inputs are set up in this application.
Figure 35 shows the sequence of events that occurs if the main
power supply generated by the PSU starts to fail in the power
meter application shown in Figure 34. The SAG detection can
provide the earliest warning of a potential problem on VDD.
When a SAG event occurs, user code can be configured to back up
data and prepare for battery switchover if desired. The relative
spacing of these interrupts depends on the design of the power
supply.
Figure 36 shows the sequence of events that occurs if the main
power supply starts to fail in the power meter application shown
in Figure 34, with battery switchover on low VDCIN or low VDD
enabled.
Finally, the transition between VDD and VBAT and the different
power supply modes (see the Operating Modes section) are
represented in Figure 37 and Figure 38.
VOLTAGE
SUPERVISORY
POWER SUPPLY
MANAGEMENT
IPSMF SFR
(ADDR. 0xF8)
V
SW
V
BAT
V
SWOUT
V
DD
58
61
60
VOLTAGE
SUPERVISORY
64
V
DCIN
3.3V
REGULATOR
5V TO 12V DC
PSU
50
SAG
DETECTION
49
45
BCTRL
V
P
V
N
(240V, 220V, 110V TYPICAL)
AC INPUT
06353-013
Figure 34. Power Supply Management for Energy Meter Application
t1
t2
VDD
VDCIN
VP – VN
2.75V
1.2V
SAG LEVEL TRIP POINT
SAGCYC = 1
SAG EVENT
(FSAG = 1)
VDCIN EVENT
(FVDCIN = 1)
IF SWITCHOVER ON LOW V
DD IS ENABLED,
AUTOMATIC BATTERY SWITCHOVER
OCCURS. VSWOUT IS CONNECTED TO VBAT.
BSO EVENT
(FBSO = 1)
06353-014
Figure 35. Power Supply Management Interrupts and Battery Switchover with Only VDD Enabled for Battery Switchover
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 36 of 152
Table 27. Power Supply Event Timing Operating Modes
Parameter Time Description
t1 10 ns min Time between when VDCIN goes below 1.2 V and when FVDCIN is raised.
t2 10 ns min Time between when VDD falls below 2.75 V and when battery switchover occurs.
t3 30 ms typ Time between when VDCIN falls below 1.2 V and when battery switchover occurs if VDCIN is enabled to cause
battery switchover.
t4 130 ms typ Time between when power supply restore conditions are met (VDCIN > 1.2 V and VDD > 2.75 V if BATPRG[1:0] =
0b01 or VDD > 2.75 V if BATPRG[1:0] = 0b00) and when VSWOUT switches to VDD.
06353-015
t
1
t
3
V
DD
V
DCIN
V
P
– V
N
2.75V
1.2V
SAG LEVEL TRIP POINT
SAGCYC = 1
SAG EVENT
(FSAG = 1)
V
DCIN
EVENT
(FVDCIN = 1)
IF SWITCHOVER ON LOW V
DCIN
IS
ENABLED, AUTOMATIC BATTERY
SWITCHOVER OCCURS. V
SWOUT
IS CONNECTED TO V
BAT
.
BSO EVENT
(FBSO = 1)
Figure 36. Power Supply Management Interrupts and Battery Switchover with VDD or VDCIN Enabled for Battery Switchover
V
P
− V
N
SAG LEVEL
TRIP POINT
SAG EVENT
V
DCIN
1.2V
30ms MIN. 130ms MIN.
V
DCIN
EVENT
V
DCIN
EVENT
V
BAT
V
DD
2.75V
V
SW
BATTERY SWITCH
ENABLED ON
LOW V
DCIN
V
SW
BATTERY SWITCH
ENABLED ON
LOW V
DD
PSM0 PSM0
PSM0 PSM0
PSM1 OR PSM2
06353-016
PSM1 OR PSM2
Figure 37. Power Supply Management Transitions Between Modes
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 37 of 152
OPERATING MODES
PSM0 (NORMAL MODE)
In PSM0, or normal operating mode, VSWOUT is connected to
VDD. All of the analog circuitry and the digital circuitry powered
by VINTD and VINTA are enabled by default. In normal mode, the
default clock frequency, fCORE, which is established during a
power-on reset or software reset, is 1.024 MHz.
PSM1 (BATTERY MODE)
In PSM1, or battery mode, VSWOUT is connected to VBAT. In this
operating mode, the 8052 core and all of the digital circuitry are
enabled by default. The analog circuitry for the ADE energy
metering DSP powered by VINTA is disabled. This analog circuitry
automatically restarts, and the switch to the VDD power supply
occurs, when the VDD supply is >2.75 V and the PWRDN bit in
the MODE1 register (Address 0x0B) is cleared (see Table 33). The
default fCORE for PSM1, established during a power-on reset or
software reset, is 1.024 MHz.
PSM2 (SLEEP MODE)
PSM2 is a low power consumption sleep mode for use in battery
operation. In this mode, VSWOUT is connected to VBAT. All of the
2.5 V digital and analog circuitry powered through VINTA and VINTD
is disabled, including the MCU core, resulting in the following:
• The RAM in the MCU is no longer valid.
• The program counter for the 8052, also held in volatile
memory, becomes invalid when the 2.5 V supply is shut
down. Therefore, the program does not resume from
where it left off but always starts from the power-on reset
vector when the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 exit PSM2.
The 3.3 V peripherals (temperature ADC1, VDCIN ADC1, RTC,
and LCD) are active in PSM2. They can be enabled or disabled
to reduce power consumption and are configured for PSM2
operation when the MCU core is active (see Table 29 for more
information about the peripherals and their PSM2 configuration).
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 remain in PSM2 until an event occurs to wake them up.
In PSM2 mode, the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 provide four scratch pad RAM SFRs that
are maintained during this mode. These SFRs can be used
to save data from PSM0 or PSM1 mode when entering PSM2
mode (see Table 22 to Table 25).
In PSM2, the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 maintain some SFRs (see Table 28). The
SFRs that are not listed in this table should be restored when the
part enters PSM0 or PSM1 mode from PSM2 mode.
Table 28. SFRs Maintained in PSM2 Mode
I/O Configuration Power Supply Management RTC Peripherals LCD Peripherals
Interrupt pins configuration SFR
(INTPR, Address 0xFF); see Table 17
Battery detection threshold SFR
(BATVTH, Address 0xFA); see
Table 52
RTC nominal compensation SFR
(RTCCOMP, Address 0xF6); see
Table 134
LCD Segment Enable 2 SFR
(LCDSEGE2, Address 0xED); see
Table 98
Peripheral configuration SFR
(PERIPH, Address 0xF4);
see Table 20
Battery switchover configuration
SFR (BATPR, Address 0xF5); see
Table 19
RTC temperature compensation
SFR (TEMPCAL, Address 0xF7);
see Table 135
LCD Configuration Y SFR
(LCDCONY, Address 0xB1); see
Table 91
Port 0 weak pull-up enable SFR
(PINMAP0, Address 0xB2); see
Table 157
Battery ADC value SFR
(BATADC, Address 0xDF); see
Table 541
RTC configuration SFR (TIMECON,
Address 0xA1); see Table 128
LCD Configuration X SFR
(LCDCONX, Address 0x9C); see
Table 89
Port 1 weak pull-up enable SFR
(PINMAP1, Address 0xB3); see
Table 158
Peripheral ADC strobe period SFR
(STRBPER, Address 0xF9);
see Table 491
Hundredths of a second counter
SFR (HTHSEC, 0xA2); see Table 129
LCD configuration SFR
(LCDCON, Address 0x95); see
Table 88
Port 2 weak pull-up enable SFR
(PINMAP2, Address 0xB4); see
Table 159
Temperature and supply delta SFR
(DIFFPROG, Address 0xF3); see
Table 501
Seconds counter SFR (SEC, 0xA3);
see Table 130
LCD clock SFR (LCDCLK,
Address 0x96); see Table 92
Scratch Pad 1 SFR (SCRATCH1,
Address 0xFB); see Table 22
VDCIN ADC value SFR (VDCINADC,
Address 0xEF); see Table 531
Minutes counter SFR (MIN, 0xA4);
see Table 131
LCD segment enable SFR
(LCDSEGE, Address 0x97); see
Table 95
Scratch Pad 2 SFR (SCRATCH2,
Address 0xFC); see Table 23
Temperature ADC value SFR
(TEMPADC, Address 0xD7); see
Table 551
Hours counter SFR (HOUR, 0xA5);
see Table 132
LCD pointer SFR (LCDPTR,
Address 0xAC); see Table 96
Scratch Pad 3 SFR (SCRATCH3,
Address 0xFD); see Table 24
Alarm interval SFR (INTVAL, 0xA6);
see Table 133
LCD data SFR (LCDDAT,
Address 0xAE); see Table 97
Scratch Pad 4 SFR (SCRATCH4,
Address 0xFE); see Table 25
1 This feature is not available in the ADE7116.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 38 of 152
3.3 V PERIPHERALS AND WAKE-UP EVENTS
Some of the 3.3 V peripherals are capable of waking the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 from PSM2
mode. The events that can cause the devices to wake up from
PSM2 mode are listed in the Wake-Up Event column in Table 2 9.
The interrupt flag associated with these events must be cleared
prior to executing instructions that put the ADE7116/ADE7156/
ADE7166/ADE7169/ADE7566/ADE7569 in PSM2 mode after
wake-up.
Table 29. 3.3 V Peripherals and Wake-Up Events
3.3 V
Peripheral
Wake-
Up
Event
Wake-Up
Enable Bits Flag
Interrupt
Vector Comments
Temperature
ADC
∆T Maskable The temperature ADC can wake up the ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569. A pending interrupt is generated
according to the description in the Temperature Measurement
section. This wake-up event can be disabled by disabling temperature
measurements in the temperature and supply delta SFR (DIFFPROG,
Address 0xF3) in PSM2 mode. The temperature interrupt needs to be
serviced and acknowledged prior to entering PSM2 mode.
VDCIN ADC ΔV Maskable FVADC IPSM The VDCIN measurement can wake up the ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569. FVADC is set according to the
description in the External Voltage Measurement section. This wake-
up event can be disabled by clearing EVADC in the power manage-
ment interrupt enable SFR (IPSME, Address 0xEC); see Table 21. The
FVADC flag needs to be cleared prior to entering PSM2 mode.
Power Supply
Management
PSR Nonmaskable PSR IPSM
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 wake
up if the power supply is restored (if VSWOUT switches to be connected
to VDD). The VSWSOURCE flag, Bit 6 of the peripheral configuration SFR
(PERIPH, Address 0xF4), is set to indicate that VSWOUT is connected to VDD.
RTC Midnight Nonmaskable Midnight IRTC
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
wake up at midnight every day to update their calendars. The RTC
interrupt needs to be serviced and acknowledged prior to entering
PSM2 mode.
Alarm Maskable ALARM IRTC An alarm can be set to wake the ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569 after the desired amount of time. The
RTC alarm is enabled by setting the ALARM bit in the RTC configur-
ation SFR (TIMECON, 0xA1). The RTC interrupt needs to be serviced
and acknowledged prior to entering PSM2 mode.
I/O Ports1INT0 INT0PRG = 1 IE0 The edge of the interrupt is selected by the IT0 bit in the TCON SFR
(TCON, Address 0x88). The IE0 flag bit in the TCON SFR is not affected.
The Interrupt 0 interrupt needs to be serviced and acknowledged
prior to entering PSM2 mode.
INT1 INT1PRG = 11x IE1 The edge of the interrupt is selected by the IT1 bit in the TCON SFR
(TCON, Address 0x88). The IE1 flag bit in the TCON SFR is not affected.
The Interrupt 1 interrupt needs to be serviced and acknowledged
prior to entering PSM2 mode.
Rx Edge
RXPROG[1:0] =
11
PERIPH[7]
(RXFG)
An Rx edge event occurs if a rising or falling edge is detected on the
Rx line. The UART RxD flag needs to be cleared prior to entering
PSM2 mode.
External
Reset
RESET Nonmaskable If the RESET pin is brought low while the ASE7116/ADE7156/
ADE7166/ADE7169/ADE7566/ADE7569 are in PSM2 mode, they
wake up to PSM1 mode.
LCD The LCD can be enabled/disabled in PSM2 mode. The LCD data
memory remains intact.
Scratch Pad The four SCRATCHx registers remain intact in PSM2 mode.
1 All I/O pins are treated as inputs. The weak pull-up on each I/O pin can be disabled individually in the Port 0 weak pull-up enable SFR (PINMAP0, Address 0xB2), Port 1
weak pull-up enable SFR (PINMAP1, Address 0xB3), and Port 2 weak pull-up enable SFR (PINMAP2, Address 0xB4) to decrease current consumption. The interrupts can
be enabled or disabled.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 39 of 152
TRANSITIONING BETWEEN OPERATING MODES
The operating mode of the ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569 is determined by the power
supply connected to VSWOUT. Therefore, changes in the power
supply, such as when VSWOUT switches from VDD to VBAT or when
VSWOUT switches to VDD, alter the operating mode. This section
describes events that change the operating mode.
Automatic Battery Switchover (PSM0 to PSM1)
If any of the enabled battery switchover events occurs (see the
Battery Switchover section), VSWOUT switches to VBAT. This
switchover results in a transition from PSM0 to PSM1 operating
mode. When battery switchover occurs, the analog circuitry
used in the ADE energy measurement DSP is disabled. To
reduce power consumption, the user code can initiate a
transition to PSM2.
Entering Sleep Mode (PSM1 to PSM2)
To reduce power consumption when VSWOUT is connected to
VBAT, user code can initiate sleep mode, PSM2, by setting Bit 4
in the power control SFR (POWCON, Address 0xC5) to shut
down the MCU core. Events capable of waking the MCU can be
enabled (see the 3.3 V Peripherals and Wake-Up Events section).
Servicing Wake-Up Events (PSM2 to PSM1)
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 may need to wake up from PSM2 mode to service
wake-up events (see the 3.3 V Peripherals and Wake-Up Events).
PSM1 code execution begins at the power-on reset vector. After
servicing the wake-up event, the ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569 can return to PSM2 mode by
setting Bit 4 in the power control SFR (POWCON, Address
0xC5) to shut down the MCU core.
Automatic Switch to VDD (PSM2 to PSM0)
If the conditions to switch VSWOUT from VBAT to VDD occur (see
the Battery Switchover section), the operating mode switches to
PSM0. When this switch occurs, the analog circuitry used in the
ADE energy measurement DSP automatically restarts. Note that
code execution continues normally. A software reset can be perf-
ormed to start PSM0 code execution at the power-on reset vector.
USING THE POWER MANAGEMENT FEATURES
Because program flow is different for each operating mode, the
status of VSWOUT must be known at all times. The VSWSOURCE
bit in the peripheral configuration SFR (PERIPH, Address
0xF4) indicates the power supply to which VSWOUT is connected
(see Table 20 ). This bit can be used to control program flow on
wake-up. Because code execution always starts at the power-on
reset vector, Bit 6 of the PERIPH SFR can be tested to determine
which power supply is being used and to branch to normal code
execution or to wake up event code execution. Power supply
events can also occur when the MCU core is active. To be aware
of the events that change what VSWOUT is connected to, use the
following guidelines:
• Enable the battery switchover interrupt (EBSO)
if VSWOUT = VDD at power-up.
• Enable the power supply restored interrupt (EPSR)
if VSWOUT = VBAT at power-up.
An early warning that battery switchover is about to occur is
provided by SAG detection and, possibly, by low VDCIN detection
(see the Battery Switchover section).
For a user-controlled battery switchover, enable automatic
battery switchover on low VDD only. Next, enable the low VDCIN
event to generate the PSM interrupt. When a low VDCIN event
occurs, start data backup. Upon completion of the data backup,
enable battery switchover on low VDCIN. Battery switchover
occurs 30 ms later.
PSM1
BATTERY MODE
V
SWOUT
CONNECTED TO V
BAT
PSM0
NORMAL MODE
V
SWOUT
CONNECTED TO V
DD
PSM2
SLEEP MODE
V
SWOUT
CONNECTED TO V
BAT
POWER SUPPLY
RESTORED
AUTOMATIC BATTERY
SWITCHOVER
WAKE-UP
EVENT
USER CODE DIRECTS MCU
TO SHUT DOWN CORE AFTER
SERVICING WAKE-UP EVENT
POWER SUPPLY
RESTORED
06353-017
Figure 38. Transitioning Between Operating Modes
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 40 of 152
ENERGY MEASUREMENT
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 offer a fixed function, energy measurement, digital
processing core that provides all the information needed to
measure energy in single-phase energy meters. The part
provides two ways to access the energy measurements: direct
access through SFRs for time sensitive information and indirect
access through address and data SFRs for the majority of energy
measurements. The Irms, Vrms, interrupts, and waveform registers
are readily available through the SFRs, as shown in Table 31 .
Other energy measurement information is mapped to a page of
memory that is accessed indirectly through the MADDPT,
MDATL, MDATM, and MDATH SFRs. The address and data
SFRs act as pointers to the energy measurement internal
registers.
ACCESS TO ENERGY MEASUREMENT SFRs
Access to the energy measurement SFRs is achieved by reading
or writing to the SFR addresses provided in Table 31. The
internal data for the MIRQx SFRs is latched byte by byte into
the SFR when the SFR is read.
The WAV1x, WAV2x, VRMSx, and IRMSx registers are all 3-byte
SFRs. The 24-bit data is latched into these SFRs when the high
byte is read. Reading the low or medium byte before the high
byte results in reading the data from the previous latched sample.
Sample code to read the VRMSx register is as follows:
MOV R1, VRMSH //latches data in VRMSH,
VRMSM, and VRMSL SFRs
MOV R2, VRMSM
MOV R3, VRMSL
ACCESS TO INTERNAL ENERGY MEASUREMENT
REGISTERS
Access to the internal energy measurement registers is achieved
by writing to the energy measurement pointer address SFR
(MADDPT, Address 0x91). This SFR selects the energy measure-
ment register to be accessed and determines whether a read or
a write is performed (see Table 30).
Table 30. Energy Measurement Pointer Address SFR
(MADDPT, Address 0x91)
Bit Description
7 1 = write, 0 = read
[6:0] Energy measurement internal register address
Writing to the Internal Energy Measurement Registers
When Bit 7 of the energy measurement pointer address SFR
(MADDPT, Address 0x91) is set, the content of the MDATx
SFRs (MDATL, MDATM, and MDATH) is transferred to the
internal energy measurement register designated by the address
in the MADDPT SFR. If the internal register is one byte long,
only the MDATL SFR content is copied to the internal register,
and the MDATM SFR and MDATH SFR contents are ignored.
The energy measurement core functions with an internal clock
of 4.096 MHz/5 or 819.2 kHz. Because the 8052 core functions
with another clock, 4.096 MHz2CD, synchronization between
the two clock environments when CD = 0 or 1 is an issue. When
data is written to the internal energy measurement registers, a
small wait period needs to be implemented before another read
or write to these registers can take place.
Sample code to write 0x0155 to the 2-byte SAGLVL register
located at Address 0x14 in the energy measurement memory
space is as follows:
MOV MDATM,#01h
MOV MDATL,#55h
MOV MADDPT,#SAGLVL_W (Address 0x94)
MOV A,#05h
DJNZ ACC,$
;Next write or read to energy
measurement SFR can be done after
this.
Reading the Internal Energy Measurement Registers
When Bit 7 of the energy measurement pointer address SFR
(MADDPT, Address 0x91) is cleared, the content of the internal
energy measurement register designated by the address in
MADDPT is transferred to the MDATx SFRs. If the internal
register is one byte long, only the MDATL SFR content is
updated with a new value, and the MDATM SFR and MDATH
SFR contents are reset to 0x00.
The energy measurement core functions with an internal clock
of 4.096 MHz/5 or 819.2 kHz. Because the 8052 core functions
with another clock, 4.096 MHz2CD, synchronization between
the two clock environments when CD = 0 or 1 is an issue. When
data is read from the internal energy measurement registers, a
small wait period needs to be implemented before the MDATx
SFRs are transferred to another SFR.
Sample code to read the peak voltage in the 2-byte VPKLVL
register located at 0x16 into the data pointer is as follows:
MOV MADDPT,#VPKLVL_R (Address 0x16)
MOV A,#05h
DJNZ ACC,$
MOV DPH,MDATM
MOV DPL,MDATL
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 41 of 152
Table 31. Energy Measurement SFRs
Address R/W Mnemonic Description
0x91 R/W MADDPT Energy measurement pointer address.
0x92 R/W MDATL Energy measurement pointer data LSB.
0x93 R/W MDATM Energy measurement pointer data middle byte.
0x94 R/W MDATH Energy measurement pointer data MSB.
0xD1 R VRMSL Vrms measurement LSB.
0xD2 R VRMSM Vrms measurement middle byte.
0xD3 R VRMSH Vrms measurement MSB.
0xD4 R IRMSL Irms measurement LSB.
0xD5 R IRMSM Irms measurement middle byte.
0xD6 R IRMSH Irms measurement MSB.
0xD9 R/W MIRQENL Energy measurement interrupt enable LSB.
0xDA R/W MIRQENM Energy measurement interrupt enable middle byte.
0xDB R/W MIRQENH Energy measurement interrupt enable MSB.
0xDC R/W MIRQSTL Energy measurement interrupt status LSB.
0xDD R/W MIRQSTM Energy measurement interrupt status middle byte.
0xDE R/W MIRQSTH Energy measurement interrupt status MSB.
0xE2 R WAV1L Selection 1 sample LSB.
0xE3 R WAV1M Selection 1 sample middle byte.
0xE4 R WAV1H Selection 1 sample MSB.
0xE5 R WAV2L Selection 2 sample LSB.
0xE6 R WAV2M Selection 2 sample middle byte.
0xE7 R WAV2H Selection 2 sample MSB.
ADC
DFC
×2
MULTIPLIER
INTEGRATOR
WATTOS[15:0]
VAGAIN[11:0]
VADIV[7:0]
IRMSOS[11:0]
VRMSOS[11:0]
WGAIN[11:0]
dt
METERING SFRs
PHCAL[7:0]
VN
VP
PGA2
CF1
WDIV[7:0]
%%
Ф
π
2
×2
×1, ×2, ×4,
×8, ×16
ADC
IP
IN
PGA1
I
{GAIN[2:0]}
VARDIV[7:0]
%
VAROS[15: 0]
VARGAIN[11:0]
DFC
CF2NUM[15:0]
CF2DEN[15:0]
CF1DEN[15:0]
CF1NUM[15:0]
CF2
HPF
HPF
LPF
LPF
LPF2
LPF2
06353-092
Figure 39. ADE7566 and ADE7569 Energy Metering Block Diagram
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 42 of 152
ADC
DFC
×2
MULTIPLIER
INTEGRATOR
WATTOS[15:0]
VAGAIN[11:0]
VADIV[7:0]
IRMSOS[11:0]
VRMSOS[11:0]
WGAIN[11:0]
dt
PHCAL[7:0]
METERING SFRs
V2N
PGA2
V2P
CF1
WDIV[7:0]
%%
Ф
π
2
×2
×1, ×2, ×4,
×8, ×16
ADC
IPA
IN
PGA1
I
{GAIN[2:0]}
VARDIV[7:0]
%
VAROS[15:0]
VARGAIN[11:0]
DFC
CF2NUM[15:0]
CF2DEN[15:0]
CF1DEN[15:0]
CF1NUM[15:0]
CF2
HPF
HPF
ADC
IPB
PGA1
HPF
LPF
LPF
LPF2
LPF2
06353-118
IBGAIN[11:0]
Figure 40. ADE7116, ADE7156, ADE7166, and ADE7169 Energy Metering Block Diagram
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 43 of 152
ENERGY MEASUREMENT REGISTERS
Table 32. Energy Measurement Register List
Address
MADDPT[6:0] Mnemonic R/W
Length
(Bits)
Signed/
Unsigned Default Description
0x01 WATTHR R 24 S 0 Reads Wh accumulator without reset.
0x02 RWATTHR R 24 S 0 Reads Wh accumulator with reset.
0x03 LWATTHR R 24 S 0 Reads Wh accumulator synchronous to line cycle.
0x04 VARHR1R 24 S 0 Reads VARh accumulator without reset.
0x05 RVARHR1
R 24 S 0 Reads VARh accumulator with reset.
0x06 LVARHR1
R 24 S 0 Reads VARh accumulator synchronous to line cycle.
0x07 VAHR R 24 S 0
Reads VAh accumulator without reset. If the VARMSCFCON bit in the
MODE2 register (Address 0x0C) is set, this register accumulates Irms.
0x08 RVAHR R 24 S 0
Reads VAh accumulator with reset. If the VARMSCFCON bit in the
MODE2 register (Address 0x0C) is set, this register accumulates Irms.
0x09 LVAHR R 24 S 0
Reads VAh accumulator synchronous to line cycle. If the VARMSCFCON
bit in the MODE2 register (Address 0x0C) is set, this register accumulates
Irms.
0x0A PER_FREQ R 16 U 0 Reads line period or frequency register depending on MODE2 register.
0x0B MODE1 R/W 8 U 0x06 Sets basic configuration of energy measurement (see Table 33).
0x0C MODE2 R/W 8 U 0x40 Sets basic configuration of energy measurement (see Table 34).
0x0D WAVMODE R/W 8 U 0
Sets configuration of Waveform Sample 1 and Waveform Sample 2
(see Table 35).
0x0E NLMODE R/W 8 U 0 Sets level of energy no load thresholds (see Table 36).
0x0F ACCMODE R/W 8 U 0
Sets configuration of watt and var accumulation and various tamper
alarms (see Table 37).
0x10 PHCAL R/W 8 S 0x40 Sets phase calibration register (see the Phase Compensation section).
0x11 ZXTOUT R/W 12 0x0FFF
Sets timeout for zero-crossing timeout detection (see the Zero-
Crossing Timeout section).
0x12 LINCYC R/W 16 U 0xFFFF
Sets number of half-line cycles for LWATTHR, LVARHR, and LVAHR
accumulators.
0x13 SAGCYC R/W 8 U 0xFF
Sets number of half-line cycles for SAG detection (see the Line
Voltage SAG Detection section).
0x14 SAGLVL R/W 16 U 0
Sets detection level for SAG detection (see the Line Voltage SAG
Detection section).
0x15 IPKLVL R/W 16 U 0xFFFF
Sets peak detection level for current peak detection (see the Peak
Detection section).
0x16 VPKLVL R/W 16 U 0xFFFF
Sets peak detection level for voltage peak detection (see the Peak
Detection section).
0x17 IPEAK R 24 U 0 Reads current peak level without reset (see the Peak Detection section).
0x18 RSTIPEAK R 24 U 0 Reads current peak level with reset (see the Peak Detection section).
0x19 VPEAK R 24 U 0
Reads voltage peak level without reset (see the Peak Detection
section).
0x1A RSTVPEAK R 24 U 0 Reads voltage peak level with reset (see the Peak Detection section).
0x1B GAIN R/W 8 U 0 Sets PGA gain of analog inputs (see Table 38).
0x1C IBGAIN2R/W 12 S 0 Sets matching gain for IPB current input.
0x1D WGAIN R/W 12 S 0 Sets watt gain register.
0x1E VARGAIN1
R/W 12 S 0 Sets var gain register.
0x1F VAGAIN R/W 12 S 0 Sets VA gain register.
0x20 WATTOS R/W 16 S 0 Sets watt offset register.
0x21 VAROS1
R/W 16 S 0 Sets var offset register.
0x22 IRMSOS R/W 12 S 0 Sets current rms offset register.
0x23 VRMSOS R/W 12 S 0 Sets voltage rms offset register.
0x24 WDIV R/W 8 U 0 Sets watt energy scaling register.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 44 of 152
Address
MADDPT[6:0] Mnemonic R/W
Length
(Bits)
Signed/
Unsigned Default Description
0x25 VARDIV R/W 8 U 0 Sets var energy scaling register.
0x26 VADIV R/W 8 U 0 Sets VA energy scaling register.
0x27 CF1NUM R/W 16 U 0 Sets CF1 numerator register.
0x28 CF1DEN R/W 16 U 0x003F Sets CF1 denominator register.
0x29 CF2NUM R/W 16 U 0 Sets CF2 numerator register.
0x2A CF2DEN R/W 16 U 0x003F Sets CF2 denominator register.
0x3B Reserved 0 This register must be set to its default value for proper operation.
0x3C Reserved 0x0300 This register must be set to its default value for proper operation.
0x3D CALMODE2
R/W 8 U 0 Set calibration mode.
0x3E Reserved 0 This register must be set to its default value for proper operation.
0x3F Reserved 0 This register must be set to its default value for proper operation.
1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
2 This function is not available in the ADE7566 or ADE7569.
ENERGY MEASUREMENT INTERNAL REGISTER DETAILS
Table 33. MODE1 Register (MODE1, Address 0x0B)
Bit Mnemonic Default Description
7 SWRST 0 Setting this bit resets all of the energy measurement registers to their default values.
6 DISZXLPF 0 Setting this bit disables the zero-crossing low-pass filter.
5 INTE 0 Setting this bit enables the digital integrator for use with a di/dt sensor.
4 SWAPBITS 0 Setting this bit swaps CH1 ADC and CH2 ADC.
3 PWRDN 0 Setting this bit powers down voltage and current ADCs.
2 DISCF2 1 Setting this bit disables Frequency Output CF2.
1 DISCF1 1 Setting this bit disables Frequency Output CF1.
0 DISHPF 0 Setting this bit disables the HPFs in voltage and current channels.
Table 34. MODE2 Register (MODE2, Address 0x0C)
Bit Mnemonic Default Description
[7:6] CF2SEL 01 Configuration bits for CF2 output.
CF2SEL Result
00 CF2 frequency is proportional to active power.
01 CF2 frequency is proportional to reactive power.1
1X CF2 frequency is proportional to apparent power or Irms.
[5:4] CF1SEL 00 Configuration bits for CF1 output.
CF1SEL Result
00 CF1 frequency is proportional to active power.
01 CF1 frequency is proportional to reactive power.1
1X CF1 frequency is proportional to apparent power or Irms.
3 VARMSCFCON 0 Configuration bits for apparent power or Irms for CF1, CF2 outputs and VA accumulation registers
(VAHR, RVAHR, and LVAHR). Note that CF1 cannot be proportional to VA if CF2 is proportional to
Irms, and vice versa.
VARMSCFCON Result
0 If CF1SEL[1:0] = 1X, CF1 is proportional to VA.
If CF2SEL[1:0] = 1X, CF2 is proportional to VA.
1 If CF1SEL[1:0] = 1X, CF1 is proportional to Irms.
If CF2SEL[1:0] = 1X, CF2 is proportional to Irms.
2 ZXRMS 0 Logic 1 enables update of rms values synchronously to Voltage ZX.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 45 of 152
Bit Mnemonic Default Description
1 FREQSEL 0 Configuration bits to select period or frequency measurement for PER_FREQ register
(Address 0x0A).
FREQSEL Result
0 PER_FREQ register holds a period measurement.
1 PER_FREQ register holds a frequency measurement.
0 WAVEN 0 When this bit is set, waveform sampling mode is enabled.
1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
Table 35. Waveform Mode Register (WAVMODE, Address 0x0D)
Bit Mnemonic Default Description
[7:5] WAV2SEL 000 Waveform Sample 2 selection for samples mode.
WAV2SEL Source
000 Current
001 Voltage
010 Active power multiplier output
011 Reactive power multiplier output1
100 VA multiplier output
101 Irms LPF output
Others Reserved
[4:2] WAV1SEL 000 Waveform Sample 1 selection for samples mode.
WAV1SEL Source
000 Current
001 Voltage
010 Active power multiplier output
011 Reactive power multiplier output1
100 VA multiplier output
101 Irms LPF output (low 24-bit)
Others Reserved
[1: 0] DTRT 00 Waveform samples output data rate.
DTRT Update Rate (Clock = fCORE/5 = 819.2 kHz)
00 25.6 kSPS (clock/32)
01 12.8 kSPS (clock/64)
10 6.4 kSPS (clock/128)
11 3.2 kSPS (clock/256)
1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
Table 36. No Load Configuration Register (NLMODE, Address 0x0E)
Bit Mnemonic Default Description
7 DISVARCMP10 Setting this bit disables fundamental var gain compensation over line frequency.
6 IRMSNOLOAD 0 Logic 1 enables Irms no load threshold detection. The level is defined by the setting of the
VANOLOAD bits.
[5:4] VANOLOAD 00 Apparent power no load threshold.
VANOLOAD Result
00 No load detection disabled
01 No load detection enabled with threshold = 0.030% of full scale
10 No load detection enabled with threshold = 0.015% of full scale
11 No load detection enabled with threshold = 0.0075% of full scale
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 46 of 152
Bit Mnemonic Default Description
[3:2] VARNOLOAD1
00 Reactive power no load threshold.
VARNOLOAD Result
00 No load detection disabled
01 No load detection enabled with threshold = 0.015% of full scale
10 No load detection enabled with threshold = 0.0075% of full scale
11 No load detection enabled with threshold = 0.0037% of full scale
[1:0] APNOLOAD 00 Active power no load threshold.
APNOLOAD Result
00 No load detection disabled
01 No load detection enabled with threshold = 0.015% of full scale
10 No load detection enabled with threshold = 0.0075% of full scale
11 No load detection enabled with threshold = 0.0037% of full scale
1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
Table 37. Accumulation Mode Register (ACCMODE, Address 0x0F)
Bit Mnemonic Default Description
7 ICHANNEL10 This bit indicates the current channel used to measure energy in antitampering mode.
0 = Channel A (IPA)
1 = Channel B (IPB)
6 FAULTSIGN1
0 Configuration bit to select the event that triggers a fault interrupt.
0 = FAULT interrupt occurs when part enters fault mode
1 = FAULT interrupt occurs when part enters normal mode
5 VARSIGN20 Configuration bit to select the event that triggers a reactive power sign interrupt. If cleared to 0,
a VARSIGN interrupt occurs when reactive power changes from positive to negative. If set to 1, a
VARSIGN interrupt occurs when reactive power changes from negative to positive.
4 APSIGN 0 Configuration bit to select event that triggers an active power sign interrupt. If cleared to 0, an
APSIGN interrupt occurs when active power changes from positive to negative. If set to 1, an
APSIGN interrupt occurs when active power changes from negative to positive.
3 ABSVARM2
0 Logic 1 enables absolute value accumulation of reactive power in energy register and pulse
output.
2 SAVARM2
0 Logic 1 enables reactive power accumulation depending on the sign of the active power. If
active power is positive, var is accumulated as it is. If active power is negative, the sign of the var
is reversed for the accumulation. This accumulation mode affects both the var registers (VARHR,
RVARHR, LVARHR) and the pulse output when connected to var.2
1 POAM 0 Logic 1 enables positive-only accumulation of active power in energy register and pulse output.
0 ABSAM 0 Logic 1 enables absolute value accumulation of active power in energy register and pulse
output.
1 This function is not available in the ADE7566 or ADE7569.
2 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
Table 38. Gain Register (GAIN, Address 0x1B)
Bit Mnemonic Default Description
[7:5] PGA2 000 These bits define the voltage channel input gain.
PGA2 Result
000 Gain = 1
001 Gain = 2
010 Gain = 4
011 Gain = 8
100 Gain = 16
4 Reserved 0 Reserved.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 47 of 152
Bit Mnemonic Default Description
3 CFSIGN_OPT 0 This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is
implemented.
CFSIGN_OPT Result
0
1
Filtered power signal
On a per-CF basis
[2:0] PGA1 000 These bits define the current channel input gain.
PGA1 Result
000 Gain = 11
001 Gain = 2
010 Gain = 4
011 Gain = 8
100 Gain = 16
1 This gain is not recommended in the ADE7166 or ADE7169 because it can create an overranging of the ADC when both current inputs are in opposite phase.
Table 39. Calibration Mode Register (CALMODE, Address 0x3D)1
Bit Mnemonic Default Description
[7:6] Reserved 0 These bits must be kept at 0 for proper operation.
[5:4] SEL_I_CH 0 These bits define the current channel used for energy measurements.
SEL_I_CH Result
00 Current channel automatically selected by the tampering condition
01 Current channel connected to IPA
10 Current channel connected to IPB
11 Current channel automatically selected by the tampering condition
3 V_CH_SHORT 0 Logic 1 shorts the voltage channel to ground.
2 I_CH_SHORT 0 Logic 1 shorts the current channel to ground.
[1:0] Reserved These bits must be kept at 0 for proper operation.
1 This register is not available in the ADE7566 or ADE7569.
INTERRUPT STATUS/ENABLE SFRs
Table 40. Interrupt Status 1 SFR (MIRQSTL, Address 0xDC)
Bit Interrupt Flag Description
7 ADEIRQFLAG
This bit is set if any of the ADE status flags that are enabled to generate an ADE interrupt is set. This bit is
automatically cleared when all of the enabled ADE status flags are cleared.
6 Reserved Reserved.
5 FAULTSIGN1Logic 1 indicates that the fault mode has changed according to the configuration of the ACCMODE register.
4 VARSIGN2Logic 1 indicates that the reactive power sign has changed according to the configuration of the ACCMODE
register.
3 APSIGN Logic 1 indicates that the active power sign has changed according to the configuration of the ACCMODE register.
2 VANOLOAD
Logic 1 indicates that an interrupt has been caused by apparent power no load detection. This interrupt is
also used to reflect that the part is entering the Irms no load mode.
1 RNOLOAD2
Logic 1 indicates that an interrupt has been caused by reactive power no load detection.
0 APNOLOAD Logic 1 indicates that an interrupt has been caused by active power no load detection.
1 This function is not available in the ADE7566 or ADE7569.
2 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 48 of 152
Table 41. Interrupt Status 2 SFR (MIRQSTM, Address 0xDD)
Bit Interrupt Flag Description
7 CF2 Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if the CF2 pulse output is not
enabled by clearing Bit 2 of the MODE1 register.
6 CF1 Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if the CF1 pulse output is not
enabled by clearing Bit 1 of the MODE1 register.
5 VAEOF Logic 1 indicates that the VAHR register has overflowed.
4 REOF1Logic 1 indicates that the VARHR register has overflowed.
3 AEOF Logic 1 indicates that the WATTHR register has overflowed.
2 VAEHF Logic 1 indicates that the VAHR register is half full.
1 REHF1
Logic 1 indicates that the VARHR register is half full.
0 AEHF Logic 1 indicates that the WATTHR register is half full.
1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
Table 42. Interrupt Status 3 SFR (MIRQSTH, Address 0xDE)
Bit Interrupt Flag Description
7 RESET Indicates the end of a reset (for both software and hardware reset).
6 Reserved Reserved.
5 WFSM Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7).
4 PKI Logic 1 indicates that the current channel has exceeded the IPKLVL value.
3 PKV Logic 1 indicates that the voltage channel has exceeded the VPKLVL value.
2 CYCEND Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles.
1 ZXTO Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles.
0 ZX Logic 1 indicates detection of a zero crossing in the voltage channel.
Table 43. Interrupt Enable 1 SFR (MIRQENL, Address 0xD9)
Bit Interrupt Enable Bit Description
[7:6] Reserved Reserved.
5 FAULTSIGN1When this bit is set to Logic 1, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052 core.
4 VARSIGN2When this bit is set to Logic 1, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core.
3 APSIGN When this bit is set to Logic 1, the APSIGN flag set creates a pending ADE interrupt to the 8052 core.
2 VANOLOAD When this bit is set to Logic 1, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core.
1 RNOLOAD2
When this bit is set to Logic 1, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
0 APNOLOAD When this bit is set to Logic 1, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
1 This function is not available in the ADE7566 or ADE7569.
2 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
Table 44. Interrupt Enable 2 SFR (MIRQENM, Address 0xDA)
Bit Interrupt Enable Bit Description
7 CF2 When this bit is set to Logic 1, a CF2 pulse creates a pending ADE interrupt to the 8052 core.
6 CF1 When this bit is set to Logic 1, a CF1 pulse creates a pending ADE interrupt to the 8052 core.
5 VAEOF When this bit is set to Logic 1, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.
4 REOF1When this bit is set to Logic 1, the REOF flag set creates a pending ADE interrupt to the 8052 core.
3 AEOF When this bit is set to Logic 1, the AEOF flag set creates a pending ADE interrupt to the 8052 core.
2 VAEHF When this bit is set to Logic 1, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.
1 REHF1
When this bit is set to Logic 1, the REHF flag set creates a pending ADE interrupt to the 8052 core.
0 AEHF When this bit is set to Logic 1, the AEHF flag set creates a pending ADE interrupt to the 8052 core.
1 This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 49 of 152
Table 45. Interrupt Enable 3 SFR (MIRQENH, Address 0xDB)
Bit Interrupt Enable Bit Description
[7:6] Reserved Reserved.
5 WFSM When this bit is set to Logic 1, the WFSM flag set creates a pending ADE interrupt to the 8052 core.
4 PKI When this bit is set to Logic 1, the PKI flag set creates a pending ADE interrupt to the 8052 core.
3 PKV When this bit is set to Logic 1, the PKV flag set creates a pending ADE interrupt to the 8052 core.
2 CYCEND When this bit is set to Logic 1, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.
1 ZXTO When this bit is set to Logic 1, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.
0 ZX When this bit is set to Logic 1, the ZX flag set creates a pending ADE interrupt to the 8052 core.
ANALOG INPUTS
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 has two fully differential voltage input channels. The
maximum differential input voltage for the VP/VN and IP/IN
input pairs is ±0.4 V.
For the ADE7116/ADE7156/ADE7166/ADE7169, PGA1 = 1 is not
recommended because, at full scale, when both IPA and IPB are
180° out of phase, the ADC can be overranged. It is recom-
mended, for these products, that PGA1 = 2, 4, 8, or 16 be used.
Each analog input channel has a programmable gain amplifier
(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The
gain selections are made by writing to the GAIN register (see
Table 38 and Figure 41). Bit 2 to Bit 0 select the gain for the PGA
in the current channel, and Bit 7 to Bit 5 select the gain for the
PGA in the voltage channel. Figure 42 shows how a gain selec-
tion for the current channel is made using the gain register.
00000000
76543210
GAIN REGISTER*
CURRENT AND VOLTAGE CHANNELS PGA CONTROL
PGA2 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
PGA1 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
RESERVED
*REGISTER CONTENTS SHOW POWER-ON DEFAULTS.
ADDR:
0x1B
06353-019
CFSIGN_OPT
Figure 41. Analog Gain Register
K × V
IN
I
P
I
N
00000000
76543210
GAIN[7:0]
GAIN (K)
SELECTION
V
IN
06353-018
Figure 42. PGA in Current Channel
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 50 of 152
ANALOG-TO-DIGITAL CONVERSION
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 has two Σ- analog-to-digital converters (ADCs). The
outputs of these ADCs are mapped directly to waveform sampling
SFRs (Address 0xE2 to Address 0xE7) and are used for energy
measurement internal digital signal processing. In PSM1 (battery
mode) and PSM2 (sleep mode), the ADCs are powered down to
minimize power consumption.
For simplicity, the block diagram in Figure 44 shows a first-
order Σ-∆ ADC. The converter is made up of the Σ-∆ modulator
and the digital low-pass filter (LPF).
A Σ-∆ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569, the sampling clock is equal to 4.096 MHz/5. The
1-bit DAC in the feedback loop is driven by the serial data
stream. The DAC output is subtracted from the input signal. If
the loop gain is high enough, the average value of the DAC
output (and, therefore, the bit stream) can approach that of the
input signal level.
For any given input value in a single sampling interval, the data
from the 1-bit ADC is virtually meaningless. Only when a large
number of samples are averaged is a meaningful result obtained.
This averaging is carried into the second part of the ADC, the
digital LPF. By averaging a large number of bits from the
modulator, the low-pass filter can produce 24-bit data-words
that are proportional to the input signal level.
The Σ-∆ converter uses two techniques to achieve high
resolution from what is essentially a 1-bit conversion technique.
The first is oversampling. Oversampling means that the signal is
sampled at a rate (frequency) that is many times higher than the
bandwidth of interest. For example, the sampling rate in the
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
is 4.096 MHz/5 (819.2 kHz), and the band of interest is 40 Hz to
2 kHz. Oversampling has the effect of spreading the quantization
noise (noise due to sampling) over a wider bandwidth. With the
noise spread more thinly over a wider bandwidth, the quantiza-
tion noise in the band of interest is lowered (see Figure 43).
However, oversampling alone is not efficient enough to improve
the signal-to-noise ratio (SNR) in the band of interest. For example,
an oversampling ratio of four is required to increase the SNR by
only 6 dB (1 bit). To keep the oversampling ratio at a reasonable
level, it is possible to shape the quantization noise so that the
majority of the noise lies at the higher frequencies. In the Σ-∆
modulator, the noise is shaped by the integrator, which has a
high-pass-type response for the quantization noise. The result is
that most of the noise is at the higher frequencies where it can
be removed by the digital LPF. This noise shaping is shown in
Figure 43.
409.60 819.22
NOISE
SIGNAL
DIGITAL
FILTER
ANTIALIAS
FILTER (RC) SAMPLING
FREQUENCY
HIGH RESOLUTION
OUTPUT FROM DIGITAL
LPF
SHAPED
NOISE
409.60 819.22
NOISE
SIGNAL
FREQUENCY (kHz)
FREQUENCY (kHz)
06353-021
Figure 43. Noise Reduction Due to Oversampling and
Noise Shaping in the Analog Modulator
+
–
INTEGRATOR
V
REF
1-BIT DAC
DIGITAL
LOW-PASS
FILTER
24
MCLK/5
C
R
ANALOG
LOW-PASS FILTER
... 10100101 ...
LATCHED
COMPARATOR
06353-020
Figure 44. First-Order
Σ
-∆ ADC
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 51 of 152
Antialiasing Filter
Figure 44 also shows an analog LPF (RC) on the input to the
modulator. This filter is present to prevent aliasing, an artifact
of all sampled systems. Aliasing means that frequency com-
ponents in the input signal to the ADC that are higher than half
the sampling rate of the ADC appear in the sampled signal at a
frequency below half the sampling rate. Figure 45 illustrates the
effect. Frequency components (the black arrows) above half the
sampling frequency (also known as the Nyquist frequency, that
is, 409.6 kHz) are imaged or folded back down below 409.6 kHz.
This happens with all ADCs, regardless of the architecture. In
the example shown, only frequencies near the sampling
frequency (819.2 kHz) move into the band of interest for
metering (40 Hz to 2 kHz). This allows the use of a very simple
LPF (low-pass filter) to attenuate high frequency (at
approximately 819.2 kHz) noise and prevents distortion in the
band of interest.
For conventional current sensors, a simple RC filter (single-pole
LPF) with a corner frequency of 10 kHz produces an attenuation
of approximately 40 dB at 819.2 kHz (see Figure 45). The 20 dB
per decade attenuation is usually sufficient to eliminate the effects
of aliasing for conventional current sensors. However, for a
di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per
decade gain. This neutralizes the −20 dB per decade attenuation
produced by one simple LPF. Therefore, when using a di/dt
sensor, care should be taken to offset the 20 dB per decade gain.
One simple approach is to cascade two RC filters to produce the
−40 dB per decade attenuation needed.
409.60 819.22
FREQUENCY (kHz)
SAMPLING
FREQUENCY
ALIASING EFFECTS
IMAGE
FREQUENCIES
06353-022
Figure 45. ADC and Signal Processing in Current Channel Outline Dimensions
ADC Transfer Function
Both ADCs in the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 are designed to produce the same output
code for the same input signal level. With a full-scale signal on
the input of 0.4 V and an internal reference of 1.2 V, the ADC
output code is nominally 2,147,483 or 0x20C49B. The maximum
code from the ADC is ±4,194,304; this is equivalent to an input
signal level of ±0.794 V. However, for specified performance, it
is recommended that the full-scale input signal level of 0.4 V
not be exceeded.
Current Channel ADC
Figure 46 and Figure 47 show the ADC and signal processing
chain for the current channel. In waveform sampling mode, the
ADC outputs a signed, twos complement, 24-bit data-word at a
maximum of 25.6 kSPS (4.096 MHz/160).
With the specified full-scale analog input signal of 0.4 V and
PGA1 = 1, the ADC produces an output code that is approximately
between 0x20C49B (+2,147,483d) and 0xDF3B65 (−2,147,483d).
For inputs of 0.25 V, 0.125 V, 62.5 mV, and 31.3 mV with PGA1 = 2,
4, 8, and 16, respectively, the ADC produces an output code that
is approximately between 0x28F5C2 (+2,684,354d) and 0xD70A3E
(−2,684,354d).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 52 of 152
PGA1 ADC
I
P
I
N
I
REFERENCE
×1, ×2, ×4
×8, ×16
{GAIN[2:0]}
HPF
DIGITAL
INTEGRATOR*
dt
MODE1[5] CURRENT RMS (I
rms
)
CALCULATION
WAVEFORM SAMPLE
REGISTER
ACTIVE AND REACTIVE
POWER CALCULATION
0V
V1
ANALOG
INPUT
RANGE
0.25V, 0.125V,
62.5mV, 31.3mV
CURRENT CHANNEL
WAVEFORM
DATA RANGE
0x28F5C2
0x000000
0xD70A3E
CURRENT CHANNEL
WAVEFORM
DATA RANGE AFTER
INTEGRATOR (50Hz)
0x342CD0
0x000000
0xCBD330
CURRENT CHANNEL
WAVEFORM
DATA RANGE AFTER
INTEGRATOR (60Hz)
0x2B7850
0x000000
0xD487B0
60Hz
50Hz
*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED
DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADE
FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT IS NOT FURTHER ATTENUATED.
NOT AVAILABLE IN THE ADE7566.
06353-023
Figure 46. ADC and Signal Processing in Current Channel with PGA1 = 1, 2, 4, 8, or 16 for the ADE7566 and ADE7569
PGA1 ADC
I
PA
I
PB
I
N
I
REFERENCE
IBGAIN
×1, ×2, ×4
×8, ×16
{GAIN[2:0]}
HPF
DIGITAL
INTEGRATOR*
dt
MODE1[5] CURRENT RMS (I
rms
)
CALCULATION
WAVEFORM SAMPLE
REGISTER
ACTIVE AND REACTIVE
POWER CALCULATION
0V
V1
ANALOG
INPUT
RANGE
0.25V, 0.125V,
62.5mV, 31.3mV
CURRENT CHANNEL
WAVEFORM
DATA RANGE
0x28F5C2
0x000000
0xD70A3E
CURRENT CHANNEL
WAVEFORM
DATA RANGE AFTER
INTEGRATOR (50Hz)
0x342CD0
0x000000
0xCBD330
CURRENT CHANNEL
WAVEFORM
DATA RANGE AFTER
INTEGRATOR (60Hz)
0x2B7850
0x000000
0xD487B0
60Hz
50Hz
*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED
DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADE
FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT IS NOT FURTHER ATTENUATED.
NOT AVAILABLE IN THE ADE7116, ADE7156, OR ADE7166.
06353-117
PGA1 ADC
HPF
Figure 47. ADC and Signal Processing in Current Channel with PGA1 = 2, 4, 8, or 16 for the ADE7116, ADE7156, ADE7166, and ADE7169
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 53 of 152
Voltage Channel ADC
Figure 48 shows the ADC and signal processing chain for the
voltage channel. In waveform sampling mode, the ADC outputs
a signed, twos complement, 24-bit data-word at a maximum
of 25.6 kSPS (MCLK/160). The ADC produces an output code
that is approximately between 0x28F5 (+10,485d) and 0xD70B
(−10,485d).
Channel Sampling
The waveform samples of the current ADC and voltage ADC
can also be routed to the waveform registers to be read by the
MCU core. The active, reactive, and apparent power and energy
calculation remain uninterrupted during waveform sampling.
When in waveform sampling mode, one of four output sample
rates can be chosen by using the DTRT[1:0] bits of the
WAVMO D E r eg i ste r ( s ee Tabl e 35). The output sample rate can
be 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS. If the WFSM
enable bit is set in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB), the 8052 core has a pending ADE interrupt.
The sampled signals selected in the WAVMODE register are
latched into the waveform SFRs when the waveform high byte
(WAV1H or WAV2H) is read.
The ADE interrupt stays active until the WFSM status bit is
cleared (see the Energy Measurement Interrupts section).
ANALOG
INPUT
RANGE
HPF
ADC
REFERENCE
V2
0V
0.5V, 0.25V,
0.125V, 62.5mV,
31.3mV
VOLTAGE RMS (V
rms
)
CALCULATION
V
P
V
N
PGA2
V2
VOLTAGE CHANNEL
WAVEFORM
DATA RANGE
0xD70B
0x0000
0x28F5
ACTIVE AND REACTIVE
POWER CALCULATION
LPF1
f
–3dB
= 63.7Hz
MODE 1[6]
ZX SIGNAL
DATA RANGE FOR 60Hz SIGNAL
0xE230
0x0000
0x1DD0
ZX DETECTION
ZX SIGNAL
DATA RANGE FOR 50Hz SIGNAL
0xDFC9
0x0000
0x2037
VOLTAGE PEAK DETECT
×1, ×2, ×4,
×8, ×16
{GAIN[7:5]}
WAVEFORM SAMPLE
REGISTER
06353-024
Figure 48. ADC and Signal Processing in Voltage Channel
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 54 of 152
FAULT DETECTION
The ADE7116/ADE7156/ADE7166/ADE7169 incorporate a
fault detection scheme that warns of fault conditions and allows
the part to continue accurate measurement during a fault event.
(This function is not available in the ADE7566/ ADE7569.) The
ADE7116/ADE7156/ADE7166/ADE7169 do this by continu-
ously monitoring both current inputs (IPA and IPB). For ease of
understanding, these currents are referred to as phase and
neutral (return) currents. A fault condition is defined when the
difference between IPA and IPB is greater than 6.25% of the active
channel. If a fault condition is detected and the inactive channel
is larger than the active channel, the ADE7116/ADE7156/
ADE7166/ADE7169 automatically switch current measurement to
the inactive channel. During a fault, the active, reactive, and
apparent power and the Irms are generated using the larger of the
two currents. On power-up, IPA is the current input selected for
active, reactive, and apparent power and Irms calculations.
To prevent a false alarm, averaging is done for the fault
detection, and a fault condition is detected approximately
1 second after the event. Fault detection is automatically
disabled when the voltage signal is less than 0.3% of the full-
scale input range. This eliminates false detection of a fault due
to noise at light loads.
Because the ADE7116/ADE7156/ADE7166/ADE7169 look for
a difference between the voltage signals on IPA and IPB, it is
important that both current transducers be closely matched.
Channel Selection Indication
The current channel selected for measurement is indicated by
Bit 7 (ICHANNEL) in the ACCMODE register (Address 0x0F).
When this bit is cleared, IPA is selected and, when it is set, IPB is
selected. The ADE7166/ADE7169 automatically switch from
one channel to the other and report the channel configuration
in the ACCMODE register (Address 0x0F).
The current channel selected for measurement can also be
forced. Setting the SEL_I_CH[1:0] bits in the CALMODE
register (Address 0x3D) selects IPA and IPB, respectively. When
both bits are cleared or set, the current channel used for
measurement is selected automatically based on the fault
detection.
Fault Indication
The ADE7116/ADE7156/ADE7166/ADE7169 provide an
indication of the part going in or out of a fault condition. The
new fault condition is indicated by the FAULTSIGN flag (Bit 5)
in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC).
When the FAULTSIGN bit (Bit 6) of the ACCMODE register
(Address 0x0F) is cleared, the FAULTSIGN flag in the Interrupt
Status 1 SFR (MIRQSTL, Address 0xDC) is set when the part is
entering a fault condition or a normal condition.
When the FAULTSIGN bit (Bit 5) is set in the Interrupt Enable
1 SFR (MIRQENL, Address 0xD9), and the FAULTSIGN flag
(Bit 5) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC)
is set, the 8052 core has a pending ADE interrupt.
Fault with Active Input Greater Than Inactive Input
If IPA is the active current input (that is, being used for billing),
and the voltage signal on IPB (the inactive input) falls below
93.75% of IPA, and the FAULTSIGN bit (Bit 6) of the ACCMODE
register (Address 0x0F) is cleared, the FAULTSIGN flag (Bit 5)
in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set.
Both analog inputs are filtered and averaged to prevent false
triggering of this logic output. As a consequence of the filtering,
there is a time delay of approximately 3 seconds on the logic
output after the fault event. The FAULTSIGN flag is indepen-
dent of any activity. Because IPA is the active input and it is still
greater than IPB, billing is maintained on IPA; that is, no swap to
the IPB input occurs. IPA remains the active input.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 55 of 152
Fault with Inactive Input Greater Than Active Input
If the difference between IPB, the inactive input, and IPA, the
active input (that is, being used for billing), becomes greater
than 6.25% of IPB, and the FAULTSIGN bit (Bit 6) of the
ACCMODE register (Address 0x0F) is cleared, the FAULTSIGN
flag (Bit 5) in the Interrupt Status 1 SFR (MIRQSTL, Address
0xDC) is set. The IPB analog input becomes the active input.
Again, a time constant of about 3 seconds is associated with this
swap. IPA does not become the active channel again until IPA is
greater than IPB and the difference between IPA and IPB—in this
order—becomes greater than 6.25% of IPB. However, if the
FAULTSIGN bit (Bit 6) of the ACCMODE register (Address 0x0F)
is set, the FAULTSIGN flag (Bit 5) in the Interrupt Status 1 SFR
(MIRQSTL, Address 0xDC) is set as soon as IPA is within 6.25%
of IPB. This threshold eliminates potential chatter between IPA
and IPB.
Calibration Concerns
Typically, when a meter is calibrated, the voltage and current
circuits are separated, as shown in Figure 49. Current passes
through only the phase circuit or the neutral circuit. Figure 49
shows current being passed through the phase circuit. This is
the preferred option because the ADE7116/ADE7156/
ADE7166/ADE7169 start billing on the IPA input on power-up.
The phase circuit CT is connected to IPA in the diagram.
Because the current sensors are not perfectly matched, it is
important to match current inputs. The ADE7116/
ADE7156/ADE7166/ADE7169 provide a gain calibration
register for IPB, IBGAIN (Address 0x1C). IBGAIN is a 12-bit,
signed, twos complement register that provides a gain
resolution of 0.0244%/LSB.
For calibration, a first measurement should be done on IPA by
setting the SEL_I_CH bits to 0b01 in the CALMODE register
(Address 0x3D). This measurement should be compared to the
measurement on IPB. Measuring IPB can be forced by setting the
SEL_I_CH bits to 0b10 in the CALMODE register (Address 0x3D).
The gain error between these two measurements can be evaluated
using the following equation:
() () ()
()
A
AB ItMeasuremen
ItMeasuremenItMeasuremen
Error −
=% (2)
The two channels, IPA and IPB, can then be matched by writing
−Error(%)/(1 + Error (%)) × 212 to the IBGAIN register
(Address 0x1C). This matching adjustment is valid for all
energy measurements made by the ADE7116/ADE7156/
ADE7166/ADE7169, including active power, reactive power
(ADE7169 only), apparent power, and Irms.
AGND
I
PB
I
N
I
PA
R
F
R
F
C
F
C
F
CT
CT
R
B
R
B
0V
V
A
0
I
PB
PHASE
NEUTRAL
R
F
R
A
V
P
R
F
V
N
C
T
C
F
V
TEST
CURRENT
240V rms
06353-025
Figure 49. Fault Conditions for Inactive Input Greater Than Active Input
di/dt CURRENT SENSOR AND DIGITAL
INTEGRATOR FOR THE ADE7169/ADE7569
A di/dt sensor, a feature available for the AD7169/ADE7569 but
not for the ADE7116/ADE7156/ADE7166/ADE7169, detects
changes in the magnetic field caused by ac currents. Figure 50
shows the principle of a di/dt current sensor.
MAGNETIC FIELD CREATED BY CURRENT
(DIRECTLY PROPORTIONAL TO CURRENT)
+ EMF (ELECTROMOTIVE FORCE)
– INDUCED BY CHANGES IN
MAGNETIC FLUX DENSITY (di/dt)
06353-026
Figure 50. Principle of a di/dt Current Sensor
The flux density of a magnetic field induced by a current is
directly proportional to the magnitude of the current. The
changes in the magnetic flux density passing through a conductor
loop generate an electromotive force (EMF) between the two
ends of the loop. The EMF is a voltage signal that is proportional
to the di/dt of the current. The voltage output from the di/dt
current sensor is determined by the mutual inductance between
the current-carrying conductor and the di/dt sensor. The current
signal needs to be recovered from the di/dt signal before it can
be used. An integrator is, therefore, necessary to restore the
signal to its original form.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 56 of 152
FREQUENCY (Hz)
–1.0
–6.040 7045
GAIN (dB)
50 55 60 65
–1.5
–2.0
–2.5
–3.5
–4.5
–5.5
–3.0
–4.0
–5.0
06353-029
The ADE7169/ADE7569 have a built-in digital integrator to
recover the current signal from the di/dt sensor. The digital
integrator on the current channel is switched off by default when
the ADE7169/ADE7569 are powered up. Setting the INTE bit
(Bit 5) in the MODE1 register (Address 0x0B) turns on the
integrator. Figure 51 to Figure 54 show the gain and phase
response of the digital integrator.
FREQUENCY (Hz)
10
GAIN (dB)
0
–10
–20
–30
–40
–50
100 1000
06353-027
Figure 53. Combined Gain Response of the Digital Integrator and
Phase Compensator (40 Hz to 70 Hz)
–89.75
–89.80
–89.85
–89.90
–89.95
–90.00
FREQUENCY (Hz)
PHASE (Degrees)
40 45 7050 55 60 65
–90.05
–89.70
06353-030
Figure 51. Combined Gain Response of the Digital Integrator and
Phase Compensator
FREQUENCY (Hz)
10
2
10
3
06353-106
FREQ
–88.0
PHASE (Degrees)
–88.5
–89.0
–89.5
–90.0
–90.5
Figure 54. Combined Phase Response of the Digital Integrator and
Phase Compensator (40 Hz to 70 Hz)
Note that the integrator has a −20 dB/dec attenuation and an
approximately −90° phase shift. When combined with a di/dt
sensor, the resulting magnitude and phase response should be a
flat gain over the frequency band of interest. The di/dt sensor
has a 20 dB/dec gain associated with it. It also generates
significant high frequency noise. Therefore, a more effective
antialiasing filter is needed to avoid noise due to aliasing (see
the Antialiasing Filter section).
Figure 52. Combined Phase Response of the Digital Integrator and
Phase Compensator
When the digital integrator is switched off, the ADE7169/ADE7569
can be used directly with a conventional current sensor, such as a
current transformer (CT), or with a low resistance current
shunt.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 57 of 152
POWER QUALITY MEASUREMENTS
Zero-Crossing Detection
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 has a zero-crossing detection circuit on the voltage
channel. This zero crossing is used to produce a zero-crossing
internal signal (ZX) and is used in calibration mode.
The zero crossing is generated by default from the output of
LPF1. This filter has a low cutoff frequency and is intended for
50 Hz and 60 Hz systems. If needed, this filter can be disabled
to allow a higher frequency signal to be detected or to limit the
group delay of the detection. If the voltage input fundamental
frequency is below 60 Hz, and a time delay in ZX detection is
acceptable, it is recommended that LPF1 be enabled. Enabling
LPF1 limits the variability in the ZX detection by eliminating
the high frequency components. Figure 55 shows how the zero-
crossing signal is generated.
×1, ×2, ×4,
×8, ×16
ADC 2
REFERENCE
LPF1
f
–3dB
= 63.7Hz
PGA2
{GAIN [7:5]}
V
P
V
N
ZERO
CROSSING
ZX
HPF
MODE 1[6]
43.24° @ 60Hz
1.0
0.73 ZX
V2 LPF1
06353-031
Figure 55. Zero-Crossing Detection on the Voltage Channel
The zero-crossing signal, ZX, is generated from the output of
LPF1 (bypassed or not). LPF1 has a single pole at 63.7 Hz (at
MCLK = 4.096 MHz). As a result, there is a phase lag between
the analog input signal V2 and the output of LPF1. The phase
lag response of LPF1 results in a time delay of approximately
2 ms (@ 60 Hz) between the zero crossing on the analog inputs
of the voltage channel and ZX detection.
The zero-crossing detection also drives the ZX flag in the
Interrupt Status 3 SFR (MIRQSTH, Address 0xDE). If the ZX
bit in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB)
is set, the 8052 core has a pending ADE interrupt. The ADE
interrupt stays active until the ZX status bit is cleared (see the
Energy Measurement Interrupts section).
Zero-Crossing Timeout
The zero-crossing detection also has an associated timeout
register, ZXTOUT (Address 0x11). This unsigned, 12-bit register is
decremented (1 LSB) every 160/MCLK seconds. The register is
reset to its user programmed, full-scale value every time a zero
crossing is detected on the voltage channel. The default power-on
value in this register is 0xFFF. If the internal register decrements
to 0 before a zero crossing is detected in the Interrupt Status 3
SFR (MIRQSTH, Address 0xDE), and the ZXTO bit (Bit 1) in
the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) is set,
the 8052 core has a pending ADE interrupt.
The ADE interrupt stays active until the ZXTO status bit is
cleared (see the Energy Measurement Interrupts section). The
ZXTOUT register (Address 0x11) can be written to or read by
the user (see the Energy Measurement Register List section).
The resolution of the register is 160/MCLK seconds per LSB.
Thus, the maximum delay for an interrupt is 0.16 seconds
(1/MCLK × 212) when MCLK = 4.096 MHz.
Figure 56 shows the mechanism of the zero-crossing timeout
detection when the line voltage stays at a fixed dc level for more
than MCLK/160 × ZXTOUT seconds.
12-BIT INTERNAL
REGISTER VALUE
ZXTOUT
ZXTO
FLAG
BIT
VOLTAGE
CHANNEL
06353-032
Figure 56. Zero-Crossing Timeout Detection
Period or Frequency Measurements
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 provide the period or frequency measurement of the
line. The period or frequency measurement is selected by clearing
or setting the FREQSEL bit (Bit 1) in the MODE2 register
(Address 0x0C). The period/frequency register, PER_FREQ
(Address 0x0A), is an unsigned 16-bit register that is updated
every period. If LPF1 is enabled, a settling time of 1.8 sec is
associated with this filter before the measurement is stable.
When the period measurement is selected, the measurement has a
2.44 µs/LSB (4.096 MHz/10) resolution, which represents 0.014%
when the line frequency is 60 Hz. When the line frequency is
60 Hz, the value of the period register is approximately 0d6827.
The length of the register enables the measurement of line
frequencies as low as 12.5 Hz. The period register is stable at
±1 LSB when the line is established, and the measurement does
not change.
When the frequency measurement is selected, the measurement
has a 0.0625 Hz/LSB resolution when MCLK = 4.096 MHz,
which represents 0.104% when the line frequency is 60 Hz.
When the line frequency is 60 Hz, the value of the frequency
register is 0d960. The frequency register is stable at ±4 LSB when
the line is established, and the measurement does not change.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 58 of 152
Line Voltage SAG Detection
In addition to detection of the loss of the line voltage signal
(zero crossing), the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 can also be programmed to detect when
the absolute value of the line voltage drops below a certain peak
value for a number of line cycles. This condition is illustrated in
Figure 57.
SAG RESET LOW
WHEN VOLTAGE
CHANNEL EXCEEDS
SAGLVL [15:0] AND
SAG FLAG RESET
FULL SCALE
SAGLVL [15:0]
SAG FLAG
SAGCYC [7:0] = 0x04
3 LINE CYCLES
06353-033
VOLTAGE CHANNEL
Figure 57. SAG Detection
Figure 57 shows the line voltage falling below a threshold that is
set in the SAG level register (SAGLVL[15:0], Address 0x14) for
three line cycles. The quantities 0 and 1 are not valid for the
SAGCYC register, and the contents represent one more than the
desired number of full line cycles. For example, when the SAG
cycle (SAGCYC[7:0], Address 0x13) contains 0x04, FSAG (Bit 5) in
the power management interrupt flag SFR (IPSMF, Address 0xF8)
is set at the end of the third line cycle after the line voltage falls
below the threshold. If the SAG enable bit (ESAG, Bit 5) in the
power management interrupt enable SFR (IPSME, Address 0xEC)
is set, the 8052 core has a pending power supply management
interrupt. The PSM interrupt stays active until the ESAG bit is
cleared (see the Power Supply Management (PSM) Interrupt
section).
In Figure 57, the SAG flag (FSAG) is set on the fifth line cycle
after the signal on the voltage channel first dropped below the
threshold level.
SAG Level Set
The 2-byte contents of the SAG level register (SAGLVL, Address
0x14) are compared to the absolute value of the output from LPF1.
Therefore, when LPF1 is enabled, writing 0x2038 to the SAG
level register puts the SAG detection level at full scale (see
Figure 57). Writing 0x00 or 0x01 puts the SAG detection level at
0. The SAG level register is compared to the input of the ZX
detection, and detection is made when the ZX input falls below
the contents of the SAG level register.
Peak Detection
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 can also be programmed to detect when the absolute
value of the voltage or current channel exceeds a specified peak
value. Figure 58 illustrates the behavior of the peak detection
for the voltage channel. Both voltage and current channels are
monitored at the same time.
PKV RESET
LOW WHEN
MIRQSTH SFR
IS READ
VPKLVL[15:0]
V
2
RESET BIT PKV
IN MIRQSTH SFR
PKV INTERRUPT
FLAG
06353-034
Figure 58. Peak Level Detection
Figure 58 shows a line voltage exceeding a threshold that is set
in the voltage peak register (VPKLVL, Address 0x16). The voltage
peak event is recorded by setting the PKV flag in the Interrupt
Status 3 SFR (MIRQSTH, Address 0xDE). If the PKV enable bit
(Bit 3) is set in the Interrupt Enable 3 SFR (MIRQENH, Address
0xDB), the 8052 core has a pending ADE interrupt. Similarly,
the current peak event is recorded by setting the PKI flag (Bit 4)
in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE). The
ADE interrupt stays active until the PKV or PKI status bit is
cleared (see the Energy Measurement Interrupts section).
Peak Level Set
The contents of the VPKLVL (Address 0x16) and IPKLVL
(Address 0x15) registers are compared to the absolute value of the
voltage and 2 MSBs of the current channel, respectively. Thus, for
example, the nominal maximum code from the current channel
ADC with a full-scale signal is 0x28F5C2 (see the Current
Channel ADC section). Therefore, writing 0x28F5 to the IPKLVL
register puts the current channel peak detection level at full
scale and sets the current peak detection to its least sensitive
value. Writing 0x00 puts the current channel detection level at 0.
The detection is done by comparing the contents of the IPKLVL
register to the incoming current channel sample. The PKI flag
indicates that the peak level is exceeded. If the PKI or PKV bit is set
in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB), the
8052 core has a pending ADE interrupt.
Peak Level Record
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 records the maximum absolute value reached by the
current and voltage channels in two different registers, IPEAK
(Address 0x17) and VPEAK (Address 0x19), respectively. Each
register is a 24-bit unsigned register that is updated each time the
absolute value of the waveform sample from the corresponding
channel is above the value stored in the IPEAK or VPEAK
register. The contents of the VPEAK register correspond to the
maximum absolute value observed on the voltage channel input.
The contents of IPEAK and VPEAK represent the maximum
absolute value observed on the current and voltage input,
respectively. Reading the RSTIPEAK (Address 0x18) and
RSTVPEAK (Address 0x1A) registers clears their respective
contents after the read operation.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 59 of 152
PHASE COMPENSATION
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 must work with transducers that can have inherent
phase errors. For example, a phase error of 0.1° to 0.3° is not
uncommon for a current transformer (CT). These phase errors
can vary from part to part, and they must be corrected to perform
accurate power calculations. The errors associated with phase
mismatch are particularly noticeable at low power factors. The
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
provide a means of digitally calibrating these small phase errors.
The part allows a small time delay or time advance to be intro-
duced into the signal processing chain to compensate for small
phase errors. Because the compensation is in time, this technique
should be used only for small phase errors in the range of 0.1°
to 0.5°. Correcting large phase errors using a time shift technique
can introduce significant phase errors at higher harmonics.
The phase calibration register (PHCAL[7:0], Address 0x10) is a
twos complement, signed, single-byte register that has values
ranging from 0x82 (−126d) to 0x68 (+104d).
The PHCAL register is centered at 0x40, meaning that writing
0x40 to the register gives 0 delay. By changing this register, the
time delay in the voltage channel signal path can change from
−231.93 µs to +48.83 µs (MCLK = 4.096 MHz). One LSB is
equivalent to a 1.22 µs (4.096 MHz/5) time delay or advance.
A line frequency of 60 Hz gives a phase resolution of 0.026° at
the fundamental (that is, 360° × 1.22 µs × 60 Hz).
Figure 59 illustrates how the phase compensation is used to
remove a 0.1° phase lead in the current channel due to the
external transducer. To cancel the lead (0.1°) in the current
channel, a phase lead must also be introduced into the voltage
channel. The resolution of the phase adjustment allows the
introduction of a phase lead in increments of 0.026°. The phase
lead is achieved by introducing a time advance into the voltage
channel. A time advance of 4.88 µs is made by writing −4 (0x3C)
to the time delay block, thus reducing the amount of time delay
by 4.88 µs or, equivalently, a phase lead of approximately 0.1° at a
line frequency of 60 Hz (0x3C represents −4 because the register is
centered with 0 at 0x40).
110100
1
70
PGA1
I
PA
I
N
IADC 1
HPF 24
PGA2
V
P
V
N
VADC 2
24 LPF2
V
I
60Hz
0.1°
I
V
CHANNEL 2 DELAY
REDUCED BY 4.88µs
(0.1°LEAD AT 60Hz)
0x0B IN PHCAL[7:0]
PHCAL[7:0]
–231.93µs TO +48.83µs
60Hz
11
DELAY BLOCK
1.22µs/LSB
06353-035
Figure 59. Phase Calibration
RMS CALCULATION
The root mean square (rms) value of a continuous signal V(t) is
defined as
∫
×=
T
rms dttV
T
V
0
2)(
1 (3)
For time sampling signals, rms calculation involves squaring the
signal, taking the average, and obtaining the square root. The
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
implement this method by serially squaring the inputs, averaging
them, and then taking the square root of the average. The averaging
part of this signal processing is done by implementing a low-pass
filter (LPF3 in Figure 60, Figure 62, and Figure 63). This LPF
has a −3 dB cutoff frequency of 2 Hz when MCLK = 4.096 MHz.
()
)sin(2 tVtV ω×= (4)
where V is the rms voltage.
(
tVVtV ω−= 2cos)( 222
)
(5)
When this signal goes through LPF3, the cos(2ωt) term is attenu-
ated and only the dc term, Vrms2 (shown as V2 in Figure 60) goes
through.
V
LPF3
INPUT
V
2
(t) = V
2
– V
2
cos (2ωt)
V
2
(t) = V
2
V(t) = √2 × V sin(ωt)
06353-036
Figure 60. RMS Signal Processing
The Irms signal can be read from the waveform register by setting
the WAVMODE register (Address 0x0D) and setting the WFSM
bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH, Address
0xDB). Like the current and voltage channel waveform sampling
modes, the waveform data is available at sample rates of
25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and 3.2 kSPS.
It is important to note that when the current input is larger than
40% of full scale, the Irms waveform sample register does not
represent the true processed rms value. The rms value processed
with this level of input is larger than the 24-bit read by the wave-
form register, making the value read truncated on the high end.
Current Channel RMS Calculation
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 simultaneously calculates the rms values for the current
and voltage channels in different registers. Figure 61 and Figure 62
show the details of the signal processing chain for the rms
calculation on the current channel. The current channel rms
value is processed from the samples used in the current channel
waveform sampling mode and is stored in an unsigned 24-bit
register (Irms). One LSB of the current channel rms register is
equivalent to 1 LSB of a current channel waveform sample.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 60 of 152
Current Channel RMS Offset Compensation
The update rate of the current channel rms measurement is
4.096 MHz/5. To minimize noise in the reading of the register,
the Irms register can also be configured to update only with the
zero crossing of the voltage input. This configuration is done by
setting the ZXRMS bit (Bit 2) in the MODE2 register (Address
0x0C).
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 incorporate a current channel rms offset compensa-
tion register (IRMSOS). This is a 12-bit signed register that can
be used to remove offset in the current channel rms calculation.
An offset can exist in the rms calculation due to input noises
that are integrated into the dc component of V2(t).
With the different specified full-scale analog input signal PGA1
values, the ADC produces an output code that is approximately
±0d2,147,483 (PGA1 = 1) or ±0d2,684,354 (PGA1 = 2, 4, 8, or 16);
see the Current Channel ADC section. Similarly, the equivalent
rms value of a full-scale ac signal is 0d1,518,499 (0x172BA3) when
PGA = 1 and 0d1,898,124 (0x1CF68C) when PGA1 = 2, 4, 8, or 16.
One LSB of the current channel rms offset is equivalent to
16,384 LSBs of the square of the current channel rms register.
Assuming that the maximum value from the current channel
rms calculation is 0d1,898,124 with full-scale ac inputs, then
1 LSB of the current channel rms offset represents 0.23% of
measurement error at −60 dB down from full scale.
The current rms measurement provided in the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 is accurate
to within 0.5% for signal inputs between full scale and full
scale/500. The conversion from the register value to amps must
be done externally in the microprocessor using an amps/LSB
constant.
768,32
2×+= IRMSOSII 0
rmsrms (6)
where Irms0 is the rms measurement without offset correction.
I
rms
(t)
0x00
+
IRMSOS[11:0]
I
rms
[23:0]
2
26
2
25
sgn 2
27
2
17
2
16
2
18
24
24
dt
MODE1[5]
CURRENT CHANNEL
WAVEFORM
DATA RANGE WITH
INTEGRATOR OFF
0xD70A3E
0x000000
0x28F5C2
60Hz
0xD487B0
0x2B7850
0x000000
CURRENT CHANNEL
WAVEFORM
DATA RANGE WITH
INTEGRATOR ON (60Hz)
HPF1
DIGITAL
INTEGRATOR* LPF3
06353-037
HPF
I
P
*NOT AVAILABLE IN THE ADE7566.
Figure 61. ADE7566/ADE7569 Current Channel RMS Signal Processing with PGA1 = 1, 2, 4, 8, or 16
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 61 of 152
I
rms
(t)
0x00
+
IRMSOS[11:0]
I
rms
[23:0]
2
26
2
25
sgn 2
27
2
17
2
16
2
18
24
24
dt
HPF
MODE1[5]
HPF
CURRENT CHANNEL
WAVEFORM
DATA RANGE WITH
INTEGRATOR OFF
0xD70A3E
0x000000
0x28F5C2
60Hz
0xD487B0
I
PA
I
PB
0x2B7850
0x000000
CURRENT CHANNEL
WAVEFORM
DATA RANGE WITH
INTEGRATOR ON (60Hz)
HPF1
DIGITAL
INTEGRATOR* LPF3
06353-116
IBGAIN
*NOT AVAILABLE IN THE ADE7116, ADE7156, OR ADE7166.
Figure 62. ADE7116/ADE7156/ADE7166/ADE7169 Current Channel RMS Signal Processing with PGA1 = 2, 4, 8, or 16
06353-038
LPF3
LPF1
VOLTAGE CHANNEL
0x28F5C2
++
VRMSOS[11:0]
VOLTAGE SIGNAL (V(t))
0x28F5
0x0
0xD70B
2
16
sgn 2
15
2
7
2
6
2
8
V
rmsx
(t)
0x00
V
rmsx
[23:0]
|X|
Figure 63. Voltage Channel RMS Signal Processing
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 62 of 152
Voltage Channel RMS Calculation
Figure 63 shows details of the signal processing chain for the rms
calculation on the voltage channel. This voltage rms estimation is
done in the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 using the mean absolute value calculation,
as shown in Figure 63. The voltage channel rms value is processed
from the samples used in the voltage channel waveform sampling
mode and is stored in the unsigned 24-bit Vrms register.
The update rate of the voltage channel rms measurement is
MCLK/5. To minimize noise in the reading of the register, the
Vrms register can also be configured to update only with the zero
crossing of the voltage input. This configuration is done by setting
the ZXRMS bit (Bit 2) in the MODE2 register (Address 0x0C).
With the specified full-scale ac analog input signal of 0.4 V, the
output from LPF1 in Figure 63 swings between 0x28F5 and
0xD70B at 60 Hz (see the Voltage Channel AD C section). The
equivalent rms value of this full-scale ac signal is approximately
0d1,898,124 (0x1CF68C) in the Vrms register. The voltage rms
measurement provided in the ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569 is accurate to within ±0.5% for
signal input between full scale and full scale/20. The conversion
from the register value to volts must be done externally in the
microprocessor using a V/LSB constant.
Voltage Channel RMS Offset Compensation
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 incorporate a voltage channel rms offset compensation
register (VRMSOS). This is a 12-bit signed register that can be
used to remove offset in the voltage channel rms calculation. An
offset can exist in the rms calculation due to input noises and dc
offset in the input samples. One LSB of the voltage channel rms
offset is equivalent to 64 LSBs of the rms register. Assuming that
the maximum value from the voltage channel rms calculation is
0d1,898,124 with full-scale ac inputs, then 1 LSB of the voltage
channel rms offset represents 3.37% of measurement error at
−60 dB down from full scale.
Vrms = Vrms0 + 64 × VRMSOS (7)
where Vrms0 is the rms measurement without offset correction.
ACTIVE POWER CALCULATION
Active power is defined as the rate of energy flow from source
to load. It is the product of the voltage and current waveforms.
The resulting waveform is called the instantaneous power signal
and is equal to the rate of energy flow at every instant of time.
The unit of power is the watt or joules/second. Equation 8 gives an
expression for the instantaneous power signal in an ac system.
()
)sin(2 tVtv ω×= (8)
()
)sin(2 tIti ω×= (9)
where:
v is the rms voltage.
i is the rms current.
)()()( titvtp ×=
)2cos()( tVIVItp ω−= (10)
The average power over an integral number of line cycles (n) is
given by the expression in Equation 11.
∫== nT VIdttp
nT
P0)(
1 (11)
where:
T is the line cycle period.
P is referred to as the active or real power.
Note that the active power is equal to the dc component of the
instantaneous power signal p(t) in Equation 11, that is, VI. This
is the relationship used to calculate active power in the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569. The instan-
taneous power signal p(t) is generated by multiplying the current
and voltage signals. The dc component of the instantaneous power
signal is then extracted by LPF2 (low-pass filter) to obtain the
active power information. This process is illustrated in Figure 64.
INSTANTANEOUS
POWER SIGNAL p(t) = v × i – v × i × cos(2ωt)
ACTIVE REAL POWER
SIGNAL = v × i
0x19999A
VI
0xCCCCD
0x00000
CURRENT
i(t) = √2 × i × sin(ωt)
VOLTAGE
v(t) = √2 × v × sin(ωt)
06353-039
Figure 64. Active Power Calculation
Because LPF2 does not have an ideal brick wall frequency
response (see Figure 65), the active power signal has some
ripple due to the instantaneous power signal. This ripple is
sinusoidal and has a frequency equal to twice the line frequency.
Because of its sinusoidal nature, the ripple is removed when the
active power signal is integrated to calculate energy (see the
Active Energy Calculation section).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 63 of 152
FREQUENCY (Hz)
–24
1
(dB)
–20
310301
–12
–16
–8
–4
0
06353-040
00
Figure 65. Frequency Response of LPF2
Active Power Gain Calibration
Figure 66 shows the signal processing chain for the active power
calculation in the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569. The active power is calculated by filtering
the output of the multiplier with a low-pass filter. Note that,
when reading the waveform samples from the output of LPF2,
the gain of the active energy can be adjusted by using the multi-
plier and watt gain register (WGAIN[11:0], Address 0x1D). The
gain is adjusted by writing a twos complement 12-bit word to
the watt gain register. Equation 12 shows how the gain
adjustment is related to the contents of the watt gain register.
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
⎭
⎬
⎫
⎩
⎨
⎧+×= 12
2
1WGAIN
PowerActiveWGAINOutput (12)
For example, when 0x7FF is written to the watt gain register, the
power output is scaled up by 50% (0x7FF = 2047d, 2047/212 = 0.5).
Similarly, 0x800 = −2048d (signed, twos complement) and
power output is scaled by −50%. Each LSB scales the power
output by 0.0244%. The minimum output range is given when
the watt gain register contents are equal to 0x800, and the
maximum range is given by writing 0x7FF to the watt gain
register. This can be used to calibrate the active power (or
energy) calculation in the ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569.
Active Power Offset Calibration
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 also incorporate an active power offset register
(WATTOS[15:0], Address 0x20). It is a signed, twos complement,
16-bit register that can be used to remove offsets in the active
power calculation (see Figure 64). An offset can exist in the
power calculation due to crosstalk between channels on the
PCB or in the IC itself. The offset calibration allows the contents
of the active power register to be maintained at 0 when no power
is being consumed.
The 256 LSBs (WATTOS = 0x0100) written to the active power
offset register are equivalent to 1 LSB in the waveform sample
register. Assuming the average value, output from LPF2 is
0xCCCCD (838,861d) when inputs on the voltage and current
channels are both at full scale. At −60 dB down on the current
channel (1/1000 of the current channel full-scale input), the
average word value output from LPF2 is 838.861 (838,861/1000).
One LSB in the LPF2 output has a measurement error of
1/838.861 × 100% = 0.119% of the average value. The active
power offset register has a resolution equal to 1/256 LSB of the
waveform register. Therefore, the power offset correction
resolution is 0.000464%/LSB (0.119%/256) at −60 dB.
Active Power Sign Detection
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 detect a change of sign in the active power. The
APSIGN flag (Bit 3) in the Interrupt Status 1 SFR (MIRQSTL,
Address 0xDC) records when a change of sign has occurred
according to the APSIGN bit (Bit 4) in the ACCMODE register
(Address 0x0F). If the APSIGN flag (Bit 3) is set in the Interrupt
Enable 1 SFR (MIRQENL, Address 0xD9), the 8052 core has a
pending ADE interrupt. The ADE interrupt stays active until
the APSIGN status bit is cleared (see the Energy Measurement
Interrupts section).
When APSIGN (Bit 4) in the ACCMODE register (Address
0x0F) is cleared (default), the APSIGN flag (Bit 3) in the
Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set when a
transition from positive to negative active power occurs.
When the APSIGN bit (Bit 4) in the ACCMODE register
(Address 0x0F) is set, the APSIGN flag (Bit 3) in the MIRQSTL
SFR (Address 0xDC) is set when a transition from negative to
positive active power occurs.
Active Power No Load Detection
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 include a no load threshold feature on the active
energy that eliminates any creep effects in the meter. The part
accomplishes this by not accumulating energy if the multiplier
output is below the no load threshold. When the active power is
below the no load threshold, the APNOLOAD flag (Bit 0) in the
Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. If the
APNOLOAD bit (Bit 0) is set in the Interrupt Enable 1 SFR
(MIRQENL, Address 0xD9), the 8052 core has a pending ADE
interrupt. The ADE interrupt stays active until the APNOLOAD
status bit is cleared (see the Energy Measurement Interrupts
section).
The no load threshold level is selectable by setting the
APNOLOAD bits (Bits[1:0]) in the NLMODE register (Address
0x0E). Setting these bits to 0b00 disables the no load detection,
and setting them to 0b01, 0b10, or 0b11 sets the no load
detection threshold to 0.015%, 0.0075%, or 0.0037% of the
multiplier’s full-scale output frequency, respectively. The IEC
62053-21 specification states that the meter must start up with a
load of ≤0.4% IPB, which translates to 0.0167% of the full-scale
output frequency of the multiplier.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 64 of 152
ACTIVE ENERGY CALCULATION
As stated in the Active Power Calculation section, power is
defined as the rate of energy flow. This relationship can be
expressed mathematically, as shown in Equation 13.
dt
dE
P= (13)
where:
P is power.
E is energy.
Conversely, energy is given as the integral of power.
∫
=dttPE )( (14)
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 achieve the integration of the active power signal by
continuously accumulating the active power signal in an
internal, nonreadable, 49-bit energy register. The register
(WATTHR[23:0], Address 0x01) represents the upper 24 bits
of this internal register. This discrete time accumulation or
summation is equivalent to integration in continuous time.
Equation 15 expresses the relationship.
⎭
⎬
⎫
⎩
⎨
⎧×== ∑
∫∞
=
→1
0)(lim)(
n
tTnTpdttpE (15)
where:
n is the discrete time sample number.
T is the sample period.
The discrete time sample period (T) for the accumulation
register in the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 is 1.22 µs (5/MCLK). In addition to
calculating the energy, this integration removes any sinusoidal
components that may be in the active power signal. Figure 66
shows this discrete time integration or accumulation. The active
power signal in the waveform register is continuously added to
the internal active energy register.
The active energy accumulation depends on the setting of
POAM (Bit 1) and ABSAM (Bit 0) in the ACCMODE register
(Address 0x0F). When both bits are cleared, the addition is
signed and, therefore, negative energy is subtracted from the
active energy contents. When both bits are set, the ADE7166/
ADE7169/ADE7566/ADE7569 are set to be in the more
restrictive mode, the positive-only accumulation mode.
When POAM (Bit 1) in the ACCMODE register (Address 0x0F)
is set, only positive power contributes to the active energy
accumulation. When ABSAM (Bit 0) in the ACCMODE
register (Address 0x0F) is set, the absolute active power is used
for the active energy accumulation (see the Wat t- Ab solu te
Accumulation Mode section).
The output of the multiplier is divided by the value in the WDIV
register (Address 0x24). If the value in the WDIV register is
equal to 0, the internal active energy register is divided by 1.
WDIV is an 8-bit, unsigned register. After dividing by WDIV,
the active energy is accumulated in a 49-bit internal energy
accumulation register. The upper 24 bits of this register are
accessible through a read to the active energy register
(WATTHR[23:0], Address 0x01). A read to the RWATTHR
register (Address 0x02) returns the contents of the WATTHR
register, and the upper 24 bits of the internal register are cleared.
As shown in Figure 66, the active power signal is accumulated
in an internal 49-bit signed register. The active power signal can
be read from the waveform register by setting the WAVMODE
register (Address 0x0D) and setting the WFSM bit (Bit 5) in the
Interrupt Enable 3 SFR (MIRQENH, Address 0xDB). Like the
current and voltage channels waveform sampling modes, the
waveform data is available at sample rates of 25.6 kSPS, 12.8 kSPS,
6.4 kSPS, and 3.2 kSPS.
WGAIN[11:0]
WDIV[7:0]
LPF2
CURRENT
CHANNEL
VOLTAGE
CHANNEL
OUTPUT LPF2
TIME (nT)
5
CLKIN
T
ACTIVE POWER
SIGNAL
++
WATTHR[23:0]
OUTPUTS FROM THE LPF2 ARE
ACCUMULATED (INTEGRATED) IN
THE INTERNAL ACTIVE ENERGY REGISTER
UPPER 24 BITS ARE
ACCESSIBLE THROUGH
WATTHR[23:0] REGISTER
23 0
48 0
%
WATTOS[15:0]
2
6
sgn 2
5
2
–6
2
–7
2
–8
+
+
FOR WAVEFORM
SAMPLING
TO
DIGITAL-TO-FREQUENCY
CONVERTER
WAVEFORM
REGISTER
VALUES
06353-041
Figure 66. Active Energy Calculation
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 65 of 152
Figure 67 shows this energy accumulation for full-scale signals
(sinusoidal) on the analog inputs. The three displayed curves
illustrate the minimum period of time it takes the energy register
to roll over when the active power gain register contents are
0x7FF, 0x000, and 0x800. The watt gain register is used to carry
out power calibration in the ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569. As shown, the fastest
integration time occurs when the watt gain register is set to
maximum full scale, that is, 0x7FF.
0x00,0000
0x7F,FFFF
0x3F,FFFF
0x40,0000
0x80,0000
WATTHR[23:0]
6.823.41 10.2 13.7 TIME (Minutes)
WGAIN = 0x7FF
WGAIN = 0x000
WGAIN = 0x800
06353-042
Figure 67. Energy Register Rollover Time for Full-Scale Power
(Minimum and Maximum Power Gain)
Note that the energy register contents roll over to full-scale
negative (0x800000) and continue to increase in value when the
power or energy flow is positive (see Figure 67). Conversely, if
the power is negative, the energy register underflows to full-
scale positive (0x7FFFFF) and continues to decrease in value.
Using the interrupt enable register (MIRQENM, Address 0xDA),
the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 can be configured to issue an ADE interrupt to the
8052 core when the active energy register is half full (positive
or negative) or when an overflow or underflow occurs.
Integration Time Under Steady Load: Active Energy
As mentioned in the Active Energy Calculation section, the
discrete time sample period (T) for the accumulation register is
1.22 µs (5/MCLK). With full-scale sinusoidal signals on the
analog inputs and the WGAIN register (Address 0x1D) set to
0x000, the average word value from each LPF2 is 0xCCCCD
(see Figure 64). The maximum positive value that can be stored
in the internal 49-bit register is 248 (or 0xFFFF,FFFF,FFFF)
before it overflows. The integration time under these conditions
when WDIV = 0 is calculated in the following equation:
Time =
min82.6sec6.409s22.1
xCCCCD0
FFFFFFFF,xFFFF,0 ==μ× (16)
When WDIV is set to a value other than 0, the integration time
varies, as shown in Equation 17.
Time = TimeWDIV = 0 × WDIV (17)
Active Energy Accumulation Modes
Watt -Signed Accumulation Mo de
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 active energy default accumulation mode is a watt-
signed accumulation based on the active power information.
Watt Positive-Only Accumulation Mode
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 are placed in watt positive-only accumulation mode
by setting the POAM bit (Bit 1) in the ACCMODE register
(Address 0x0F). In this mode, the energy accumulation is done
only for positive power, ignoring any occurrence of negative
power above or below the no load threshold (see Figure 68).
The CF pulse also reflects this accumulation method when in
this mode. The default setting for this mode is off. Detection of
the transitions in the direction of power flow and detection of
no load threshold are active in this mode.
POSPOS
INTERRUPT STATUS REGISTERS
NEG
APSIGN FLAG
NO-LOAD
THRESHOLD
ACTIVE POWER
NO-LOAD
THRESHOLD
ACTIVE ENERGY
06353-043
Figure 68. Energy Accumulation in Positive-Only Accumulation Mode
Watt-Absolute Accumulation Mode
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 are placed in watt-absolute accumulation mode by
setting the ABSAM bit (Bit 0) in the ACCMODE register
(Address 0x0F). In this mode, the energy accumulation is done
using the absolute active power, ignoring any occurrence of
power below the no load threshold (see Figure 69). The CF
pulse also reflects this accumulation method when in this
mode. The default setting for this mode is off. Detection of the
transitions in the direction of power flow, and detection of no
load threshold are active in this mode.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 66 of 152
POSPOS
INTERRUPT STATUS REGISTERS
NEG
APSIGN FLAG
NO-LOAD
THRESHOLD
ACTIVE POWER
NO-LOAD
THRESHOLD
ACTIVE ENERGY
APNOLOAD APNOLOAD
06353-044
Figure 69. Energy Accumulation in Absolute Accumulation Mode
Active Energy Pulse Output
All of the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 circuitry has a pulse output whose frequency is
proportional to active power (see the Active Power Calculation
section). This pulse frequency output uses the calibrated signal
from the WGAIN register (Address 0x1D) output, and its
behavior is consistent with the setting of the active energy
accumulation mode in the ACCMODE register (Address 0x0F).
The pulse output is active low and should preferably be
connected to an LED, as shown in Figure 80.
Line Cycle Active Energy Accumulation Mode
In line cycle active energy accumulation mode, the energy accumu-
lation of the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 can be synchronized to the voltage channel
zero crossing so that active energy can be accumulated over an
integral number of half-line cycles. The advantage of summing
the active energy over an integer number of line cycles is that the
sinusoidal component in the active energy is reduced to 0. This
eliminates any ripple in the energy calculation. Energy is
calculated more accurately and more quickly because the
integration period can be shortened. By using this mode, the
energy calibration can be greatly simplified, and the time
required to calibrate the meter can be significantly reduced.
In the line cycle active energy accumulation mode, the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
accumulate the active power signal in the LWATTHR register
(Address 0x03) for an integral number of line cycles, as shown in
Figure 70. The number of half-line cycles is specified in the
LINCYC register.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 can accumulate active power for up to 65,535 half-
line cycles. Because the active power is integrated on an integral
number of line cycles, the CYCEND flag (Bit 2) in the Interrupt
Status 3 SFR (MIRQSTH, Address 0xDE) is set at the end of an
active energy accumulation line cycle. If the CYCEND enable
bit (Bit 2) in the Interrupt Enable 3 SFR (MIRQENH, Address
0xDB) is set, the 8052 core has a pending ADE interrupt. The
ADE interrupt stays active until the CYCEND status bit is
cleared (see the Energy Measurement Interrupts section).
Another calibration cycle starts as soon as the CYCEND flag is
set. If the LWATTHR register (Address 0x03) is not read before a
new CYCEND flag is set, the LWATTHR register is overwritten
by a new value.
WDIV[7:0]WATTOS[15:0]
WGAIN[11:0]
LPF1
++
LWATTHR[23:0]
ACTIVE ENERGY
IS ACCUMULATED IN
THE INTERNAL REGISTER,
AND THE LWATTHR
REGISTER IS UPDATED
AT THE END OF THE LINCYC
HALF-LINE CYCLES
OUTPUT
FROM
LPF2
FROM VOLTAGE
CHANNEL
ADC
23 0
LINCYC[15:0]
48 0
%
ZERO-CROSSING
DETECTION
CALIBRATION
CONTROL
TO
DIGITAL-TO-FREQUENCY
CONVERTER
06353-046
Figure 70. Line Cycle Active Energy Accumulation
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 67 of 152
When a new half-line cycle is written in the LINCYC register
(Address 0x12), the LWATTHR register (Address 0x03) is reset,
and a new accumulation starts at the next zero crossing. The
number of half-line cycles is then counted until LINCYC is
reached. This implementation provides a valid measurement at
the first CYCEND interrupt after writing to the LINCYC
register (see Figure 71). The line active energy accumulation
uses the same signal path as the active energy accumulation.
The LSB size of these two registers is equivalent.
LINCYC
VALUE
CYCEND IRQ
LWATTHR REGISTER
06353-045
Figure 71. Energy Accumulation When LINCYC Changes
Using the information from Equation 10 and Equation 11,
()
()
dtft
f
VI
dtVItE
nTnT π
⎪
⎪
⎭
⎪
⎪
⎬
⎫
⎪
⎪
⎩
⎪
⎪
⎨
⎧
⎟
⎠
⎞
⎜
⎝
⎛
+
−= ∫∫ 2cos
9.8
10
2
0
(18)
where:
n is an integer.
T is the line cycle period.
Because the sinusoidal component is integrated over an integer
number of line cycles, its value is always 0. Therefore,
0
0
+= ∫
nT
VIdtE (19)
E(t) = VInT (20)
Note that in this mode, the 16-bit LINCYC register can hold a
maximum value of 65,535. In other words, the line energy
accumulation mode can be used to accumulate active energy for
a maximum duration of over 65,535 half-line cycles. At a 60 Hz
line frequency, it translates to a total duration of 65,535/120 Hz
= 546 sec.
REACTIVE POWER CALCULATION
(ADE7169/ADE7569)
Reactive power, a function available for the ADE7169/ADE7569
only, is defined as the product of the voltage and current wave-
forms when one of these signals is phase-shifted by 90°. The
resulting waveform is called the instantaneous reactive power
signal. Equation 23 gives an expression for the instantaneous
reactive power signal in an ac system when the phase of the
current channel is shifted by 90°.
)sin(2)( θtVtv +ω= (21)
)sin(2)( tIti ω=
⎟
⎠
⎞
⎜
⎝
⎛π
+ω=
′2
sin2)( tIti (22)
where:
θ is the phase difference between the voltage and current channel.
v is the rms voltage.
i is the rms current.
q(t) = v(t) × i’(t) (23)
q(t) = VI sin (θ) + VI sin
)2( θ+ωt
The average reactive power over an integral number of lines (n)
is given in Equation 24.
∫θ== nT
VIdttq
nT
Q
0
)sin()(
1 (24)
where:
T is the line cycle period.
q is referred to as the reactive power.
Note that the reactive power is equal to the dc component of
the instantaneous reactive power signal q(t) in Equation 23.
The instantaneous reactive power signal q(t) is generated by
multiplying the voltage and current channels. In this case, the
phase of the current channel is shifted by 90°. The dc component of
the instantaneous reactive power signal is then extracted by a
low-pass filter to obtain the reactive power information (see
Figure 72).
In addition, the phase-shifting filter has a nonunity magnitude
response. Because the phase-shifted filter has a large attenuation
at high frequency, the reactive power is primarily for calculation
at line frequency. The effect of harmonics is largely ignored in
the reactive power calculation. Note that, because of the mag-
nitude characteristic of the phase shifting filter, the weight of
the reactive power is slightly different from the active power
calculation (see the Energy Register Scaling section).
The frequency response of the LPF in the reactive signal path is
identical to the one used for LPF2 in the average active power
calculation. Because LPF2 does not have an ideal brick wall
frequency response (see Figure 65), the reactive power signal has
some ripple due to the instantaneous reactive power signal. This
ripple is sinusoidal and has a frequency equal to twice the line
frequency. Because the ripple is sinusoidal in nature, it is removed
when the reactive power signal is integrated to calculate energy.
The reactive power signal can be read from the waveform register
by setting the WAVMODE register (Address 0x0D) and the
WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB). Like the current and voltage channels waveform
sampling modes, the waveform data is available at sample rates of
25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and 3.2 kSPS.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 68 of 152
Reactive Power Gain Calibration
Figure 72 shows the signal processing chain for the ADE7169/
ADE7569 reactive power calculation. As explained in the
Reactive Power Calculation (ADE7169/ADE7569) section, the
reactive power is calculated by applying a low-pass filter to the
instantaneous reactive power signal. Note that, when reading
the waveform samples from the output of LPF2, the gain of the
reactive energy can be adjusted by using the multiplier and by
writing a twos complement, 12-bit word to the var gain register
(VARGAIN[11:0], Address 0x1E). Equation 25 shows how the
gain adjustment is related to the contents of the var gain register.
Output VARGAIN =
⎟
⎠
⎞
⎜
⎝
⎛
⎭
⎬
⎫
⎩
⎨
⎧+× 12
2
1VARGAIN
PowerReactive (25)
The resolution of the VARGAIN register is the same as the
WGAIN register (see the Active Power Gain Calibration
section). VARGAIN can be used to calibrate the reactive
power (or energy) calculation in the ADE7169/ADE7569.
Reactive Power Offset Calibration
The ADE7169/ADE7569 also incorporate a reactive power
offset register (VAROS[15:0], Address 0x21). This signed, twos
complement, 16-bit register can be used to remove offsets in the
reactive power calculation (see Figure 72). An offset can exist in
the reactive power calculation due to crosstalk between channels
on the PCB or in the IC itself. The offset calibration allows the
contents of the reactive power register to be maintained at 0
when no power is being consumed.
The 256 LSBs (VAROS = 0x100) written to the reactive power
offset register are equivalent to 1 LSB in the WAVMODE register
(Address 0x0D).
Sign of Reactive Power Calculation
Note that the average reactive power is a signed calculation.
The phase shift filter has −90° phase shift when the integrator
is enabled, and +90° phase shift when the integrator is disabled.
Table 46 summarizes the relationship of the phase difference
between the voltage and the current and the sign of the resulting
var calculation.
Table 46. Sign of Reactive Power Calculation
Angle Integrator Sign
Between 0° to +90° Off Positive
Between −90° to 0° Off Negative
Between 0° to +90° On Positive
Between −90° to 0° On Negative
Reactive Power Sign Detection
The ADE7169/ADE7569 detect a change of sign in the reactive
power. The VARSIGN flag (Bit 4) in the Interrupt Status 1 SFR
(MIRQSTL, Address 0xDC) records when a change of sign has
occurred according to the VARSIGN bit (Bit 5) in the
ACCMODE register (Address 0x0F). If the VARSIGN bit is set
in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), the
8052 core has a pending ADE interrupt. The ADE interrupt stays
active until the VARSIGN status bit is cleared (see the Energy
Measurement Interrupts section).
When VARSIGN (Bit 5) in the ACCMODE register (Address
0x0F) is cleared (default), the VARSIGN flag (Bit 4) in the
Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set when
a transition from positive to negative reactive power occurs.
When VARSIGN in the ACCMODE register (Address 0x0F) is
set, the VARSIGN flag in the Interrupt Status 1 SFR (MIRQSTL,
Address 0xDC) is set when a transition from negative to positive
reactive power occurs.
Reactive Power No Load Detection
The ADE7169/ADE7569 include a no load threshold feature on
the reactive energy that eliminates any creep effects in the
meter. The ADE7169/ADE7569 accomplish this by not
accumulating reactive energy when the multiplier output is
below the no load threshold. When the reactive power is below
the no load threshold, the RNOLOAD flag (Bit 1) in the Interrupt
Status 1 SFR (MIRQSTL, Address 0xDC) is set. If the RNOLOAD
bit (Bit 1) is set in the Interrupt Enable 1 SFR (MIRQENL,
Address 0xD9), the 8052 core has a pending ADE interrupt. The
ADE interrupt stays active until the RNOLOAD status bit is
cleared (see the Energy Measurement Interrupts section).
The no load threshold level is selectable by setting the
VARNOLOAD bits (Bits[3:2]) in the NLMODE register
(Address 0x0E). Setting these bits to 0b00 disables the no load
detection, and setting them to 0b01, 0b10, or 0b11 sets the no
load detection threshold to 0.015%, 0.0075%, and 0.0037% of
the full-scale output frequency of the multiplier, respectively.
REACTIVE ENERGY CALCULATION
(ADE7169/ADE7569)
As for active energy, the ADE7169/ADE7569 achieve the
integration of the reactive power signal by continuously
accumulating the reactive power signal in an internal, nonreadable,
49-bit energy register. The reactive energy register (VARHR[23:0],
Address 0x04) represents the upper 24 bits of this internal
register. The VARHR register and its function are available for
the ADE7169/ADE7569 only.
The discrete time sample period (T) for the accumulation register
in the ADE7169/ADE7569 is 1.22 µs (5/MCLK). As well as
calculating the energy, this integration removes any sinusoidal
components that may be in the active power signal. Figure 72
shows this discrete time integration or accumulation. The
reactive power signal in the waveform register is continuously
added to the internal reactive energy register.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 69 of 152
The reactive energy accumulation depends on the setting of the
SAVARM and ABSVARM bits in the ACCMODE register
(Address 0x0F). When both bits are cleared, the addition is
signed and, therefore, negative energy is subtracted from the
reactive energy contents. When both bits are set, the
ADE7169/ADE7569 are set to be in the more restrictive mode,
which is the absolute accumulation mode. When the SAVARM
bit (Bit 2) in the ACCMODE register (Address 0x0F) is set, the
reactive power is accumulated depending on the sign of the
active power. When the active power is positive, the reactive
power is added as it is to the reactive energy register. When the
active power is negative, the reactive power is subtracted from
the reactive energy accumulator (see the Var Ant it amp er
Accumulation Mode section).
When the ABSVARM bit (Bit 3) in the ACCMODE register
(Address 0x0F) is set, the absolute reactive power is used for
the reactive energy accumulation (see the Var Abs olute
Accumulation Mode section).
The output of the multiplier is divided by VARDIV. If the value
in the VARDIV register (Address 0x25) is equal to 0, the internal
reactive energy register is divided by 1. VARDIV is an 8-bit,
unsigned register. After dividing by VARDIV, the reactive
energy is accumulated in a 49-bit internal energy accumulation
register. The upper 24 bits of this register are accessible through
a read to the reactive energy register (VARHR[23:0], Address
0x04). A read to the RVAHR register (Address 0x08) returns the
content of the VARHR register, and the upper 24 bits of the
internal register are cleared.
As shown in Figure 72, the reactive power signal is accumulated
in an internal 49-bit, signed register. The reactive power signal
can be read from the waveform register by setting the WAVMODE
register (Address 0x0D) and setting the WFSM bit (Bit 5) in the
Interrupt Enable 3 SFR (MIRQENH, Address 0xDB). Like the
current and voltage channel waveform sampling modes, the wave-
form data is available at sample rates of 25.6 kSPS, 12.8 kSPS,
6.4 kSPS, and 3.2 kSPS.
Figure 67 shows this energy accumulation for full-scale signals
(sinusoidal) on the analog inputs. These curves also apply for
the reactive energy accumulation.
Note that the energy register contents roll over to full-scale
negative (0x800000) and continue to increase in value when the
power or energy flow is positive. Conversely, if the power is
negative, the energy register underflows to full-scale positive
(0x7FFFFF) and continues to decrease in value.
Using the Interrupt Enable 2 SFR (MIRQENM, Address 0xDA),
the ADE7169/ADE7569 can be configured to issue an ADE
interrupt to the 8052 core when the reactive energy register is
half-full (positive or negative) or when an overflow or
underflow occurs.
VARGAIN[11:0]
VARDIV[7:0]
LPF2
CURRENT
CHANNEL
VOLTAGE
CHANNEL
OUTPUT LPF2
TIME (nT)
5
CLKIN
T
REACTIVE POWER
SIGNAL
++
VARHR[23:0]
UPPER 24 BITS ARE
ACCESSIBLE THROUGH
VARHR[23:0] REGISTER
23 0
48 0
WAVEFORM
REGISTER
VALUES
%
VAROS[15:0]
2
6
sgn 2
5
2
–6
2
–7
2
–8
+
+
FOR WAVEFORM
SAMPLING
HPF
Π
2
PHCAL[7:0]
90° PHASE
SHIFTING FILTER
06353-047
OUTPUTS FROM THE LPF2 ARE
ACCUMULATED (INTEGRATED) IN
THE INTERNAL REACTIVE ENERGY
REGISTER
TO
DIGITAL-TO-FREQUENCY
CONVERTER
Figure 72. Reactive Energy Calculation
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 70 of 152
Integration Time Under Steady Load: Reactive Energy
As mentioned in the Active Energy Calculation section, the
discrete time sample period (T) for the accumulation register is
1.22 µs (5/MCLK). With full-scale sinusoidal signals on the
analog inputs and the VARGAIN register (Address 0x1E) and
the VARDIV register (Address 0x25) set to 0x000, the
integration time before the reactive energy register overflows is
calculated in Equation 26.
Time =
min82.6sec6.409s22.1
0xCCCCD
FFFFFFFF,0xFFFF, ==μ× (26)
When VARDIV is set to a value different from 0, the integration
time varies, as shown in Equation 27.
VARDIVTimeTime WDIV ×= =0 (27)
Reactive Energy Accumulation Modes
Var Signed Accumulation Mode
The ADE7169/ADE7569 reactive energy default accumulation
mode is a signed accumulation based on the reactive power
information.
Var Antitamper Accumulation Mode
The ADE7169/ADE7569 are placed in var antitamper
accumulation mode by setting the SAVARM bit in the ACCMODE
register (Address 0x0F). In this mode, the reactive power is
accumulated depending on the sign of the active power. When
the active power is positive, the reactive power is added as it is
to the reactive energy register. When the active power is
negative, the reactive power is subtracted from the reactive
energy accumulator (see Figure 73). The CF pulse also reflects
this accumulation method when in this mode. The default setting
for this mode is off. Transitions in the direction of power flow and
no load threshold are active in this mode.
POSPOS
INTERRUPT STATUS REGISTERS
NEG
APSIGN FLAG
ACTIVE POWER
NO-LOAD
THRESHOLD
NO-LOAD
THRESHOLD
REACTIVE ENERGY
NO-LOAD
THRESHOLD
REACTIVE POWER
NO-LOAD
THRESHOLD
0
6353-048
Figure 73. Reactive Energy Accumulation in
Antitamper Accumulation Mode
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 71 of 152
Line Cycle Reactive Energy Accumulation Mode
Var Absolute Accumulation Mode
In line cycle reactive energy accumulation mode, the energy
accumulation of the ADE7169/ADE7569 can be synchronized
to the voltage channel zero crossing so that reactive energy can
be accumulated over an integral number of half-line cycles. The
advantages of this mode are similar to the ones described in the
Line Cycle Active Energy Accumulation Mode section.
The ADE7169/ADE7569 are placed in absolute accumulation
mode by setting the ABSVARM bit (Bit 3) in the ACCMODE
register (Address 0x0F). In absolute accumulation mode, the
reactive energy accumulation is done by using the absolute
reactive power and ignoring any occurrence of power below the
no load threshold for the reactive energy (see Figure 74). The CF
pulse also reflects this accumulation method when in the
absolute accumulation mode. The default setting for this mode is
off. Transitions in the direction of power flow and no load
threshold are active in this mode.
In line cycle active energy accumulation mode, the
ADE7169/ADE7569 accumulate the reactive power signal in
the LVARHR register (Address 0x06) for an integral number of
line cycles, as shown in Figure 75. The number of half-line cycles
is specified in the LINCYC register (Address 0x12). The
ADE7169/ADE7569 can accumulate active power for up to
65,535 half-line cycles.
REACTIVE ENERGY
NO-LOAD
THRESHOLD
NO-LOAD
THRESHOLD
REACTIVE POWER
06353-049
Because the reactive power is integrated on an integral number
of line cycles, the CYCEND flag (Bit 2) in the Interrupt Status 3
SFR (MIRQSTH, Address 0xDE) is set at the end of an active
energy accumulation line cycle. If the CYCEND enable bit
(Bit 2) in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB)
is set, the 8052 core has a pending ADE interrupt. The ADE
interrupt stays active until the CYCEND status bit is cleared
(see the Energy Measurement Interrupts section). Another
calibration cycle starts as soon as the CYCEND flag is set. If
the LVARHR register (Address 0x06) is not read before a new
CYCEND flag is set, the LVARHR register is overwritten by a
new value.
Figure 74. Reactive Energy Accumulation in Absolute Accumulation Mode
Reactive Energy Pulse Output
The ADE7169/ADE7569 provide all the circuitry with a pulse
output whose frequency is proportional to reactive power (see
the Energy-to-Frequency Conversion section). This pulse
frequency output uses the calibrated signal after VARGAIN,
and its behavior is consistent with the setting of the reactive
energy accumulation mode in the ACCMODE register
(Address 0x0F). The pulse output is active low and should
preferably be connected to an LED, as shown in Figure 80.
When a new half-line cycle is written in the LINCYC register
(Address 0x12), the LVARHR register is reset, and a new
accumulation starts at the next zero crossing. The number of
half-line cycles is then counted internally until the value
programmed in LINCYC is reached. This implementation
provides a valid measurement at the first CYCEND interrupt
after writing to the LINCYC register. The line reactive energy
accumulation uses the same signal path as the reactive energy
accumulation. The LSB size of these two registers is equivalent.
LPF1
++
OUTPUT
FROM
LPF2
FROM VOLTAGE
CHANNEL ADC
23 0
LINCYC[15:0]
48 0
%
ZERO-CROSSING
DETECTION
LVARHR[23:0]
CALIBRATION
CONTROL
VARDIV[7:0]VAROS[15:0]
VARGAIN[11:0]
06353-050
TO
DIGITAL -TO-FREQUENCY
CONVERTER
ACTIVE ENERGY
IS ACCUMULATED IN
THE INTERNAL REGISTER,
AND THE LWATTHR
REGISTER IS UPDATED
AT THE END OF THE LINCYC
HALF-LINE CYCLES
Figure 75. Line Cycle Reactive Energy Accumulation Mode
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 72 of 152
APPARENT POWER CALCULATION
Apparent power is defined as the maximum power that can be
delivered to a load. Vrms and Irms are the effective voltage and
current delivered to the load, respectively. Therefore, the apparent
power (AP) = Vrms × Irms. This equation is independent of the
phase angle between the current and the voltage.
Equation 31 gives an expression of the instantaneous power
signal in an ac system with a phase shift.
() 2 sin( )
rms
vt V t
ω
= (28)
()
)sin(2 θ+ω= tIti rms (29)
)()()( titvtp ×= (30)
()
)2cos()cos( θ+ω−θ= tIVIVtp rmsrmsrmsrms (31)
Figure 76 illustrates the signal processing for the calculation of
the apparent power in the ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569.
The apparent power signal can be read from the waveform register
by setting the WAVMODE register (Address 0x0D) and setting the
WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB). Like the current and voltage channel waveform
sampling modes, the waveform data is available at sample rates
of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and 3.2 kSPS.
The gain of the apparent energy can be adjusted by using the
multiplier and by writing a twos complement, 12-bit word to the
VAGAIN register (VAGAIN[11:0], Address 0x1F). Equation 32
shows how the gain adjustment is related to the contents of the
VAG AIN r e g i s te r.
Output VAGAIN =
⎟
⎠
⎞
⎜
⎝
⎛
⎭
⎬
⎫
⎩
⎨
⎧+× 12
2
1VAGAIN
PowerApparent (32)
For example, when 0x7FF is written to the VAGAIN register, the
power output is scaled up by 50% (0x7FF = 2047d, 2047/212 = 0.5).
Similarly, 0x800 = −2047d (signed twos complement) and power
output is scaled by −50%. Each LSB represents 0.0244% of the
power output. The apparent power is calculated with the current
and voltage rms values obtained in the rms blocks of the
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569.
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation register to
calibrate and eliminate the dc component in the rms value (see the
Current Channel RMS Calculation and the Voltage Channel
RMS Calculation section). The voltage and current channels
rms values are then multiplied together in the apparent power
signal processing. Because no additional offsets are created in
the multiplication of the rms values, there is no specific offset
compensation in the apparent power signal processing. The
offset compensation of the apparent power measurement is
done by calibrating each individual rms measurement.
06353-051
V
rms
I
rms
0x1A36E2
APPARENT POWER
SIGNAL (P)
CURRENT RMS SIGNAL – i(t)
VOLTAGE RMS SIGNAL – v(t)
0x00
0x1CF68C
0x00
0x1CF68C
VAGAIN
TO
DIGITAL-TO-FREQUENCY
CONVERTER
VARMSCFCON
Figure 76. Apparent Power Signal Processing
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 73 of 152
APPARENT ENERGY CALCULATION
The apparent energy is given as the integral of the apparent power.
∫
=dttPowerApparentEnergyApparent )( (33)
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 achieve the integration of the apparent power signal
by continuously accumulating the apparent power signal in an
internal 48-bit register. The apparent energy register
(VAHR[23:0], Address 0x07) represents the upper 24 bits of this
internal register. This discrete time accumulation or summation
is equivalent to integration in continuous time. Equation 34
expresses the relationship.
⎭
⎬
⎫
⎩
⎨
⎧×= ∑
∞
=
→0
0)(lim n
TTnTPowerApparentEnergyApparent (34)
where:
n is the discrete time sample number.
T is the sample period.
The discrete time sample period (T) for the accumulation
register in the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 is 1.22 µs (5/MCLK).
Figure 77 shows this discrete time integration or accumulation.
The apparent power signal is continuously added to the internal
register. This addition is a signed addition even if the apparent
energy theoretically remains positive.
The 49 bits of the internal register are divided by VADIV. If the
value in the VADIV register (Address 0x26) is 0, the internal
apparent energy register is divided by 1. VADIV is an 8-bit,
unsigned register. The upper 24 bits are then written in the
24-bit apparent energy register (VAHR[23:0], Address 0x07).
The RVAHR register (Address 0x08), which is 24 bits long, is
provided to read the apparent energy. This register is reset to 0
after a read operation.
Note that the apparent energy register is unsigned. By setting the
VAEHF bit (Bit 2) and the VAEOF bit (Bit 5) in the Interrupt
Enable 2 SFR (MIRQENM, Address 0xDA), the device can be
configured to issue an ADE interrupt to the 8052 core when the
apparent energy register is half-full or when an overflow occurs.
The half-full interrupt for the unsigned apparent energy register
is based on 24 bits as opposed to 23 bits for the signed active
energy register.
Integration Time Under Steady Load: Apparent Energy
As mentioned in the Apparent Energy Calculation section, the
discrete time sample period (T) for the accumulation register is
1.22 µs (5/MCLK). With full-scale sinusoidal signals on the
analog inputs and the VAGAIN register (Address 0x1F) set to
0x000, the average word value from the apparent power stage is
0x1A36E2 (see the Apparent Power Calculation section). The
maximum value that can be stored in the apparent energy
register before it overflows is 224 or 0xFF,FFFF. The average
word value is added to the internal register, which can store 248
or 0xFFFF,FFFF,FFFF before it overflows. Therefore, the
integration time under these conditions with VADIV = 0 is
calculated as follows:
Time =
min33.3sec199s22.1
0xD055
FFFFFFFF,0xFFFF, ==μ× (35)
When VADIV is set to a value different from 0, the integration
time varies, as shown in Equation 36.
Time = TimeWDIV = 0 × VADIV (36)
06353-052
VADIV
APPARENT POWER
or
I
rms
+
+
VAHR[23:0]
APPARENT POWER OR I
rms
IS
ACCUMULATED (INTEGRATED)
IN THE APPARENT ENERGY
REGISTER
23 0
48
0
48 0
%
TIME (nT)
T
APPARENT
POWER SIGNAL = P
Figure 77. Apparent Energy Calculation
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 74 of 152
Apparent Energy Pulse Output
All the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 circuitry has a pulse output whose frequency is
proportional to apparent power (see the Energy-to-Frequency
Conversion section). This pulse frequency output uses the
calibrated signal after VAGAIN. This output can also be used to
output a pulse whose frequency is proportional to Irms. The pulse
output is active low and should preferably be connected to an
LED, as shown in Figure 80.
Line Apparent Energy Accumulation
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 are designed with a special apparent energy
accumulation mode that simplifies the calibration process. By
using the on-chip, zero-crossing detection, the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
accumulate the apparent power signal in the LVAHR register
(Address 0x09) for an integral number of half cycles, as shown in
Figure 78. The line apparent energy accumulation mode is
always active.
The number of half-line cycles is specified in the LINCYC
register (Address 0x12), which is an unsigned 16-bit register.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 can accumulate apparent power for up to 65,535
combined half cycles. Because the apparent power is integrated
on the same integral number of line cycles as the line active
register and reactive energy register, these values can easily be
compared. The energies are calculated more accurately because
of this precise timing control and provide all the information
needed for reactive power and power factor calculation.
At the end of an energy calibration cycle, the CYCEND flag (Bit 2)
in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) is set.
If the CYCEND enable bit (Bit 2) in the Interrupt Enable 3 SFR
(MIRQENH, Address 0xDB) is enabled, the 8052 core has a
pending ADE interrupt.
As for LWATTHR, when a new half-line cycle is written
in the LINCYC register (Address 0x12), the LVAHR register
(Address 0x09) is reset and a new accumulation starts at the next
zero crossing. The number of half-line cycles is then counted until
LINCYC is reached.
This implementation provides a valid measurement at the first
CYCEND interrupt after writing to the LINCYC register.
The line apparent energy accumulation uses the same signal
path as the apparent energy accumulation. The LSB size of these
two registers is equivalent.
Apparent Power No Load Detection
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 include a no load threshold feature on the apparent
power that eliminates any creep effects in the meter. The ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 accomplish
this by not accumulating energy if the multiplier output is below
the no load threshold. When the apparent power is below the
no load threshold, the VANOLOAD flag (Bit 2) in the Interrupt
Status 1 SFR (MIRQSTL, Address 0xDC) is set. If the VANOLOAD
bit (Bit 2) is set in the Interrupt Enable 1 SFR (MIRQENL,
Address 0xD9), the 8052 core has a pending ADE interrupt.
The ADE interrupt stays active until the APNOLOAD status bit
is cleared (see the Energy Measurement Interrupts section).
The no load threshold level is selectable by setting the
VANOLOAD bits (Bits[5:4]) in the NLMODE register (Address
0x0E). Setting these bits to 0b00 disables the no load detection,
and setting them to 0b01, 0b10, or 0b11 sets the no load
detection threshold to 0.030%, 0.015%, and 0.0075% of the full-
scale output frequency of the multiplier, respectively.
This no load threshold can also be applied to the Irms pulse
output when selected. In this case, the level of no load threshold
is the same as for the apparent energy.
AMPERE-HOUR ACCUMULATION
In a tampering situation where no voltage is available to the energy
meter, the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 are capable of accumulating the ampere-hour instead of
apparent power into the VAHR, RVAHR, and LVAHR. When the
VARMSCFCON bit (Bit 3) of the MODE2 register (Address 0x0C)
is set, the VAHR, RVAHR, and LVAHR, and the input for the
digital-to-frequency converter accumulate Irms instead of apparent
power. All the signal processing and calibration registers
available for apparent power and energy accumulation remain
the same when ampere-hour accumulation is selected. However,
the scaling difference between Irms and apparent power requires
independent values for gain calibration in the VAGAIN
(Address 0x1F), VADIV (Address 0x26), CFxNUM (Address
0x27 and Address 0x29), and CFxDEN (Address 0x28 and
Address 0x2A) registers.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 75 of 152
06353-053
LPF1
++
LVAHR[23:0]
LVAHR REGISTER IS
UPDATED EVERY LINCYC
ZERO CROSSING WITH THE
TOTAL APPARENT ENERGY
DURING THAT DURATION
FROM
VOLTAGE CHANNEL
ADC
23 0
LINCYC[15:0]
48 0
%
ZERO-CROSSING
DETECTION
CALIBR
ATI ON
CONTROL
VADIV[7:0]
APPARENT POWER
or I
rms
Figure 78. Line Cycle Apparent Energy Accumulation
ENERGY-TO-FREQUENCY CONVERSION
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 also provide two energy-to-frequency conversions for
calibration purposes. After initial calibration at manufacturing,
the manufacturer or end customer often verifies the energy meter
calibration. One convenient way to do this is for the manufacturer
to provide an output frequency that is proportional to the active
power, reactive power, apparent power, or Irms under steady load
conditions. This output frequency can provide a simple single-
wire, optically isolated interface to external calibration equipment.
Figure 79 illustrates the energy-to-frequency conversion in the
ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569.
VAR*
VA
CFxSEL[1:0]
WATT
VARMSCFCON
*AVAILABLE ONLY IN THE ADE7569 AND ADE7169
MODE2 REGISTER 0x0C
I
rms
CFx PULSE
OUTPUT
CFxNUM
CFxDEN
÷
DFC
06353-054
Figure 79. Energy-to-Frequency Conversion
Two digital-to-frequency converters (DFC) are used to generate
the pulsed outputs. When WDIV = 0 or 1, the DFC generates a
pulse each time 1 LSB in the energy register is accumulated. An
output pulse is generated when a CFxNUM/CFxDEN number
of pulses is generated at the DFC output. Under steady load
conditions, the output frequency is proportional to the active
power, reactive power, apparent power, or Irms, depending on the
CFxSEL bits in the MODE2 register (Address 0x0C).
Both pulse outputs can be enabled or disabled by clearing or
setting the DISCF1 bit (Bit 1) and the DISCF2 bit (Bit 2) in the
MODE1 register (Address 0x0B), respectively.
Both pulse outputs set separate flags in the Interrupt Status 2 SFR
(MIRQSTM, Address 0xDD): CF1 (Bit 6) and CF2 (Bit 7). If the
CF1 enable bit (Bit 6) and CF2 enable bit (Bit 7) in the Interrupt
Enable 2 SFR (MIRQENM, Address 0xDA) are set, the 8052 core
has a pending ADE interrupt. The ADE interrupt stays active
until the CF1 or CF2 status bit is cleared (see the Energy
Measurement Interrupts section).
Pulse Output Configuration
The two pulse output circuits have separate configuration bits
in the MODE2 register (Address 0x0C). Setting the CFxSEL bits
to 0b00, 0b01, or 0b1X configures the DFC to create a pulse
output proportional to active power , reactive power (ADE7169/
ADE7569 only), or apparent power or Irms, respectively.
The selection between Irms and apparent power is done by the
VARMSCFCON bit in the MODE2 register (Address 0x0C).
With this selection, CF2 cannot be proportional to apparent
power if CF1 is proportional to Irms, and CF1 cannot be
proportional to apparent power if CF2 is proportional to Irms.
Pulse Output Characteristic
The pulse output for both DFCs stays low for 90 ms if the pulse
period is longer than 180 ms (5.56 Hz). If the pulse period is
shorter than 180 ms, the duty cycle of the pulse output is 50%.
The pulse output is active low and should be connected to an
LED, as shown in Figure 80.
V
DD
CF
06353-055
Figure 80. CF Pulse Output
The maximum output frequency with ac input signals at
full scale and with CFxNUM = 0x00 and CFxDEN = 0x00
is approximately 21.1 kHz.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 incorporate two registers per DFC, CFxNUM[15:0]
and CFxDEN[15:0], to set the CFx frequency. These unsigned,
16-bit registers can be used to adjust the CFx frequency to a wide
range of values. These frequency scaling registers are 16-bit
registers that can scale the output frequency by 1/216 to 1 with
a step of 1/216.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 76 of 152
If 0 is written to any of these registers, 1 is applied to the register.
The ratio of CFxNUM/CFxDEN should be less than 1 to ensure
proper operation. If the ratio of the CFxNUM/CFxDEN registers
is greater than 1, the register values are adjusted to a ratio of 1.
For example, if the output frequency is 1.562 kHz, and the
content of CFxDEN is 0 (0x000), the output frequency can be
set to 6.1 Hz by writing 0xFF to the CFxDEN register.
ENERGY REGISTER SCALING
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 provide measurements of active, reactive, and
apparent energies that use separate paths and filtering for
calculation. The difference in data paths can result in small
differences in LSB weight between active, reactive, and apparent
energy registers. These measurements are internally compensated
so that the scaling is nearly one to one. The relationship between
these registers is shown in Table 4 7.
Table 47. Energy Registers Scaling
Line Frequency = 50 Hz Line Frequency = 60 Hz Integrator
Var = 0.9952 × Watt Var = 0.9949 × Watt Off
VA = 0.9978 × Watt VA = 1.0015 × Watt Off
Var = 0.9997 × Watt Var = 0.9999 × Watt On
VA = 0.9977 × Watt VA = 1.0015 × Watt On
ENERGY MEASUREMENT INTERRUPTS
The energy measurement part of the ADE7116/ADE7156/
ADE7166/ADE7169/ADE7566/ADE7569 has its own interrupt
vector for the 8052 core, Vector Address 0x004B (see the
Interrupt Vectors section). The bits set in the Interrupt Enable 1
SFR (MIRQENL, Address 0xD9), Interrupt Enable 2 SFR
(MIRQENM, Address 0xDA), and Interrupt Enable 3 SFR
(MIRQENH, Address 0xDB) enable the energy measurement
interrupts that are allowed to interrupt the 8052 core. If an
event is not enabled, it cannot create a system interrupt.
The ADE interrupt stays active until the status bit that has created
the interrupt is cleared. The status bit is cleared when a 0 is
written to this register bit.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 77 of 152
TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS
The ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 include
temperature measurements as well as battery and supply voltage
measurements. (This feature is not available in the ADE7116.)
These measurements enable many forms of compensation. The
temperature and supply voltage measurements can be used to
compensate external circuitry. The RTC can be calibrated over
temperature to ensure that it does not drift. Supply voltage
measurements allow the LCD contrast to be maintained despite
variations in voltage. Battery measurements allow low battery
detection to be performed. All ADC measurements are
configured through the SFRs, as shown in Tabl e 48.
The temperature, battery, and supply voltage measurements can
be configured to continue functioning in PSM1 and PSM2.
Keeping the temperature measurement active ensures that it is
not necessary to wait for the temperature measurement to settle
before using it for compensation.
Table 48. Temperature, Battery, and Supply Voltage Measurement SFRs
SFR Address R/W Mnemonic Description
0xF9 R/W STRBPER Peripheral ADC strobe period (see Table 49).
0xF3 R/W DIFFPROG Temperature and supply delta (see Table 50).
0xD8 R/W ADCGO Start ADC measurement (see Table 51).
0xFA R/W BATVTH Battery detection threshold (see Table 52).
0xEF R/W VDCINADC VDCIN ADC value (see Table 53).
0xDF R/W BATADC Battery ADC value (see Table 54).
0xD7 R/W TEMPADC Temperature ADC value (see Table 55).
Table 49. Peripheral ADC Strobe Period SFR (STRBPER, Address 0xF9)
Bit Mnemonic Default Description
[7:6] Reserved 00 These bits must be kept at 0 for proper operation.
[5:4] VDCIN_PERIOD 0 Period for background external voltage measurements.
VDCIN_PERIOD Result
00 No VDCIN measurement
01 8 min
10 2 min
11 1 min
[3:2] BATT_PERIOD 0 Period for background battery level measurements.
BATT_PERIOD Result
00 No battery measurement
01 16 min
10 4 min
11 1 min
[1:0] TEMP_PERIOD 0 Period for background temperature measurements.
TEMP_PERIOD Result
00 No temperature measurement
01 8 min
10 2 min
11 1 min
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 78 of 152
Table 50. Temperature and Supply Delta SFR (DIFFPROG, Address 0xF3)
Bit Mnemonic Default Description
[7:6] Reserved 0 Reserved.
[5:3] TEMP_DIFF 0 Difference threshold between last temperature measurement interrupting 8052 and new
temperature measurement that should interrupt 8052.
TEMP_DIFF Result
000 No interrupt
001 1 LSB (≈ 0.8°C)
010 2 LSB (≈ 1.6°C)
011 3 LSB (≈ 2.4°C)
100 4 LSB (≈ 3.2°C)
101 5 LSB (≈ 4°C)
110 6 LSB (≈ 4.8°C)
111 Every temperature measurement
[2:0] VDCIN_DIFF 0 Difference threshold between last external voltage measurement interrupting 8052 and new
external measurement that should interrupt 8052.
VDCIN_DIFF Result
000 No interrupt
001 1 LSB (≈ 120 mV)
010 2 LSB (≈ 240 mV)
011 3 LSB (≈ 360 mV)
100 4 LSB (≈ 480 mV)
101 5 LSB (≈ 600 mV)
110 6 LSB (≈ 720 mV)
111 Every VDCIN measurement
Table 51. Start ADC Measurement SFR (ADCGO, Address 0xD8)
Bit Address Mnemonic Default Description
7 0xDF PLLACK 0 Set this bit to clear the PLL fault bit, PLL_FLT, in the PERIPH register (Address
0xF4). A PLL fault is generated if a reset is caused because the PLL lost lock.
[6:3] 0xDE to 0xDB Reserved 0 Reserved.
2 0xDA VDCIN_ADC_GO 0 Set this bit to initiate an external voltage measurement. This bit is cleared
when the measurement request is received by the ADC.
1 0xD9 TEMP_ADC_GO 0 Set this bit to initiate a temperature measurement. This bit is cleared when
the measurement request is received by the ADC.
0 0xD8 BATT_ADC_GO 0 Set this bit to initiate a battery measurement. This bit is cleared when the
measurement request is received by the ADC.
Table 52. Battery Detection Threshold SFR (BATVTH, Address 0xFA)
Bit Mnemonic Default Description
[7:0] BATVTH 0 The battery ADC value is compared to this register, the battery threshold register. If
BATADC is lower than the threshold, an interrupt is generated.
Table 53. VDCIN ADC Value SFR (VDCINADC, Address 0xEF)
Bit Mnemonic Default Description
[7:0] VDCINADC 0 The VDCINADC value in this register is updated when an ADC interrupt occurs.
Table 54. Battery ADC Value SFR (BATADC, Address 0xDF)
Bit Mnemonic Default Description
[7:0] BATADC 0 The battery ADC value in this register is updated when an ADC interrupt occurs.
Table 55. Temperature ADC Value SFR (TEMPADC, Address 0xD7)
Bit Mnemonic Default Description
[7:0] TEMPADC 0 The temperature ADC value in this register is updated when an ADC interrupt occurs.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 79 of 152
TEMPERATURE MEASUREMENT
To provide a digital temperature measurement, each ADE7156/
ADE7166/ADE7169/ADE7566/ADE7569 includes a dedicated
ADC. An 8-bit temperature ADC value SFR (TEMPADC,
Address 0xD7) holds the results of the temperature conversion.
The resolution of the temperature measurement is 0.78°C/LSB.
There are two ways to initiate a temperature conversion: a single
temperature measurement or background temperature
measurements.
Single Temperature Measurement
Set the TEMP_ADC_GO bit (Bit 1) in the start ADC measure-
ment SFR (ADCGO, Address 0xD8) to obtain a temperature
measurement (see Table 51). An interrupt is generated when the
conversion is complete and when the temperature measurement
is available in the temperature ADC value SFR (TEMPADC,
Address 0xD7).
Background Temperature Measurements
Background temperature measurements are disabled by default.
To configure the background temperature measurement mode,
set a temperature measurement interval in the peripheral ADC
strobe period SFR (STRBPER, Address 0xF9). Temperature
measurements are then performed periodically in the background
(see Table 49).
When a temperature conversion completes, the new temperature
ADC value is compared to the last temperature ADC value that
created an interrupt. If the absolute difference between the two
values is greater than the setting in the TEMP_DIFF bits in the
temperature and supply delta SFR (DIFFPROG, Address 0xF3),
a TEMPADC interrupt is generated (see Table 50). This allows
temperature measurements to take place completely in the
background, requiring MCU activity only if the temperature
changes more than a configurable delta.
To set up background temperature measurement,
1. Initiate a single temperature measurement by setting the
TEMP_ADC_GO bit in the start ADC measurement SFR
(ADCGO, Address 0xD8).
2. Upon completion of this measurement, configure the
TEMP_DIFF bits in the temperature and supply delta SFR
(DIFFPROG, Address 0xF3) to establish the change in
temperature that triggers an interrupt.
3. Set up the interval for background temperature measurements
by configuring the TEMP_PERIOD[1:0] bits in the periph-
eral ADC strobe period SFR (STRBPER, Address 0xF9).
Temperature ADC in PSM0, PSM1, and PSM2
Depending on the operating mode of the ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569, a temperature conversion is
initiated only by certain actions.
• In PSM0 operating mode, the 8052 is active. Temperature
measurements are available in the background measurement
mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active, and the part is
battery powered. Single temperature measurements can be
initiated by setting the TEMP_ADC_GO bit in the start
ADC measurement SFR (ADCGO, Address 0xD8).
Background temperature measurements are not available.
• In PSM2 operating mode, the 8052 is not active.
Temperature conversions are available through the
background measurement mode only.
The temperature ADC value SFR (TEMPADC, Address 0xD7) is
updated with a new value only when a temperature ADC
interrupt occurs.
Temperature ADC Interrupt
The temperature ADC can generate an ADC interrupt when at
least one of the following conditions occurs:
• The difference between the new temperature ADC value and
the last temperature ADC value generating an ADC interrupt
is larger than the value set in the TEMP_DIFF bits.
• The temperature ADC conversion, initiated by setting the
start ADC measurement SFR (ADCGO, Address 0xD8),
finishes.
When the ADC interrupt occurs, a new value is available in the
temperature ADC value SFR (TEMPADC, Address 0xD7). Note
that there is no flag associated with this interrupt.
BATTERY MEASUREMENT
To provide a digital battery measurement, each ADE7156/
ADE7166/ADE7169/ADE7566/ADE7569 includes a dedicated
ADC. The battery measurement is available in the 8-bit battery
ADC value SFR (BATADC, Address 0xDF). The battery
measurement has a resolution of 14.6 mV/LSB. A battery
conversion can be initiated by two methods: a single battery
measurement or background battery measurements.
Single Battery Measurement
Set the BATT_ADC_GO bit (Bit 0) in the start ADC measurement
SFR (ADCGO, Address 0xD8) to obtain a battery measurement.
An interrupt is generated when the conversion is done and
when the battery measurement is available in the battery ADC
value SFR (BATADC, Address 0xDF).
Background Battery Measurements
To configure background measurements for the battery, establish
a measurement interval in the peripheral ADC strobe period
SFR (STRBPER, Address 0xF9). Battery measurements are then
performed periodically in the background (see Table 49).
When a battery conversion completes, the battery ADC value is
compared to the low battery threshold, established in the battery
detection threshold SFR (BATVTH, Address 0xFA). If the battery
ADC value is below this threshold, a low battery flag is set. This
low battery flag is the FBAT bit (Bit 2) in the power manage-
ment interrupt flag SFR (IPSMF, Address 0xF8), used for power
supply management.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 80 of 152
This low battery flag can be enabled to generate the PSM
interrupt by setting the EBAT bit (Bit 2) in the power
management interrupt enable SFR (IPSME, Address 0xEC).
This method allows battery measurements to take place
completely in the background, requiring MCU activity only if the
battery drops below a user-specified threshold. To set up
background battery measurements, follow these steps:
1. Configure the battery detection threshold SFR (BATVTH,
Address 0xFA) to establish a low battery threshold. If the
BATADC measurement is below this threshold, the FBAT
bit (Bit 2) in the power management interrupt flag SFR
(IPSMF, Address 0xF8) is set.
2. Set up the interval for background battery measurements
by configuring the BATT_PERIOD bits in the peripheral
ADC strobe period SFR (STRBPER, Address 0xF9).
Battery ADC in PSM0, PSM1, and PSM2 Modes
Depending on the operating mode, a battery conversion is
initiated only by certain actions.
• In PSM0 operating mode, the 8052 is active. Battery
measurements are available in the background measure-
ment mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active and the part is
battery powered. Single battery measurements can be
initiated by setting the BATT_ADC_GO bit (Bit 0) in the
start ADC measurement SFR (ADCGO, Address 0xD8).
Background battery measurements are not available.
• In PSM2 operating mode, the 8052 is not active. Unlike
temperature and VDCIN measurements, the battery
conversions are not available in this mode.
Battery ADC Interrupt
The battery ADC can generate an ADC interrupt when at least
one of the following conditions occurs:
• The new battery ADC value is smaller than the value set in
the battery detection threshold SFR (BATVTH, Address
0xFA), indicating a battery voltage loss.
• A single battery measurement initiated by setting the
BATT_ADC_GO bit finishes.
When the battery flag (FBAT, Bit 2) is set in the power manage-
ment interrupt flag SFR (IPSMF, Address 0xF8), a new ADC
value is available in the battery ADC value SFR (BATADC,
Address 0xDF). This battery flag can be enabled as a source of
the PSM interrupt to generate a PSM interrupt every time the
battery drops below a set voltage threshold or after a single
conversion initiated by setting the BATT_ADC_GO bit is ready.
The battery ADC value SFR (BATADC, Address 0xDF) is
updated with a new value only when the battery flag (FBAT) is
set in the power management interrupt flag SFR (IPSMF,
Address 0xF8).
EXTERNAL VOLTAGE MEASUREMENT
The ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
include a dedicated ADC to provide a digital measurement of
an external voltage on the VDCIN pin. An 8-bit SFR, the VDCIN
ADC value SFR (VDCINADC, Address 0xEF), holds the results
of the conversion. The resolution of the external voltage measure-
ment is 15.3 mV/LSB. There are two ways to initiate an external
voltage conversion: a single external voltage measurement or
background external voltage measurements.
Single External Voltage Measurement
To obtain an external voltage measurement, set the
VDCIN_ADC_GO bit (Bit 2) in the start ADC measurement
SFR (ADCGO, Address 0xD8). An interrupt is generated when
the conversion is done and when the external voltage measure-
ment is available in the VDCIN ADC value SFR (VDCINADC,
Address 0xEF).
Background External Voltage Measurements
Background external voltage measurements are disabled by
default. To configure the background external voltage
measurement mode, set an external voltage measurement
interval in the peripheral ADC strobe period SFR (STRBPER,
Address 0xF9). External voltage measurements are performed
periodically in the background (see Table 4 9).
When an external voltage conversion is complete, the new
external voltage ADC value is compared to the last external
voltage ADC value that created an interrupt. If the absolute diff-
erence between the two values is greater than the setting in the
VDCIN_DIFF[2:0] bits in the temperature and supply delta SFR
(DIFFPROG, Address 0xF3), a VDCIN ADC flag is set. This VDCIN
ADC flag is FVADC (Bit 3) in the power management interrupt
flag SFR (IPSMF, Address 0xF8), which is used for power supply
management. This VDCIN ADC flag can be enabled to generate a
PSM interrupt by setting the EVADC bit (Bit 3) in the power
management interrupt enable SFR (IPSME, Address 0xEC).
This method allows external voltage measurements to take place
completely in the background, requiring MCU activity only if
the external voltage has changed more than a configurable delta.
To set up background external voltage measurements, follow
these steps:
1. Initiate a single external voltage measurement by setting
the VDCIN_ADC_GO bit (Bit 2) in the start ADC
measurement SFR (ADCGO, Address 0xD8).
2. Upon completion of this measurement, configure the
VDCIN_DIFF[2:0] bits to establish the change in voltage
that sets the FVDCIN bit (Bit 0) in the power management
interrupt flag SFR (IPSMF, Address 0xF8).
3. Set up the interval for background external voltage measure-
ments by configuring the VDCIN_PERIOD bits in the
peripheral ADC strobe period SFR (STRBPER, Address 0xF9).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 81 of 152
External Voltage ADC in PSM0, PSM1, and PSM2 Modes
An external voltage conversion is initiated only by certain actions
that depend on the operating mode of the ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569.
• In PSM0 operating mode, the 8052 is active. External
voltage measurements are available in the background
measurement mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active and the part is
powered from battery. Single external voltage measurements
can be initiated by setting the VDCIN_ADC_GO bit (Bit 2)
in the start ADC measurement SFR (ADCGO, Address
0xD8). Background external voltage measurements are not
available.
• In PSM2 operating mode, the 8052 is not active. External
voltage conversions are available through the background
measurement mode only.
The external voltage ADC in the VDCIN ADC value SFR
(VDCINADC, Address 0xEF) is updated with a new value only
when an external voltage ADC interrupt occurs.
External Voltage ADC Interrupt
The external voltage ADC can generate an ADC interrupt when
at least one of the following conditions occurs:
• The difference between the new external voltage ADC
value and the last external voltage ADC value generating
an ADC interrupt is larger than the value set in the
VDCIN_DIFF[2:0] bits in the temperature and supply
delta SFR (DIFFPROG, Address 0xF3).
• The external voltage ADC conversion initiated by setting
VDCIN_ADC_GO, finishes.
When the ADC interrupt occurs, a new value is available in the
VDCIN ADC value SFR (VDCINADC, Address 0xEF). Note that
there is no flag associated with this interrupt.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 82 of 152
8052 MCU CORE ARCHITECTURE
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 have an 8052 MCU core and use the 8052 instruction
set. Some of the standard 8052 peripherals, such as the UART,
have been enhanced. This section describes the standard 8052
core and enhancements that have been made to it in the
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569.
The special function register (SFR) space is mapped into the upper
128 bytes of internal data memory space and is accessed by direct
addressing only. It provides an interface between the CPU and
all on-chip peripherals. See Figure 81 for a block diagram of the
programming model for the ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569 via the SFR area.
All registers except the program counter (PC), instruction
register (IR), and the four general-purpose register banks
reside in the SFR area. The SFR registers include control,
configuration, and data registers that provide an interface
between the CPU and all on-chip peripherals.
ENERGY
MEASUREMENT
PC
16kB ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE
PROGRAM/DATA
MEMORY
8052
COMPATIBLE
CORE
256 BYTES XRAM OTHER ON-CHIP
PERIPHERALS:
• SERIAL I/O
• WDT
• TIMERS
BATTERY
ADC
LCD DRIVER
TEMPERATURE
ADC
RTC
POWER
MANAGEMENT
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
IR
STACK
256 BYTES
GENERAL-
PURPOSE
RAM
REGISTER
BANKS
06353-056
Figure 81. Block Diagram Showing Programming Model via the SFRs
MCU REGISTERS
The registers used by the MCU are summarized in this section.
Table 56. 8052 SFRs
SFR Address Bit Addressable Description
ACC 0xE0 Yes Accumulator.
B 0xF0 Yes Auxiliary math.
PSW 0xD0 Yes Program status word (see Table 57).
PCON 0x87 No Program control (see Table 58).
DPL 0x82 No Data pointer low (see Table 59).
DPH 0x83 No Data pointer high (see Table 60).
DPTR 0x82 and 0x83 No Data pointer (see Table 61).
SP 0x81 No Stack pointer (see Table 62).
CFG 0xAF No Configuration (see Table 63).
Table 57. Program Status Word SFR (PSW, Address 0xD0)
Bit Bit Address Mnemonic Description
7 0xD7 CY Carry flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
6 0xD6 AC Auxiliary carry flag. Modified by ADD and ADDC instructions.
5 0xD5 F0 General-purpose flag available to the user.
[4:3] 0xD4, 0xD3 RS1, RS0 Register bank select bits.
RS1 RS0 Selected Bank
0 0 0
0 1 1
1 0 2
1 1 3
2 0xD2 OV Overflow flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
1 0xD1 F1 General-purpose flag available to the user.
0 0xD0 P Parity bit. The number of bits set in the accumulator added to the value of the parity bit is
always an even number.
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Rev. B | Page 83 of 152
Table 58. Program Control SFR (PCON, Address 0x87)
Bit Mnemonic Default Description
7 SMOD 0 Double baud rate control.
[6:0] Reserved 0 Reserved. These bits must be kept at 0 for proper operation.
Table 59. Data Pointer Low SFR (DPL, Address 0x82)
Bit Mnemonic Default Description
[7:0] DPL 0 These bits contain the low byte of the data pointer.
Table 60. Data Pointer High SFR (DPH, Address 0x83)
Bit Mnemonic Default Description
[7:0] DPH 0 These bits contain the high byte of the data pointer.
Table 61. Data Pointer SFR (DPTR, Address 0x82 and Address 0x83)
Bit Mnemonic Default Description
[15:0] DP 0 These bits contain the 2-byte address of the data pointer. DPTR is a combination of the DPH and DPL
SFRs.
Table 62. Stack Pointer SFR (SP, Address 0x81)
Bit Mnemonic Default Description
[7:0] SP 7 These bits contain the eight LSBs of the pointer for the stack.
Table 63. Configuration SFR (CFG, Address 0xAF)
Bit Mnemonic Default Description
7 Reserved 1 Reserved. This bit should be left set for proper operation.
6 EXTEN 0 Enhanced UART enable bit.
EXTEN Result
0 Standard 8052 UART without enhanced error-checking features.
1 Enhanced UART with enhanced error checking (see the UART Additional
Features section).
5 SCPS 0 Synchronous communication selection bit.
SCPS Result
0 I2C port is selected for control of the shared I2C/SPI pins and SFRs.
1 SPI port is selected for control of the shared I2C/SPI pins and SFRs.
4 MOD38EN 0 38 kHz modulation enable bit.
MOD38EN Result
0 38 kHz modulation is disabled.
1 38 kHz modulation is enabled on the pins selected by the MOD38[7:0]
bits in the extended port configuration SFR (EPCFG, Address 0x9F).
[3:2] Reserved 00 Reserved. These bits should be kept at 0 for proper operation.
[1:0] XREN1, XREN0 01 XREN[1:0] Result
XREN1 OR XREN0 = 1 Enable MOVX instruction to use 256 bytes of extended RAM.
XREN1 AND XREN0 = 0 Disable MOVX instruction.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 84 of 152
BASIC 8052 REGISTERS
Program Counter (PC)
The program counter holds the 2-byte address of the next
instruction to be fetched. The PC is initialized with 0x00 at reset
and is incremented after each instruction is performed. Note
that the amount that is added to the PC depends on the number
of bytes in the instruction, therefore, the increment can range
from one to three bytes. The program counter is not directly
accessible to the user but can be directly modified by CALL and
JMP instructions that change which part of the program is active.
Instruction Register (IR)
The instruction register holds the opcode of the instruction
being executed. The opcode is the binary code that results from
assembling an instruction. This register is not directly accessible
to the user.
Register Banks
There are four banks, each containing an 8-byte-wide register, for
a total of 32 bytes of registers. These registers are convenient for
temporary storage of mathematical operands. An instruction
involving the accumulator and a register can be executed in one
clock cycle, as opposed to two clock cycles to perform an
instruction involving the accumulator and a literal or a byte of
general-purpose RAM. The register banks are located in the first
32 bytes of RAM.
The active register bank is selected by the RS0 and RS1 bits in
the program status word SFR (PSW, Address 0xD0).
Accumulator
The accumulator is a working register, storing the results of
many arithmetic or logical operations. The accumulator is used
in more than half of the 8052 instructions where it is usually
referred to as A. The program status register (PSW) constantly
monitors the number of bits that are set in the accumulator to
determine if it has even or odd parity. The accumulator is stored
in the SFR space (see Tabl e 56).
B Register
The B register is used by the multiply and divide instructions,
MUL AB and DIV AB to hold one of the operands. Because it is
not used for many instructions, it can be used as a scratch pad
register like those in the register banks. The B register is stored
in the SFR space (see Tabl e 56).
Program Status Word (PSW)
The PSW register (PSW, Address 0xD0) reflects the status of
arithmetic and logical operations through carry, auxiliary carry,
and overflow flags. The parity flag reflects the parity of the
contents of the accumulator, which can be helpful for
communication protocols. The program status word SFR is bit
addressable.
Data Pointer (DPTR)
The data pointer SFR (DPTR, Address 0x82 and Address 0x83)
is made up of two 8-bit registers: DPL (low byte, Address 0x82),
and DPH (high byte, Address 0x83). These SFRs provide
memory addresses for internal code and data access. The DPTR
can be manipulated as a 16-bit register (DPTR = DPH, DPL) or
as two independent 8-bit registers (DPH and DPL) (see Ta bl e
59 and Table 60).
The 8052 MCU core architecture supports dual data pointers
(see the 8052 MCU Core Architecture section).
Stack Pointer (SP)
The stack pointer SFR (SP, Address 0x81) keeps track of the
current address of the top of the stack. To push a byte of data
onto the stack, the stack pointer is incremented and the data is
moved to the new top of the stack. To pop a byte of data off the
stack, the top byte of data is moved into the awaiting address
and the stack pointer is decremented. The stack is a last in, first
out (LIFO) method of data storage because the most recent
addition to the stack is the first to come off it.
The stack is used during CALL and RET instructions to keep
track of the address to move into the PC when returning from
the function call. The stack is also manipulated when vectoring
for interrupts to keep track of the prior state of the PC.
The stack resides in the internal extended RAM, and the
SP register holds the address of the stack in the extended RAM.
The advantage of this solution is that the stack is segregated to
the internal XRAM. The use of the general-purpose RAM can
be limited to data storage. The use of the extended internal
RAM can be limited to the stack pointer. This separation limits
the chance of data RAM corruption when the stack pointer
overflows in data RAM.
Data can still be stored in XRAM by using the MOVX command.
0x00
0xFF 0xFF
0x00
256 BYTES OF
ON-CHIP XRAM
DATA + STACK
256 BYTES OF
RAM
(DATA)
06353-057
Figure 82. Extended Stack Pointer Operation
To change the default starting address for the stack, move a
value into the stack pointer (SP). For example, to enable the
extended stack pointer and initialize it at the beginning of the
XRAM space, use the following code:
MOV SP,#00H
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 85 of 152
STANDARD 8052 SFRs
The standard 8052 SFRs include the accumulator (ACC), B,
PSW, DPTR, and SP SFRs, as described in the Basic 8052
Registers section. The 8052 also defines standard timers, serial
port interfaces, interrupts, I/O ports, and power-down modes.
Timer SFRs
The 8052 contains three 16-bit timers: the identical Timer 0 and
Timer 1, as well as a Timer 2. These timers can also function as
event counters. Timer 2 has a capture feature in which the value
of the timer can be captured in two 8-bit registers upon the
assertion of an external input signal (see Table 112 and the
Timers section).
Serial Port SFRs
The full-duplex serial port peripheral requires two registers, one
for setting up the baud rate and other communication parameters,
and another byte for the transmit/receive buffer. The ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 also
provide enhanced serial port functionality with a dedicated timer
for baud rate generation with a fractional divisor and additional
error detection. See Table 139 and the UART Serial Interface
section.
Interrupt SFRs
There is a two-tiered interrupt system standard in the 8052 core.
The priority level for each interrupt source is individually
selectable as high or low. The ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569 enhance this interrupt system
by creating, in essence, a third interrupt tier for a highest
priority power supply management interrupt (PSM). See
the Interrupt System section.
I/O Port SFRs
The 8052 core supports four I/O ports, P0 through P3, where
Port 0 and Port 2 are typically used for access to external code
and data spaces. The ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569, unlike standard 8052 products, provide
internal nonvolatile flash memory so that an external code
space is unnecessary. The on-chip LCD driver requires many
pins, some of which are dedicated to LCD functionality, and
others that can be configured as LCD or general-purpose I/O.
Due to the limited number of I/O pins, the
ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569
do not allow access to external code and data spaces.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 provide 20 pins that can be used for general-purpose
I/O. These pins are mapped to Port 0, Port 1, and Port 2 and are
accessed through three bit-addressable 8052 SFRs: P0, P1, and
P2. Another enhanced feature of these parts is that the weak
pull-ups standard on 8052 Port 1, Port 2, and Port 3 can be
disabled to make open-drain outputs, as is standard on Port 0.
The weak pull-ups can be enabled on a pin-by-pin basis. See the
I/O Ports section.
Power Control Register (PCON, Address 0x87)
The 8052 core defines two power-down modes: power-down and
idle. The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 enhance the power control capability of the traditional
8052 MCU with additional power management functions. The
POWCON register is used to define power control-specific
functionality for the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569. The program control SFR (PCON, Address
0x87) is not bit addressable. See the Power Management section.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 have many other peripherals not standard to the
8052 core:
• ADE energy measurement DSP
• RTC
• LCD driver
• Battery switchover/power management
• Temperature ADC
• Battery ADC
• SPI/I2C communication
• Flash memory controller
• Watchdo g ti mer
MEMORY OVERVIEW
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 contain three memory blocks:
• 16 kB of on-chip Flash/EE program and data memory
• 256 bytes of general-purpose RAM
• 256 bytes of internal extended RAM (XRAM)
The 256 bytes of general-purpose RAM share the upper 128 bytes
of its address space with the SFRs. All of the memory spaces are
shown in Figure 81. The addressing mode specifies which
memory space to access.
General-Purpose RAM
General-purpose RAM resides in Memory Location 0x00
through Memory Location 0xFF. It contains the register banks.
11
10
01
00
RESET VALUE OF
STACK POINTER
FOUR BANKS OF EIGHT
REGISTERS R0 TO R7
BIT-ADDRESSABLE
(BIT ADDRESSES)
GENERAL-PURPOSE
AREA
BANKS
SELECTED
VIA
BITS IN PSW
0x
00
0x08
0x10
0x18
0x20
0x30
0x07
0x0F
0x17
0x1F
0x2F
0x7F
06353-058
Figure 83. Lower 128 Bytes of Internal Data Memory
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 86 of 152
Address 0x80 through Address 0xFF of general-purpose RAM
are shared with the SFRs. The mode of addressing determines
which memory space is accessed, as shown in Figure 84.
GENERAL-PURPOSE RAM
SPECIAL FUNCTION REGISTERS (SFRs)
ACCESSIBLE BY
INDIRECT ADDRESSING
ONLY
ACCESSIBLE BY
DIRECT AND INDIRECT
ADDRESSING
ACCESSIBLE BY
DIRECT ADDRESSING
ONLY
0xFF
0x80
0x7F
0x00
06353-059
Figure 84. General-Purpose RAM and SFR Memory Address Overlap
Both direct and indirect addressing can be used to access general-
purpose RAM from 0x00 through 0x7F, but indirect addressing
must be used to access general-purpose RAM with addresses in
the range from 0x80 through 0xFF because they share the same
address space with the SFRs.
The 8052 core also has the means to access individual bits of
certain addresses in the general-purpose RAM and special
function memory spaces. The individual bits of general-purpose
RAM, Address 0x20 to Address 0x2F, can be accessed through
Bit Address 0x00 to Bit Address 0x7F. The benefit of bit
addressing is that the individual bits can be accessed quickly,
without the need for bit masking, which takes more code memory
and execution time. The bit addresses for general-purpose RAM
Address 0x20 through Address 0x2F can be seen in Figure 85.
BYTE
ADDRESS BIT ADDRESSES (HEXA)
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
7F
77
6F
67
5F
57
4F
47
3F
37
2F
27
1F
17
0F
07
7E
76
6E
66
5E
56
4E
46
3E
36
2E
26
1E
16
0E
06
7D
75
6D
65
5D
55
4D
45
3D
35
2D
25
1D
15
0D
05
7C
74
6C
64
5C
54
4C
44
3C
34
2C
24
1C
14
0C
04
7B
73
6B
63
5B
53
4B
43
3B
33
2B
23
1B
13
0B
03
7A
72
6A
62
5A
52
4A
42
3A
32
2A
22
1A
12
0A
02
79
71
69
61
59
51
49
41
39
31
29
21
19
11
09
01
78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
06353-060
Figure 85. Bit Addressable Area of General-Purpose RAM
Bit addressing can be used for instructions that involve Boolean
variable manipulation and program branching (see the
Instruction Set section).
Special Function Registers (SFRs)
Special function registers are registers that affect the function of
the 8052 core or its peripherals. These registers are located in
RAM at Address 0x80 through Address 0xFF. They are accessible
only through direct addressing as shown in Figure 84.
The individual bits of some of the SFRs can be accessed for use
in Boolean and program branching instructions. These SFRs are
labeled as bit-addressable and the bit addresses are given in
Table 15 .
Extended Internal RAM (XRAM)
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 provide 256 bytes of extended on-chip RAM. No
external RAM is supported. This RAM is located in Address
0x00 through Address 0xFF in the extended RAM space. To
select the extended RAM memory space, the extended indirect
addressing modes are used.
256 BYTES OF
EXTENDED INTERNAL
RAM (XRAM)
0x00FF
0x0000
06353-061
Figure 86. Extended Internal RAM (XRAM) Space
Code Memory
Code and data memory is stored in the 16 kB flash memory
space. No external code memory is supported. To access code
memory, code indirect addressing is used.
ADDRESSING MODES
The 8052 core provides several addressing modes. The
addressing mode determines how the core interprets the
memory location or data value specified in assembly language
code. There are six addressing modes, as shown in Table 64.
Table 64. 8052 Addressing Modes
Addressing Mode Example Bytes
Core Clock
Cycles
Immediate MOV A,#A8h 2 2
MOV DPTR,#A8h 3 3
Direct MOV A, A8h 2 2
MOV A, IE 2 2
MOV A, R0 1 1
Indirect MOV A, @R0 1 2
Extended Direct MOVX A, @DPTR 1 4
Extended Indirect MOVX A, @R0 1 4
Code Indirect MOVC A, @A+DPTR 1 4
MOVC A, @A+PC 1 4
JMP @A+ DPTR 1 3
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 87 of 152
Immediate Addressing
In immediate addressing, the expression entered after the
number sign (#) is evaluated by the assembler and stored in the
memory address specified. This number is referred to as a literal
because it refers only to a value and not to a memory location.
Instructions using this addressing mode are slower than those
between two registers because the literal must be stored and
fetched from memory. The expression can be entered as a
symbolic variable or as an arithmetic expression; the value is
computed by the assembler.
Direct Addressing
With direct addressing, the value at the source address is moved
to the destination address. Direct addressing provides the fastest
execution time of all the addressing modes when an instruction
is performed between registers. Note that indirect or direct
addressing modes can be used to access general-purpose RAM
Address 0x00 through Address 0x7F. An instruction with direct
addressing that uses an address between 0x80 and 0xFF refers to
a special function memory location.
Indirect Addressing
With indirect addressing, the value pointed to by the register is
moved to the destination address. For example, to move the
contents of internal RAM Address 0x82 to the accumulator, use
the following two instructions, which require a total of four
clock cycles and three bytes of storage in the program memory:
MOV R0,#82h
MOV A,@R0
Indirect addressing allows addresses to be computed and is
useful for indexing into data arrays stored in RAM.
Note that an instruction that refers to Address 0x00 through
Address 0x7F is referring to internal RAM, and indirect or
direct addressing mode can be used. An instruction with
indirect addressing that uses an address between 0x80 and 0xFF
refers to internal RAM, not to an SFR.
Extended Direct Addressing
The DPTR register (see Table 6 1) is used to access internal
extended RAM in extended indirect addressing mode. The
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
have 256 bytes of XRAM, accessed through MOVX instructions.
External memory spaces are not supported on this device.
In extended direct addressing mode, the DPTR register points
to the address of the byte of extended RAM. The following code
moves the contents of extended RAM Address 0x100 to the
accumulator:
MOV DPTR,#100h
MOVX A,@DPTR
These two instructions require a total of seven clock cycles and
four bytes of storage in the program memory.
Extended Indirect Addressing
The internal extended RAM is accessed through a pointer to the
address in indirect addressing mode. The ADE7116/ADE7156/
ADE7166/ADE7169/ADE7566/ADE7569 have 256 bytes of
internal extended RAM, accessed through MOVX instructions.
External memory is not supported on the devices.
In extended indirect addressing mode, a register holds the address
of the byte of extended RAM. The following code moves the
contents of extended RAM Address 0x80 to the accumulator:
MOV R0,#80h
MOVX A,@R0
These two instructions require six clock cycles and three bytes
of storage.
Note that there are 256 bytes of extended RAM, so both extended
direct and extended indirect addressing can cover the whole
address range. There is a storage and speed advantage to using
extended indirect addressing because the additional byte of
addressing available through the DPTR register that is not
needed is not stored.
From the three examples demonstrating the access of internal
RAM from 0x80 through 0xFF and extended internal RAM
from 0x00 through 0xFF, it can be seen that it is most efficient
to use the entire internal RAM accessible through indirect
access before moving to extended RAM.
Code Indirect Addressing
The internal code memory can be accessed indirectly. This can
be useful for implementing lookup tables and other arrays of
constants that are stored in flash memory. For example, to move
the data stored in flash memory at Address 0x8002 into the
accumulator, use the following code:
MOV DPTR,#8002h
CLR A
MOVX A,@A+DPTR
The accumulator can be used as a variable index into the array
of flash memory located at DPTR.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 88 of 152
INSTRUCTION SET
Table 65 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles,
resulting in a 4-MIPS peak performance. Note that throughout this section, A represents the accumulator.
Table 65. Instruction Set
Mnemonic Description Bytes Cycles
Arithmetic
ADD A,Rn Add register to A 1 1
ADD A,@Ri Add indirect memory to A 1 2
ADD A,dir Add direct byte to A 2 2
ADD A,#data Add immediate to A 2 2
ADDC A,Rn Add register to A with carry 1 1
ADDC A,@Ri Add indirect memory to A with carry 1 2
ADDC A,dir Add direct byte to A with carry 2 2
ADDC A,#data Add immediate to A with carry 2 2
SUBB A,Rn Subtract register from A with borrow 1 1
SUBB A,@Ri Subtract indirect memory from A with borrow 1 2
SUBB A,dir Subtract direct from A with borrow 2 2
SUBB A,#data Subtract immediate from A with borrow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC @ Ri increment indirect memory 1 2
INC dir Increment direct byte 2 2
INC DPTR Increment data pointer 1 3
DEC A Decrement A 1 1
DEC Rn Decrement register 1 1
DEC @Ri Decrement indirect memory 1 2
DEC dir Decrement direct byte 2 2
MUL AB Multiply A by B 1 9
DIV AB Divide A by B 1 9
DA A A Decimal adjust A 1 2
Logic
ANL A,Rn AND register to A 1 1
ANL A,@Ri AND indirect memory to A 1 2
ANL A,dir AND direct byte to A 2 2
ANL A,#data AND immediate to A 2 2
ANL dir,A AND A to direct byte 2 2
ANL dir,#data AND immediate data to direct byte 3 3
ORL A,Rn OR register to A 1 1
ORL A,@Ri OR indirect memory to A 1 2
ORL A,dir OR direct byte to A 2 2
ORL A,#data OR immediate to A 2 2
ORL dir,A OR A to direct byte 2 2
ORL dir,#data OR immediate data to direct byte 3 3
XRL A,Rn Exclusive-OR register to A 1 1
XRL A,@Ri Exclusive-OR indirect memory to A 2 2
XRL A,#data Exclusive-OR immediate to A 2 2
XRL dir,A Exclusive-OR A to direct byte 2 2
XRL A,dir Exclusive-OR indirect memory to A 2 2
XRL dir,#data Exclusive-OR immediate data to direct 3 3
CLR A Clear A 1 1
CPL A Complement A 1 1
SWAP A Swap nibbles of A 1 1
RL A Rotate A left 1 1
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 89 of 152
Mnemonic Description Bytes Cycles
RLC A Rotate A left through carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through carry 1 1
Data Transfer
MOV A,Rn Move register to A 1 1
MOV A,@Ri Move indirect memory to A 1 2
MOV Rn,A Move A to register 1 1
MOV @Ri,A Move A to indirect memory 1 2
MOV A,dir Move direct byte to A 2 2
MOV A,#data Move immediate to A 2 2
MOV Rn,#data Move register to immediate 2 2
MOV dir,A Move A to direct byte 2 2
MOV Rn,dir Move register to direct byte 2 2
MOV dir,Rn Move direct to register 2 2
MOV @Ri,#data Move immediate to indirect memory 2 2
MOV dir,@Ri Move indirect to direct memory 2 2
MOV @Ri,dir Move direct to indirect memory 2 2
MOV dir,dir Move direct byte to direct byte 3 3
MOV dir,#data Move immediate to direct byte 3 3
MOV DPTR,#data Move immediate to data pointer 3 3
MOVC A,@A+DPTR Move code byte relative DPTR to A 1 4
MOVC A,@A+PC Move code byte relative PC to A 1 4
MOVX A,@Ri Move external (A8) data to A 1 4
MOVX A,@DPTR Move external (A16) data to A 1 4
MOVX @Ri,A Move A to external data (A8) 1 4
MOVX @DPTR,A Move A to external data (A16) 1 4
PUSH dir Push direct byte onto stack 2 2
POP dir Pop direct byte from stack 2 2
XCH A,Rn Exchange A and register 1 1
XCH A,@Ri Exchange A and indirect memory 1 2
XCHD A,@Ri Exchange A and indirect memory nibble 1 2
XCH A,dir Exchange A and direct byte 2 2
Boolean
CLR C Clear carry 1 1
CLR bit Clear direct bit 2 2
SETB C Set carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement carry 1 1
CPL bit Complement direct bit 2 2
ANL C,bit AND direct bit and carry 2 2
ANL C,/bit AND direct bit inverse to carry 2 2
ORL C,bit OR direct bit and carry 2 2
ORL C,/bit OR Direct bit inverse to carry 2 2
MOV C,bit Move direct bit to carry 2 2
MOV bit,C Move carry to direct bit 2 2
Branching
JMP @A+DPTR Jump indirect relative to DPTR 1 3
RET Return from subroutine 1 4
RETI Return from interrupt 1 4
ACALL addr11 Absolute jump to subroutine 2 3
AJMP addr11 Absolute jump unconditional 2 3
SJMP rel Short jump (relative address) 2 3
JC rel Jump on carry equal to 1 2 3
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 90 of 152
Mnemonic Description Bytes Cycles
JNC rel Jump on carry equal to 0 2 3
JZ rel Jump on accumulator = 0 2 3
JNZ rel Jump on accumulator ≠ 0 2 3
DJNZ Rn,rel Decrement register, JNZ relative 2 3
LJMP Long jump unconditional 3 4
LCALL addr16 Long jump to subroutine 3 4
JB bit,rel Jump on direct bit = 1 3 4
JNB bit,rel Jump on direct bit = 0 3 4
JBC bit,rel Jump on direct bit = 1 and clear 3 4
CJNE A,dir,rel Compare A, direct JNE relative 3 4
CJNE A,#data,rel Compare A, immediate JNE relative 3 4
CJNE Rn,#data,rel Compare register, immediate JNE relative 3 4
CJNE @Ri,#data,rel Compare indirect, immediate JNE relative 3 4
DJNZ dir,rel Decrement direct byte, JNZ relative 3 4
MISCELLANEOUS
NOP No operation 1 1
READ-MODIFY-WRITE INSTRUCTIONS
Some 8052 instructions read the latch and others read the pin.
The state of the pin is read for instructions that input a port bit.
Instructions that read the latch rather than the pins are the ones
that read a value, possibly change it, and rewrite it to the latch.
Because these instructions involve modifying the port, it is
assumed that the pins being modified are outputs, so the output
state of the pin is read from the latch. This prevents a possible
misinterpretation of the voltage level of a pin. For example, if a
port pin is used to drive the base of a transistor, a 1 is written to
the bit to turn on the transistor. If the CPU reads the same port
bit at the pin rather than the latch, it reads the base voltage of
the transistor and interprets it as Logic 0. Reading the latch
rather than the pin returns the correct value of 1.
The instructions that read the latch rather than the pins are
called read-modify-write instructions and are listed in Table 66.
When the destination operand is a port or a port bit, these
instructions read the latch rather than the pin.
Table 66. Read-Modify-Write Instructions
Instruction Example Description
ANL ANL P0,A Logic AND
ORL ORL P1,A Logic OR
XRL XRL P2,A Logic EX-OR
JBC JBC P1.1,LABEL Jump if bit = 1 and clear bit
CPL CPL P2.0 Complement bit
INC INC P2 Increment
DEC DEC P2 Decrement
DJNZ DJNZ P0,LABEL Decrement and jump if not zero
MOV PX.Y,C1 MOV P0.0,C Move carry to Bit Y of Port X
CLR PX.Y1 CLR P0.0 Clear Bit Y of Port X
SETB PX.Y1 SETB P0.0 Set Bit Y of Port X
1 These instructions read the port byte (all eight bits), modify the addressed
bit, and write the new byte back to the latch.
INSTRUCTIONS THAT AFFECT FLAGS
Many instructions explicitly modify the carry bit, such as the
MOV C bit and CLR C instructions. Other instructions that
affect status flags are listed in this section.
ADD A, Source
This instruction adds the source to the accumulator. No status
flags are referenced by the instruction.
Table 67. ADD A (Source) Affected Status Flags
Flag Description
C Set if there is a carry out of Bit 7. Cleared otherwise.
Used to indicate an overflow if the operands are
unsigned.
OV Set if there is a carry out of Bit 6 or a carry out of Bit 7,
but not if both are set. Used to indicate an overflow for
signed addition. This flag is set if two positive operands
yield a negative result or if two negative operands yield
a positive result.
AC Set if there is a carry out of Bit 3. Cleared otherwise.
ADDC A, Source
This instruction adds the source and the carry bit to the accu-
mulator. The carry status flag is referenced by the instruction.
Table 68. ADDC A (Source) Affected Flags
Flag Description
C Set if there is a carry out of Bit 7. Cleared otherwise.
Used to indicate an overflow if the operands are
unsigned.
OV Set if there is a carry out of Bit 6 or a carry out of Bit 7, but
not if both are set. Used to indicate an overflow for
signed addition. This flag is set if two positive operands
yield a negative result or if two negative operands yield
a positive result.
AC Set if there is a carry out of Bit 3. Cleared otherwise.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 91 of 152
SUBB A, Source
This instruction subtracts the source byte and the carry
(borrow) flag from the accumulator. It references the carry
(borrow) status flag.
Table 69. SUBB A (Source) Affected Status Flags
Flag Description
C Set if there is a borrow needed for Bit 7. Cleared
otherwise. Used to indicate an overflow if the
operands are unsigned.
OV Set if there is a borrow needed for Bit 6 or Bit 7, but
not for both. Used to indicate an overflow for signed
subtraction. This flag is set if a negative number
subtracted from a positive number yields a negative
result or if a positive number subtracted from a
negative number yields a positive result.
AC Set if a borrow is needed for Bit 3. Cleared otherwise.
MUL AB
This instruction multiplies the accumulator by the B SFR. This
operation is unsigned. The lower byte of the 16-bit product is
stored in the accumulator and the higher byte is left in the B
register. No status flags are referenced by the instruction.
Table 70. MUL AB Affected Status Flags
Flag Description
C Cleared
OV Set if the result is greater than 255. Cleared otherwise.
DIV AB
This instruction divides the accumulator by the B SFR. This
operation is unsigned. The integer part of the quotient is stored
in the accumulator and the remainder goes into the B register.
No status flags are referenced by the instruction.
Table 71. DIV AB Affected Status Flags
Flag Description
C Cleared
OV Cleared unless the B register is equal to 0, in which
case the results of the division are undefined and the
OV flag is set.
DA A
This instruction adjusts the accumulator to hold two 4-bit digits
after the addition of two binary coded decimals (BCDs) with
the ADD or ADDC instructions. If the AC bit is set or if the value
of Bit 0 to Bit 3 exceeds 9, 0x06 is added to the accumulator
to correct the lower four bits. If the carry bit is set when the
instruction begins, or if 0x06 is added to the accumulator in the
first step, 0x60 is added to the accumulator to correct the higher
four bits.
The carry and AC status flags are referenced by this instruction.
Table 72. DA A Affected Status Flag
Flag Description
C Set if the result is greater than 0x99. Cleared
otherwise.
RRC A
This instruction rotates the accumulator to the right through
the carry flag. The old LSB of the accumulator becomes the new
carry flag, and the old carry flag is loaded into the new MSB of
the accumulator.
The carry status flag is referenced by this instruction.
Table 73. RRC A Affected Status Flag
Flag Description
C Equal to the state of ACC[0] before execution of the
instruction.
RLC A
This instruction rotates the accumulator to the left through the
carry flag. The old MSB of the accumulator becomes the new
carry flag, and the old carry flag is loaded into the new LSB of
the accumulator.
The carry status flag is referenced by this instruction.
Table 74. RLC A Affected Status Flag
Flag Description
C Equal to the state of ACC[7] before execution of the
instruction.
CJNE Destination, Source, Relative Jump
This instruction compares the source value to the destination
value and branches to the location set by the relative jump if
they are not equal. If the values are equal, program execution
continues with the instruction after the CJNE instruction.
No status flags are referenced by this instruction.
Table 75. CJNE Destination (Source, Relative Jump) Affected
Status Flags
Flag Description
C Set if the source value is greater than the destination
value. Cleared otherwise.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 92 of 152
DUAL DATA POINTERS
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 incorporates two data pointers. The second data
pointer is a shadow data pointer and is selected via the data
pointer control SFR (DPCON, Address 0xA7). DPCON features
automatic hardware postincrement and postdecrement, as well as
an automatic data pointer toggle.
Note that this is the only section of the data sheet where the
main and shadow data pointers are distinguished. Whenever the
data pointer (DPTR) is mentioned elsewhere in the data sheet,
active DPTR is implied.
In addition, only the MOVC/MOVX @DPTR instructions
automatically postincrement and postdecrement the DPTR.
Other MOVC/MOVX instructions, such as MOVC PC
or MOVC @Ri, do not cause the DPTR to automatically
postincrement and postdecrement.
To illustrate the operation of DPCON, the following code copies
256 bytes of code memory at Address 0xD000 into XRAM,
starting from Address 0x0000:
MOV DPTR,#0 ;Main DPTR = 0
MOV DPCON,#55H ;Select shadow DPTR
;DPTR1 increment mode
;DPTR0 increment mode
;DPTR auto toggling ON
MOV DPTR,#0D000H ;DPTR = D000H
MOVELOOP: CLR A
MOVC A,@A+DPTR ;Get data
;Post Inc DPTR
;Swap to Main DPTR(Data)
MOVX @DPTR,A ;Put ACC in XRAM
;Increment main DPTR
;Swap Shadow DPTR(Code)
MOV A, DPL
JNZ MOVELOOP
Table 76. Data Pointer Control SFR (DPCON, Address 0xA7)
Bit Mnemonic Default Description
7 0 Not implemented. Write don’t care.
6 DPT 0 Data pointer automatic toggle enable. Cleared by the user to disable autoswapping of the DPTR.
Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction.
[5:4] DP1m1,
DP1m0
0 Shadow data pointer mode. These bits enable extra modes of the shadow data pointer operation,
allowing more compact and more efficient code size and execution.
DP1m1 DP1m0 Result (Behavior of the Shadow Data Pointer)
0 0 8052 behavior.
0 1 DPTR is postincremented after a MOVX or a MOVC instruction.
1 0 DPTR is postdecremented after a MOVX or MOVC instruction.
1 1
DPTR LSB is toggled after a MOVX or MOVC instruction. This instruction can be
useful for moving 8-bit blocks to/from 16-bit devices.
[3:2] DP0m1,
DP0m0
0 Main data pointer mode. These bits enable extra modes of the main data pointer operation, allowing
more compact and more efficient code size and execution.
DP0m1 DP0m0 Result (Behavior of the Main Data Pointer)
0 0 8052 behavior.
0 1 DPTR is postincremented after a MOVX or a MOVC instruction.
1 0 DPTR is postdecremented after a MOVX or MOVC instruction.
1 1
DPTR LSB is toggled after a MOVX or MOVC instruction. This instruction is useful
for moving 8-bit blocks to/from 16-bit devices.
1 0 Not implemented. Write don’t care.
0 DPSEL 0 Data pointer select. Cleared by the user to select the main data pointer, meaning that the contents of
this 16-bit register are placed into the DPL SFR and DPH SFR. Set by the user to select the shadow data
pointer, meaning that the contents of a separate 16-bit register appear in the DPL SFR and DPH SFR.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 93 of 152
INTERRUPT SYSTEM
The unique power management architecture of the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 includes
an operating mode (PSM2) where the 8052 MCU core is shut
down. Events can be configured to wake the 8052 MCU core
from the PSM2 operating mode. A distinction is drawn here
between events that can trigger the wake-up of the 8052 MCU
core and events that can trigger an interrupt when the MCU
core is active. Events that can wake the core are referred to as
wake-up events, whereas events that can interrupt the program
flow when the MCU is active are called interrupts. See the 3.3 V
Peripherals and Wake-Up Events section to learn more about
events that can wake the 8052 core from PSM2 mode.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 provide 12 interrupt sources with three priority levels.
The power management interrupt is at the highest priority level.
The other two priority levels are configurable through the
interrupt priority SFR (IP, Address 0xB8) and the interrupt
enable and Priority 2 SFR (IEIP2, Address 0xA9).
STANDARD 8052 INTERRUPT ARCHITECTURE
The standard 8052 interrupt architecture includes two tiers of
interrupts, where some interrupts are assigned a high priority
and others are assigned a low priority.
PRIORITY 1
PRIORITY 0
HIGH
LOW
06353-062
Figure 87. Standard 8052 Interrupt Priority Levels
A Priority 1 interrupt can interrupt the service routine of a
Priority 0 interrupt, and if two interrupts of different priorities
occur at the same time, the Priority 1 interrupt is serviced first.
An interrupt cannot be interrupted by another interrupt of the
same priority level. If two interrupts of the same priority level
occur simultaneously, a polling sequence is observed. See the
Interrupt Priority section.
INTERRUPT ARCHITECTURE
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 possess advanced power supply management
features. To ensure a fast response to time-critical power supply
issues, such as a loss of line power, the power supply manage-
ment interrupt should be able to interrupt any interrupt service
routine. To enable the user to have full use of the standard 8052
interrupt priority levels, an additional priority level is added for the
power supply management (PSM) interrupt. The PSM interrupt
is the only interrupt at this highest interrupt priority level.
PRIORITY 1
PRIORITY 0
PSM
HIGH
LOW
06353-063
Figure 88. Interrupt Architecture
See the Power Supply Management (PSM) Interrupt section for
more information on the PSM interrupt.
INTERRUPT REGISTERS
The control and configuration of the interrupt system are carried
out through four interrupt-related SFRs, discussed in this section.
Table 77. Interrupt SFRs
SFR Address Default Bit Addressable Description
IE 0xA8 0x00 Yes Interrupt enable (see Table 78).
IP 0xB8 0x00 Yes Interrupt priority (see Table 79).
IEIP2 0xA9 0xA0 No Interrupt enable and Priority 2 (see Table 80).
WDCON 0xC0 0x10 Yes Watchdog timer (see Table 85 and the Writing to the Watchdog Timer SFR (WDCON,
Address 0xC0) section).
Table 78. Interrupt Enable SFR (IE, Address 0xA8)
Bit Bit Address Mnemonic Description
7 0xAF EA Enables all interrupt sources. Set by the user. Cleared by the user to disable all interrupt sources.
6 0xAE ETEMP1Enables the temperature ADC interrupt. Set by the user.
5 0xAD ET2 Enables the Timer 2 interrupt. Set by the user.
4 0xAC ES Enables the UART serial port interrupt. Set by the user.
3 0xAB ET1 Enables the Timer 1 interrupt. Set by the user.
2 0xAA EX1 Enables External Interrupt 1 (INT1). Set by the user.
1 0xA9 ET0 Enables the Timer 0 interrupt. Set by the user.
0 0xA8 EX0 Enables External Interrupt 0 (INT0). Set by the user.
1 This feature is not available in the ADE7116.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 94 of 152
Table 79. Interrupt Priority SFR (IP, Address 0xB8)
Bit Bit Address Mnemonic Description
7 0xBF PADE ADE energy measurement interrupt Priority (1 = high, 0 = low).
6 0xBE PTEMP Temperature ADC interrupt priority (1 = high, 0 = low).
5 0xBD PT2 Timer 2 interrupt priority (1 = high, 0 = low).
4 0xBC PS UART serial port interrupt priority (1 = high, 0 = low).
3 0xBB PT1 Timer 1 interrupt priority (1 = high, 0 = low).
2 0xBA PX1 INT1 (External Interrupt 1) priority (1 = high, 0 = low).
1 0xB9 PT0 Timer 0 interrupt priority (1 = high, 0 = low).
0 0xB8 PX0 INT0 (External Interrupt 0) priority (1 = high, 0 = low).
Table 80. Interrupt Enable and Priority 2 SFR (IEIP2, Address 0xA9)
Bit Mnemonic Description
7 Reserved
6 PTI RTC interrupt priority (1 = high, 0 = low).
5 Reserved
4 PSI SPI/I2C interrupt priority (1 = high, 0 = low).
3 EADE Enables the energy metering interrupt (ADE). Set by the user.
2 ETI Enables the RTC interval timer interrupt. Set by the user.
1 EPSM Enables the PSM power supply management interrupt. Set by the user.
0 ESI Enables the SPI/I2C interrupt. Set by the user.
INTERRUPT PRIORITY
If two interrupts of the same priority level occur simultaneously, the polling sequence is observed (as shown in Table 81).
Table 81. Priority Within Interrupt Level
Source Priority Description
IPSM 0 (highest) Power supply monitor interrupt.
IRTC 1 RTC interval timer interrupt.
IADE 2 ADE energy measurement interrupt.
WDT 3 Watchdog timer overflow interrupt.
ITEMP14 Temperature ADC interrupt
IE0 5 External interrupt 0.
TF0 6 Timer/Counter 0 interrupt.
IE1 7 External Interrupt 1.
TF1 8 Timer/Counter 1 Interrupt.
ISPI/I2CI 9 SPI/I2C interrupt.
RI/TI 10 UART serial port interrupt.
TF2/EXF2 11 (lowest) Timer/Counter 2 interrupt.
1 This feature is not available in the ADE7116.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 95 of 152
INTERRUPT FLAGS
The interrupt flags and status flags associated with the interrupt vectors are shown in Table 82 and Tabl e 83. Most of the interrupts have
flags associated with them.
Table 82. Interrupt Flags
Interrupt Source Flag Bit Name Description
IE0 TCON.1 IE0 External interrupt 0.
TF0 TCON.5 TF0 Timer 0.
IE1 TCON.3 IE1 External interrupt 1.
TF1 TCON.7 TF1 Timer 1.
RI + TI SCON.1 TI Transmit interrupt.
SCON.0 RI Receive interrupt.
TF2 + EXF2 T2CON.7 TF2 Timer 2 overflow flag.
T2CON.6 EXF2 Timer 2 external flag.
ITEMP (Temperature ADC)1N/A N/A Temperature ADC interrupt. Does not have an interrupt flag associated with it.
IPSM (Power Supply) IPSMF.6 FPSM PSM interrupt flag.
IADE (Energy Measurement DSP) MIRQSTL.7 ADEIRQFLAG Read MIRQSTH, MIRQSTM, MIRQSTL.
1 This feature is not available in the ADE7116.
Table 83. Status Flags
Interrupt Source Flag Bit Address Description
ITEMP (Temperature ADC)1N/A N/A Temperature ADC interrupt. Does not have a status flag associated with it.
ISPI/I2CI SPI2CSTAT N/A SPI interrupt status register.
SPI2CSTAT N/A I2C interrupt status register.
IRTC (RTC Interval Timer) TIMECON.7 MIDNIGHT RTC midnight flag.
TIMECON.2 ALARM RTC alarm flag.
WDT (Watchdog Timer) WDCON.2 WDS Watchdog timeout flag.
1 This feature is not available in the ADE7116.
A functional block diagram of the interrupt system is shown in
Figure 89. Note that the PSM interrupt is the only interrupt in
the highest priority level.
If an external wake-up event occurs to wake the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 from PSM2
mode, a pending external interrupt is generated. When the EX0
bit (Bit 0) or the EX1 bit (Bit 2) in the interrupt enable SFR (IE,
Address 0xA8) is set to enable external interrupts, the program
counter is loaded with the IE0 or IE1 interrupt vector. The IE0
and IE1 interrupt flags (Bit 1 and Bit 3, respectively) in the
Timer/Counter 0 and Timer/Counter 1 control SFR (TCON,
Address 0x88) are not affected by events that occur when the
8052 MCU core is shut down during PSM2. See the Power
Supply Management (PSM) Interrupt section.
The RTC, temperature ADC, and I2C/SPI interrupts are latched
such that pending interrupts cannot be cleared without entering
their respective interrupt service routines. Clearing the RTC
midnight flags and alarm flags does not clear a pending RTC
interrupt. Similarly, clearing the I2C/SPI status bits in the SPI
Interrupt Status SFR (SPISTAT, Address 0xEA) does not cancel
a pending I2C/SPI interrupt. These interrupts remain pending
until the RTC or I2C/SPI interrupt vectors are enabled. Their
respective interrupt service routines are entered shortly
thereafter.
Figure 89 shows how the interrupts are cleared when the
interrupt service routines are entered. Some interrupts with
multiple interrupt sources are not automatically cleared;
specifically, the PSM, ADE, UART, and Timer 2 interrupt
vectors. Note that the INT0 and INT1 interrupts are only
cleared only if the external interrupt is configured to be
triggered by a falling edge by setting IT0 (Bit 0) in the
Timer/Counter 0 and Timer/Counter 1 control SFR (TCON,
Address 0x88). If INT0 or INT1 is configured to interrupt on a
low level, the interrupt service routine is reentered until the
respective pin goes high.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 96 of 152
IPSMF FPSM
(IPSMF.6)
IPSME
INDIVIDUAL
INTERRUPT
ENABLE
IE/IEIP2 REGISTERS IP/IEIP2 REGISTERS
WATCHDOG TIMEOUT
WDIR
LOW HIGH HIGHEST
MIDNIGHT
ALARM
IN OUT
LATCH
RESET
MIRQSTH MIRQSTM MIRQSTL
MIRQENH MIRQENM MIRQENL
MIRQSTL.7
TEMPADC INTERRUPT IN OUT
LATCH
RESET
INT0
IT0
0
1
IE0
TF0
INT1
IT1
0
1
TF1
CFG.5
0
1
I
2
C INTERRUPT
SPI INTERRUPT
RI
TI
TF2
EXF2
INTERRUPT
POLLING
SEQUENCE
PSM
RTC
ADE
WATCHDOG
TEMP ADC*
EXTERNAL
INTERRUPT 0
TIMER 0
EXTERNAL
INTERRUPT 1
TIMER 1
I
2
C/SPI
UART
TIMER 2
AUTOMATIC
CLEAR SIGNAL
LEGEND
IT0
IE1
IT1
PSM2
PSM2
PRIORITY LEVEL
GLOBAL
INTERRUPT
ENABLE (EA)
IN OUT
LATCH
RESET
06353-064
*NOT AVAILABLE IN THE ADE7116.
Figure 89. Interrupt System Functional Block Diagram
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 97 of 152
INTERRUPT VECTORS
When an interrupt occurs, the program counter is pushed
onto the stack, and the corresponding interrupt vector address
is loaded into the program counter. When the interrupt service
routine is complete, the program counter is popped off the stack
by an RETI instruction. This allows program execution to resume
from where it was interrupted. The interrupt vector addresses
are shown in Table 84.
Table 84. Interrupt Vector Addresses
Source Vector Address
IE0 0x0003
TF0 0x000B
IE1 0x0013
TF1 0x001B
RI + TI 0x0023
TF2 + EXF2 0x002B
ITEMP (Temperature ADC)1 0x0033
ISPI/I2CI 0x003B
IPSM (Power Supply) 0x0043
IADE (Energy Measurement DSP) 0x004B
IRTC (RTC Interval Timer) 0x0053
WDT (Watchdog Timer) 0x005B
1 This feature is not available in the ADE7116.
INTERRUPT LATENCY
The 8052 architecture requires that at least one instruction
execute between interrupts. To ensure this, the 8052 MCU
core hardware prevents the program counter from jumping to
an ISR immediately after completing an RETI instruction or an
access of the IP and IE SFRs.
The shortest interrupt latency is 3.25 instruction cycles, 800 ns
with a clock of 4.096 MHz. The longest interrupt latency for a
high priority interrupt results when a pending interrupt is
generated during a low priority interrupt RETI, followed by a
multiply instruction. This results in a maximum interrupt
latency of 16.25 instruction cycles, 4 µs with a clock of 4.096 MHz.
CONTEXT SAVING
When the 8052 vectors to an interrupt, only the program counter
is saved on the stack. Therefore, the interrupt service routine
must be written to ensure that registers used in the main
program are restored to their pre-interrupt state. Common
SFRs that can be modified in the ISR are the accumulator
register and the PSW register. Any general-purpose registers
that are used as scratch pads in the ISR should also be restored
before exiting the interrupt. The following example 8052 code
shows how to restore some commonly used registers:
GeneralISR:
; save the current Accumulator value
PUSH ACC
; save the current status and register bank
selection
PUSH PSW
; service interrupt
…
; restore t he status and regi ster ban k
selection
POP PSW
; restore the accumulator
POP ACC
RETI
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 98 of 152
WATCHDOG TIMER
The watchdog timer generates a device reset or interrupt within
a reasonable amount of time if the ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569 enter an erroneous state, possibly
due to a programming error or electrical noise. The watchdog is
enabled by default with a timeout of two seconds and creates a
system reset if not cleared within two seconds. The watchdog
function can be disabled by clearing the watchdog enable bit
(WDE, Bit 1) in the watchdog timer SFR (WDCON, Address
0xC0).
The watchdog circuit generates a system reset or interrupt
(WDS, Bit 2) if the user program fails to set the WDE bit within
a predetermined amount of time (set by the PRE bits).
The watchdog timer is clocked from the 32.768 kHz external
crystal connected between the XTAL1 and XTAL2 pins.
The WDCON SFR can be written to by user software only if the
double write sequence described in Table 85 is initiated on
every write access to the WDCON SFR.
To prevent any code from inadvertently disabling the watchdog, a
watchdog protection can be activated. This watchdog protection
locks in the watchdog enable and event settings so they cannot
be changed by user code. The protection is activated by clearing
a watchdog protection bit in the flash memory. The watchdog
protection bit is the most significant bit at Address 0x3FFA of
the flash memory. When this bit is cleared, the WDIR bit (Bit 3) is
forced to 0, and the WDE bit is forced to 1. Note that the
sequence for configuring the flash protection bits must be
followed to modify the watchdog protection bit at Address
0x3FFA (see the Protecting the Flash section).
Table 85. Watchdog Timer SFR (WDCON, Address 0xC0)
Bit Address Mnemonic Default Description
[7:4] 0xC7 to
0xC4
PRE 7
Watchdog prescaler. In normal mode, the 16-bit watchdog timer is clocked by the input
clock (32.768 kHz). The PRE bits set which of the upper bits of the counter are used as the
watchdog output, as follows:
CLKIN
tPRE
WATCHDOG
9
2
2×=
PRE Result (Watchdog Timeout)
0000 15.6 ms
0001 31.2 ms
0010 62.5 ms
0011 125 ms
0100 250 ms
0101 500 ms
0110 1 sec
0111 2 sec
1000 0 sec, automatic reset
1001 0 sec, serial download reset
1010 to 1111 Not a valid selection
3 0xC3 WDIR 0 Watchdog interrupt response bit. When cleared, the watchdog generates a system reset
when the watchdog timeout period has expired. When set, the watchdog generates an
interrupt when the watchdog timeout period has expired.
2 0xC2 WDS 0 Watchdog status bit. This bit is set to indicate that a watchdog timeout has occurred. It is
cleared by writing a 0 or by an external hardware reset. A watchdog reset does not clear
WDS; therefore, it can be used to distinguish between a watchdog reset and a hardware
reset from the RESET pin.
1 0xC1 WDE 1 Watchdog enable bit. When set, this bit enables the watchdog and clears its counter. The
watchdog counter is subsequently cleared again whenever WDE is set. If the watchdog is
not cleared within its selected timeout period, it generates a system reset or watchdog
interrupt, depending on the WDIR bit.
0 0xC0 WDWR 0 Watchdog write enable bit (see the Writing to the Watchdog Timer SFR (WDCON, Address
0xC0) section).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 99 of 152
Table 86. Watchdog and Flash Protection Byte in Flash (Flash Address = 0x3FFA)
Bit Mnemonic Default Description
7 WDPROT_PROTKY7 1 This bit holds the protection for the watchdog timer and the seventh bit of the flash protection key.
When this bit is cleared, the watchdog enable and event bits WDE and WDIR cannot be changed
by user code. The watchdog configuration is then fixed to WDIR = 0 and WDE = 1. The watchdog
timeout in the PRE bits can still be modified by user code.
The value of this bit is also used to set the flash protection key. If this bit is cleared to protect the
watchdog, then the default value for the flash protection key is 0x7F instead of 0xFF (see the
Protecting the Flash section for more information on how to clear this bit).
[6:0] PROTKY[6:0] 0xFF These bits hold the flash protection key. The content of this flash address is compared to the
flash protection key SFR (PROTKY, Address 0xBB) when the protection is being set or changed. If
the two values match, the new protection is written to the flash Address 0x3FFF to Address
0x3FFB. See the Protecting the Flash section for more information on how to configure these
bits.
Writing to the Watchdog Timer SFR (WDCON, Address
0xC0)
Writing data to the WDCON SFR involves a double instruction
sequence. The WDWR (Bit 0) bit must be set, and the following
instruction must be a write instruction to the WDCON SFR.
; Disable Watchdog
CLR EA
SETB WDWR
CLR WDE
SETB EA
This sequence is necessary to protect the WDCON SFR from
code execution upsets that may unintentionally modify this
SFR. Interrupts should be disabled during this operation due to
the consecutive instruction cycles.
Watchdog Timer Interrupt
If the watchdog timer is not cleared within the watchdog timeout
period, a system reset occurs unless the watchdog timer interrupt
is enabled. The watchdog timer interrupt response bit (WDIR,
Bit 3) is located in the watchdog timer SFR (WDCON, Address
0xC0). Enabling the WDIR bit allows the program to examine
the stack or other variables that may have led the program to
execute inappropriate code. The watchdog timer interrupt also
allows the watchdog to be used as a long interval timer.
Note that WDIR is automatically configured as a high priority
interrupt. This interrupt cannot be disabled by the EA bit (Bit 7)
in the interrupt enable SFR (IE, Address 0xA8; see Table 78).
Even if all of the other interrupts are disabled, the watchdog is
kept active to watch over the program.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 100 of 152
LCD DRIVER
Using shared pins, the LCD module is capable of directly driving
an LCD panel of 17 × 4 segments without compromising any
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
functions. It is capable of driving LCDs with 2×, 3×, and 4× multi-
plexing. The LCD waveform voltages generated through internal
charge pump circuitry support up to 5 V LCDs for the ADE7156/
ADE7166/ADE7169/ADE7566/ADE7569. An external resistor
ladder for LCD waveform voltage generation is also supported.
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 has an embedded LCD control circuit, driver, and
power supply circuit. The LCD module is functional in all
operating modes (see the Operating Modes section).
LCD REGISTERS
There are six LCD control registers that configure the driver for
the specific type of LCD in the end system and set up the user
display preferences. The LCD configuration SFR (LCDCON,
Address 0x95), LCD Configuration X SFR (LCDCONX,
Address 0x9C), and LCD Configuration Y SFR (LCDCONY,
Address 0xB1) contain general LCD driver configuration
information including the LCD enable and reset, as well as the
method of LCD voltage generation and multiplex level. The
LCD clock SFR (LCDCLK, Address 0x96) configures timing
settings for LCD frame rate and blink rate. LCD pins are
configured for LCD functionality in the LCD segment enable
SFR (LCDSEGE, Address 0x97) and the LCD Segment Enable 2
SFR (LCDSEGE2, Address 0xED).
Table 87. LCD Driver SFRs
SFR Address R/W Mnemonic Description
0x95 R/W LCDCON LCD configuration SFR (see Table 88).
0x96 R/W LCDCLK LCD clock (see
Table 92).
0x97 R/W LCDSEGE LCD segment Enable (see Table 95).
0x9C R/W LCDCONX LCD configuration X (see Table 89).
0xAC R/W LCDPTR LCD pointer (see Table 96).
0xAE R/W LCDDAT LCD data (see Table 97).
0xB1 R/W LCDCONY LCD configuration Y (see Table 91).
0xED R/W LCDSEGE2 LCD segment Enable 2 (see Table 98).
Table 88. LCD Configuration SFR (LCDCON, Address 0x95)
Bit Mnemonic Default Description
7 LCDEN 0 LCD enable. If this bit is set, the LCD driver is enabled.
6 LCDRST 0 LCD data registers reset. If this bit is set, the LCD data registers are reset to 0.
5 BLINKEN 0 Blink mode enable bit. If this bit is set, blink mode is enabled. The blink mode is configured by the
BLKMOD and BLKFREQ bits in the LCD clock SFR (LCDCLK, Address 0x96).
4 LCDPSM2 0 Forces LCD off when in PSM2 (sleep) mode. Note that the internal voltage reference must be enabled by
setting the REF_BAT_EN bit in the Peripheral Configuration SFR (PERIPH, Address 0xF4) to allow LCD
operation in PSM2 mode.
LCDPSM2 Result
0 The LCD is disabled or enabled in PSM2 by the LCDEN bit
1 The LCD is disabled in PSM2 regardless of LCDEN setting
3 CLKSEL 0 LCD clock selection.
CLKSEL Result
0 fLCDCLK = 2048 Hz
1 fLCDCLK = 128 Hz
2 BIAS 0 Bias mode.
BIAS Result
0 1/2
1 1/3
[1:0] LMUX 0 LCD multiplex level.
LMUX Result
00 Reserved.
01 2× multiplexing. FP27/COM3 is used as FP27, and FP28/COM2 is used as FP28.
10 3× multiplexing. FP27/COM3 is used as FP27, and FP28/COM2 is used as COM2.
11 4× multiplexing. FP27/COM3 is used as COM3, and FP28/COM2 is used as COM2.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 101 of 152
Table 89. LCD Configuration X SFR (LCDCONX, Address 0x9C)
Bit Mnemonic Default Description
7 Reserved 0 Reserved.
6 EXTRES 0 External resistor ladder selection bit.
EXTRES Result
0 External resistor ladder is disabled. Charge pump is enabled.
1 External resistor ladder is enabled. Charge pump is disabled.
[5:0] BIASLV 0 Bias level selection bits. See Table 90.1
1 This feature is not available in the ADE7116.
Table 90. LCD Bias Voltage When Contrast Control Is Enabled1
BIASLVL[5] VA (V)
1/2 Bias 1/3 Bias
VB V
C V
B V
C
0
[
]
31
04BLVL
VREF
:
× VB = VA V
C = 2 × VA VB = 2 × VA VC = 3 × VA
1
[
]
⎟
⎠
⎞
⎜
⎝
⎛+× 31
0:4BLVL
1VREF
VB = VA VC = 2 × VA VB = 2 × VA VC = 3 × VA
1 This feature is not available in the ADE7116.
Table 91. LCD Configuration Y SFR (LCDCONY, Address 0xB1)
Bit Mnemonic Default Description
7 Reserved 0 This bit should be kept cleared for proper operation.
6 INV_LVL 0 Frame inversion mode enable bit. If this bit is set, frames are inverted every other frame. If this bit is
cleared, frames are not inverted.
[5:2] Reserved 0000 These bits should be kept cleared to 0 for proper operation.
1 UPDATEOVER 0 Update finished flag bit. This bit is updated by the LCD driver. When set, this bit indicates that the
LCD memory has been updated and a new frame has begun.
0 REFRESH 0 Refresh LCD data memory bit. This bit should be set by the user. When set, the LCD driver does not
use the data in the LCD data registers to update the display. The LCD data registers can be updated
by the 8052. When cleared, the LCD driver uses the data in the LCD data registers to update display
at the next frame.
Table 92. LCD Clock SFR (LCDCLK, Address 0x96)
Bit Mnemonic Default Description
[7:6] BLKMOD 0 Blink mode clock source configuration bits.
BLKMOD Result
00 The blink rate is controlled by software; the display is off.
01 The blink rate is controlled by software; the display is on.
10 The blink rate is 2 Hz.
11 The blink rate is set by BLKFREQ.
[5:4] BLKFREQ 0 Blink rate configuration bits. These bits control the LCD blink rate if the BLKMOD bits = 11.
BLKFREQ Result (Blink Rate)
00 1 Hz
01 1/2 Hz
10 1/3 Hz
11 1/4 Hz
[3:0] FD 0 LCD frame rate selection bits. See Table 93 and Table 94.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 102 of 152
Table 93. LCD Frame Rate Selection for fLCDCLK = 2048 Hz (LCDCON[3] = 0)
2× Multiplexing 3× Multiplexing 4× Multiplexing
FD3 FD2 FD1 FD0 fLCD (Hz) Frame Rate (Hz) fLCD (Hz) Frame Rate (Hz) fLCD (Hz) Frame Rate (Hz)
0 0 0 1 256 1281341.3 170.71 512 1281
0 0 1 0 170.7 85.3 341.3 113.81 341.3 85.3
0 0 1 1 128 64 256 85.3 256 64
0 1 0 0 102.4 51.2 204.8 68.3 204.8 51.2
0 1 0 1 85.3 42.7 170.7 56.9 170.7 42.7
0 1 1 0 73.1 36.6 146.3 48.8 146.3 36.6
0 1 1 1 64 32 128 42.7 128 32
1 0 0 0 56.9 28.5 113.8 37.9 113.8 28.5
1 0 0 1 51.2 25.6 102.4 34.1 102.4 25.6
1 0 1 0 46.5 23.25 93.1 31 93.1 23.25
1 0 1 1 42.7 21.35 85.3 28.4 85.3 21.35
1 1 0 0 39.4 19.7 78.8 26.3 78.8 19.7
1 1 0 1 36.6 18.3 73.1 24.4 73.1 18.3
1 1 1 0 34.1 17.05 68.3 22.8 68.3 17.05
1 1 1 1 32 16 64 21.3 64 16
0 0 0 0 16 8 32 10.7 32 8
1 Not within the range of typical LCD frame rates.
Table 94. LCD Frame Rate Selection for fLCDCLK = 128 Hz (LCDCON[3] = 1)
2× Multiplexing 3× Multiplexing 4× Multiplexing
FD3 FD2 FD1 FD0 fLCD (Hz) Frame Rate (Hz) fLCD (Hz) Frame Rate (Hz) fLCD (Hz) Frame Rate (Hz)
0 0 0 1 32 16132 10.7 32 8
0 0 1 0 21.3 10.6 32 10.7 32 8
0 0 1 1 16 8 32 10.7 32 8
0 1 0 0 16 8 32 10.7 32 8
0 1 0 1 16 8 32 10.7 32 8
0 1 1 0 16 8 32 10.7 32 8
0 1 1 1 16 8 32 10.7 32 8
1 0 0 0 16 8 32 10.7 32 8
1 0 0 1 16 8 32 10.7 32 8
1 0 1 0 16 8 32 10.7 32 8
1 0 1 1 16 8 32 10.7 32 8
1 1 0 0 16 8 32 10.7 32 8
1 1 0 1 16 8 32 10.7 32 8
1 1 1 0 16 8 32 10.7 32 8
1 1 1 1 128 64 128 42.7 128 32
0 0 0 0 64 32 64 21.3 64 16
1 Not within the range of typical LCD frame rates.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 103 of 152
Table 95. LCD Segment Enable SFR (LCDSEGE, Address 0x97)
Bit Mnemonic Default Description
7 FP25EN 0 FP25 function select bit. 0 = general-purpose I/O, 1 = LCD function.
6 FP24EN 0 FP24 function select bit. 0 = general-purpose I/O, 1 = LCD function.
5 FP23EN 0 FP23 function select bit. 0 = general-purpose I/O, 1 = LCD function.
4 FP22EN 0 FP22 function select bit. 0 = general-purpose I/O, 1 = LCD function.
3 FP21EN 0 FP21 function select bit. 0 = general-purpose I/O, 1 = LCD function.
2 FP20EN 0 FP20 function select bit. 0 = general-purpose I/O, 1 = LCD function.
[1:0] Reserved 0 These bits must be kept at 0 for proper operation.
Table 96. LCD Pointer SFR (LCDPTR, Address 0xAC)
Bit Mnemonic Default Description
7 R/W 0 Read or write LCD bit. If this bit is set to 1, the data in LCD data SFR (LCDDAT, Address 0xAE) is
written to the address indicated by the ADDRESS bits (LCDPTR, Address 0xAC).
6 Reserved 0 Reserved.
[5:0] ADDRESS 0 LCD memory address (see Table 99).
Table 97. LCD Data SFR (LCDDAT, Address 0xAE)
Bit Mnemonic Default Description
[7:0] LCDDATA 0 Data to be written into or read out of the LCD memory SFRs.
Table 98. LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED)
Bit Mnemonic Default Description
[7:4] Reserved 0 Reserved.
3 FP19EN 0 FP19 function select bit. 0 = general-purpose I/O, 1 = LCD function.
2 FP18EN 0 FP18 function select bit. 0 = general-purpose I/O, 1 = LCD function.
1 FP17EN 0 FP17 function select bit. 0 = general-purpose I/O, 1 = LCD function.
0 FP16EN 0 FP16 function select bit. 0 = general-purpose I/O, 1 = LCD function.
LCD SETUP
The LCD configuration SFR (LCDCON, Address 0x95)
configures the LCD module to drive the type of LCD in the user
end system. The BIAS bit (Bit 2) and the LMUX bits in this SFR
should be set according to the LCD specifications.
The COM2/FP28 and COM3/FP27 pins default to LCD segment
lines. Selecting the 3× multiplex level in the LCD configuration
SFR (LCDCON, Address 0x95) by setting LMUX[1:0] to 10
changes the FP28 pin functionality to COM2. The 4× multiplex
level selection, LMUX[1:0] = 11, changes the FP28 pin
functionality to COM2 and the FP27 pin functionality to
COM3.
The LCD segments of FP0 to FP15 and FP26 are enabled by
default. Additional pins are selected for LCD functionality in
the LCD segment enable SFR (LCDSEGE, Address 0x97) and
LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED) where
there are individual enable bits for the FP16 to FP25 segment
pins. The LCD pins do not have to be enabled sequentially. For
example, if the alternate function of FP23, the Timer 2 input, is
required, any of the other shared pins, FP16 to FP25, can be
enabled instead.
The Display Element Control section contains details about
setting up the LCD data memory to turn individual LCD
segments on and off. Setting the LCDRST bit (Bit 6) in the LCD
Configuration SFR (LCDCON, Address 0x95) resets the LCD
data memory to its default (0). A power-on reset also clears the
LCD data memory.
LCD TIMING AND WAVEFORMS
An LCD segment acts like a capacitor that is charged and
discharged at a certain rate. This rate, the refresh rate, determines
the visual characteristics of the LCD. A slow refresh rate results
in the LCD blinking on and off between refreshes. A fast refresh
rate presents a screen that appears to be continuously lit. In
addition, a faster refresh rate consumes more power.
The frame rate, or refresh rate, for the LCD module is derived
from the LCD clock, fLCDCLK. The LCD clock is selected as 2048 Hz
or 128 Hz by the CLKSEL bit (Bit 3) in the LCD Configuration
SFR (LCDCON, Address 0x95). The minimum refresh rate
needed for the LCD to appear solid (without blinking) is
independent of the multiplex level.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 104 of 152
The LCD waveform frequency, fLCD, is the frequency at which
the LCD switches the active common line. Thus, the LCD
waveform frequency depends heavily on the multiplex level.
The frame rate and LCD waveform frequency are set by fLCDCLK,
the multiplex level, and the FD[3:0] frame rate selection bits in
the LCD clock SFR (LCDCLK, Address 0x96).
The LCD module provides 16 different frame rates for
fLCDCLK = 2048 Hz, ranging from 8 Hz to 128 Hz for an LCD
with 4× multiplexing. Fewer options are available with
fLCDCLK = 128 Hz, ranging from 8 Hz to 32 Hz for a 4× multi-
plexed LCD. The 128 Hz clock is beneficial for battery
operation because it consumes less power than the 2048 Hz
clock. The frame rate is set by the FD bits in the LCD clock
SFR (LCDCLK, Address 0x96); see Tabl e 93 and Table 9 4.
The LCD waveform is inverted at twice the LCD waveform
frequency, fLCD. This way, each frame has an average dc offset
of 0. ADC offset degrades the lifetime and performance of
the LCD.
BLINK MODE
Blink mode is enabled by setting the BLINKEN bit (Bit 5) in the
LCD Configuration SFR (LCDCON, Address 0x95). This mode
is used to alternate between the LCD on state and LCD off state
so that the LCD screen appears to blink. There are two blinking
modes: a software controlled blink mode and an automatic
blink mode.
Software Controlled Blink Mode
The LCD blink rate can be controlled by user code with the
BLKMOD bits in the LCD clock SFR (LCDCLK, Address 0x96)
by toggling the bits to turn the display on and off at a rate
determined by the MCU code.
Automatic Blink Mode
There are five blink rates available if the RTC peripheral is
enabled. These blink rates are selected by the BLKMOD and
BLKFREQ bits in the LCD clock SFR (LCDCLK, Address 0x96);
see Tabl e 92.
DISPLAY ELEMENT CONTROL
A bank of 15 bytes of data memory located in the LCD module
controls the on or off state of each segment of the LCD. The
LCD data memory is stored in Address 0 through Address 14 in
the LCD module. Each byte configures the on and off states of two
segment lines. The LSBs store the state of the even numbered
segment lines, and the MSBs store the state of the odd numbered
segment lines. For example, LCD Data Address 0 refers to
Segment Line 1 and Segment Line 0 (see Table 99). Note that the
LCD data memory is maintained in the PSM2 operating mode.
The LCD data memory is accessed indirectly through the LCD
pointer SFR (LCDPTR, Address 0xAC) and LCD Data SFR
(LCDDAT, Address 0xAE). Moving a value to the LCDPTR SFR
selects the LCD data byte to be accessed and initiates a read or
write operation (see Table 96 ).
Writing to LCD Data Registers
To update the LCD data memory, first set the LSB of the LCD
Configuration Y SFR (LCDCONY, Address 0xB1) to freeze the
data being displayed on the LCD while updating it. This
operation ensures that the data displayed on the screen does not
change while the data is being changed. Then, move the data to
the LCD data SFR (LCDDAT, Address 0xAE) prior to accessing
the LCD pointer SFR (LCDPTR, Address 0xAC). When the
MSB of the LCD pointer SFR (LCDPTR, Address 0xAC) is set,
the content of the LCD data SFR (LCDDAT, Address 0xAE) is
transferred to the internal LCD data memory designated by the
address in the LCDPTR SFR. Clear the LSB of the LCD
Configuration Y SFR (LCDCONY, Address 0xB1) when all of
the data memory has been updated to allow the use of the new
LCD setup for display.
Sample 8052 code to update the segments attached to FP10 and
FP11 pins, use the following sample 8052 code:
ORL LCDCONY,#01h ;start updating the data
MOV LCDDAT,#FFh
MOV LCDPTR,#80h OR 05h
ANL LCDCONY,#0FEh ;update finished
Reading LCD Data Registers
When the MSB of the LCD Pointer SFR (LCDPTR, Address
0xAC) is cleared, the content of the LCD data memory address
designated by LCDPTR is transferred to the LCD data SFR
(LCDDAT, Address 0xAE).
Sample 8052 code to read the contents of LCD Data Memory
Address 0x07, which holds the on and off state of the segments
attached to FP14 and FP15, is as follows.
MOV LCDPTR,#07h
MOV R1, LCDDAT
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 105 of 152
Table 99. LCD Data Memory Accessed Indirectly Through LCD Pointer SFR (LCDPTR, Address 0xAC) and LCD Data SFR (LCDDAT,
Address 0xAE)1, 2
LCD Pointer SFR (LCDPTR, Address 0xAC) LCD Pointer SFR (LCDDAT, Address 0xAE)
LCD Memory Address COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
0x0E FP28 FP28 FP28 FP28
0x0D FP27 FP27 FP27 FP27 FP26 FP26 FP26 FP26
0x0C FP25 FP25 FP25 FP25 FP24 FP24 FP24 FP24
0x0B FP23 FP23 FP23 FP23 FP22 FP22 FP22 FP22
0x0A FP21 FP21 FP21 FP21 FP20 FP20 FP20 FP20
0x09 FP19 FP19 FP19 FP19 FP18 FP18 FP18 FP18
0x08 FP17 FP17 FP17 FP17 FP16 FP16 FP16 FP16
0x07 FP15 FP15 FP15 FP15 FP14 FP14 FP14 FP14
0x06 FP13 FP13 FP13 FP13 FP12 FP12 FP12 FP12
0x05 FP11 FP11 FP11 FP11 FP10 FP10 FP10 FP10
0x04 FP9 FP9 FP9 FP9 FP8 FP8 FP8 FP8
0x03 FP7 FP7 FP7 FP7 FP6 FP6 FP6 FP6
0x02 FP5 FP5 FP5 FP5 FP4 FP4 FP4 FP4
0x01 FP3 FP3 FP3 FP3 FP2 FP2 FP2 FP2
0x00 FP1 FP1 FP1 FP1 FP0 FP0 FP0 FP0
1 COMx designates the common lines.
2 FPx designates the segment lines.
VOLTAGE GENERATION
The ADE7166/ADE7169/ADE7566/ADE7569 provide two ways
to generate the LCD waveform voltage levels. The on-chip charge
pump option can generate 5 V. This makes it possible to use 5 V
LCDs with the 3.3 V ADE7166/ADE7169/ADE7566/ADE7569.
There is also an option to use an external resistor ladder with a
3.3 V LCD. The EXTRES bit (Bit 6) in the LCD Configuration X
SFR (LCDCONX, Address 0x9C) selects the resistor ladder or
charge pump option. In the ADE7116 only, the resistor driver
option is available.
When selecting how to generate the LCD waveform voltages,
the following should be considered:
• Lifetime performance power consumption
• Contrast control
Lifetime Performance Power Consumption
In most LCDs, a high amount of current is required when the LCD
waveforms change state. The external resistor ladder option draws a
constant amount of current, whereas the charge pump circuitry
allows dynamic current consumption. If the LCD module is used
with the internal charge pump option when the display is disabled,
the voltage generation is disabled so that no power is consumed by
the LCD function. This feature results in significant power
savings if the display is turned off during battery operation.
Contrast Control
The electrical characteristics of the liquid in the LCD change
over temperature. This requires adjustments in the LCD waveform
voltages to ensure a readable display. An added benefit of the
internal charge pump voltage generation is a configurable bias
voltage that can be compensated over temperature and supply
to maintain contrast on the LCD. These compensations can be
performed based on the ADE7166/ADE7169/ADE7566/
ADE7569 temperature and supply voltage measurements (see
the Temperature, Battery, and Supply Voltage Measurements
section). This dynamic contrast control is not easily implemented
with external resistor ladder voltage generation.
The LCD bias voltage sets the contrast of the display when
the charge pump provides the LCD waveform voltages. The
ADE7166/ADE7169/ADE7566/ADE7569 provide 64 bias levels
selected by the BIASLVL[5:0] bits in the LCD Configuration X
SFR (LCDCONX, Address 0x9C). The voltage level on LCDVA,
LCDVB, and LCDVC depend on the internal voltage reference
value (VREF), BIASLVL[5:0] selection, and the biasing selected
as described in Table 90.
Lifetime Performance
DC offset on a segment degrades its performance over time.
The voltages generated through the internal charge pump
switch faster than those generated by the external resistor
ladder, reducing the likelihood of a dc voltage being applied
to a segment and increasing the lifetime of the LCD.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 106 of 152
LCD EXTERNAL CIRCUITRY
The voltage generation selection is made by the EXTRES bit (Bit
6) in the LCD configuration X SFR (LCDCONX, Address 0x9C).
This bit is cleared by default for charge pump voltage generation,
but it can be set to enable an external resistor ladder.
Charge Pump
Voltage generation through the charge pump requires external
capacitors to store charge. (Note that this feature is not available
in the ADE7116 or ADE7156.) The external connections to
LCDVA, LCDVB, and LCDVC, as well as to LCDVP1 and
LCDVP2, are shown in Figure 90.
LCDVC
LCDVB
LCDVA
LCDVP1
LCDVP2
CHARGE PUMP
AND
LCD WAVEFORM
CIRCUITRY
100nF
470nF
470nF
470nF
06353-065
Figure 90. External Circuitry for Charge Pump Option
External Resistor Ladder
To enable the external resistor ladder option, set the EXTRES
bit (Bit 6) in the LCD Configuration X SFR (LCDCONX,
Address 0x9C). When EXTRES = 1, the LCD waveform voltages
are supplied by the external resistor ladder. Because the LCD
voltages are not generated on-chip, the LCD bias compensation
implemented to maintain contrast over temperature and supply
is not possible.
The external circuitry needed for the resistor ladder option is
shown in Figure 92. The resistors required should be in the
range of 10 kΩ to 100 kΩ and should be based on the current
required by the LCD being used.
LCDVC
LCDVB
LCDVA
LCDVP1
LCDVP2
LCD WAVEFORM
CIRCUITRY
07327-076
Figure 91. External Circuitry for External Resistor Ladder Option:
1/2 Bias Configuration
LCDVC
LCDVB
LCDVA
LCDVP1
LCDVP2
LCD WAVEFORM
CIRCUITRY
06353-066
Figure 92. External Circuitry for External Resistor Ladder Option:
1/3 Bias Configuration
LCD FUNCTION IN PSM2 MODE
The LCDPSM2 (Bit 4) and LCDEN (Bit 7) in the LCD config-
uration SFR (LCDCON, Address 0x95) control the LCD
functionality in the PSM2 operating mode (see Table 100).
Note that the internal voltage reference must be enabled by setting
REF_BAT_EN bit (Bit 3) in the peripheral configuration SFR
(PERIPH, Address 0xF4) to allow LCD operation in PSM2 mode
(see Tabl e 2 0).
Table 100. Bits Controlling LCD Functionality in PSM2
Mode
LCDPSM2 LCDEN Result
0 0 The display is off in PSM2.
0 1 The display is on in PSM2.
1 X The display is off in PSM2.
In addition, note that the LCD configuration and data memory
is retained when the display is turned off.
Example LCD Setup
An example of how to set up the LCD peripheral for a specific
LCD is described in this section with the following parameters:
• Type of LCD: 5 V, 4× multiplexed with 1/3 bias, 96 segment
• Voltage generation: internal charge pump
• Refresh rate: 64 Hz
A 96-segment LCD with 4× multiplexing requires 96/4 = 24
segment lines. Sixteen pins, FP0 to FP15, are automatically
dedicated for use as LCD segments. Eight more pins must be
chosen for the LCD function. Because the LCD has 4× multi-
plexing, all four common lines are used. As a result, COM2/FP28
and COM3/FP27 cannot be used as segment lines. Based on the
alternate functions of the pins used for FP16 through FP25,
FP16 to FP23 are chosen for the eight remaining segment lines.
These pins are enabled for LCD functionality in the LCD
segment enable SFR (LCDSEGE, Address 0x97) and LCD
Segment Enable 2 SFR (LCDSEGE2, Address 0xED).
To determine contrast setting for this 5 V LCD, Table 90 shows
the BIASLVL[5:0] setting in the LCD Configuration X SFR
(LCDCONX, Address 0x9C) that corresponds to a VC of 5 V in
1/3 bias mode. The maximum bias level setting for this LCD is
BIASLVL[5:0] = 101110.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 107 of 152
The LCD is set up with the following 8052 code:
; set up LCD pins to have LCD functionality
MOV LCDSEG,#FP20EN+FP21EN+FP22EN+FP23EN
MOV LCDSEGX,#FP16EN+FP17EN+FP18EN+FP19EN
; set up LCDCON for fLCDCLK=2048Hz, 1/3 bias and 4x multiplexing
MOV LCDCON,#BIAS+LMUX1+LMUX0
; setup LCDCONX for charge pump and BIASLVL[110111]
MOV LCDCONX,#BIASLVL5+BIASLVL4+BIASLVL3+BIASLVL2+BIASLVL1+BIASLVL0
; set up refresh rate for 64Hz with fLCDCLK=2048Hz
MOV LCDCLK,#FD3+FD2+FD1+FD0
; set up LCD data registers with data to be displayed using
; LCDPTR and LCDDATA registers
; turn all segments on FP27 ON and FP26 OFF
ORL LCDCONY,#01h ; start data memory refresh
MOV LCDDAT,#F0H
MOV LCDPTR, #80h OR 0DH
ANL LCDCONY,#0FEh ; end of data memory refresh
ORL LCDCON,#LCDEN ; enable LCD
To set up the same 3.3 V LCD for use with an external resistor ladder:
; set up LCDCONX for external resistor ladder
MOV LCDCONX,#EXTRES
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 108 of 152
FLASH MEMORY
FLASH MEMORY OVERVIEW
Flash memory is a type of nonvolatile memory that is in-circuit
programmable. The default, erased state of a byte of flash memory
is 0xFF. When a byte of flash memory is programmed, the required
bits change from 1 to 0. The flash memory must be erased to
turn the 0s back to 1s. A byte of flash memory cannot, however,
be erased individually. The entire segment, or page, of flash
memory that contains the byte must be erased.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 provide 16 kB of flash program/information memory.
This memory is segmented into 32 pages that each contain 512
bytes each. To reprogram one byte of flash memory, the other
511 bytes in that page must be erased. The flash memory can be
erased by page or all at once in a mass erase. There is a command
to verify that a flash write operation has completed successfully.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 flash memory controller also offers configurable flash
memory protection.
The 16 kB of flash memory are provided on-chip to facilitate
code execution without any external discrete ROM device
requirements. The program memory can be programmed in-
circuit, using the serial download mode provided or using
conventional third party memory programmers.
Flash/EE Memory Reliability
The flash memory arrays on the ADE7116/ADE7156/
ADE7166/ADE7169/ADE7566/ADE7569 are fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. In real
terms, a single endurance cycle is composed of four independent,
sequential events:
1. Initial page erase sequence.
2. Read/verify sequence.
3. Byte program sequence.
4. Second read/verify sequence.
In reliability qualification, every byte in both the program and
data Flash/EE memory is cycled from 0x00 to 0xFF until a first
fail is recorded, signifying the endurance limit of the on-chip
Flash/EE memory.
As indicated in the Specifications section, the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 flash
memory endurance qualification has been carried out in
accordance with JEDEC Standard 22 Method A117 over the
industrial temperature range of −40°C, +25°C, and +85°C. The
results allow the specification of a minimum endurance figure
over supply and temperature of 100,000 cycles, with a minimum
endurance figure of 20,000 cycles of operation at 25°C.
Retention is the ability of the flash memory to retain its
programmed data over time. Again, the parts have been
qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature
(TJ = 55°C).
As part of this qualification procedure, the flash memory is
cycled to its specified endurance limit described previously,
before data retention is characterized. This means that the flash
memory is guaranteed to retain its data for its full specified
retention lifetime every time the flash memory is
reprogrammed. It should also be noted that retention lifetime,
based on an activation energy of 0.6 eV, derates with TJ as
shown in Figure 93.
40 60 70 90
T
J
JUNCTION TEMPERATURE (°C)
RETENTION
(Years)
250
200
150
100
50
050 80 110
300
100
ANALOG DEVICES
SPECIFICATION
100 YEARS MIN.
AT T
J
= 55
°
C
06353-067
Figure 93. Flash/EE Memory Data Retention
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 109 of 152
FLASH MEMORY ORGANIZATION
The 16 kB array of flash memory provided by the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 are
segmented into 32 pages of 512 bytes each. It is up to the user to
decide which flash memory is to be used for data memory. It is
recommended that each page be dedicated solely to program or
data memory so that an instance does not arise where the
program counter is loaded with data memory instead of an
opcode from the program memory or where program memory
is erased to update a byte of data memory.
0x3E00
0x3DFF
0x3C00
0x3BFF
0x3A00
0x39FF
0x3800
0x37FF
0x3600
0x35FF
0x3400
0x33FF
0x3200
0x31FF
0x3000
0x2FFF
0x2E00
0x2DFF
0x2C00
0x2BFF
0x2A00
0x29FF
0x2800
0x27FF
0x2600
0x25FF
0x2400
0x23FF
0x2200
0x21FF
0x2000
0x3FFF
CONTAINS PROTECTION SETTINGS.
READ
PROTECT
BIT 7
READ
PROTECT
BIT 6
READ
PROTECT
BIT 5
READ
PROTECT
BIT 4
PAGE 30
PAGE 29
PAGE 28
PAGE 27
PAGE 26
PAGE 25
PAGE 24
PAGE 23
PAGE 22
PAGE 21
PAGE 20
PAGE 19
PAGE 18
PAGE 17
PAGE 16
PAGE 31 0x1E00
0x1DFF
0x1C00
0x1BFF
0x1A00
0x19FF
0x1800
0x17FF
0x1600
0x15FF
0x1400
0x13FF
0x1200
0x11FF
0x1000
0x0FFF
0x0E00
0x0DFF
0x0C00
0x0BFF
0x0A00
0x09FF
0x0800
0x07FF
0x0600
0x05FF
0x0400
0x03FF
0x0200
0x01FF
0x0000
0x1FFF
READ
PROTECT
BIT 3
READ
PROTECT
BIT 2
READ
PROTECT
BIT 1
READ
PROTECT
BIT 0
PAGE 14
PAGE 13
PAGE 12
PAGE 11
PAGE 10
PAGE 9
PAGE 8
PAGE 7
PAGE 6
PAGE 5
PAGE 4
PAGE 3
PAGE 2
PAGE 1
PAGE 0
PAGE 15
06353-068
Figure 94. Flash Memory Organization
The flash memory can be protected from read or write/erase
access. The protection is implemented in the upper page of
user program memory, Page 31. Four of the bytes from this
page are used to set up write/erase protection for each page.
Another byte is used for configuring read protection of the flash
memory. The read protection is selected in groups of four pages.
Finally, there is a byte used to store the key required for
modifying the protection scheme. The last page of flash
memory must be write/erase protected at a minimum.
The implication of write/erase protecting the last page is that
the content of the 506 bytes in this page that are available to the
user must not change.
Thus, it is recommended that if code protection is enabled, the
last page of user accessible flash memory should be used only to
store data that does not need modification in the field. If the
firmware requires protection and may need updating in the
future, the last page should be reserved for constants used by
the user code that do not require modification during
emulation or debug.
Page 0 through Page 30 are, therefore, available for general
program and data memory use. It is recommended that Page 31
be used for constants or code that do not require future
modifications. Note that the last six bytes of Page 31 are
reserved for the flash memory protection and are, therefore,
unavailable to the user.
USING THE FLASH MEMORY
The 16 kB of flash memory are configured as 32 pages, each
comprising 512 bytes. As with the other ADE7116/ADE7156/
ADE7166/ADE7169/ADE7566/ADE7569 peripherals, the
interface to this memory space is via a group of registers
mapped in the SFR space (see Table 101).
The flash data SFR, (EDATA, Address 0xBC) holds the byte of data
to be accessed. The byte of flash memory is addressed via the
EADRH SFR (Address 0xC7) and the EADRL SFR (Address
0xC6). Finally, the ECON SFR (Address 0xB9) is an 8-bit
control register that can be written to with one of seven flash
memory access commands to trigger various read, write, erase,
and verify functions.
Table 101. Flash SFRs
SFR Address Default
Bit
Addressable Description
ECON 0xB9 0x00 No Flash control.
FLSHKY 0xBA 0xFF No Flash key.
PROTKY 0xBB 0xFF No Flash protection
key.
EDATA 0xBC 0x00 No Flash data.
PROTB0 0xBD 0xFF No Flash W/E
Protection 0.
PROTB1 0xBE 0xFF No Flash W/E
Protection 1.
PROTR 0xBF 0xFF No Flash read
protection.
EADRL 0xC6 0x00 No Flash low byte
address.
EADRH 0xC7 0x00 No Flash high byte
address.
Figure 95 demonstrates the steps required for access to the flash
memory.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 110 of 152
EADRH
FLSHKY
EADRL
ADDRESS ADDRESS
DECODER
FLSHKY = 0 × 3B?
PROTECTION
DECODER
ECON
COMMAND
ACCESS
ALLOWED?
FLASH
PROTECTION KEY
TRUE: ACCESS
ALLOWED
ECON = 0
FALSE: ACCESS
DENIED
ECON = 1
06353-069
Figure 95. Flash Memory Read/Write/Erase Protection Block Diagram
ECON—Flash Control SFR
Programming flash memory is done through the Flash Control
SFR (ECON, Address 0xB9). This SFR allows the user to read,
write, erase, or verify the 16 kB of flash memory. As a method of
security, a key must be written to the FLSHKY, Address 0xBA)
to initiate any user access to the flash memory. Upon completion
of the flash memory operation, the FLSHKY SFR is reset such that
it must be written to before another flash memory operation.
Requiring the key to be set before an access to the flash memory
decreases the likelihood of user code or data being overwritten
by a runaway program.
The program counter, PC, is held on the instruction where the
ECON SFR is written to until the flash memory controller is
done performing the requested operation. Then, the PC
increments to continue with the next instruction.
Any interrupt requests that occur while the flash controller is
performing an operation are not handled until the flash operation
is complete. All peripherals, such as timers and counters, continue
to operate as configured throughout the flash memory access.
Table 102. Flash Control SFR (ECON, Address 0xB9)
Bit Mnemonic Default Value Description
[7:0] ECON 0 1 Write byte. The value in EDATA is written to the flash memory at the page address given by
EADRH (Address 0xC7) and EADRL (Address 0xC6). Note that the byte being addressed must be
pre-erased.
2
Erase page. A 512-byte page of flash memory address is erased. The page is selected by the
address in EADRH and EADRL. Any address in the page can be written to EADRH and EADRL to
select it for erasure.
3
Erase all. All 16 kB of the available flash memory are erased. Note that this command is used
during serial mode and parallel download mode but should not be executed by user code.
4 Read byte. The byte in the flash memory addressed by EADRH/EADRL is read into EDATA.
5
Erase Page and Write Byte. The page that holds the byte addressed by EADRH/EADRL is erased.
Data in EDATA is then written to the byte of flash memory addressed by EADRH/EADRL.
8 Protect code (see the Protecting the Flash section).
Table 103. Flash Key SFR (FLSHKY, Address 0xBA)
Bit Mnemonic Default Description
[7:0] FLSHKY 0xFF The content of this SFR is compared to the flash key, 0x3B. If the two values match, the next ECON
operation is allowed (see the Protecting the Flash section).
Table 104. Flash Protection Key SFR (PROTKY, Address 0xBB)
Bit Mnemonic Default Description
[7:0] PROTKY 0xFF The content of this SFR is compared to the flash memory location at Address 0x3FFA. If the two values
match, the update of the write/erase and read protection setup is allowed (see the Protecting the Flash
section).
If the protection key in the flash is 0xFF, the PROTKY SFR value is not used for comparison. This SFR is
also used to write the protection key in the flash. This is done by writing the desired value in PROTKY
and by writing 0x08 in the ECON SFR. This operation can only be done once.
Table 105. Flash Data SFR (EDATA, Address 0xBC)
Bit Mnemonic Default Description
[7:0] EDATA 0 Flash pointer data.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 111 of 152
Table 106. Flash Write/Erase Protection 0 SFR (PROTB0, Address 0xBD)
Bit Mnemonic Default Description
[7:0] PROTB0 0xFF This SFR is used to write the write/erase protection bits for Page 0 to Page 7 of the flash memory
(see the Protecting the Flash section). Clearing the bits enables the protection.
PROTB0.7 PROTB0.6 PROTB0.5 PROTB0.4 PROTB0.3 PROTB0.2 PROTB0.1 PROTB0.0
Page 7 Page 6 Page 5 Page 4 Page 3 Page 2 Page 1 Page 0
Table 107. Flash Write/Erase Protection 1 SFR (PROTB1, Address 0xBE)
Bit Mnemonic Default Description
[7:0] PROTB1 0xFF This SFR is used to write the write/erase protection bits for Page 8 to Page 15 of the flash memory
(see the Protecting the Flash section). Clearing the bits enables the protection.
PROTB1.7 PROTB1.6 PROTB1.5 PROTB1.4 PROTB1.3 PROTB1.2 PROTB1.1 PROTB1.0
Page 15 Page 14 Page 13 Page 12 Page 11 Page 10 Page 9 Page 8
Table 108. Flash Read Protection SFR (PROTR, Address 0xBF)
Bit Mnemonic Default Description
[7:0] PROTR 0xFF This SFR is used to write the read protection bits for Page 0 to Page 31 of the flash memory
(see the Protecting the Flash section). Clearing the bits enables the protection.
PROTR.7 PROTR.6 PROTR.5 PROTR.4 PROTR.3 PROTR.2 PROTR.1 PROTR.0
Page 28 to
Page 31
Page 24 to
Page 27
Page 20 to
Page 23
Page 16 to
Page 19
Page 12 to
Page 15
Page 8 to
Page 11
Page 4 to
Page 7
Page 0 to
Page 3
Table 109. Flash Low Byte Address SFR (EADRL, Address 0xC6)
Bit Mnemonic Default Description
[7:0] EADRL 0 Flash pointer low byte address. This SFR is also used to write the write/erase protection bits for Page 16
to Page 23 of the flash memory (see the Protecting the Flash section). Clearing the bits enables the
protection.
EADRL.7 EADRL.6 EADRL.5 EADRL.4 EADRL.3 EADRL.2 EADRL.1 EADRL.0
Page 23 Page 22 Page 21 Page 20 Page 19 Page 18 Page 17 Page 16
Table 110. Flash High Byte Address SFR (EADRH, Address 0xC7)
Bit Mnemonic Default Description
[7:0] EADRH 0 Flash Pointer High Byte Address. This SFR is also used to write the write/erase protection bits for Page 24
to Page 31 of the flash memory (see the Protecting the Flash section). Clearing the bits enables the
protection.
EADRH.7 EADRH.6 EADRH.5 EADRH.4 EADRH.3 EADRH.2 EADRH.1 EADRH.0
Page 31 Page 30 Page 29 Page 28 Page 27 Page 26 Page 25 Page 24
Flash Functions
The following sample 8052 code is provided to demonstrate
how to use the flash functions. For these examples, Flash
Memory Byte 0x3C00 is accessed.
Write By te
Write 0xF3 into flash memory byte 0x3C00.
MOV EDATA,#F3h ; Data to be written
MOV EADRH,#3Ch ; Set up byte address
MOV EADRL,#00h
MOV FLSHKY, #3Bh ; Write Flash security
key.
MOV ECON,#01h ; Write Byte
Erase Page
Erase the page containing Flash Memory Byte 0x3C00.
MOV EADRH,#3Ch ; Select page through
byte address
MOV EADRL,#00h
MOV FLSHKY,#3Bh ; Write Flash security
key.
MOV ECON,#02h ; Erase Page
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 112 of 152
Erase All
Erase all of the 16 kB flash memory.
MOV FLSHKY,#3Bh ; Write Flash security
key.
MOV ECON,#03h ; Erase all
Read Byte
Read flash memory byte 0x3C00.
MOV EADRH,#3Ch ; Setup byte address
MOV EADRL,#00h
MOV FLSHKY,#3Bh ; Write Flash security
key.
MOV ECON,#04h ; Read Byte
; Data is ready in EDATA register
Erase Page and Write Byte
Erase the page containing flash memory byte 0x3C00 and then
write 0xF3 to that address. Note that the other 511 bytes in this
page are erased.
MOV EDATA,#F3h ; Data to be written
MOV EADRH,#3Ch ; Set up byte address
MOV EADRL,#00h
MOV FLSHKY,#3Bh ; Write flash security
key.
MOV ECON,#05h ; Erase page and then write
byte
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 113 of 152
PROTECTING THE FLASH MEMORY
Two forms of protection are offered for this flash memory: read
protection and write/erase protection. The read protection ensures
that any pages that are read protected cannot be read by the end
user. The write protection ensures that the flash memory cannot
be erased or written over. This protects the end system from
tampering and can prevent the code from being overwritten in the
event of a runaway program.
Write/erase protection is individually selectable for all 32 pages.
Read protection is selected in groups of four pages (see Figure
94 for the groupings). The protection bits are stored in the last
flash memory locations, Address 0x3FFA through Address
0x3FFF (see Figure 96); four bytes are reserved for write/erase
protection, one byte is for read protection, and another byte to
set the flash protection key (PROTKY, Address 0xBB). The user
must enable write/erase protection for the last page, at a
minimum, for the entire protection scheme to work.
Note that the read protection does not prevent MOVC
commands from being executed within the code.
There is an additional layer of protection offered by a protection
security key (PROTKY). The user can set up a protection
security key so that the protection scheme cannot be changed
without this key. When the protection key has been configured,
it cannot be modified.
Enabling Flash Protection by Code
The protection bytes in the flash can be programmed using the
flash controller command and programming ECON to 0x08. In
this case, the EADRH, EADRL, PROTB1, and PROTB0 bytes
are used to store the data to be written to the 32 bits of write
protection. Note that the EADRH and EADRL registers are not
used as data pointers here but to store write protection data.
06353-070
PROTR
PROTKY
PROTB0
PROTB1
EADRL
EADRH
RP
31:28
RP
27:24
RP
23:20
RP
19:16
RP
15:12
RP
11:8
RP
7:4
RP
3:0
WP
7
WP
6
WP
5
WP
4
WP
3
WP
2
WP
1
WP
0
WP
15
WP
14
WP
13
WP
12
WP
11
WP
10
WP
9
WP
8
WP
23
WP
22
WP
21
WP
20
WP
19
WP
18
WP
17
WP
16
WP
31
WP
30
WP
29
WP
28
WP
27
WP
26
WP
25
WP
24
PROTECTION KEY
0x3FFF
0x3FFE
0x3FFD
0x3FFC
0x3FFB
0x3FFA
0x3FF9
0x3E00
WDOG
LOCK
Figure 96. Flash Protection in Page 31
The sequence for writing the flash protection follows:
1. Set up the EADRH, EADRL, PROTB1, and PROTB0 SFRs
with the write/erase protection bits. When erased, the
protection bits default to 1, like any other bit of flash
memory. The default protection setting is for no protection.
To enable protection, write a 0 to the bits corresponding to
the pages that should be protected.
2. Set up the PROTR SFR with the read protection bits. Note
that every read protection bit protects four pages. To enable
the read protection bit, write a 0 to the bits that should be
read protected.
3. To enable the protection key, write to the PROTKY SFR.
If enabled, the protection key is required to modify the
protection scheme. The protection key, Flash Memory
Address 0x3FFA, defaults to 0xFF; if the PROTKY register
is not written to, it remains 0xFF. If the protection key is
written to, the PROTKY SFR must be written with this
value every time the protection functionality is accessed.
Note that after the protection key is configured, it cannot
be modified. Also note that the most significant bit of
Address 0x3FFA is used to enable a lock mechanism for
the watchdog settings (see the Watchdo g Ti mer section for
more information).
4. Run the protection command by writing 0x08 to the
ECON SFR.
5. Reset the chip to activate the new protection.
To enable read and write/erase protection for the last page only,
use the following 8052 code. Writing the flash protection
command to the ECON SFR initiates programming of the
protection bits in the flash.
; enable read protection on the last four
pages only
MOV PROTR,#07Fh
; set up a protection key of 0A3h. This
command can be
; omitted to use the default protection key
of 0xFF
MOV PROTKY,#0A3h
; write the flash key to the FLSHKY register
to enable flash
; access. The flash access key is not
configurable.
MOV FLSHKY,#3Bh
; write flash protection command to the ECON
register
MOV ECON,#08h
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 114 of 152
Enabling Flash Protection by Emulator Commands
Another way to set the flash protection bytes is to use the
reserved emulator commands available only in download mode.
These commands write directly to the SFRs and can be used to
duplicate the operation described in the Enabling Flash
Protection by Code section. When these flash bytes are written,
the part can exit emulation mode by reset and the protections
are effective. This method can be used in production and
implemented after downloading the program. The commands
used for this operation are an extension of the commands listed
in Application Note uC004, Understanding the Serial Download
Protocol, available at www.analog.com.
• Command with ASCII Code I or 0x49 writes the data into R0.
• Command with ASCII Code F or 0x46 writes R0 into the
SFR address defined in the data of this command.
Omitting the protocol defined in uC004, the sequence to load
protections is similar to the sequence mentioned in the
Enabling Flash Protection by Code section, except that two
emulator commands are necessary to replace one assembly
command. For example, to write the protection value in
EADRH (Address 0xC7), the following two commands must be
executed:
• Command I with data = value of Protection Byte 0x3FFF.
• Command F with data = 0xC7.
With this protocol, the protection can be written to the flash
memory using the same sequence as described in the Enabling
Flash Protection by Code section. When the part is reset, the
protection is effective.
Notes on Flash Protection
The flash protection scheme is disabled by default so that none
of the pages of the flash are protected from reading or writing/
erasing.
The last page must be write/erase protected for the protection
scheme to work.
To activate the protection settings, the ADE7116/ADE7156/
ADE7166/ADE7169/ADE7566/ADE7569 must be reset after
configuring the protection.
After configuring protection on the last page and resetting the
part, protections that have been enabled can be removed only
by mass erasing the flash memory. The protection bits are read
and erase protected by enabling read and write/erase protection
on the last page, but the protection bits are never truly write
protected.
Protection bits can be modified from a 1 to a 0, even after the
last page has been protected. In this way, more protection can
be added but none can be removed.
When the last page is read protected, the protection bits can still
be read by the user code. All other bits on this page are not
available for reading.
The protection scheme is intended to protect the end system. Pro-
tection should be disabled while developing and emulating code.
Flash Memory Timing
Typical program and erase times for the flash memory are
shown in Table 111.
Table 111. Flash Memory Program and Erase Times
Command
Bytes
Affected
Flash Memory
Timing
Write Byte 1 byte 30 μs
Erase Page 512 bytes 20 ms
Erase All 16 kB 200 ms
Read Byte 1 byte 100 ns
Erase Page and Write Byte 512 bytes 21 ms
Verify Byte 1 byte 100 ns
Note that the core microcontroller operation is idled until the
requested flash memory operation is complete. In practice, this
means that even though the flash operation is typically initiated
with a two-machine-cycle MOV instruction to write to the flash
control SFR (ECON, Address 0xB9), the next instruction is not
executed until the Flash/EE operation is complete. This means
that the core cannot respond to interrupt requests until the
Flash/EE operation is complete, although the core peripheral
functions, such as counter/timers, continue to count, as
configured throughout this period.
IN-CIRCUIT PROGRAMMING
Serial Downloading
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 facilitate code download via the standard UART
serial port. The parts enter serial download mode after a reset or
a power cycle if the SDEN pin is pulled low through an external
1 kΩ resistor. Once in serial download mode, the hidden
embedded download kernel executes. This allows the user to
download code to the full 16 kB of flash memory while the
device is in-circuit in its target application hardware.
Protection configured in the last page of the ADE7116/ADE7156/
ADE7166/ADE7169/ADE7566/ADE7569 affects whether flash
memory can be accessed in serial download mode. Read
protected pages cannot be read. Write/erase protected pages
cannot be written or erased.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 115 of 152
TIMERS
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 has three 16-bit timer/counters: Timer/Counter 0,
Timer/Counter 1, and Timer/Counter 2. The timer/counter
hardware is included on-chip to relieve the processor core of
overhead inherent in implementing timer/counter functionality
in software. Each timer/counter consists of two 8-bit registers:
THx and TLx (x = 0, 1, or 2). All three timers can be configured
to operate as timers or as event counters.
When functioning as a timer, the TLx SFR is incremented every
machine cycle. (Users can think of it as counting machine cycles.)
Because a machine cycle on a single-cycle core consists of one core
clock period, the maximum count rate is the core clock frequency.
When functioning as a counter, the TLx register is incremented
by a 1-to-0 transition at its corresponding external input pin:
T0, T1, or T2. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. Because it takes
two machine cycles (two core clock periods) to recognize a 1-to-0
transition, the maximum count rate is half the core clock frequency.
There are no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at least once
before it changes, it must be held for a minimum of one full
machine cycle. User configuration and control of all timer
operating modes is achieved via the SFRs listed in Table 112.
Table 112. Timer SFRs
SFR Address Bit Addressable Description
TCON 0x88 Yes Timer/Counter 0 and Timer/Counter 1 control (see Table 114).
TMOD 0x89 No Timer/Counter 0 and Timer./Counter 1 mode (see Table 113).
TL0 0x8A No Timer 0 low byte (see Table 117).
TL1 0x8B No Timer 1 low byte (see Table 119).
TH0 0x8C No Timer 0 high byte (see Table 116).
TH1 0x8D No Timer 1 high byte (see Table 118).
T2CON 0xC8 Yes Timer/Counter 2 control (see Table 115).
RCAP2L 0xCA No Timer 2 reload/capture low byte (see Table 123).
RCAP2H 0xCB No Timer 2 reload/capture high byte (see Table 122).
TL2 0xCC No Timer 2 low byte (Table 121).
TH2 0xCD No Timer 2 high byte (see Table 120).
TIMER REGISTERS
Table 113. Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, Address 0x89)
Bit Mnemonic Default Description
7 Gate1 0 Timer 1 gating control. Set by software to enable Timer/Counter 1 only when the INT1 pin is high and the
TR1 control is set. Cleared by software to enable Timer 1 whenever the TR1 control bit is set.
6 C/T1 0 Timer 1 timer or counter select bit. Set by software to select counter operation (input from T1 pin). Cleared
by software to select the timer operation (input from internal system clock).
[5:4] T1/M1,
T1/M0
00 Timer 1 mode select bits.
T1/M1, T1/M0 Result
00 TH1 (Address 0x8D) operates as an 8-bit timer/counter. TL1 (Address 0x8D) serves as
5-bit prescaler.
01 16-bit timer/counter. TH1 and TL1 are cascaded; there is no prescaler.
10 8-bit autoreload timer/counter. TH1 holds a value to reload into TL1 each time it overflows.
11 Timer/Counter 1 stopped.
3 Gate0 0 Timer 0 gating control. Set by software to enable Timer/Counter 0 only when the INT0 pin is high and the TR0
control bit is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set in the
Timer/Counter 0 and Timer/Counter 1 control SFR (TCON, Address 0x88)
2 C/T0 0 Timer 0 timer or counter select bit. Set by software to the select counter operation (input from T0 pin).
Cleared by software to the select timer operation (input from internal system clock).
[1:0] T0/M1,
T0/M0
00 Timer 0 mode select bits.
T0/M1, T0/M0 Result
00 TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.
01 16-bit timer/counter. TH0 and TL0 are cascaded; there is no prescaler.
10 8-bit autoreload timer/counter. TH0 holds a value to reload into TL0 each time it overflows.
11 TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an
8-bit timer only, controlled by Timer 1 control bits.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 116 of 152
Table 114. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, Address 0x88)
Bit
Bit
Address Mnemonic Default Description
7 0x8F TF1 0 Timer 1 overflow flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware
when the program counter (PC) vectors to the interrupt service routine.
6 0x8E TR1 0 Timer 1 run control bit. Set by the user to turn on Timer/Counter 1. Cleared by the user to
turn off Timer/Counter 1.
5 0x8D TF0 0 Timer 0 overflow flag. Set by hardware on a Timer/Counter 0 overflow. Cleared by hardware
when the PC vectors to the interrupt service routine.
4 0x8C TR0 0 Timer 0 run control bit. Set by the user to turn on Timer/Counter 0. Cleared by the user to
turn off Timer/Counter 0.
3 0x8B IE110 External Interrupt 1 (INT1) flag. Set by hardware by a falling edge or by a zero level applied
to the external interrupt pin, INT1, depending on the state of Bit IT1. Cleared by hardware
when the PC vectors to the interrupt service routine only if the interrupt was transition activated.
If level activated, the external requesting source, rather than the on-chip hardware, controls
the request flag.
2 0x8A IT11
0 External Interrupt 1 (IE1) trigger type. Set by software to specify edge sensitive detection, that
is, 1-to-0 transition. Cleared by software to specify level sensitive detection, that is, zero
level.
1 0x89 IE01
0 External Interrupt 0 (INT0) flag. Set by hardware by a falling edge or by a zero level being
applied to the external interrupt pin, INT0, depending on the state of Bit IT0. Cleared by
hardware when the PC vectors to the interrupt service routine only if the interrupt was
transition activated. If level activated, the external requesting source, rather than the on-chip
hardware, controls the request flag.
0 0x88 IT01
0 External Interrupt 0 (IE0) Trigger Type. Set by software to specify edge sensitive detection, that is,
1-to-0 transition. Cleared by software to specify level sensitive detection, that is, zero level.
1 These bits are not used to control Timer/Counter 0 and Timer/Counter 1 but are instead used to control and monitor the external INT0 and INT1 interrupt pins.
Table 115. Timer/Counter 2 Control SFR (T2CON, Address 0xC8)
Bit
Bit
Address Mnemonic Default Description
7 0xCF TF2 0 Timer 2 overflow flag. Set by hardware on a Timer 2 overflow. TF2 cannot be set when
either RCLK = 1 or TCLK = 1. Cleared by user software.
6 0xCE EXF2 0 Timer 2 external flag. Set by hardware when either a capture or reload is caused by a
negative transition on T2EX pin and EXEN2 = 1. Cleared by user software.
5 0xCD RCLK 0 Receive clock enable bit. Set by the user to enable the serial port to use Timer 2 overflow
pulses for its receive clock in Serial Port Mode 1 and Serial Port Mode 3. Cleared by the user
to enable Timer 1 overflow to be used for the receive clock.
4 0xCC TCLK 0 Transmit clock enable bit. Set by the user to enable the serial port to use Timer 2 overflow
pulses for its transmit clock in Serial Port Mode 1 and Serial Port Mode 3. Cleared by the user
to enable Timer 1 overflow to be used for the transmit clock.
3 0xCB EXEN2 0 Timer 2 external enable flag. Set by the user to enable a capture or reload to occur as a
result of a negative transition on the T2EX pin if Timer 2 is not being used to clock the serial
port. Cleared by the user for Timer 2 to ignore events at T2EX.
2 0xCA TR2 0 Timer 2 start/stop control bit. Set by the user to start Timer 2. Cleared by the user to stop Timer 2.
1 0xC9 C/T2 0 Timer 2 timer or counter function select bit. Set by the user to select the counter function
(input from external T2 pin). Cleared by the user to select the timer function (input from
the on-chip core clock).
0 0xC8 CAP2 0 Timer 2 capture/reload select bit. Set by the user to enable captures on negative transitions
at T2EX if EXEN2 = 1. Cleared by the user to enable autoreloads with Timer 2 overflows or
negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is
ignored and the timer is forced to autoreload on Timer 2 overflow.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 117 of 152
Table 116. Timer 0 High Byte SFR (TH0, Address 0x8C)
Bit Mnemonic Default Description
[7:0] TH0 0 Timer 0 data high byte.
Table 117. Timer 0 Low Byte SFR (TL0, Address 0x8A)
Bit Mnemonic Default Description
[7:0] TL0 0 Timer 0 data low byte.
Table 118. Timer 1 High Byte SFR (TH1, Address 0x8D)
Bit Mnemonic Default Description
[7:0] TH1 0 Timer 1 data high byte.
Table 119. Timer 1 Low Byte SFR (TL1, Address 0x8B)
Bit Mnemonic Default Description
[7:0] TL1 0 Timer 1 data low byte.
Table 120. Timer 2 High Byte SFR (TH2, Address 0xCD)
Bit Mnemonic Default Description
[7:0] TH2 0 Timer 2 data high byte.
Table 121. Timer 2 Low Byte SFR (TL2, Address 0xCC)
Bit Mnemonic Default Description
[7:0] TL2 0 Timer 2 data low byte.
Table 122. Timer 2 Reload/Capture High Byte SFR
(RCAP2H, Address 0xCB)
Bit Mnemonic Default Description
[7:0] TH2 0 Timer 2 reload/
capture high byte.
Table 123. Timer 2 Reload/Capture Low Byte SFR (RCAP2L,
Address 0xCA)
Bit Mnemonic Default Description
[7:0] TL2 0 Timer 2 reload/
capture low byte.
TIMER 0 AND TIMER 1
Timer 0 High/Low and Timer 1 High/Low Data SFRs
Each timer consists of two 8-bit SFRs. They are Timer 0 high
byte (TH0, Address 0x8C), Timer 0 low byte (TL0, Address 0x8A),
Timer 1 high byte (TH1, Address 0x8D), and Timer 1 low byte
(TL1, Address 0x8B). These SFRs can be used as independent
registers or combined into a single 16-bit register, depending on
the timer mode configuration (see Table 116 to Table 119).
Timer/Counter 0 and Timer/Counter 1 Operating Modes
This section describes the operating modes for Timer/Counter 0
and Timer/Counter 1. Unless otherwise noted, these modes of
operation are the same for both Timer 0 and Timer 1.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter. Figure 97 shows
Mode 0 operation. Note that the divide-by-12 prescaler is not
present on the single-cycle core.
CONTROL
TR0
TF0
TL0
(5 BITS)
TH0
(8 BITS)
INTERRUPT
06353-071
P0.6/T0
GATE
I
NT0
f
CORE
C/T0 = 0
C/T0 = 1
Figure 97. Timer/Counter 0, Mode 0
In this mode, the timer register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, it sets the timer
overflow flag, TF0 (Address 0x88[5]). TF0 can then be used to
request an interrupt. The counted input is enabled to the timer
when TR0 = 1 and either Gate0 to 0 or INT0 = 1. Setting Gate0
to 1 allows the timer to be controlled by the external input INT0
to facilitate pulse width measurements. TR0 is a control bit in
the Timer/Counter 0 and Timer/Counter 1 control SFR
(TCON, Address 0x88); the Gate0/Gate1 bits are in
Timer/Counter 0 and Timer/Counter 1 mode SFR (TMOD,
Address 0x89). The 13-bit register consists of all eight bits of
Timer 0 high byte SFR (TH0, Address 0x8C) and the lower five
bits of Timer 0 low byte SFR (TL0, Address 0x8A). The upper
three bits of TL0 SFR are indeterminate and should be ignored.
Setting the run flag (TR0) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0 except that the Mode 1 timer
register runs with all 16 bits. Mode 1 is shown in Figure 98.
CONTROL
TR0
TF0
TL0
(8 BITS)
TH0
(8 BITS)
INTERRUPT
0
06353-072
P0.6/T0
GATE
INT
C/T0 = 0
C/T0 = 1
f
CORE
Figure 98. Timer/Counter 0, Mode 1
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 118 of 152
Mode 2 (8-Bit Timer/Counter with Autoreload)
Mode 2 configures the timer register as an 8-bit counter (TL0)
with automatic reload as shown in Figure 99. Overflow from TL0
not only sets TF0 but also reloads TL0 with the contents of TH0,
which is preset by software. The reload leaves TH0 unchanged.
CONTROL
TF0
TL0
(8 BITS)
INTERRUPT
RELOAD
TH0
(8 BITS)
TR0
06353-073
P0.6/T0
GATE
INT0
C/T = 0
C/T = 1
f
CORE
Figure 99. Timer/Counter 0, Mode 2
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. This configuration is shown in Figure 100.
TL0 uses the Timer 0 control bits, C/T, Gate0 (see ),
TR0 and TF0 (see ), and the
Table 113
Table 114 INT0 pin. TH0 is locked
into a timer function (counting machine cycles) and takes over
the use of TR1 and TF1 from Timer 1. Therefore, TH0 controls the
Timer 1 interrupt. Mode 3 is provided for applications requiring
an extra 8-bit timer or counter.
When Timer 0 is in Mode 3, Timer 1 can be turned on and off
by switching it out of and into its own Mode 3, or it can be used
by the serial interface as a baud rate generator. In fact, Timer 1
can be used in any application not requiring an interrupt from
Timer 1 itself.
CONTROL
CORE
CLK/12
TF0
TL0
(8 BITS)
INTERRUPT
P0.6/T0
GATE
TR0
TF1
TH0
(8 BITS)
INTERRUPT
f
CORE
/12
TR1
0INT
C/T = 0
C/T = 1
06353-074
f
CORE
Figure 100. Timer/Counter 0, Mode 3
TIMER 2
Timer/Counter 2 Data Registers
Timer/Counter 2 also has two pairs of 8-bit data registers
associated with it: Timer 2 high byte SFR (TH2, Address 0xCD),
Timer 2 low byte SFR (TL2, Address 0xCC), Timer 2 reload/
capture high byte SFR (RCAP2H, Address 0xCB), and Timer 2
reload/capture low byte SFR (RCAP2L, Address 0xCA). These
are used both as timer data registers and as timer capture/reload
registers (see Table 120 to Table 123).
Timer/Counter 2 Operating Modes
The following sections describe the operating modes for
Timer/Counter 2. The operating modes are selected by bits in
the Timer/Counter 2 control SFR (T2CON, Address 0xC8), as
shown in Table 115 and Tabl e 124 .
Table 124. T2CON Operating Modes
RCLK (or) TCLK CAP2 TR2 Mode
0 0 1 16-bit autoreload
0 1 1 16-bit capture
1 X 1 Baud rate
X X 0 Off
16-Bit Autoreload Mode
The 16-bit autoreload mode has two options that are selected by
EXEN2 (Bit 3) in the Timer/Counter 2 control SFR (T2CON,
Address 0xC8). If EXEN2 = 0 when Timer 2 rolls over, it not
only sets TF2 but also causes the Timer 2 SFRs to be reloaded
with the 16-bit value in both the Timer 2 reload/capture high byte
SFR (RCAP2H, Address 0xCB) and Timer 2 reload/capture low
byte SFR (RCAP2L, Address 0xCA) registers, which are preset
by software. If EXEN2 = 1, Timer 2 performs the same events as
when EXEN2 = 0 but adds a 1-to-0 transition at the external
input, T2EX, which triggers the 16-bit reload and sets EXF2.
Autoreload mode is shown in Figure 101.
16-Bit Capture Mode
The 16-bit capture mode has two options that are selected by
EXEN2 (Bit 3) in the Timer/Counter 2 control SFR (T2CON,
Address 0xC8). If EXEN2 = 0, Timer 2 is a 16-bit timer or
counter that, upon overflowing, sets the Timer 2 overflow bit
(TF2, Bit 7). This bit can be used to generate an interrupt. If
EXEN2 = 1, then Timer 2 performs the same events as when
EXEN2 = 0, but it adds a l-to-0 transition on the T2E external
input, causing the current value in the Timer 2 SFRs, TL2
(Address 0xCC) and TH2 (Address 0xCD), to be captured into
the RCAP2L (Address 0xCA) and RCAP2H (Address 0xCB)
SFRs, respectively. In addition, the transition at T2EX causes the
EXF2 bit (Bit 6) in the T2CON SFR (Address 0xC8) to be set,
and EXF2, like TF2, can generate an interrupt. Capture mode is
shown in Figure 102. The baud rate generator mode is selected
by RCLK = 1 and/or TCLK = 1.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 119 of 152
In either case, if Timer 2 is used to generate the baud rate, the TF2
interrupt flag does not occur. Therefore, Timer 2 interrupts do not
occur and do not have to be disabled. In this mode, the EXF2 flag
can, however, still cause interrupts that can be used as a third
external interrupt. Baud rate generation is described as part of the
UART serial port operation in the UART Serial Interface section.
TR2
CONTROL
TL2
(8 BITS)
TH2
(8 BITS)
RELOAD
TF2
EXF2
TIMER
INTERRUPT
EXEN2
CONTROL
TRANSITION
DETECTOR
RCAP2L RCAP2H
C/ T2 = 0
06353-075
P1.4/T2
P1.3/
T2EX
C/ T2 = 1
f
CORE
Figure 101. Timer/Counter 2, 16-Bit Autoreload Mode
TF2
P1.4/T2
P1.3/
T2EX
TR2
CONTROL
TL2
(8 BITS)
TH2
(8 BITS)
CAPTURE
EXF2
TIMER
INTERRUPT
EXEN2
CONTROL
TRANSITION
DETECTOR
RCAP2L RCAP2H
C/ T2 = 1
C/ T2 = 0
06353-076
f
CORE
Figure 102. Timer/Counter 2, 16-Bit Capture Mode
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 120 of 152
PLL
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 are intended for use with a 32.768 kHz watch crystal.
A PLL locks onto a multiple of this frequency to provide a stable
4.096 MHz clock for the system. The core can operate at this
frequency or at binary submultiples of it to allow power savings
when maximum core performance is not required. The default
core clock is the PLL clock divided by 4, or 1.024 MHz. The ADE
energy measurement clock is derived from the PLL clock and is
maintained at 4.096 MHz/5 MHz, 819.2 kHz across all CD
settings.
The PLL is controlled by the CD bits in the power control SFR
(POWCON, Address 0xC5). To protect erroneous changes to
the POWCON SFR, a key is required to modify the register.
First, the key SFR (KYREG, Address 0xC1) is written with the
key, 0xA7, and then a new value is written to the POWCON SFR.
If the PLL loses lock, the MCU is reset and the PLL_FLT bit (Bit 4)
is set in the peripheral configuration SFR (PERIPH, Address 0xF4).
Set the PLLACK bit in the start ADC measurement SFR
(ADCGO, Address 0xD8) to acknowledge the PLL fault,
clearing the PLL_FLT bit.
PLL REGISTERS
Table 125. Power Control SFR (POWCON, Address 0xC5)
Bit Mnemonic Default Description
7 Reserved 1 Reserved.
6 METER_OFF 0 Set this bit to 1 to turn off the modulators and energy metering DSP circuitry to reduce power if
metering functions are not needed in PSM0.
5 Reserved 0 This bit should be kept at 0 for proper operation.
4 COREOFF 0 Set this bit to 1 to shut down the core if in the PSM1 operating mode.
3 Reserved Reserved.
[2:0] CD 010 Controls the core clock frequency (fCORE). fCORE = 4.096 MHz/2CD.
CD Result (fCORE in MHz)
000 4.096
001 2.048
010 1.024
011 0.512
100 0.256
101 0.128
110 0.064
111 0.032
Writing to the Power Control SFR (POWCON, Address 0xC5)
Note that writing data to the POWCON SFR involves writing 0xA7 into the key SFR (KYREG, Address 0xC1) followed by a write to the
POWCON SFR.
Table 126. Key SFR (KYREG, Address 0xC1)
Bit Mnemonic Default Description
[7:0] KYREG 0 Write 0xA7 to the KYREG SFR before writing to the POWCON SFR to unlock it.
Write 0xEA to the KYREG SFR before writing to the INTPR, HTHSEC, SEC, MIN, or HOUR timekeeping SFRs
to unlock them.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 121 of 152
REAL-TIME CLOCK (RTC)
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 have an embedded real-time clock (RTC) as shown in
Figure 103. The external 32.768 kHz crystal is used as the clock
source for the RTC. Calibration is provided to compensate the
nominal crystal frequency and for variations in the external
crystal frequency over temperature. By default, the RTC is
maintained active in all power saving modes. The RTC counters
retain their values through watchdog resets and external resets.
They are only reset during a power-on reset.
8-BIT
PRESCALER
SECO ND COUNTE R
SEC
MI NU TE COUN T E R
MIN
HOUR COUNTER
HOUR
ITEN
ALARM
EVENT
8-BIT
INT E RVAL CO UNTER
INTVAL SFR
INTERVAL
TIMEBASE
SELECTION
MUX
RTCEN
32.768kHz
CRYSTAL
ITS1 ITS0
EQUAL?
CALIBRATION
RTCCOMP TEMPCAL
MIDNIGHT EVE NT
CALIBRATED
32.768kHz
06353-077
HUNDREDTHS COUNTE R
HTHSEC
Figure 103. RTC Implementation
RTC SFRS
Note that none of the real-time clock SFRs are bit addressable.
Table 127. Real-Time Clock SFR
SFR Address Description
TIMECON 0xA1 RTC Configuration (see Table 128).
HTHSEC 0xA2 Hundredths of a Second Counter
(see Table 129).
SEC 0xA3 Seconds Counter (see Table 130).
MIN 0xA4 Minutes Counter (see Table 131).
HOUR 0xA5 Hours Counter (see Table 132).
INTVAL 0xA6 Alarm Interval (see Table 133).
RTCCOMP 0xF6 RTC Nominal Compensation (see
Table 134).
TEMPCAL 0xF7 RTC Temperature Compensation (see
Table 135).
Protecting the RTC from Runaway Code
To protect the RTC from runaway code, a key must be written
to the KYREG SFR (Address, 0xC1) to obtain write access to the
interrupt pins configuration SFR (INTPR, Address 0xFF),
hundredths of a second counter SFR (HTHSEC, Address 0xA2),
seconds counter SFR (SEC, 0xA3), minutes counter SFR (MIN,
Address 0xA4), and hours counter SFR (HOUR, Address 0xA5).
KYREG should be set to 0xEA to unlock it and reset it to zero
after a timekeeping register is written to. The RTC registers can
be written using the following 8052 assembly code:
MOV KYREG,#0EAh
MOV INTPR,#080h
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 122 of 152
Table 128. RTC Configuration SFR (TIMECON, Address 0xA1)
Bit Mnemonic Default Description
7 MIDNIGHT 0 Midnight flag. This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by the user to
indicate that the midnight event has been serviced. In twenty-four hour mode, the midnight flag is
raised once a day at midnight. When this interrupt is used for wake-up from PSM2 to PSM1 mode, the
RTC interrupt must be serviced and the flag cleared to be allowed to enter PSM2 mode.
6 TFH 0 Twenty-four hour mode. This bit is retained during a watchdog reset or an external reset. It is reset after a
power-on reset (POR).
TFH Result
0 256-hour mode. The HOUR register rolls over from 255 to 0.
1 24-hour mode. The HOUR register rolls over from 23 to 0.
[5:4] ITS 0 Interval timer time base selection.
ITS Result (Time Base)
00 1/128 sec.
01 Second.
10 Minute.
11 Hour.
3 SIT 0 Interval Timer 1 alarm.
SIT Result
0 The ALARM flag is set after INTVAL counts, and then another interval count starts.
1 The ALARM flag is set after one time interval.
2 ALARM 0 Interval timer alarm flag. This bit is set when the configured time interval has elapsed. It can be cleared
by the user to indicate that the alarm event has been serviced. This bit cannot be set to 1 by user code.
1 ITEN 0 Interval timer enable.
ITEN Result
0 The interval timer is disabled. The 8-bit interval timer counter is reset.
1 Set this bit to enable the interval timer.
0 Reserved 1 This bit must be left set for proper operation.
Table 129. Hundredths of a Second Counter SFR (HTHSEC, Address 0xA2)
Bit Mnemonic Default Description
[7:0] HTHSEC 0 This counter updates every 1/128 second, referenced from the calibrated 32.768 kHz clock. It overflows
from 127 to 00, incrementing the seconds counter (SEC). This register is retained during a watchdog
reset or an external reset. It is reset after a POR.
Table 130. Seconds Counter SFR (SEC, Address 0xA3)
Bit Mnemonic Default Description
[7:0] SEC 0 This counter updates every second, referenced from the calibrated 32.768 kHz clock. It overflows from 59 to
00, incrementing the minutes counter (MIN). This register is retained during a watchdog reset or an
external reset. It is reset after a POR.
Table 131. Minutes Counter SFR (MIN, Address 0xA4)
Bit Mnemonic Default Description
[7:0] MIN 0 This counter updates every minute, referenced from the calibrated 32.768 kHz clock. It overflows from 59 to
00, incrementing the hours counter, HOUR. This register is retained during a watchdog reset or an
external reset. It is reset after a POR.
Table 132. Hours Counter SFR (HOUR, Address 0xA5)
Bit Mnemonic Default Description
[7:0] HOUR 0 This counter updates every hour, referenced from the calibrated 32.768 kHz clock. If the TFH bit in the
RTC configuration SFR (TIMECON, 0xA1) is set, the HOUR SFR overflows from 23 to 00, setting the
MIDNIGHT bit and creating a pending RTC interrupt. If the TFH bit is cleared, the HOUR SFR overflows from
255 to 00, setting the MIDNIGHT bit and creating a pending RTC interrupt. This register is retained during
a watchdog reset or an external reset. It is reset after a POR.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 123 of 152
Table 133. RTC Alarm Interval SFR (INTVAL, Address 0xA6)
Bit Mnemonic Default Description
[7:0] INTVAL 0 The interval timer counts according to the time base established in the ITS bits of the RTC configuration SFR
(TIMECON, 0xA1). When the number of counts is equal to INTVAL, the ALARM flag is set and a pending
RTC interrupt is created. Note that the interval counter is eight bits. Therefore, it can count up to 255 seconds,
for example.
Table 134. RTC Nominal Compensation SFR (RTCCOMP, Address 0xF6)
Bit Mnemonic Default Description
[7:0] RTCCOMP 0 Holds the nominal RTC compensation value at 25°C. This register is retained during a watchdog reset
or an external reset. It is reset after a POR.
Table 135. RTC Temperature Compensation SFR (TEMPCAL, Address 0xF7)
Bit Mnemonic Default Description
[7:0] TEMPCAL 0 The TEMPCAL SFR is adjusted based on the temperature read in the TEMPADC SFR to calibrate the RTC
over temperature. This allows the external crystal shift to be compensated over temperature. This
register is retained during a watchdog reset or an external reset. It is reset after a POR.
Table 136. Interrupt Pins Configuration SFR (INTPR, Address 0xFF)
Bit Mnemonic Default Description
7 RTCCAL 0 Controls the RTC calibration output. When set, the RTC calibration frequency selected by the FSEL bits
is output on the P0.2/CF1/RTCCAL pin.
[6:5] FSEL Sets RTC calibration output frequency and calibration window.
FSEL Result (Calibration Window, Frequency)
0 0 30.5 sec, 1 Hz
0 1 30.5 sec, 512 Hz
1 0 0.244 sec, 500 Hz
1 1 0.244 sec, 16 kHz
4 Reserved
[3:1] INT1PRG 000 Controls the function of the INT1 pin.
INT1PRG Result
x 0 0 GPIO
x 0 1 BCTRL
0 1 x INT1 input disabled
1 1 x INT1 input enabled
0 INT0PRG 0 Controls the function of the INT0 pin.
INT0PRG Result
0 INT0 input disabled
1 INT0 input enabled
Table 137. Key SFR (KYREG, Address 0xC1)
Bit Mnemonic Default Description
[7:0] KYREG 0 Write 0xA7 to this SFR before writing to the POWCON SFR, which unlocks KYREG.
Write 0xEA to this SFR before writing to the INTPR, HTHSEC, SEC, MIN, or HOUR timekeeping registers
to unlock KYREG.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 124 of 152
READ AND WRITE OPERATIONS
Writing to the RTC Registers
The RTC circuitry runs off a 32.768 kHz clock. The timekeeping
registers, the hundredths of a second counter SFR (HTHSEC,
Address 0xA2), seconds counter SFR (SEC, Address 0xA3),
minutes counter SFR (MIN, Address 0xA4), and hours counter
SFR (HOUR, Address 0xA5), are updated with a 32.768 kHz
clock. However, the RTC configuration SFR (TIMECON,
Address 0xA1) and alarm interval SFR (INTVAL, Address 0xA6)
are updated with a 128 Hz clock. It takes up to two 128 Hz clock
cycles from when the MCU writes to the TIMECON SFR or
INTVAL SFR until there is a successful update in the RTC.
To protect the RTC timekeeping registers from runaway code,
a key must be written to the Key SFR (KYREG, Address 0xC1),
which is described in Table 126, to obtain write access to the
HTHSEC, SEC, MIN and HOUR SFRs. KYREG should be set to
0xEA to unlock the timekeeping registers and reset to 0 after a
timekeeping register is written to. The RTC registers can be
written to using the following 8052 assembly code:
MOV RTCKey,#0EAh
CALL UpdateRTC
…
UpdateRTC:
MOV KYREG,RTCKey
MOV SEC,#30
MOV KYREG,RTCKey
MOV MIN,#05
MOV KYREG,RTCKey
MOV HOUR,#04
MOV KYREG,#00h
RET
Reading the RTC Counter SFRs
The RTC cannot be stopped to read the current time because
stopping the RTC introduces an error in its timekeeping.
Therefore, the RTC is read on the fly, and the counter registers
must be checked for overflow. This can be accomplished
through the following 8052 assembly code:
ReadAgain:
MOV R0,HTHSEC ; using Bank 0
MOV R1,SEC
MOV R2,MIN
MOV R3,HOUR
MOV A,HTHSEC
CJNE A, 00h, Re adAgai n ; 00h is R0 in
Bank 0
RTC MODES
The RTC can be configured in a 24-hour mode or a 256-hour
mode. A midnight event is generated when the RTC hour
counter rolls over from 23 to 0 or 255 to 0, depending on
whether the TFH bit is set in the RTC Configuration SFR
(TIMECON, Address 0xA1). The midnight event sets the
MIDNIGHT flag in the TIMECON SFR, and a pending RTC
interrupt is created. The RTC midnight event wakes the 8052
MCU core if the MCU is asleep in PSM2 mode when the
midnight event occurs.
In the 24-hour mode, the midnight event is generated once a
day at midnight. The 24-hour mode is useful for updating a
software calendar to keep track of the current day. The 256-hour
mode results in power savings during extended operation in
PSM2 mode because the MCU core wakes up less frequently.
RTC INTERRUPTS
The RTC midnight interrupt and alarm interrupt are enabled by
setting the ETI bit in the Interrupt Enable and Priority 2 SFR
(IEIP2, Address 0xA9). When a midnight or alarm event
occurs, a pending RTC interrupt is generated. If the RTC
interrupt is enabled, the program vectors to the RTC interrupt
address and the pending interrupt are cleared. If the RTC
interrupt is disabled, the RTC interrupt remains pending until
the RTC interrupt is enabled. The program then vectors to the
RTC interrupt address.
The MIDNIGHT flag and ALARM flag are set when the
midnight event and alarm event occur, respectively. The user
should manage these flags to keep track of which event caused
an RTC interrupt by servicing the event and clearing the
appropriate flag in the RTC interrupt servicing routine.
Note that if the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 are awakened by an RTC event, either by
the MIDNIGHT event or an ALARM event, the pending RTC
interrupt must be serviced before the device can go back to
sleep again. The ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 keep waking up until this interrupt has
been serviced.
Interval Timer Alarm
The RTC can be used as an interval timer. When the interval
timer is enabled by setting the ITEN bit in the RTC Configuration
SFR (TIMECON, Address 0xA1), the interval timer clock source
selected by the ITS1 and ITS0 bits is passed through an 8-bit
counter. This counter increments on every interval timer clock
pulse until it is equal to the value in the alarm interval SFR
(INTVAL, Address 0xA6). Then, an alarm event is generated,
setting the ALARM flag and creating a pending RTC interrupt.
If the SIT bit in the RTC configuration SFR (TIMECON,
Address 0xA1) is cleared, the 8-bit counter is cleared and starts
counting again. If the SIT bit is set, the 8-bit counter is held in
reset after the alarm occurs.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 125 of 152
Take care when changing the interval timer time base. The
recommended procedure is as follows:
1. If the alarm interval SFR (INTVAL, Address 0xA6) is going
to be modified, write to this register first. Then, wait for
one 128 Hz clock cycle to synchronize with the RTC,
64,000 cycles at a 4.096 MHz instruction cycle clock.
2. Disable the interval timer by clearing the ITEN bit in the
RTC configuration SFR (TIMECON, Address 0xA1).
Then, wait for one 128 Hz clock cycle to synchronize with
the RTC, 64,000 cycles at a 4.096 MHz instruction cycle
clock.
3. Read the TIMECON SFR to ensure that the ITEN bit is
clear. If it is not, wait for another 128 Hz clock cycle.
4. Set the time-base bits (ITS) in the TIMECON SFR to
configure the interval. Wait for a 128 Hz clock cycle for this
change to take effect.
The RTC alarm event wakes the 8052 MCU core if the MCU is
in PSM2 mode when the alarm event occurs.
RTC CALIBRATION
The RTC provides registers to compensate for the tolerance of
the crystal frequency and its variation over temperature.
Up to ±248 ppm frequency error can be calibrated with the RTC
circuitry. The compensation is fully digital and implemented by
adding or subtracting pulses from the crystal clock signal.
The resolution of the RTC nominal compensation SFR
(RTCCOMP, Address 0xF6) is ±2 ppm/LSB or 0.17 sec/day/LSB.
The RTC compensation circuitry adds the RTC temperature
compensation SFR (TEMPCAL, Address 0xF7) and the RTC
nominal compensation SFR (RTCCOMP, Address 0xF6) to
determine how much compensation is required. The sum of
these two registers is limited to ±248 ppm or 42.85 sec/day.
Calibrating the RTC
The nominal crystal frequency can be calibrated by adjusting
the RTCCOMP SFR so that the clock going into the RTC is
precisely 32.768 kHz at 25°C.
Calibration Flow
An RTC calibration pulse output is provided on the P0.2/CF1/
RTCCAL pin. Enable the RTC output by setting the RTCCAL
bit in the interrupt pins configuration SFR (INTPR,
Address 0xFF).
The RTC calibration is accurate to within ±2 ppm over a 30.5 sec
window in all operational modes: PSM0, PSM1, and PSM2. Two
output frequencies are offered for the normal RTC mode: 1 Hz
with FSEL = 00 and 512 Hz with FSEL = 01 in the interrupt pins
configuration SFR (INTPR, Address 0xFF).
A shorter window of 0.244 sec is offered for fast calibration
during PSM0 or PSM1 mode. Two output frequencies are
offered for this RTC calibration output mode: 500 Hz with
FSEL = 10 and 16 kHz with FSEL = 11 in the INTPR SFR.
Note that for the 0.244 second calibration window, the RTC is
clocked 125 times faster than in normal mode, resulting in
timekeeping registers that represent seconds/125, minutes/125,
and hours/125 instead of seconds, minutes, and hours.
Therefore, this mode should be used for calibration only.
Table 138. RTC Calibration Options
Option FSEL
Calibration
Window (sec)
fRTCCAL
(Hz)
Normal Mode 0 00 30.5 1
Normal Mode 1 01 30.5 512
Calibration Mode 0 10 0.244 500
Calibration Mode 1 11 0.244 16,000
When no RTC compensation is applied, RTCCOMP and
TEMPCAL are equal to zero, the nominal compensation
required to account for the error in the external crystal can be
determined. In this case, it is not necessary to wait for an entire
calibration window to determine the error in the pulse output.
Calculating at the error in frequency between two consecutive
pulses on the P0.2/CF1/RTCCAL pin is sufficient.
The value to write to the RTCCOMP SFR is calculated from the
% error or seconds per day error on the frequency output. Each
LSB of the RTCCOMP SFR represents 2 ppm of correction
where 1 sec/day error is equal to 11.57 ppm.
)(%5000 ErrorRTCCOMP ×=
)(
57.112
1Errorsec/dayRTCCOMP ×
×
=
During calibration, user software writes the current time. Refer
to the Read and Write Operations section for more information
on how to read and write to the RTC timekeeping registers.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 126 of 152
UART SERIAL INTERFACE
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 UART can be configured in one of four modes.
• Shift register with baud rate fixed at fCORE/12
• 8-bit UART with variable baud rate
• 9-bit UART with baud rate fixed at fCORE/64 or fCORE/32
• 9-bit UART with variable baud rate
Variable baud rates are defined by using an internal timer to
generate any rate between 300 bauds/sec and 115,200 bauds/sec.
The UART serial interface provided in the ADE7166/ADE7169/
ADE7566/ADE7569 is a full-duplex serial interface. It is also
receive buffered by storing the first received byte in a receive
buffer until the reception of the second byte is complete. The
physical interface to the UART is provided via the RxD
(P1.0/RxD) and TxD (P1.1/TxD) pins, and the firmware
interface is through the SFRs presented in Table 139.
Both the serial port receive and transmit registers are accessed
through the serial port buffer SFR (SBUF, Address 0x99).
Writing to SBUF loads the transmit register, and reading SBUF
accesses a physically separate receive register.
An enhanced UART mode is offered by using the UART timer
and by providing enhanced frame error, break error, and
overwrite error detection. This mode is enabled by setting the
EXTEN bit in the configuration SFR (CFG, Address 0xAF). See
the UART Additional Features section. The enhanced serial
baud rate control SFR (SBAUDT, Address 0x9E) and UART
timer fractional divider SFR (SBAUDF, Address 0x9D) are used
to configure the UART timer and to indicate the enhanced
UART errors.
UART SFRS
Table 139. Serial Port SFRs
SFR Address Bit Addressable Description
SCON 0x98 Yes Serial communications control (see Table 140).
SBUF 0x99 No Serial port buffer (see Table 141).
SBAUDT 0x9E No Enhanced serial baud rate control (see Table 142).
SBAUDF 0x9D No UART timer fractional divider (see Table 143).
Table 140. Serial Communications Control SFR (SCON, Address 0x98)
Bit Bit Address Mnemonic Default Description
[7:6] 0x9F, 0x9E SM0, SM1 00 UART serial mode select bits. These bits select the serial port operating mode.
SM0, SM1 Result (Selected Operating Mode)
00 Mode 0, shift register, fixed baud rate (fCORE/12).
01 Mode 1, 8-bit UART, variable baud rate.
10 Mode 2, 9-bit UART, fixed baud rate (fCORE/32) or (fCORE/16).
11 Mode 3, 9-bit UART, variable baud rate.
5 0x9D SM2 0 Multiprocessor communication enable bit. Enables multiprocessor communication in
Mode 2 and Mode 3 and framing error detection in Mode 1.
In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received.
If SM2 is cleared, RI is set as soon as the byte of data is received.
In Mode 2 or Mode 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0.
If SM2 is cleared, RI is set as soon as the byte of data is received.
4 0x9C REN 0 Serial port receive enable bit. Set by user software to enable serial port reception.
Cleared by user software to disable serial port reception.
3 0x9B TB8 0 Serial port transmit (Bit 9). The data loaded into TB8 is the ninth data bit transmitted in
Mode 2 and Mode 3.
2 0x9A RB8 0 Serial port receiver (Bit 9). The ninth data bit received in Mode 2 and Mode 3 is latched
into RB8. For Mode 1, the stop bit is latched into RB8.
1 0x99 TI 0 Serial port transmit interrupt flag. Set by hardware at the end of the eighth bit in Mode 0 or
at the beginning of the stop bit in Mode 1, Mode 2, and Mode 3.
TI must be cleared by user software.
0 0x98 RI 0 Serial port receive interrupt flag. Set by hardware at the end of the eighth bit in Mode 0 or
halfway through the stop bit in Mode 1, Mode 2, and Mode 3.
RI must be cleared by user software.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 127 of 152
Table 141. Serial Port Buffer SFR (SBUF, Address 0x99)
Bit Mnemonic Default Description
[7:0] SBUF 0 Serial port data buffer.
Table 142. Enhanced Serial Baud Rate Control SFR (SBAUDT, Address 0x9E)
Bit Mnemonic Default Description
7 OWE 0 Overwrite error. This bit is set when new data is received and RI = 1 (Bit 0 in the SCON SFR, Address
0x98). It indicates that SBUF was not read before the next character was transferred in, causing the
prior SBUF data to be lost. Write a 0 to this bit to clear it.
6 FE 0 Frame error. This bit is set when the received frame does not have a valid stop bit. This bit is read
only and updated every time a frame is received.
5 BE 0 Break error. This bit is set whenever the receive data line (Rx) is low for longer than a full transmission
frame, which is the time required for a start bit, eight data bits, a parity bit, and half a stop bit. This
bit is updated every time a frame is received.
[4:3] SBTH 0 Extended divider ratio for baud rate setting as shown in Table 144.
[2:0] DIV 0 Binary divider. See Table 144.
DIV[2:0] Result
000 Divide by 1.
001 Divide by 2.
010 Divide by 4.
011 Divide by 8.
100 Divide by 16.
101 Divide by 32.
110 Divide by 64.
111 Divide by 128.
Table 143. UART Timer Fractional Divider SFR (SBAUDF, Address 0x9D)
Bit Mnemonic Default Description
7 UARTBAUDEN 0 UART baud rate enable. Set to enable UART timer to generate the baud rate. When set, the SMOD
bit (PCON[7]), the TCLK bit (T2CON[4]), and the RCLK bit (T2CON[5]) are ignored.
Cleared to let the baud rate be generated as per a standard 8052.
6 Not implemented, write don’t care.
[5:0] SBAUDF 0 UART timer fractional divider Bit 5.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 128 of 152
Table 144. Common Baud Rates Using UART Timer with a 4.096 MHz PLL Clock
Ideal Baud CD SBTH DIV SBAUDT SBAUDF % Error
115,200 0 0 1 0x01 0x87 +0.16
115,200 1 0 0 0x00 0x87 +0.16
57,600 0 0 2 0x02 0x87 +0.16
57,600 1 0 1 0x01 0x87 +0.16
38,400 0 0 2 0x02 0xAB −0.31
38,400 1 0 1 0x01 0xAB −0.31
38,400 2 0 0 0x00 0xAB −0.31
19,200 0 0 3 0x03 0xAB −0.31
19,200 1 0 2 0x02 0xAB −0.31
19,200 2 0 1 0x01 0xAB −0.31
19,200 3 0 0 0x00 0xAB −0.31
9600 0 0 4 0x04 0xAB −0.31
9600 1 0 3 0x03 0xAB −0.31
9600 2 0 2 0x02 0xAB −0.31
9600 3 0 1 0x01 0xAB −0.31
9600 4 0 0 0x00 0xAB −0.31
4800 0 0 5 0x05 0xAB −0.31
4800 1 0 4 0x04 0xAB −0.31
4800 2 0 3 0x03 0xAB −0.31
4800 3 0 2 0x02 0xAB −0.31
4800 4 0 1 0x01 0xAB −0.31
4800 5 0 0 0x00 0xAB −0.31
2400 0 0 6 0x06 0xAB −0.31
2400 1 0 5 0x05 0xAB −0.31
2400 2 0 4 0x04 0xAB −0.31
2400 3 0 3 0x03 0xAB −0.31
2400 4 0 2 0x02 0xAB −0.31
2400 5 0 1 0x01 0xAB −0.31
2400 6 0 0 0x00 0xAB −0.31
300 0 2 7 0x17 0xAB −0.31
300 1 1 7 0x0F 0xAB −0.31
300 2 0 7 0x07 0xAB −0.31
300 3 0 6 0x06 0xAB −0.31
300 4 0 5 0x05 0xAB −0.31
300 5 0 4 0x04 0xAB −0.31
300 6 0 3 0x03 0xAB −0.31
300 7 0 2 0x02 0xAB −0.31
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 129 of 152
UART OPERATION MODES
Mode 0 (Shift Register with Baud Rate Fixed at fCORE/12)
Mode 0 is selected when the SM0 and SM1 bits in the serial
communications control register SFR (SCON, Address 0x98)
are cleared. In this shift register mode, serial data enters and
exits through the RxD pin. TxD outputs the shift clock. The baud
rate is fixed at fCORE/12. Eight data bits are transmitted or received.
Transmission is initiated by any instruction that writes to the
serial port buffer SFR (SBUF, Address 0x99). The data is shifted
out of the RxD line. The eight bits are transmitted with the least
significant bit (LSB) first.
Reception is initiated when the serial port receive enable bit
(REN, Bit 4) is 1 and the serial port receive interrupt bit (RI, Bit
0) is 0. When RI is cleared, the data is clocked into the RxD line,
and the clock pulses are output from the TxD line as shown in
Figure 104.
RxD
(DATA OUT)
TxD
(SHIFT CLOCK)
DATA BIT 0 DATA BIT 1 DATA BIT 6 DATA BIT 7
06353-078
Figure 104. 8-Bit Shift Register Mode
Mode 1 (8-Bit UART, Variable Baud Rate)
Mode 1 is selected by clearing SM0 (Bit 7) and setting SM1 (Bit
6). Each data byte (LSB first) is preceded by a start bit (0) and
followed by a stop bit (1). Therefore, each frame consists of 10
bits transmitted on the TxD pin or received on the RxD pin.
The baud rate is set by a timer overflow rate. Timer 1 or Timer 2
can be used to generate baud rates, or both timers can be used
simultaneously where one generates the transmit rate and the
other generates the receive rate. There is also a dedicated timer
for baud rate generation, the UART timer, which has a fractional
divisor to precisely generate any baud rate (see the UART Timer
Generated Baud Rates section).
Transmission is initiated by a write to the serial port buffer SFR
(SBUF, Address 0x99). Next, a stop bit (1) is loaded into the
ninth bit position of the interval serial port shift register. The
data is output bit-by-bit until the stop bit appears on TxD and
the transmit interrupt flag (TI) is automatically set as shown in
Figure 105.
TxD
TI
(SCON.1)
START
BIT D0 D1 D2 D3 D4 D5 D6 D7
STOP BIT
SET INTERRUPT
(FOR EXAMPLE,
READY FOR MORE DATA)
06353-079
Figure 105. 8-Bit Variable Baud Rate
Reception is initiated when a 1-to-0 transition is detected on
the RxD pin. Assuming that a valid start bit is detected,
character reception continues. The eight data bits are clocked
into the serial port shift register.
All of the following conditions must be met at the time the final
shift pulse is generated to receive a character:
• If the extended UART is disabled (EXTEN = 0 in the CFG
SFR, Address 0xAF)), RI must be 0 to receive a character.
This ensures that the data in the SBUF SFR is not
overwritten if the last received character has not been read.
• If frame error checking is enabled by setting SM2, the
received stop bit must be set to receive a character. This
ensures that every character received comes from a valid
frame, with both a start bit and a stop bit.
If any of these conditions is not met, the received frame is
irretrievably lost, and the receive interrupt flag (RI) is not set.
If the received frame has met these conditions, the following
events occur:
• The eight bits in the receive shift register are latched into
the SBUF SFR.
• The ninth bit (stop bit) is clocked into RB8 in the SCON SFR.
• The receiver interrupt flag (RI) is set.
Mode 2 (9-Bit UART with Baud Fixed at fCORE/64 or fCORE/32)
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode, the UART operates in 9-bit mode with a fixed baud rate.
The baud rate is fixed at fCORE/64 by default, although setting the
SMOD bit in the program control SFR (PCON, Address 0x87)
doubles the frequency to fCORE/32. Eleven bits are transmitted or
received: a start bit (0), eight data bits, a programmable ninth
bit, and a stop bit (1). The ninth bit is most often used as a parity
bit or as part of a multiprocessor communication protocol,
although it can be used for anything, including a ninth data bit,
if required.
To use the ninth data bit as part of a communication protocol for
a multiprocessor network such as RS-485, the ninth bit is set to
indicate that the frame contains the address of the device with
which the master wants to communicate. The devices on the
network are always listening for a packet with the ninth bit set
and are configured such that if the ninth bit is cleared, the frame
is not valid, and a receive interrupt is not generated. If the ninth
bit is set, all devices on the network receive the address and obtain a
receive character interrupt. The devices examine the address and, if
it matches one of the preprogrammed addresses of the devices,
that device configures itself to listen to all incoming frames, even
those with the ninth bit cleared. Because the master has initiated
communication with that device, all the following packets with
the ninth bit cleared are intended specifically for that addressed
device until another packet with the ninth bit set is received. If
the address does not match, the device continues to listen for
address packets.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 130 of 152
To transmit, the eight data bits must be written into the serial
port buffer SFR (SBUF, Address 0x99). The ninth bit must be
written to TB8 (Bit 3) in the serial communications control
Register Bit Description SFR (SCON, 0x98). When transmission
is initiated, the eight data bits from SBUF are loaded into the
transmit shift register (LSB first). The ninth data bit, held in
TB8, is loaded into the ninth bit position of the transmit shift
register. The transmission starts at the next valid baud rate
clock. The serial port transmit interrupt flag (TI, Bit 1) is set as
soon as the transmission completes, when the stop bit appears
on TxD.
All of the following conditions must be met at the time the final
shift pulse is generated to receive a character:
• If the extended UART is disabled (EXTEN = 0 in the CFG
SFR), RI must be 0 to receive a character. This ensures that
the data in SBUF is not overwritten if the last received
character has not been read.
• If multiprocessor communication is enabled by setting
SM2, the received ninth bit must be set to receive a character.
This ensures that only frames with the ninth bit set, which
are frames that contain addresses, generate a receive
interrupt.
If any of these conditions is not met, the received frame is
irretrievably lost, and the receive interrupt flag (RI) is not set.
Reception for Mode 2 is similar to that of Mode 1. The eight
data bytes are input at the RxD pin (LSB first) and loaded onto
the receive shift register. If the received frame has met the
previous criteria, the following events occur:
• The eight bits in the receive shift register are latched into
the SBUF SFR.
• The ninth data bit is latched into RB8 in the SCON SFR.
• The receiver interrupt flag (RI) is set.
Mode 3 (9-Bit UART with Variable Baud Rate)
Mode 3 is selected by setting both SM0 and SM1. In this mode,
the 8052 UART serial port operates in 9-bit mode with a variable
baud rate. The baud rate is set by a timer overflow rate. Timer 1
or Timer 2 can be used to generate baud rates, or both timers
can be used simultaneously where one generates the transmit
rate and the other generates the receive rate. There is also a
dedicated timer for baud rate generation, the UART timer,
which has a fractional divisor to precisely generate any baud
rate (see the UART Timer Generated Baud Rates section). The
operation of the 9-bit UART is the same as for Mode 2, but the
baud rate can be varied.
In all four modes, transmission is initiated by any instruction
that uses SBUF as a destination register. Reception is initiated in
Mode 0 when RI = 0 and REN = 1. Reception is initiated in the
other modes by the incoming start bit if REN = 1.
UART BAUD RATE GENERATION
Mode 0 Baud Rate Generation
The baud rate in Mode 0 is fixed.
⎟
⎠
⎞
⎜
⎝
⎛
=12
CORE
f
d RateMode 0 Bau
Mode 2 Baud Rate Generation
The baud rate in Mode 2 depends on the value of the PCON.7
(SMOD) bit in the program control SFR (PCON, 0x87). If
SMOD = 0, the baud rate is 1/32 of the core clock. If SMOD = 1,
the baud rate is 1/16 of the core clock.
Mode 2 Baud Rate = 32
2SMOD
× fCORE
Mode 1 and Mode 3 Baud Rate Generation
The baud rates in Mode 1 and Mode 3 are determined by the
overflow rate of the timer generating the baud rate, that is,
Timer 1, Timer 2, or the dedicated baud rate generator, UART
timer, which has an integer and a fractional divisor.
Timer 1 Generated Baud Rates
When Timer 1 is used as the baud rate generator, the baud rates
in Mode 1 and Mode 3 are determined by the Timer 1 overflow
rate. The value of SMOD is as follows:
Mode 1 or Mode 3 Baud Rate =
×
32
2SMOD
Timer 1 Overflow Rate
The Timer 1 interrupt should be disabled in this application.
The timer itself can be configured for either timer or counter
operation and in any of its three running modes. In the most
typical application, it is configured for timer operation in
autoreload mode (high nibble of TMOD = 0010 binary). In that
case, the baud rate is given by the following formula:
Mode 1 or Mode 3 Baud Rate = )256(32
2TH1
fCORE
SMOD
−
×
Timer 2 Generated Baud Rates
Baud rates can also be generated by using Timer 2. Using Timer 2
is similar to using Timer 1 in that the timer must overflow 16 times
before a bit is transmitted or received. Because Timer 2 has a
16-bit autoreload mode, a wider range of baud rates is possible.
Mode 1 or Mode 3 Baud Rate = 16
1 × Timer 2 Overflow Rate
Therefore, when Timer 2 is used to generate baud rates, the
timer increments every two clock cycles rather than every core
machine cycle as before. It increments six times faster than
Timer 1, and, therefore, baud rates six times faster are possible.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 131 of 152
)
÷(1 + SBAUDF/64)
UART TIMER
Rx/Tx CLOCK
f
CORE
UARTBAUDEN
Rx CLOCK
Tx CLOCK
TIMER 1/TIMER 2
Rx CLOCK
FRACTIONAL
DIVIDER
0
0
1
1
TIMER 1/TIMER 2
Tx CLOCK
÷32
÷2
DIV + SBTH
06353-081
Because Timer 2 has 16-bit autoreload capability, very low baud
rates are still possible. Timer 2 is selected as the baud rate
generator by setting TCLK and/or RCLK in Timer/Counter 2
control SFR (T2CON, Address 0xC8). The baud rates for transmit
and receive can be simultaneously different. Setting RCLK
and/or TCLK puts Timer 2 into its baud rate generator mode, as
shown in Figure 107.
In this case, the baud rate is given by the following formula:
Mode 1 or Mode 3 Baud Rate =
Figure 106. UART Timer, UART Baud Rate
()
[]
(
LRCAPHRCAP
fCORE
2:26553616 −× Two SFRs, enhanced serial baud rate control SFR (SBAUDT,
Address 0x9E) and UART timer fractional divider SFR
(SBAUDF, Address 0x9D), are used to control the UART timer.
SBAUDT is the baud rate control SFR; it sets up the integer
divider (DIV) and the extended divider (SBTH) for the UART
timer.
UART Timer Generated Baud Rates
The high integer dividers in a UART block mean that high speed
baud rates are not always possible. In addition, generating baud
rates requires the exclusive use of a timer, rendering it unusable
for other applications when the UART is required. To address
this problem, each ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 has a dedicated baud rate timer (UART
timer) specifically for generating highly accurate baud rates. The
UART timer can be used instead of Timer 1 or Timer 2 for gener-
ating very accurate high speed UART baud rates, including
115,200 bps. This timer also allows a much wider range of baud
rates to be obtained. In fact, every desired bit rate from 12 bps
to 393,216 bps can be generated to within an error of ±0.8%. The
UART timer also frees up the other three timers, allowing them
to be used for different applications. A block diagram of the
UART timer is shown in Figure 106.
The appropriate value to write to DIV (Bits [2:0]) and SBTH
(Bits [4:3]) bits can be calculated using the following formula
where fCORE is defined in the POWCON SFR (see Table 26).
Note that the DIV value must be rounded down to the nearest
integer.
()
2log
16
log ⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
×
=+ RateBaud
f
SBTHDIV
CORE
f
CORE
T2
PIN
TR2
CONTROL
TL2
(8 BITS) TH2
(8 BITS)
RELOAD
EXEN2
CONTROL
T2EX
PIN
TRANSITION
DETECTOR
EXF 2 TIMER 2
INTERRUPT
RCAP2L RCAP2H
TIMER 2
OVERFLOW
2
16
16
RCLK
TCLK
Rx
CLOCK
Tx
CLOCK
0
0
1
1
10
SMOD
TIMER 1
OVERFLOW
C/ T2 = 0
C/ T2 = 1
NOTE: AVAILABILITY OF ADDITIONAL
EXTERNAL INTERRUPT
06353-080
Figure 107. Timer 2, UART Baud Rates
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 132 of 152
SBAUDF is the fractional divider ratio required to achieve the
required baud rate. The appropriate value for SBAUDF can be
calculated with the following formula:
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−
××
×= +1
216
64 RateBaud
f
SBAUDF SBTHDIV
CORE
Note that SBAUDF should be rounded to the nearest integer.
After the values for DIV and SBAUDF are calculated, the actual
baud rate can be calculated with the following formula:
⎟
⎠
⎞
⎜
⎝
⎛+××
=
+
64
1216 SBAUDF
f
RateBaudActual
SBTHDIV
CORE
For example, to obtain a baud rate of 9600 bps while operating
at a core clock frequency of 4.096 MHz with the PLL CD bits
equal to 0,
()
474.4
2log
960016
4,096,000
log
==
⎟
⎠
⎞
⎜
⎝
⎛
×
=+ SBTHDIV
Note that the DIV result is rounded down.
0x2B67.421
9600216
000,096,4
64 3==
⎟
⎠
⎞
⎜
⎝
⎛−
××
×=SBAUDF
Thus, the actual baud rate is 9570 bps, resulting in a 0.31% error.
UART ADDITIONAL FEATURES
Enhanced Error Checking
The extended UART provides frame error, break error, and
over-write error detection. Framing errors occur when a stop
bit is not present at the end of the frame. A missing stop bit
implies that the data in the frame may not have been received
properly. Break error detection indicates whether the Rx line
has been low for longer than a 9-bit frame. It indicates that the
data just received, a 0 or null character, is not valid because the
master has disconnected. Overwrite error detection indicates when
the received data has not been read fast enough and, as a result, a
byte of data has been lost.
The 8052 standard UART offers frame-error checking for an 8-bit
UART through the SM2 and RB8 bits. Setting the SM2 bit prevents
frames without a stop bit from being received. The stop bit is
latched into the RB8 bit in the serial communications control
SFR (SCON, Address 0x98). This bit can be examined to
determine if a valid frame was received. The 8052 does not,
however, provide frame error checking for a 9-bit UART. This
enhanced error checking functionality is available through the
frame error bit, FE, in the enhanced serial baud rate control SFR
(SBAUDT, Address 0x9E). The FE bit is set on framing errors
for both 8-bit and 9-bit UARTs.
Rx
RI
FE
EXTEN = 1
D7D6D5D4D3D2D1D0 STOP
START
06353-082
Figure 108. UART Timing in Mode 1
Rx
RI
FE
EXTEN = 1
D7D6D5D4D3D2D1D0 D8 STOP
START
06353-083
Figure 109. UART Timing in Mode 2 and Mode 3
The 8052 standard UART does not provide break error detection.
However, for an 8-bit UART, a break error can be detected when
the received character is 0, a null character, and when there is
no stop bit because the RB8 bit is low. Break error detection is
not possible for a 9-bit 8052 UART because the stop bit is not
recorded. The ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 enhanced break error detection is available
through the BE bit in the SBAUDT SFR.
The 8052 standard UART prevents overwrite errors by not
allowing a character to be received when the RI, receive interrupt
flag, is set. However, it does not indicate if a character has been
lost because the RI bit is set when the frame is received. The
enhanced UART overwrite error detection provides this infor-
mation. When the enhanced 8052 UART is enabled, a frame is
received regardless of the state of the RI flag. If RI = 1 when a
new byte is received, the byte in SCON is overwritten, and the
overwrite error flag is set. The overwrite error flag is cleared
when SBUF is read.
The extended UART is enabled by setting the EXTEN bit in the
Configuration SFR (CFG, Address 0xAF).
UART TxD Signal Modulation
There is an internal 38 kHz signal that can be OR’ed with the
UART transmit signal for use in remote control applications
(see the 38 kHz Modulation section).
One of the events that can wake the MCU from sleep mode is
activity on the Rx pin (see the 3.3 V Peripherals and Wake-Up
Events section).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 133 of 152
SERIAL PERIPHERAL INTERFACE (SPI)
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 integrate a complete hardware serial peripheral
interface on-chip. The SPI is full duplex so that eight bits of data
are synchronously transmitted and simultaneously received.
This SPI implementation is double buffered, allowing users to
read the last byte of received data while a new byte is shifted in.
The next byte to be transmitted can be loaded while the current
byte is shifted out.
The SPI port can be configured for master or slave operation.
The physical interface to the SPI is via the MISO (P0.5/MISO),
MOSI (P0.4/MOSI/SDATA), SCLK (P0.6/SCLK/T0), and SS
(P0.7/SS/T1) pins, while the firmware interface is via the SPI
Configuration SFR 1 (SPIMOD1, Address 0xE8), the SPI
Configuration SFR 2 (SPIMOD2, Address 0xE9), the SPI
interrupt status SFR (SPISTAT, Address 0xEA), the SPI/I2C
transmit buffer SFR (SPI2CTx, Address 0x9A), and the SPI/I2C
receive buffer SFR (SPI2CRx, Address 0x9B).
Note that the SPI pins are shared with the I2C pins. Therefore, the
user can enable only one interface at a time. The SCPS bit in the
configuration SFR (CFG, Address 0xAF) selects which peripheral
is active.
SPI REGISTERS
Table 145. SPI SFR List
SFR Address Mnemonic R/W Length (Bits) Default Description
0x9A SPI2CTx W 8 0 SPI/I2C transmit buffer (see Table 146).
0x9B SPI2CRx R 8 0 SPI/I2C receive buffer (see Table 147).
0xE8 SPIMOD1 R/W 8 0x10 SPI Configuration SFR 1 (see Table 148).
0xE9 SPIMOD2 R/W 8 0 SPI Configuration SFR 2 (see Table 149).
0xEA SPISTAT R/W 8 0 SPI/I2C interrupt status (see Table 150).
Table 146. SPI/I2C Transmit Buffer SFR (SPI2CTx, Address 0x9A)
Bit Mnemonic Default Description
[7:0] SPI2CTx 0 SPI or I2C transmit buffer. When the SPI2CTx SFR is written, its content is transferred to the transmit
FIFO input. When a write is requested, the FIFO output is sent on the SPI or I2C bus.
Table 147. SPI/I2C Receive Buffer SFR (SPI2CRx, Address 0x9B)
Bit Mnemonic Default Description
[7:0] SPI2CRx 0 SPI or I2C receive buffer. When SPI2CRx SFR is read, one byte from the receive FIFO output is
transferred to SPI2CRx SFR. A new data byte from the SPI or I2C bus is written to the FIFO input.
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Table 148. SPI Configuration SFR 1 (SPIMOD1, Address 0xE8)
Bit Address Mnemonic Default Description
[7:6] 0xEF to
0xEE
Reserved 0 Reserved.
5 0xED INTMOD 0 SPI interrupt mode.
INTMOD Result
0 SPI interrupt is set when the SPI Rx buffer is full.
1 SPI interrupt is set when the SPI Tx buffer is empty.
4 0xEC AUTO_SS 1 Master mode, SS output control (see ). Figure 110
AUTO_SS Result
0 The SS pin is held low while this bit is cleared. This allows manual chip select
control using the SS pin.
1 Single byte read or write. The SS pin goes low during a single byte
transmission and then returns high.
Continuous Transfer. The SS pin goes low during the duration of the multibyte
continuous transfer and then returns high.
3 0xEB SS_EN 0 Slave mode, SS input enable.
When this bit is set to Logic 1, the SS pin is defined as the slave select input pin for the SPI
slave interface.
2 0xEA RxOFW 0 Receive buffer overflow write enable.
RxOFW Result
0 If the SPI2CRx SFR has not been read when a new data byte is received,
the new byte is discarded.
1 If the SPI2CRx SFR has not been read when a new data byte is received,
the new byte overwrites the old data.
[1:0] 0xE9 to
0xE8
SPIR 0 Master mode, SPI SCLK frequency.
SPIR Result
00 fCORE/8 = 512 kHz (if fCORE = 4.096 MHz).
01 fCORE/16 = 256 kHz (if fCORE = 4.096 MHz).
10 fCORE/32 = 128 kHz (if fCORE = 4.096 MHz).
11 fCORE/64 = 64 kHz (if fCORE = 4.096 MHz).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
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Table 149. SPI Configuration SFR 2 (SPIMOD2, Address 0xE9)
Bit Mnemonic Default Description
7 SPICONT 0 Master mode, SPI continuous transfer mode enable bit.
SPICONT Result
0 The SPI interface stops after one byte is transferred and SS is deasserted. A new data transfer
can be initiated after a stalled period.
1 The SPI interface continues to transfer data until no valid data is available in the SPI2CTx SFR.
SS remains asserted until the SPI2CTx SFR and the transmit shift registers are empty.
6 SPIEN 0 SPI interface enable bit.
SPIEN Result
0 The SPI interface is disabled.
1 The SPI interface is enabled.
5 SPIODO 0 SPI open-drain output configuration bit.
SPIODO Result
0 Internal pull-up resistors are connected to the SPI outputs.
1 The SPI outputs are open drain and need external pull-up resistors. The pull-up voltage should
not exceed the specified operating voltage.
4 SPIMS_b 0 SPI master mode enable bit.
SPIMS_b Result
0 The SPI interface is defined as a slave.
1 The SPI interface is defined as a master.
3 SPICPOL 0 SPI clock polarity configuration bit (see Figure 112).
SPICPOL Result
0 The default state of SCLK is low, and the first SCLK edge is rising. Depending on the SPICPHA bit,
the SPI data output changes state on the falling or rising edge of SCLK while the SPI data input is
sampled on the rising or falling edge of SCLK.
1 The default state of SCLK is high, and the first SCLK edge is falling. Depending on the SPICPHA
bit, the SPI data output changes state on the rising or falling edge of SCLK while the SPI data
input is sampled on the falling or rising edge of SCLK.
2 SPICPHA 0 SPI clock phase configuration bit (see Figure 112).
SPICPHA Result
0 The SPI data output changes state when SS goes low at the second edge of SCLK and then every
two subsequent edges, whereas the SPI data input is sampled at the first SCLK edge and then
every two subsequent edges.
1 The SPI data output changes state at the first edge of SCLK and then every two subsequent
edges, whereas the SPI data input is sampled at the second SCLK edge and then every two
subsequent edges.
1 SPILSBF 0 Master mode, LSB first configuration bit.
SPILSBF Result
0 The MSB of the SPI outputs is transmitted first.
1 The LSB of the SPI outputs is transmitted first.
0 TIMODE 1 Transfer and interrupt mode of the SPI interface.
TIMODE Result
1 This bit must be set to 1 for proper operation.
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Table 150. SPI Interrupt Status SFR (SPISTAT, Address 0xEA)
Bit Mnemonic Default Description
7 BUSY 0 SPI peripheral busy flag.
BUSY Result
0 The SPI peripheral is idle.
1 The SPI peripheral is busy transferring data in slave or master mode.
6 MMERR 0 SPI multimaster error flag.
MMERR Result
0 A multiple master error has not occurred.
1 If the SS_EN bit (SPIMOD1, Address 0xE8) is set, enabling the slave select input and
asserting the SS pin while the SPI peripheral is transferring data as a master, this flag is
raised to indicate the error.
Write a 0 to this bit to clear it.
5 SPIRxOF 0 SPI receive overflow error flag. Reading the SPI2CRx SFR clears this bit.
SPIRxOF TIMODE Result
0 X The SPI2CRx SFR (Address 0x9B) contains valid data.
1 1
This bit is set if the SPI2CRx SFR is not read before the end of the next byte
transfer. If the RxOFW bit (SPIMOD1, Address 0xF8) is set and this condition
occurs, SPI2CRx is overwritten.
4 SPIRxIRQ 0 SPI receive mode interrupt flag. Reading the SPI2CRx SFR clears this bit.
SPIRxIRQ TIMODE Result
0 X The SPI2CRx register does not contain new data.
1 0
This bit is set when the SPI2CRx register contains new data. If the SPI/I2C
interrupt is enabled, an interrupt is generated when this bit is set. If the SPI2CRx
register is not read before the end of the current byte transfer, the transfer stops
and the SS pin is deasserted.
1 1 The SPI2CRx register contains new data.
3 SPIRxBF 0 Status bit for SPI Rx buffer. When set, the Rx FIFO is full. A read of the SPI2CRx clears this flag.
2 SPITxUF 0 Status bit for SPI Tx buffer. When set, the Tx FIFO is underflowing and data can be written into SPI2CTx
(Address 0x9A). Write a 0 to this bit to clear it.
1 SPITxIRQ 0 SPI transmit mode interrupt flag. Writing new data to the SPI2CTx SFR clears this bit.
SPITxIRQ TIMODE Result
0 X The SPI2CTx SFR is full.
1 0 The SPI2CTx SFR is empty.
1 1
This bit is set when the SPI2CTx SFR is empty. If the SPI/I2C interrupt is enabled,
an interrupt is generated when this bit is set. If new data is not written into the
SPI2CTx SFR before the end of the current byte transfer, the transfer stops, and
the SS pin is deasserted. Write a 0 to this bit to clear it.
0 SPITxBF 0 Status bit for the SPI Tx buffer. When set, the SPI Tx buffer is full. Write a 0 to this bit to clear it.
SPI PINS
MISO (Master In, Slave Out Data I/O Pin)
The MISO (P0.5/MISO) pin is configured as an input line in
master mode and as an output line in slave mode. The MISO line
on the master (data in) should be connected to the MISO line in
the slave device (data out). The data is transferred as byte-wide
(8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin)
The MOSI (P0.4/MOSI/SDATA) pin is configured as an output
line in master mode and as an input line in slave mode. The
MOSI line on the master (data out) should be connected to the
MOSI line in the slave device (data in).The data is transferred as
byte-wide (8-bit) serial data, MSB first.
SCLK (Serial Clock I/O Pin)
The master serial clock (SCLK) is used to synchronize the data
being transmitted and received through the MOSI and MISO
data lines. The SCLK (P0.6/SCLK/T0) pin is configured as an
output in master mode and as an input in slave mode.
In master mode, the bit rate, polarity, and phase of the clock are
controlled by the SPI Configuration SFR 1 (SPIMOD1, Address
0xE8) and SPI Configuration SFR 2 (SPIMOD2, Address 0xE9).
In slave mode, the SPI Configuration SFR 2 (SPIMOD2,
Address 0xE9) must be configured with the phase and polarity
of the expected input clock.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
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In both master and slave modes, the data is transmitted on one
edge of the SCLK signal and sampled on the other. It is important,
therefore, that the SPICPHA and SPICPOL bits be configured
the same for the master and slave devices.
SS (Slave Select Pin)
In SPI slave mode, a transfer is initiated by the assertion of SS
low. The SPI port then transmits and receives 8-bit data until
the data is concluded by the deassertion of SS according to the
SPICON bit setting. In slave mode, SS is always an input.
In SPI master mode, the SS (P0.7/T1) can be used to control
data transfer to a slave device. In the automatic slave select
control mode, the SS is asserted low to select the slave device
and then raised to deselect the slave device after the transfer is
complete. Automatic slave select control is enabled by setting the
AUTO_SS bit in the SPI Configuration SFR 1 (SPIMOD1,
Address 0xE8).
In a multimaster system, the SS can be configured as an input so
that the SPI peripheral can operate as a slave in some situations
and as a master in others. In this case, the slave selects for the
slaves controlled by this SPI peripheral should be generated
with general I/O pins.
SPI MASTER OPERATING MODES
The double buffered receive and transmit registers can be used to
maximize the throughput of the SPI peripheral by continuously
streaming out data in master mode. The continuous transmit mode
is designed to use the full capacity of the SPI. In this mode, the
master transmits and receives data until the SPI/I2C transmit
buffer SFR (SPI2CTx, Address 0x9A) is empty at the start of
a byte transfer. Continuous mode is enabled by setting the
SPICONT bit (Bit 7) in the SPI Configuration SFR 2 (SPIMOD2,
Address 0xE9). The SPI peripheral also offers a single byte
read/write function.
In master mode, the type of transfer is handled automatically,
depending on the configuration of the SPICONT bit in the SPI
Configuration SFR 2 (SPIMOD2, 0xE9). The following
procedures show the sequence of events that should be
performed for each master operating mode. Based on the SS
configuration, some of these events take place automatically.
Procedures for Using SPI as a Master
Single Byte Write Mode, SPICONT (SPIMOD2[7]) = 0
1. Write to the SPI2CTx SFR.
2. SS is asserted low, and a write routine is initiated.
3. The SPITxIRQ interrupt flag is set when the SPI2CTx
register is empty.
4. SS is deasserted high.
5. Write to SPI2CTx SFR to clear the SPITxIRQ interrupt
flag.
6. Write to SPI2CTx SFR to clear the SPITxIRQ interrupt
flag.
Continuous Mode, SPICONT (SPIMOD2[7]) = 1
1. Write to the SPI2CTx SFR.
2. SS is asserted low, and a write routine is initiated.
3. Wait for the SPITxIRQ interrupt flag to write to SPI2CTx SFR.
4. Transfer continues until the SPI2CTx register and transmit
shift registers are empty.
5. The SPITxIRQ interrupt flag is set when the SPI2CTx
register is empty.
6. SS is deasserted high.
7. Write to SPI2CTx SFR to clear the SPITxIRQ interrupt flag.
Figure 110 shows the SPI output for certain automatic chip select
and continuous mode selections. Note that if the continuous mode
is not used, a short delay is inserted between transfers.
SCLK
SS
DOUT
DIN DIN1 DIN2
AUTO _S S = 1
SPICO NT = 0
SCLK
SS
DOUT
DIN DIN1
AUTO _S S = 1
SPICO NT = 1 DIN2
AUTO _S S = 0
SPICO NT = 0
(MANUAL SS CO NTROL )
DOUT1 DOUT2
DOUT1 DOUT2
SCLK
SS
DOUT
DIN DIN1 DIN2
DOUT1 DOUT2
06353-084
Figure 110. Automatic Chip Select and Continuous Mode Output
Note that reading the content of the SPI/I2C receive buffer SFR
(SPI2CRx, Address 0x9B) should be done using a 2-cycle
instruction set such as MOV A or SPI2CRX. Using a 3-cycle
instruction such as MOV 0x3D or SPI2CRX does not transfer
the right information into the target register.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
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SPI INTERRUPT AND STATUS FLAGS
The SPI interface has several status flags that indicate the status
of the double-buffered receive and transmit registers. Figure 111
shows when the status and interrupt flags are raised. The transmit
interrupt occurs when the internal serial port shift register is loaded
with the data in the SPI/I2C transmit buffer SFR (SPI2CTx,
Address 0x9A) register. If the SPI master is in transmit
operating mode, and the SPI/I2C transmit buffer SFR (SPI2CTx,
Address 0x9A) register has not been written with new data by
the beginning of the next byte transfer, the transmit operation
stops.
When a new byte of data is received in the SPI/I2C receive
buffer SFR (SPI2CRx, Address 0x9B), the SPI receive interrupt
flag is raised. If the data in the SPI/I2C receive buffer SFR
(SPI2CRx, Address 0x9B) is not read before new data is ready to
be loaded into the SPI/I2C receive buffer SFR (SPI2CRx,
Address 0x9B), an overflow condition has occurred. This
overflow condition, indicated by the SPIRxOF flag, forces the
new data to be discarded or overwritten if the RxOFW bit
(SPIMOD1, Address 0xE8) is set.
SPITx
TRANSMIT SHIFT REGISTER
SPITxIRQ = 1
SPITx (EMPTY)
TRANSMIT SHIFT REGISTER
STOPS TRANSFER IF TIMODE = 1
SPIRx
RECEIVE SHIFT REGISTER
SPIRxIRQ = 1
SPIRx (FULL)
RECEIVE SHIFT REGISTER
SPIRxOF = 1
06353-085
Figure 111. SPI Receive and Transmit Interrupt and Status Flags
SCLK
(SPICPOL=0)
MISO
SCLK
(SPICPOL = 1)
MOSI
SPIRx1 AND
SPITx1 FLAGS
SS_b
SPIRx0 AND
SPITx0 FLAGS
SPICPHA = 1
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB ?
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB ?
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB?
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB?
MISO
MOSI
SPIRx1 AND
SPITx1 FLAGS
SPIRx0 AND
SPITx0 FLAGS
SPICPHA = 0
06353-086
Figure 112. SPI Timing Configurations
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
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I2C-COMPATIBLE INTERFACE
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 support a fully licensed I2C interface. The I2C
interface is implemented as a full hardware master.
SDATA (P0.4/MOSI/SDATA) is the data I/O pin, and SCLK
(P0.6/SCLK/T0) is the serial clock. These two pins are shared
with the MOSI and SCLK pins of the on-chip SPI interface.
Therefore, the user can enable only one interface or the other
on these pins at any given time. The SCPS bit (Bit 5) in the
configuration SFR (CFG, Address 0xAF) selects which
peripheral is active.
The two pins used for data transfer, SDATA and SCLK, are
configured in a wire-AND format that allows arbitration in
a multimaster system.
The transfer sequence of an I2C system consists of a master device
initiating a transfer by generating a start condition while the bus
is idle. The master transmits the address of the slave device and
the direction of the data transfer in the initial address transfer. If
the slave acknowledges, the data transfer is initiated. This continues
until the master issues a stop condition and the bus becomes idle.
SERIAL CLOCK GENERATION
The I2C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (256 kHz) or standard mode (32 kHz).
The bit rate is defined in the I2CMOD SFR as follows:
]0:1[2
216 CRI
CORE
SCLK
f
f×
=
SLAVE ADDRESSES
The I2C slave address SFR (I2CADR, Address 0xE9) contains
the slave device ID. The LSB of this register contains a
read/write request. A write to this SFR starts the I2C
communication.
I2C REGISTERS
The I2C peripheral interface consists of five SFRs:
• I2CMOD
• SPI2CSTAT
• I2CADR
• SPI2CTx
• SPI2CRx
Because the SPI and I2C serial interfaces share the same pins,
they also share the same SFRs, such as the SPI2CTx and SPI2CRx
SFRs. In addition, the I2CMOD, I2CADR, and SPI2CSTAT, and
SPI2CTx SFRs are shared with the SPIMOD1, SPIMOD2, and
SPISTAT SFRs, respectively.
Table 151. I2C SFR List
SFR Address Mnemonic R/W Length Default Description
0x9A SPI2CTx W 8 SPI/I2C transmit buffer (see Table 146).
0x9B SPI2CRx R 8 0 SPI/I2C receive buffer (see Table 147).
0xE8 I2CMOD R/W 8 0 I2C mode (see Table 152).
0xE9 I2CADR R/W 8 0 I2C slave address (see Table 153).
0xEA SPI2CSTAT R/W 8 0 I2C interrupt status register (see Table 154).
Table 152. I2C Mode SFR (I2CMOD, Address 0xE8)
Bit Bit Address Mnemonic Default Description
7 0xEF I2CEN 0 I2C enable bit. When this bit is set to Logic 1, the I2C interface is enabled. A write to the
I2CADR SFR starts a communication.
[6:5] 0xEE to 0xED I2CR 0 I2C SCLK frequency.
I2CR Result
00 fCORE/16 = 256 kHz if fCORE = 4.096 MHz.
01 fCORE/32 = 128 kHz if fCORE = 4.096 MHz.
10 fCORE/64 = 64 kHz if fCORE = 4.096 MHz.
11 fCORE/128 = 32 kHz if fCORE = 4.096 MHz.
[4:0] 0xEC to 0xE8 I2CRCT 0 Configures the length of the I2C received FIFO buffer. The I2C peripheral stops when the
I2CRCT bits + 1 byte have been read, or if an error occurs.
Table 153. I2C Slave Address SFR (I2CADR, Address 0xE9)
Bit Mnemonic Default Description
[7:1] I2CSLVADR 0 Address of the I2C slave being addressed. Writing to this register starts the I2C transmission (read or write).
0 I2CR_W 0 Command bit for read or write. When this bit is set to Logic 1, a read command is transmitted on the
I2C bus. Data from the slave in the SPI2CRx SFR (Address 0x9B) is expected after a command byte.
When this bit is set to Logic 0, a write command is transmitted on the I2C bus. Data to slave is expected
in the SPI2CTx SFR.
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Table 154. I2C Interrupt Status Register SFR (SPI2CSTAT, Address 0xEA)
Bit Mnemonic Default Description
7 I2CBUSY 0 This bit is set to Logic 1 when the I2C interface is used. When set, the Tx FIFO is emptied.
6 I2CNOACK 0 I2C no acknowledgement transmit interrupt. This bit is set to Logic 1 when the slave device
does not send an acknowledgement. The I2C communication is stopped after this event.
Write a 0 to this bit to clear it.
5 I2CRxIRQ 0 I2C receive interrupt. This bit is set to Logic 1 when the receive FIFO is not empty.
Write a 0 to this bit to clear it.
4 I2CTxIRQ 0 I2C Transmit Interrupt. This bit is set to Logic 1 when the transmit FIFO is empty.
Write a 0 to this bit to clear it.
[3:2] I2CFIFOSTAT 0 Status bits for 3- or 4-bytes deep I2C FIFO. The FIFO monitored in these two bits is the one currently
used in I2C communication (receive or transmit) because only one FIFO is active at a time.
I2CFIFOSTAT Result
00 FIFO empty
01 Reserved
10 FIFO half full
11 FIFO full
1 I2CACC_ERR 0 Set when trying to write and read at the same time. Write a 0 to this bit to clear it.
0 I2CTxWR_ERR 0 Set when a write was attempted when the I2C transmit FIFO was full. Write a 0 to this bit to clear it.
READ AND WRITE OPERATIONS
SCLK
SDATA
START BY
MASTER
ACK BY
SLAVE
ACK BY
MASTER
FRAME 2
DATA BYTE 1 FROM MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
19 91
A0A1A2A3A4A5A6 R/W D0D1D2D3D4D5D6D7
91
D0D1D2D3D4D5D6D7
FRAME N + 1
DATA BYTE N FROM SLAVE
STOP BY
MASTER
NACK BY
MASTER
06353-087
Figure 113. I2C Read Operation
SCLK
SDATA
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
FRAME 2
DATA BYTE 1 FROM MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
1919
STOP BY
MASTER
A0A1A2A3A4A5A6 R/W D0D1D2D3D4D5D6D7
06353-088
Figure 114. I2C Write Operation
Figure 113 and Figure 114 depict I2C read and write operations,
respectively. Note that the LSB of the I2CADR SFR is used to
select whether a read or write operation is performed on the
slave device. During the read operation, the master acknowledges
are generated automatically by the I2C peripheral. The master
generated NACK (no acknowledge) before the end of a read
operation is also automatically generated after the I2CRCT bits
have been read from the slave. If the I2CADR register is
updated during a transmission, instead of generating a stop at
the end of the read or write operation, the master generates a
start condition and continues with the next communication.
Reading the SPI/I2C Receive Buffer SFR (SPI2CRx,
Address 0x9B)
Reading the SPI2CRx SFR should be done with a 2-cycle
instruction, such as
Mov a, spi2crx or Mov R0, spi2crx.
A 3-cycle instruction such as
Mov 3dh, spi2crx
does not transfer the right data into RAM Address 0x3D.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 141 of 152
I2C RECEIVE AND TRANSMIT FIFOS
The I2C peripheral has a 4-byte receive FIFO and a 4-byte
transmit FIFO. The buffers reduce the overhead associated with
using the I2C peripheral. Figure 115 shows the operation of the
I2C receive and transmit FIFOs.
The Tx FIFO can be loaded with four bytes to be transmitted to
the slave at the beginning of a write operation. When the
transmit FIFO is empty, the I2C transmit interrupt flag is set,
and the PC vectors to the I2C interrupt vector if this interrupt is
enabled. If a new byte is not loaded into the Tx FIFO before it is
needed in the transmit shift register, the communication stops.
An error, such as not receiving an acknowledge, also causes the
communication to terminate. In case of an error during a write
operation, the Tx FIFO is flushed.
The Rx FIFO allows four bytes to be read in from the slave
before the MCU has to read the data. A receive interrupt can
be generated after each byte is received or when the Rx FIFO
is full. If the peripheral is reading from a slave address, the
communication stops when the number of received bytes equals
the number set in the I2CRCT bits. An error, such as not
receiving an acknowledge, also causes the communication to
terminate.
I
2
CTx
4 BYTE FIFO
MOV I
2
CTx, TxDATA1
MOV I
2
CTx, TxDATA2
MOV I
2
CTx, TxDATA3
MOV I
2
CTx, TxDATA4
CODE TO FILL Tx FIFO:
TRANSMIT SHIFT REGISTER
I
2
CRx
RECEIVE SHIFT REGISTER
4 BYTE FIFO
CODE TO READ Rx FIFO:
MOV A, I
2
CRx; RESULT: A = RxDATA1
MOV A, I
2
CRx; RESULT: A = RxDATA2
MOV A, I
2
CRx; RESULT: A = RxDATA3
MOV A, I
2
CRx; RESULT: A = RxDATA4
TxDATA1
TxDATA2
TxDATA3
TxDATA4
RxDATA4
RxDATA3
RxDATA2
RxDATA1
06353-089
Figure 115. I2C FIFO Operation
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 142 of 152
I/O PORTS
PARALLEL I/O
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 use three input/output ports to exchange data with
external devices. In addition to performing general-purpose
I/O, some are capable of driving an LCD or performing alternate
functions for the peripherals available on-chip. In general, when
a peripheral is enabled, the pins associated with it cannot be
used as a general-purpose I/O. The I/O port can be configured
through the SFRs listed in Table 155.
Table 155. I/O Port SFRs
SFR Address Bit Addressable Description
P0 0x80 Yes Port 0 register.
P1 0x90 Yes Port 1 register.
P2 0xA0 Yes Port 2 register.
EPCFG 0x9F No Extended port
configuration.
PINMAP0 0xB2 No Port 0 weak
pull-up enable.
PINMAP1 0xB3 No Port 1 weak
pull-up enable.
PINMAP2 0xB4 No Port 2 weak
pull-up enable.
The three bidirectional I/O ports have internal pull-ups that can
be enabled or disabled individually for each pin. The internal
pull-ups are enabled by default. Disabling an internal pull-up
causes a pin to become open drain. Weak internal pull-ups are
configured through the PINMAPx SFRs.
Figure 116 shows a typical bit latch and I/O buffer for an I/O
pin. The bit latch (one bit in the SFR of each port) is represented
as a Type D flip-flop, which clocks in a value from the internal
bus in response to a write-to-latch signal from the CPU. The
Q output of the flip-flop is placed on the internal bus in response
to a read latch signal from the CPU. The level of the port pin
itself is placed on the internal bus in response to a read pin
signal from the CPU. Some instructions that read a port activate
the read latch signal, and others activate the read pin signal. See
the Read-Modify-Write Instructions section for details.
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
Q
LATCH
DV
DD
Px.x
PIN
INTERNAL
PULL-UP
ALTERNATE
OUTPUT
FUNCTION
ALTERNATE
INPUT
FUNCTION
Q
CLOSED: PINMAPx.x = 0
OPEN: PINMAPx.x = 1
06353-090
Figure 116. Port 0 Bit Latch and I/O Buffer
Weak Internal Pull-Ups Enabled
A pin with weak internal pull-up enabled is used as an input by
writing a 1 to the pin. The pin is pulled high by the internal pull-
ups, and the pin is read using the circuitry shown in Figure 116.
If the pin is driven low externally, it sources current because of
the internal pull-ups.
A pin with internal pull-up enabled is used as an output by
writing a 1 or a 0 to the pin to control the level of the output. If
a 0 is written to the pin, it drives a logic low output voltage
(VOL) and is capable of sinking 1.6 mA.
Open Drain (Weak Internal Pull-Ups Disabled)
When the weak internal pull-up on a pin is disabled, the pin
becomes open drain. Use this open-drain pin as a high impedance
input by writing a 1 to the pin. The pin is read using the circuitry
shown in Figure 116. The open-drain option is preferable for
inputs because it draws less current than the internal pull-ups
that were enabled.
38 kHz Modulation
Every ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 provides a 38 kHz modulation signal. The 38 kHz
modulation is accomplished by internally XOR’ing the level
written to the I/O pin with a 38 kHz square wave. Then, when
a 0 is written to the I/O pin, it is modulated as shown in
Figure 117.
38kHz MODULATION
SIGNAL
OUTPUT AT
MOD38 PIN
LEVEL WRITTEN
TO MOD38
06353-091
Figure 117. 38 kHz Modulation
Uses for this 38 kHz modulation include IR modulation of
a UART transmit signal or a low power signal to drive an
LED. The modulation can be enabled or disabled with the
MOD38EN bit (Bit 4) in the CFG SFR (Address 0xAF). The
38 kHz modulation is available on eight pins, selected by the
MOD38[7:0] bits in the extended port configuration SFR
(EPCFG, Address 0x9F).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 143 of 152
I/O REGISTERS
Table 156. Extended Port Configuration SFR (EPCFG, Address 0x9F)
Bit Mnemonic Default Description
7 MOD38_FP21 0 This bit enables 38 kHz modulation on the P1.6/FP21 pin.
6 MOD38_FP22 0 This bit enables 38 kHz modulation on the P1.5/FP22 pin.
5 MOD38_FP23 0 This bit enables 38 kHz modulation on the P1.4/T2/FP23 pin.
4 MOD38_TxD 0 This bit enables 38 kHz modulation on the P1.1/TxD pin.
3 MOD38_CF1 0 This bit enables 38 kHz modulation on the P0.2/CF1/RTCCAL pin.
2 MOD38_SSb 0 This bit enables 38 kHz modulation on the P0.7/SS/T1 pin.
1 MOD38_MISO 0 This bit enables 38 kHz modulation on the P0.5/MISO pin.
0 MOD38_CF2 0 This bit enables 38 kHz modulation on the P0.3/CF2 pin.
Table 157. Port 0 Weak Pull-Up Enable SFR (PINMAP0, Address 0xB2)
Bit Mnemonic Default Description
7 PINMAP0.7 0 The weak pull-up on P0.7 is disabled when this bit is set.
6 PINMAP0.6 0 The weak pull-up on P0.6 is disabled when this bit is set.
5 PINMAP0.5 0 The weak pull-up on P0.5 is disabled when this bit is set.
4 PINMAP0.4 0 The weak pull-up on P0.4 is disabled when this bit is set.
3 PINMAP0.3 0 The weak pull-up on P0.3 is disabled when this bit is set.
2 PINMAP0.2 0 The weak pull-up on P0.2 is disabled when this bit is set.
1 PINMAP0.1 0 The weak pull-up on P0.1 is disabled when this bit is set.
0 PINMAP0.0 0 The weak pull-up on P0.0 is disabled when this bit is set.
Table 158. Port 1 Weak Pull-Up Enable SFR (PINMAP1, Address 0xB3)
Bit Mnemonic Default Description
7 PINMAP1.7 0 The weak pull-up on P1.7 is disabled when this bit is set.
6 PINMAP1.6 0 The weak pull-up on P1.6 is disabled when this bit is set.
5 PINMAP1.5 0 The weak pull-up on P1.5 is disabled when this bit is set.
4 PINMAP1.4 0 The weak pull-up on P1.4 is disabled when this bit is set.
3 PINMAP1.3 0 The weak pull-up on P1.3 is disabled when this bit is set.
2 PINMAP1.2 0 The weak pull-up on P1.2 is disabled when this bit is set.
1 PINMAP1.1 0 The weak pull-up on P1.1 is disabled when this bit is set.
0 PINMAP1.0 0 The weak pull-up on P1.0 is disabled when this bit is set.
Table 159. Port 2 Weak Pull-Up Enable SFR (PINMAP2, Address 0xB4)
Bit Mnemonic Default Description
[7:6] Reserved 0 Reserved. Should be left cleared.
5 PINMAP2.5 0 The weak pull-up on RESET is disabled when this bit is set.
4 Reserved 0 Reserved. Should be left cleared.
3 PINMAP2.3 0 Reserved. Should be left cleared.
2 PINMAP2.2 0 The weak pull-up on P2.2 is disabled when this bit is set.
1 PINMAP2.1 0 The weak pull-up on P2.1 is disabled when this bit is set.
0 PINMAP2.0 0 The weak pull-up on P2.0 is disabled when this bit is set.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 144 of 152
Table 160. Port 0 SFR (P0, Address 0x80)
Bit Bit Address Mnemonic Default Description1
7 0x87 T1 1 This bit reflects the state of the P0.7/SS/T1 pin. It can be written to or read.
6 0x86 T0 1 This bit reflects the state of the P0.6/SCLK/T0 pin. It can be written to or read.
5 0x85 1 This bit reflects the state of the P0.5/MISO pin. It can be written to or read.
4 0x84 1 This bit reflects the state of the P0.4/MOSI/SDATA pin. It can be written to or read.
3 0x83 CF2 1 This bit reflects the state of the P0.3/CF2 pin. It can be written to or read.
2 0x82 CF1 1 This bit reflects the state of the P0.2/CF1 pin. It can be written to or read.
1 0x81 1 This bit reflects the state of the P0.1/FP19 pin. It can be written to or read.
0 0x80 INT1 1 This bit reflects the state of the BCTRL/INT1/P0.0 pin. It can be written to or read.
1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.
Table 161. Port 1 SFR (P1, Address 0x90)
Bit Bit Address Mnemonic Default Description1
7 0x97 1 This bit reflects the state of the P1.7/FP20 pin. It can be written to or read.
6 0x96 1 This bit reflects the state of the P1.6/FP21 pin. It can be written to or read.
5 0x95 1 This bit reflects the state of the P1.5/FP22 pin. It can be written to or read.
4 0x94 T2 1 This bit reflects the state of the P1.4/T2/FP23 pin. It can be written to or read.
3 0x93 T2EX 1 This bit reflects the state of the P1.3/T2EX/FP24 pin. It can be written to or read.
2 0x92 1 This bit reflects the state of the P1.2/FP25 pin. It can be written to or read.
1 0x91 TxD 1 This bit reflects the state of the P1.1/TxD pin. It can be written to or read.
0 0x90 RxD 1 This bit reflects the state of the P1.0/RxD pin. It can be written to or read.
1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.
Table 162. Port 2 SFR (P2, Address 0xA0)
Bit Bit Address Mnemonic Default Description1
[7:4] 0x97 to 0x94 0x1F These bits are unused and should remain set.
3 0x93 P2.3 1 This bit reflects the state of the P2.3/SDEN pin. It can be written only.
2 0x92 P2.2 1 This bit reflects the state of the P2.2/FP16 pin. It can be written to or read.
1 0x91 P2.1 1 This bit reflects the state of the P2.1/FP17 pin. It can be written to or read.
0 0x90 P2.0 1 This bit reflects the state of the P2.0/FP18 pin. It can be written to or read.
1 When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 145 of 152
Table 163. Port 0 Alternate Functions
Pin No. Alternate Function Alternate Function Enable
P0.0 BCTRL external battery control input Set INT1PROG = X01 in the interrupt pins configuration SFR (INTPR,
Address 0xFF).
INT1 external interrupt Set EX1 in the interrupt enable SFR (IE, Address 0xA8).
INT1 wake-up from PSM2 operating mode Set INT1PROG = 11X in the interrupt pins configuration SFR (INTPR,
Address 0xFF).
P0.1 FP19 LCD segment pin Set FP19EN in the LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED).
P0.2 CF1 ADE calibration frequency output Clear the DISCF1 bit in the ADE energy measurement internal MODE1
register (Address 0x0B).
P0.3 CF2 ADE calibration frequency output Clear the DISCF2 bit in the ADE energy measurement internal MODE1
register (Address 0x0B).
P0.4 MOSI SPI data line Set the SCPS bit in the configuration SFR (CFG, Address 0xAF) and set the
SPIEN bit in the SPI configuration SFR 2 (SPIMOD2, Address 0xE9).
SDATA I2C data line Clear the SCPS bit in the configuration SFR (CFG, Address 0xAF) and set the
I2CEN bit in the I2C Mode SFR (I2CMOD, Address 0xE8).
P0.5 MISO SPI data line Set the SCPS bit in the configuration SFR (CFG, Address 0xAF) and set the
SPIEN bit in the SPI configuration SFR 2 (SPIMOD2, Address 0xE9).
P0.6 SCLK serial clock for I2C or SPI Set the I2CEN bit in the I2C Mode SFR (I2CMOD, Address 0xE8) or the SPIEN bit
in the SPI configuration SFR 2 (SPIMOD2, Address 0xE9) to enable the I2C or
SPI interface.
T0 Timer 0 input Set the C/T0 bit in the Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD,
Address 0x89) to enable T0 as an external event counter.
P0.7 SS SPI slave select input for SPI in slave mode Set the SS_EN bit in the SPI configuration SFR 1 (SPIMOD1, Address 0xE8).
SS SPI slave select output for SPI in master mode Set the SPIMS_b bit in the SPI configuration SFR 2 (SPIMOD2, Address 0xE9).
T1 Timer 1 input Set the C/T1 bit in the timer/counter 0 and timer/counter 1 mode SFR (TMOD,
Address 0x89) to enable T1 as an external event counter.
Table 164. Port 1 Alternate Functions
Pin No. Alternate Function Alternate Function Enable
P1.0 RxD receiver data input for UART Set the REN bit in the serial communications control register bit description
SFR (SCON, Address 0x98).
Rx edge wake-up from PSM2 operating mode Set RXPROG[1:0] = 11 in the peripheral configuration SFR (PERIPH, Address
0xF4).
P1.1 TxD transmitter data output for UART This pin becomes TxD as soon as data is written into SBUF.
P1.2 FP25 LCD segment pin Set FP25EN in the LCD segment enable SFR (LCDSEGE, Address 0x97).
P1.3 FP24 LCD segment pin Set FP24EN in the LCD segment enable SFR (LCDSEGE, Address 0x97).
T2EX Timer 2 control input Set EXEN2 in the timer/counter 2 control SFR (T2CON, Address 0xC8).
P1.4 FP23 LCD segment pin Set FP23EN in the LCD segment enable SFR (LCDSEGE, Address 0x97).
T2 Timer 2 input Set the C/T2 bit in the timer/counter 2 control SFR (T2CON, Address 0xC8) to
enable T2 as an external event counter.
P1.5 FP22 LCD segment pin Set FP22EN in the LCD segment enable SFR (LCDSEGE, Address 0x97).
P1.6 FP21 LCD segment pin Set FP21EN in the LCD segment enable SFR (LCDSEGE, Address 0x97).
P1.7 FP20 LCD segment pin Set FP20EN in the LCD segment enable SFR (LCDSEGE, Address 0x97).
Table 165. Port 2 Alternate Functions
Pin No. Alternate Function Alternate Function Enable
P2.0 FP18 LCD segment pin Set FP18EN in the LCD segment enable 2 SFR (LCDSEGE2, Address 0xED).
P2.1 FP17 LCD segment pin Set FP17EN in the LCD Segment enable 2 SFR (LCDSEGE2, Address 0xED).
P2.2 FP16 LCD segment pin Set FP16EN in the LCD segment enable 2 SFR (LCDSEGE2, Address 0xED).
P2.3 SDEN serial download pin sampled on reset.
P2.3 is an output only.
Enabled by default.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 146 of 152
PORT 0
Port 0 is controlled directly through the bit-addressable Port 0
SFR (P0, Address 0x80). The weak internal pull-ups for Port 0
are configured through the Port 0 weak pull-up Enable SFR
(PINMAP0, Address 0xB2); they are enabled by default. The
weak internal pull-up is disabled by writing a 1 to PINMAP0.x.
Port 0 pins also have various secondary functions, as described
in Table 163.
The alternate functions of Port 0 pins can be activated only if
the corresponding bit latch in the Port 0 SFR contains a 1.
Otherwise, the port pin remains at 0.
PORT 1
Port 1 is an 8-bit bidirectional port controlled directly through
the bit-addressable Port 1 SFR (P1, Address 0x90). The weak
internal pull-ups for Port 1 are configured through the Port 1
weak pull-up enable SFR (PINMAP1, Address 0xB3); they are
enabled by default. The weak internal pull-up is disabled by
writing a 1 to PINMAP1.x.
Port 1 pins also have various secondary functions as described
in Table 164. The alternate functions of Port 1 pins can be
activated only if the corresponding bit latch in the Port 1 SFR
contains a 1. Otherwise, the port pin remains at 0.
PORT 2
Port 2 is a 4-bit bidirectional port controlled directly through
the bit-addressable Port 2 SFR (P2, Address 0xA0). Note that
P2.3 can be used as an output only. Consequently, any read
operation, such as a CPL P2.3, cannot be executed on this I/O.
The weak internal pull-ups for Port 2 are configured through
the Port 2 weak pull-up enable SFR (PINMAP2, Address 0xB4);
they are enabled by default. The weak internal pull-up is
disabled by writing a 1 to PINMAP2.x.
Port 2 pins also have various secondary functions as described
in Table 165. The alternate functions of Port 2 pins can be
activated only if the corresponding bit latch in the Port 2 SFR
contains a 1. Otherwise, the port pin remains at 0.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 147 of 152
DETERMINING THE VERSION OF THE PART
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 holds in its internal flash registers a value that defines
its version. This value helps to determine whether users have the
latest version of the part. The version of the ADE7116/ADE7156/
ADE7166/ADE7169/ADE7566/ADE7569 that corresponds to
this data sheet is ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 V3.4.
This value can be accessed as follows:
1. Launch HyperTerminal with a 9600 baud rate.
2. Put the part in serial download mode by first holding
SDEN to logic low, then resetting the part.
3. Hold the SDEN pin.
4. Press and release the RESET pin.
A string should appear on the HyperTerminal screen containing
the part name and version number, for example, ADE7116V3.4,
ADE7156V3.4, ADE7166V3.4, ADE7169V3.4, ADE7566V3.4,
or ADE7569V3.4.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 148 of 152
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
051706-A
TOP VIEW
(PINS DOWN)
1
16
17
33
32
48
4964
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
12.20
12.00 SQ
11. 80
PIN 1
1.60
MAX
0.75
0.60
0.45
10.20
10.00 SQ
9.80
VIEW A
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
0.15
0.05
7°
3.5°
0°
Figure 118. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
PIN 1
INDICATOR
TOP
VIEW
8.75
BSC SQ
9.00
BSC SQ
1
64
16
17
49
48
32
33
0.50
0.40
0.30
0.50 BSC 0.20 REF
12° MAX 0.80 MAX
0.65 TYP
1.00
0.85
0.80
7.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX
*4.85
4.70 SQ
4.55
EXPOSED PAD
(BOTTOM VIEW)
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
EXCEPT FOR EXPOSED PAD DIMENSION
082908-B
SEATING
PLANE
PIN 1
INDICATOR
0.30
0.25
0.18
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 119. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 149 of 152
ORDERING GUIDE
Model1
Anti-
Tamper
di/dt Sensor
Interface VAR Flash (kB)
Temperature
Range Package Description
Package
Option
ADE7116ASTZF162, 3, 4Yes No No 16 −40°C to +85°C 64-Lead LQFP ST-64-2
ADE7116ASTZF16-RL2, 3, 4
No No No 16 −40°C to +85°C 64-Lead LQFP, Reel ST-64-2
ADE7116ASTZF82, 3, 4
Yes No No 8 −40°C to +85°C 64-Lead LQFP ST-64-2
ADE7116ASTZF8-RL2, 3, 4
No No No 8 −40°C to +85°C 64-Lead LQFP, Reel ST-64-2
ADE7156ASTZF162, 4
Yes No No 16 −40°C to +85°C 64-Lead LQFP ST-64-2
ADE7156ASTZF16-RL2, 4
Yes No No 16 −40°C to +85°C 64-Lead LQFP, Reel ST-64-2
ADE7156ASTZF82, 4
Yes No No 8 −40°C to +85°C 64-Lead LQFP ST-64-2
ADE7156ASTZF8-RL2, 4
Yes No No 8 −40°C to +85°C 64-Lead LQFP, Reel ST-64-2
ADE7166ACPZF82
Yes No No 8 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1
ADE7166ACPZF8-RL2
Yes No No 8 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1
ADE7166ACPZF162
Yes No No 16 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1
ADE7166ACPZF16-RL2
Yes No No 16 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1
ADE7166ASTZF82
Yes No No 8 −40°C to +85°C 64-Lead LQFP ST-64-2
ADE7166ASTZF8-RL2
Yes No No 8 −40°C to +85°C 64-Lead LQFP, Reel ST-64-2
ADE7166ASTZF162
Yes No No 16 −40°C to +85°C 64-Lead LQFP ST-64-2
ADE7166ASTZF16-RL2
Yes No No 16 −40°C to +85°C 64-Lead LQFP, Reel ST-64-2
ADE7169ACPZF162
Yes Yes Yes 16 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1
ADE7169ACPZF16-RL2
Yes Yes Yes 16 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1
ADE7169ASTZF82
Yes Yes Yes 8 −40°C to +85°C 64-Lead LQFP ST-64-2
ADE7169ASTZF8-RL2
Yes Yes Yes 8 −40°C to +85°C 64-Lead LQFP, Reel ST-64-2
ADE7169ASTZF162
Yes Yes Yes 16 −40°C to +85°C 64-Lead LQFP ST-64-2
ADE7169ASTZF16-RL2
Yes Yes Yes 16 −40°C to +85°C 64-Lead LQFP, Reel ST-64-2
ADE7566ACPZF82
No No No 8 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1
ADE7566ACPZF8-RL2
No No No 8 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1
ADE7566ACPZF162
No No No 16 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1
ADE7566ACPZF16-RL2
No No No 16 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1
ADE7566ASTZF82
No No No 8 −40°C to +85°C 64-Lead LQFP ST-64-2
ADE7566ASTZF8-RL2
No No No 8 −40°C to +85°C 64-Lead LQFP, Reel ST-64-2
ADE7566ASTZF162
No No No 16 −40°C to +85°C 64-Lead LQFP ST-64-2
ADE7566ASTZF16-RL2
No No No 16 −40°C to +85°C 64-Lead LQFP, Reel ST-64-2
ADE7569ACPZF162
No Yes Yes 16 −40°C to +85°C 64-Lead LFCSP_VQ CP-64-1
ADE7569ACPZF16-RL2
No Yes Yes 16 −40°C to +85°C 64-Lead LFCSP_VQ, Reel CP-64-1
ADE7569ASTZF82
No Yes Yes 8 −40°C to +85°C 64-Lead LQFP ST-64-2
ADE7569ASTZF8-RL2
No Yes Yes 8 −40°C to +85°C 64-Lead LQFP, Reel ST-64-2
ADE7569ASTZF162
No Yes Yes 16 −40°C to +85°C 64-Lead LQFP ST-64-2
ADE7569ASTZF16-RL2
No Yes Yes 16 −40°C to +85°C 64-Lead LQFP, Reel ST-64-2
ADE8052Z-PRG12
ADE Programmer
ADE8052Z-DWDL12
ADE Downloader
ADE8052Z-EMUL12
ADE Emulator
EVAL-ADE7169F16EBZ2
Evaluation Board
EVAL-ADE7569F16EBZ2
Evaluation Board
1 All models have W + VA + rms, 5 V LCD, and RTC.
2 Z = RoHS Compliant Part.
3 The ADE7116 does not support battery and temperature ADC measurements.
4 The ADE7116 and the ADE7156 do not have internally adjustable LCD levels.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 150 of 152
NOTES
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 151 of 152
NOTES
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 152 of 152
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06353-0-11/08(B)
