SAA7367 - Philips Semiconductors / NXP Semiconductors

DATA SH EET

Product speciﬁcation

Supersedes data of 1996 Jun 17

File under Integrated Circuits, IC01

1998 Nov 17

INTEGRATED CIRCUITS

SAA7367

Bitstream conversion ADC for

digital audio systems

1998 Nov 17 2

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

FEATURES

•Total Harmonic Distortion plus Noise

(THD + N) = −88 dB (0.004%); DR = 93 dB;

S/N = 97 dB

•Simple interfacing to analog inputs

•Small, non-critical PCB layout

•Low pin-out SO24 package (pin-compatible to

SAA7366)

•4 flexible serial interface modes

•4.5 to 5.5 V operation

•Standby mode

•Detection of digital signal ≥−1 dB amplitude

•Up to 18 significant bits serial output

•Selectable high-pass filter.

APPLICATIONS

The device is designed for the digital acquisition of analog

audio signals for digital audio systems such as:

•Compact Disc-Recordable (CD-R)

•Audio digital signal processing systems for hi-fi and

musical instrument applications

•Digital Audio Tape (DAT).

GENERAL DESCRIPTION

The SAA7367 is a CMOS low-cost stereo

Analog-to-Digital Converter (ADC) using the Philips

bitstream conversion technique.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VDDD digital supply voltage 4.5 5.0 5.5 V

IDDD digital supply current −17 −mA

VDDA analog supply voltage 4.5 5.0 5.5 V

IDDA analog supply current −13 −mA

fBCK clock input frequency 4.60 12.288 12.8 MHz

fssample rate 18 48 50 kHz

THD + N total harmonic distortion plus

noise at 0 dB input −−88 −80 dB

DR dynamic range at −60 dB 90 93 −dB

S/N signal-to-noise ratio −97 −dB

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

SAA7367 SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

1998 Nov 17 3

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGE645

SAA7367

REFERENCE

VOLTAGE

GENERATOR

CLOCK

GENERATION

AND

CONTROL

SIGMA-

DELTA

MODULATOR

REFERENCE

CURRENT

GENERATOR

TIMING

GENERATOR

DECIMATION FILTER

STAGE 1

COMB

FILTER

STAGE 2

3 HALF-BAND

FILTERS

HIGH-PASS

FILTER

SERIAL OUTPUT

INTERFACE

SIGMA-

DELTA

MODULATOR

REFERENCE

VOLTAGE

GENERATOR

operational

amplifier operational

amplifier

operational

amplifier operational

amplifier

23 11 1

2121513

SFOR

STDB

3OVLD

VDDD

VSSD

CKIN

SDO

SWS

SCK

HPEN

TESTB

VrefR

VSSA

SLAVE

TEST1

BOR

BOL

BIL

Iref

BIR

VDACP

VDACN

VDDA VrefL

1998 Nov 17 4

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

PINNING

SYMBOL PIN DESCRIPTION

SFOR 1 TTL level input; in normal mode this input selects the serial interface output format; output

format is selected as follows:

SFOR = HIGH selects Format 1

SFOR = LOW selects Format 2 (similar to I2S)

STDB 2 schmitt-trigger input; in normal mode, this input is used to select standby mode:

STDB = HIGH selects normal operation

STDB = LOW selects standby mode (low power consumption)

OVLD 3 TTL level output; in normal mode this output indicates whether the internal digital signal is

within 1 dB of maximum; if so, the output will go HIGH for 131072 clock cycles (approximately

11 ms); in standby mode this output is forced LOW

CKIN 4 CMOS level input; system clock input; nominally clocked at 256fs

VDDD 5 digital supply voltage (4.5 to 5.5 V)

VSSD 6 digital ground

SDO 7 TTL level output (3-state); in normal mode this pin outputs data from the serial interface; in

standby mode, this output is high impedance

SWS 8 TTL level input/output; serial interface word select signal; in master mode (SLAVE = LOW),

this pin outputs the serial interface word select signal; in slave mode (SLA VE = HIGH), this pin

is the word select input to the serial interface; in standby mode (STDB = LOW) this pin is

always an input (high impedance); for polarity: see Table 1

SCK 9 TTL level input/output; in master mode (SLAVE = LOW) the pin outputs the serial interface bit

clock; in slave mode (SLAVE = HIGH) this pin is the input for the external bit clock; data on

SDO is clocked out on the HIGH-to-LOW transition of SCK; the data is valid on the

LOW-to-HIGH transition

TEST1 10 Test 1; TTL level input with internal pull-down; in slave mode (slave = HIGH), this pin is used

to select extra serial interface formats (see Table 2)

HPEN 11 TTL level input; this input is used to enable the internal high-pass ﬁlter when HIGH; in

scan-test mode (TESTB = LOW and TEST1 = LOW) this pin functions as ‘scan chain c’ input

TESTB 12 Test B; CMOS level input with internal pull-up; in normal applications, this input should be left

HIGH

VSSA 13 analog ground; this pin is internally connected to VSS via the on-chip substrate contacts

Iref 14 current reference generator output; 33 kΩ in parallel with 22 nF is connected from this pin to

VSSA

VrefR 15 right channel analog reference output voltage (1⁄2VDDA)

BIR 16 buffer operational ampliﬁer inverting input for right channel

BOR 17 buffer operational ampliﬁer output for right channel

VDACN 18 negative 1-bit DAC reference voltage input, connected to 0 V

VDACP 19 positive 1-bit DAC reference voltage input, connected to +5 V

BOL 20 buffer operational ampliﬁer output for left channel

BIL 21 buffer operational ampliﬁer inverting input for left channel

VrefL 22 left channel analog reference output voltage (1⁄2VDDA)

VDDA 23 analog supply voltage (4.5 to 5.5 V)

1998 Nov 17 5

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

Table 1 SWS polarity

Table 2 Selection of serial interface formats via TEST1

SLAVE 24 TTL level input; used to select the serial interface operating mode:

SLAVE = HIGH selects slave mode

SLAVE = LOW selects master mode

CONDITIONS POLARITY

SLAVE AND TEST1 SWS SFOR

SLAVE = LOW or TEST1 = LOW LOW LOW left data

LOW HIGH right data

SLAVE = HIGH and TEST1 = HIGH LOW LOW right data

LOW HIGH left data

CONDITIONS SELECTED FORMAT

SFOR TEST1

HIGH LOW format 1

HIGH format 3

LOW LOW format 2

HIGH format 4

SYMBOL PIN DESCRIPTION

Fig.2 Pin configuration.

handbook, halfpage

SFOR

STDB

OVLD

CKIN

VDDD

VSSD

SDO

SWS

SCK

TEST1

HPEN

TESTB

SLAVE

VDDA

VrefL

BIL

VDACP

VDACN

BOL

BOR

BIR

VrefR

Iref

VSSA

SAA7367

MGE644

FUNCTIONAL DESCRIPTION

General

The SAA7367 is a bitstream conversion CMOS ADC for

digital audio systems. The conversion is achieved using a

third-order Sigma-Delta Modulator (SDM), running at

128 times the output sample frequency (fs). The high

oversampling ratio greatly simplifies the design of the

analog input anti-alias filter. In most events, the internal

buffer operational amplifier, configured as a low-pass filter,

will suffice. The 1-bit code from the SDM is filtered and

down-sampled (decimated) to 1fs by Finite Impulse

Response (FIR) filters. An optional I2R high-pass filter is

provided to remove DC, if required. The device has been

designed with ease of use, low board area and low

application costs in mind.

Clock frequency

The external clock input on pin CKIN runs at 256fs, which

can range from 18 to 50 kHz.

1998 Nov 17 6

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

Input buffer

Two input buffers are provided, one for each channel, for

signal amplitude matching, signal buffering and anti-alias

filter purposes. These are configured for inverting use.

Access is provided by pins BIL, BIR (inverting inputs) and

BOL, BOR (outputs), for left and right channels

respectively. By the choice of feedback component values,

the application signal amplitude can be matched to the

requirements of the ADC.

Typically, the operational amplifiers are configured as

low-pass filters with a gain of 1 and a pole at

approximately 5fs.

Remark: the complete ADC is non-inverting. Hence, a

positive DC input (referenced to Vref) will yield a positive

digital output.

Input level

The overall system gain is proportional VDDA, or more

accurately the potential difference between the DAC

reference voltages (VVDACP) and (VVDACN). For

convenience, the ADC input signal amplitude is defined as

that amplitude seen on BOL or BOR, the operational

amplifier outputs (i.e. the input to the SDM). Also, the 0 dB

input level is defined as that which gives a −1 dB (actually

−1.12 dB) digital output, relative to full-scale swing. This

reduced gain provides headroom to accommodate small

random DC offsets, without causing the digital output to

clip.

Hence:

The user of the IC should ensure that, when all sources of

signal amplitude variation are taken into account, the

maximum input signal should conform to the 0 dB level.

In the event that the maximum signal level cannot be

pre-determined, e.g. live microphone input, the average

signal level should be set at −10 to −20 dB down. The

exact value will depend on the application and the balance

between headroom and operating Signal-to-Noise Ratio

(SNR).

Behaviour during overload

As previously defined, the maximum input level for normal

operation is 0 dB. If the input level exceeds this value,

clipping may occur. Within the system, excessive

amplitudes are detected after the high-pass filter.

Infringements are limited to the maximum permitted

positive or negative values 217 −1 or −217 respectively.

VI0dB()V

VDACP VVDACN

–()

5V(RMS)

-------------------------------------------------------

Input signals in the range 0 to 1 dB may or may not be

clipped, depending on the values of DC dither and small

random offsets in the analog circuitry.

When using the recommended application circuitry,

clipping will initially be observed on negative peaks, due to

the use of negative DC dither.

The maximum level of overload that can be safely

tolerated is application circuit dependent. In the case of the

recommended circuit, the following applies: the inverting

operational amplifier inputs BIL and BIR are protected

from excessive voltages (currents) by diodes to VDDA and

VSSA. These have absolute maximum ratings of

Id=±20 mA, with a safe practical limit of ±2 mA.

Given the input resistor of 10 kΩ,±2 mA diode current and

the operation of the operational amplifier, a maximum

signal (applied to the input resistor) of ±30 V can be

handled safely. This level represents an overload of 26 dB.

During overload, the in-band portion of the waveform will

be correctly converted. The out-of-band portion will be

limited as previously detailed.

Sigma-Delta Modulator (SDM)

The SAA7367 uses two third-order SDMs with a

quantization noise floor of approximately −104 dB. The

scaling of the feedback has been optimized for stable

operation, even during overload. Thus, with a maximum

signal swing of 0 V to VDDA on the input, the digital output

remains well-behaved, i.e. it does not burst into random

oscillation. During overload, the output is simply a clipped

version of the input. The gain of this stage is −4.64 dB.

Decimation ﬁlter

Decimation from 128fs is performed in two stages. The first

stage, a comb filter, uses 64 symmetrical coefficients to

implement a 3rd sin x⁄x characteristic. This filter decimates

from 128 to 8fs. The second stage, an FIR filter, consists of

three half-band filters, each decimating by a factor of 2.

The overall characteristics are given in Table 3.

1998 Nov 17 7

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

Table 3 Overall ﬁlter characteristics

High-pass ﬁlter

An optional I2R high-pass filter is provided to remove

unwanted DC components. The operation is selected

when HPEN is HIGH and deselected when LOW. The filter

has the characteristics given in Table 4.

Table 4 High-pass ﬁlter characteristics

Serial interface

The serial interface provides 2 formats in master mode

and 4 in slave mode (see Figs 3 and 4). Format 2 is similar

to Philips I2S. In all modes, the interface provides up to

18 significant bits of output data per channel. During

standby mode (STDB = LOW), all interface pins are in

their high impedance state. On recovery from standby, the

serial data output SDO is held LOW until valid data is

available from the decimation filter. This time depends on

whether the high-pass filter is selected:

HPEN = 0; T = 1024/fs, T = 21.3 ms when fs= 48 kHz

HPEN = 1; T = 12288/fs, T = 256.0 ms when

fs=48kHz

Overload detection

The OVLD output is used to indicate when the output data,

in either the left or right channel, is greater than −1dB

(actual figure −1.023 dB) of the maximum possible digital

swing. When this condition is detected, the OVLD output is

forced HIGH for at least 512fs cycles (10.6 ms at

fs= 48 kHz). This time-out is reset for each infringement.

ITEM CONDITION VALUE (dB)

Pass band ripple 0 to 0.45fs±0.1

0.45 to 0.47fs−0.5

Stop band >0.55fs−60

Dynamic range 0 to 0.42fs110

Gain DC 3.52

ITEM CONDITION VALUE

(dB)

Pass band ripple none

Pass band gain 0

Droop at 0.00042fs0.146

Attenuation at DC at 0.00000036fs>40

Dynamic range 0 to 0.45fs>110

Standby mode

The STDB pin activates a power saving mode when the

device function is not required. This pin can also be used

as a chip enable.

On a HIGH-to-LOW transition of the STDB pin, the internal

control circuitry starts a timed power-down sequence. This

takes approximately 32 system clock cycles to complete.

Transitions on STDB that are shorter than 32 clock cycles

may have an indeterminate effect. However, the device

will always recover correctly.

During standby, the following occurs:

•The internal logic clock is disabled

•The serial interface pins are forced to high impedance

•The OVLD output is forced LOW

•The analog circuitry is disabled

•The nominal external analog node voltages are

maintained by a low-power circuit. This feature ensures

a fast recovery from standby mode.

Note: since the serial interface pins are high impedance

during standby, these pins could be wire-ORed with other

serial interface ICs.

On a LOW-to-HIGH transition, the device reverts back to

normal operation. This process takes approximately

256 system clock cycles. Before SDO is enabled, the

output data is forced LOW. SDO remains LOW until good

data is available from the decimation filter

(see Section “Serial interface”).

The STDB pin has a Schmitt-trigger input. A simple

power-on-reset function can be effected using an external

capacitor to VSS and resistor to VDD.

TEST1

This pin is used to select the serial interface format in slave

mode.

1998 Nov 17 8

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. VSSD and VSSA must be connected to a common potential.

QUALITY SPECIFICATION

In accordance with

“SNW-FQ-611-E”

. The number of the quality specification can be found in the

“Quality Reference

Handbook”

CHARACTERISTICS

VDDD = 4.5 to 5.5 V; VDDA = 4.5 to 5.5 V; fs= 18 to 50 kHz; Tamb =−40 to +85 °C; unless otherwise speciﬁed.

SYMBOL PARAMETER MIN. MAX. UNIT

VDDA analog supply voltage (note 1) −0.5 +6.5 V

VIDC input voltage −0.5 +6.5 V

IIK DC input clamp diode current −±20 mA

VODC output voltage −0.5 VDD + 0.5 V

IODC output source or sink current −±20 mA

IDD(tot) total DC supply current −±0.5 A

ISStot total DC supply current −±0.5 A

Tamb operating ambient temperature −40 +85 °C

Tstg storage temperature −65 +150 °C

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDDD digital supply voltage 4.5 5 5.5 V

IDDD digital supply current fs=48kHz −17 −mA

VDDA analog supply voltage 4.5 5 5.5 V

IDDA analog supply current −13 −mA

Ptot total power dissipation fs=48kHz −150 −mW

Istb standby supply current −160 −µA

stb standby power consumption −800 −µW

Digital part: inputs

SFOR, SLAVE AND HPEN

VIL LOW level input voltage −0.5 −+0.8 V

VIH HIGH level input voltage 2.0 −VDD + 0.5 V

ILI input leakage current −10 −+10 µA

Ciinput capacitance −−10 pF

1998 Nov 17 9

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

CKIN

VIL LOW level input voltage −0.5 −0.3VDD V

VIH HIGH level input voltage 0.7VDD −VDD + 0.5 V

ILI input leakage current −10 −+10 µA

Ciinput capacitance −−10 pF

TEST1

VIL LOW level input voltage −0.5 −+0.8 V

VIH HIGH level input voltage 2.0 −VDD + 0.5 V

Riinternal resistance to VSS −50 −kΩ

Ciinput capacitance −−10 pF

TESTB

VIH HIGH level input voltage 0.7VDD −VDD + 0.5 V

Riinternal resistance to VDD −50 −kΩ

STDB (SCHMITT TRIGGER)

VIL LOW level input voltage −0.5 −0.4VDD V

VIH HIGH level input voltage 0.6VDD −VDD + 0.5 V

Vhys hysteresis voltage 200 −− mV

ILI input leakage current −10 −+10 µA

Ciinput capacitance −−10 pF

Digital part: inputs/outputs

SWS AND SCK

VIL LOW level input voltage −0.5 −+0.8 V

VIH HIGH level input voltage 2.0 VDD + 0.5 V

ILl 3-state leakage current −10 −+10 µA

Ciinput capacitance −−10 pF

VOL LOW level output voltage IO=−400 µA−−0.4 V

VOH HIGH level output voltage IO=20µA 2.4 −− V

Loutput load capacitance note 1 −−50 pF

Digital part: outputs

OVLD

VOL LOW level output voltage IO=−400 µA−−0.4 V

VOH HIGH level output voltage IO=20µA 2.4 −− V

Loutput load capacitance note 1 −−50 pF

SDO

VOL LOW level output voltage IO=−400 µA−− 0.4 V

VOH HIGH level output voltage IO=20µA 2.4 −− V

LI 3-state leakage current −10 −+10 µA

CLoutput load capacitance note 1 −−50 pF

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1998 Nov 17 10

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

Digital part: timings

CKIN

trinput rise time −−10 ns

tfinput fall time −−10 ns

fiinput frequency 4.60 −12.8 MHz

msr mark-to-space ratio fs> 32 kHz 40 −60 %

fs≤32 kHz 30 −70 %

Serial Interface master and slave modes (see Figs 5 and 6)

SCK

trrise time CL= 50 pF;

note 1 −−50 ns

tffall time CL= 50 pF;

note 1 −−50 ns

tLLOW time T = 1⁄64fs0.4T −0.6T ns

tHHIGH time T = 1⁄64fs0.4T −0.6T ns

fclk clock frequency master mode 64fs64fs64fsMHz

slave mode −−64fsMHz

tidle burst clock idle time slave mode;

T = 1/fs

0−0.5T ns

SWS

trrise time CL= 50 pF;

note 1 −−50 ns

tffall time CL= 50 pF;

note 1 −−50 ns

tLLOW time T = 1/fs0.05T 0.5T 0.95T ns

tHHIGH time T = 1/fs0.05T 0.5T 0.95T ns

fSfrequency 1fs1fs1fsMHz

tddelay from SCK master mode −50 −+50 ns

slave mode 50 −ns

tsu set-up time to SCK slave mode 150 −− ns

SDO

thdata output hold time 100 −− ns

tsu data output set-up time 50 −− ns

trdata output rise time CL= 50 pF;

note 1 −−50 ns

tfdata output fall time CL= 50 pF;

note 1 −−50 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1998 Nov 17 11

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

Notes

1. Load capacitance is valid for master mode only.

2. See also Section “Input level” of Chapter “Functional description”; valid for left or right channel.

Analog part at: VDD =V

DDA =5V; T

amb =25°C

refL AND VrefR

VOoutput voltage 0.475VDDA 0.5VDDA 0.525VDDA V

RDC DC impedance normal mode −1.3 −kΩ

standby mode −100 −kΩ

CURRENT REFERENCE:I

ref

VOout put voltage −0.5VDDA −V

IOoutput current R = 33 kΩ− 76 −µA

DACN

VIinput voltage −VSS −V

VDACP

VIinput voltage −VDDA −V

BUFFER OPERATIONAL AMPLIFIERS: BIL, BOL, BIR AND BOR

VI(off) input offset voltage −<10 −mV

RLload resistance; (drive capability) decoupled to Vref −10 −kΩ

ZOoutput impedance −100 −Ω

THD + N total harmonic distortion plus

noise f=0to20kHz −−87 −dB

OVERALL PERFORMANCE (ANALOG IN,DIGITAL OUT)

tgd group delay time T = 1/fs−25T −s

αsb stop band attenuation f > 0.546 fs60 −− dB

DR dynamic range 0 to 20 kHz 90 93 −dB

THD + N total harmonic distortion plus

noise 0to20kHz −−88 −80 dB

S/N signal-to-noise ratio A-weighted −97 −dB

αcs channel separation −92 −dB

G gain note 2 −1.4 −1−0.8 dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1998 Nov 17 12

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

Fig.3 Serial interface master mode format.

handbook, full pagewidth

MGE647

SCK

SDO MSB LSB MSB LSB MSB

FORMAT 2

FORMAT 1

1 STEREO WORD

LEFT DATA RIGHT DATA

LEFT DATARIGHT DATA

18 CLOCKS 14 CLOCKS 18 CLOCKS 14 CLOCKS

1998 Nov 17 13

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

Fig.4 Serial interface slave mode format.

handbook, full pagewidth

MGE648

FORMAT 2

FORMAT 4

SCK

SDO

SCK

SDO

FORMAT 1

FORMAT 3

1 STEREO WORD

idle N CLOCKS N CLOCKS

idle

MSB MSB MSBLSB LSB

N CLOCKS N CLOCKS

LEFT DATA

RIGHT DATA

LEFT DATA

1998 Nov 17 14

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

Fig.5 Serial interface master mode timing.

handbook, full pagewidth

MGE649

trtsu thtf

tLtH

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

VALID MSB

FORMAT 1 MSB

FORMAT 2

SCK

SWS

SDO

Fig.6 Serial interface slave mode timing.

handbook, full pagewidth

MGE650

trtsu thtf

tdtsu

tLtH

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

VALID MSB

FORMAT 1 MSB

FORMAT 2

SCK

SWS

SDO

1998 Nov 17 15

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

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APPLICATION INFORMATION

Fig.7 Application circuit.

(1) These capacitors should preferably be surface-mounted components located as close as possible to the device pins.

handbook, full pagewidth

4.7 Ω

MGE646

left channel input

68 pF

47 nF

Rdither Rdither

68 pF

47 µF

100 kΩ100 kΩ

10 kΩ

330 kΩ33 kΩ

right channel input

µF

+5 V

22 nF

24 23 22 21 20 19 18 17 16 15 14 13

123456789101112

SAA7367

system

clock

input

to microcontroller

overload detection

from microcontroller

power-down control 47 nF

to serial interface

receiver circuit

SFOR STDB OVLD CKIN SDO SWS SCK TEST1 HPEN TESTB

SLAVE BIL BOL BOR BIR

(1)

VDDD or VSSD

VDDA

VDDD VSSD

VrefL VrefR VSSA

Iref

VDACP VDACN

10 kΩ

620 kΩ

10 kΩ

4.7 Ω270

Ω270

Ω

+5 V

1998 Nov 17 16

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

PACKAGE OUTLINE

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

inches

2.65 0.30

0.10 2.45

2.25 0.49

0.36 0.32

0.23 15.6

15.2 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.1

0.4

SOT137-1

detail X

vMA

(A )

0.25

075E05 MS-013AD

pin 1 index

0.10 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.61

0.60 0.30

0.29 0.050

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

95-01-24

97-05-22

1998 Nov 17 17

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable

for surface mount ICs, or for printed-circuit boards with

high population densities. In these situations reflow

soldering is often used.

Reﬂow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary

between 100 and 200 seconds depending on heating

method.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

•Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

The footprint must incorporate solder thieves at the

downstream end.

•For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

1998 Nov 17 18

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

Suitability of surface mount IC packages for wave and reﬂow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

PACKAGE SOLDERING METHOD

WAVE REFLOW(1)

HLQFP, HSQFP, HSOP, SMS not suitable(2) suitable

PLCC(3), SO suitable suitable

LQFP, QFP, TQFP not recommended(3)(4) suitable

SQFP not suitable suitable

SSOP, TSSOP, VSO not recommended(5) suitable

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development.

Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later.

Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

1998 Nov 17 19

Philips Semiconductors Product speciﬁcation

Bitstream conversion ADC for

digital audio systems SAA7367

NOTES

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Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

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For all other countries apply to: Philips Semiconductors,

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Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,

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Tel. +91 22 493 8541, Fax. +91 22 493 0966

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Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

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Printed in The Netherlands 545102/00/02/pp20 Date of release: 1998 Nov 17 Document order number: 9397 750 04775